CN115004368A - 3d nand存储器及其形成方法 - Google Patents

3d nand存储器及其形成方法 Download PDF

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Publication number
CN115004368A
CN115004368A CN202180010962.3A CN202180010962A CN115004368A CN 115004368 A CN115004368 A CN 115004368A CN 202180010962 A CN202180010962 A CN 202180010962A CN 115004368 A CN115004368 A CN 115004368A
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China
Prior art keywords
layer
forming
hole
metal
metal silicide
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Pending
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CN202180010962.3A
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English (en)
Inventor
宋豪杰
高倩
鲍琨
何欢
黄亚俊
马艳三
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Publication of CN115004368A publication Critical patent/CN115004368A/zh
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226Via connections in a multilevel interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • H01L23/5283Cross-sectional geometry
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Memories (AREA)

Abstract

一种3D NAND存储器的形成方法,在沟道通孔中形成存储结构和位于所述存储结构上的多晶硅层,所述多晶硅层的表面低于所述介质层的顶部表面后,在所述多晶硅层表面形成第一金属硅化物层和位于第一金属硅化物层上的通孔接触金属层;将所述牺牲层替换为控制栅结构;在所述介质层中形成暴露出堆叠结构一侧的阱区部分表面的第一通孔以及暴露出相应的台阶结构表面的若干第二通孔;在所述第一通孔底部的阱区表面形成第二金属硅化物层;在所述第一通孔中形成第一接触插塞,在所述第二通孔中形成第二接触插塞。

Description

PCT国内申请,说明书已公开。

Claims (21)

  1. PCT国内申请,权利要求书已公开。
CN202180010962.3A 2020-10-19 2021-10-19 3d nand存储器及其形成方法 Pending CN115004368A (zh)

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CN202011117206.4A CN112331671B (zh) 2020-10-19 2020-10-19 3d nand存储器的形成方法
CN2020111172064 2020-10-19
PCT/CN2021/124789 WO2022083597A1 (zh) 2020-10-19 2021-10-19 3d nand存储器及其形成方法

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KR101845511B1 (ko) * 2011-10-11 2018-04-05 삼성전자주식회사 수직 구조의 비휘발성 메모리 소자 제조 방법
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CN110010619B (zh) * 2018-01-04 2021-01-05 旺宏电子股份有限公司 三维半导体元件及其制造方法
KR20200015219A (ko) * 2018-08-03 2020-02-12 삼성전자주식회사 수직형 메모리 장치 및 그 제조 방법
CN109148461B (zh) * 2018-08-17 2021-02-12 长江存储科技有限责任公司 3d存储器件及其制造方法
CN109817623B (zh) * 2019-03-27 2021-04-13 长江存储科技有限责任公司 3d nand存储器及其形成方法
CN112331671B (zh) * 2020-10-19 2021-11-05 长江存储科技有限责任公司 3d nand存储器的形成方法

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CN114188347A (zh) 2022-03-15
WO2022083597A1 (zh) 2022-04-28
CN112331671B (zh) 2021-11-05
CN112331671A (zh) 2021-02-05
US20230142924A1 (en) 2023-05-11

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