WO2022063210A1 - 半导体元胞结构、igbt元胞结构、半导体结构及其制备方法 - Google Patents

半导体元胞结构、igbt元胞结构、半导体结构及其制备方法 Download PDF

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WO2022063210A1
WO2022063210A1 PCT/CN2021/120182 CN2021120182W WO2022063210A1 WO 2022063210 A1 WO2022063210 A1 WO 2022063210A1 CN 2021120182 W CN2021120182 W CN 2021120182W WO 2022063210 A1 WO2022063210 A1 WO 2022063210A1
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trench
layer
oxide layer
region
polysilicon
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PCT/CN2021/120182
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English (en)
French (fr)
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黄宝伟
吴海平
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比亚迪半导体股份有限公司
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Priority to JP2023518892A priority Critical patent/JP2023542401A/ja
Priority to EP21871579.5A priority patent/EP4220733A4/en
Publication of WO2022063210A1 publication Critical patent/WO2022063210A1/zh
Priority to US18/187,852 priority patent/US20230246096A1/en

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    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
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Definitions

  • the present disclosure generally relates to the field of semiconductor manufacturing, and in particular relates to a semiconductor cell structure, an IGBT cell structure, a semiconductor structure and a method for preparing the IGBT cell structure.
  • IGBT Insulated Gate Bipolar Transistor, insulated gate bipolar transistor
  • IGBT has the advantages of low conduction loss, high input impedance, simple driving circuit, low driving power and fast turn-on speed.
  • IGBTs In order to obtain higher power and higher efficiency power control systems, IGBTs have been developing in the direction of low conduction loss and low switching loss.
  • IGBT has experienced the development of PT-NPT-FS in the vertical structure; in the surface structure, the IGBT has developed from a planar gate to a trench gate structure, which greatly reduces the conduction of the IGBT. losses and switching losses.
  • the introduction of the floating P region greatly reduces the conduction voltage drop of the Trench IGBT, improves the carrier storage effect, and greatly improves the forward conduction voltage drop Vce and The contradictory relationship between the off-time t off .
  • the contact surface between the gate and the collector of the Miller capacitor occupies most of the trench area, and the dielectric layer is only a thin gate oxide layer, which is extremely thin.
  • Miller capacitance with floating P-type TrenchIGBT is large.
  • the gate current increases the displacement current in addition to the gate driving current.
  • a larger Miller capacitance will cause a large displacement current in the gate of the device. voltage will be affected.
  • the larger Miller capacitance will lead to a larger voltage change rate dv/dt, a higher current peak value, and electromagnetic compatibility (EMC) during the reverse recovery of the freewheeling diode used. question.
  • EMC electromagnetic compatibility
  • the larger Miller capacitance will also increase the turn-on time and turn-off time of the device, so the device will get larger turn-on and turn-off losses.
  • an embodiment of the present disclosure provides an IGBT cell structure, which is characterized in that it includes an N-type drift layer, an N-type termination layer, a P-type collector layer, and a collector metal layer that are stacked in sequence;
  • the IGBT cell structure includes: two spaced first trenches, forming a trench-shaped insulating oxide layer on the inner wall of the first trench, a polysilicon electrode in the trench-shaped insulating oxide layer, a second trench in the first trench, and a second trench in the second trench a trench-shaped gate oxide layer in the trench, a polysilicon gate located in the trench-shaped gate oxide layer, a P hydrazine region located between the first trenches, and two spaced floating P regions; wherein,
  • the trench-shaped insulating oxide layer and the polysilicon gate in the first trench are both adjacent to the second trench in the first trench, and the depth of the floating P region does not exceed The depth of the first trench, the floating P region is separated from the P hydrazine region by the trench-shaped insulating oxide layer, and the trench-shaped gate oxide layer is separated from the trench by the polysilicon electrode
  • the trench-shaped insulating oxide layers are separated, and the gate oxide layers in the two trench-shaped insulating oxide layers are respectively adjacent to the P hydrazine regions.
  • the IGBT cell structure further includes: an N+ emitter layer, the N+ emitter layer is formed on the floating P region and the P hydrazine region facing away from the On one side of the P-type collector layer, a P+ region connected to the N+ emitter layer is arranged in the P-hydrazine region;
  • the IGBT cell structure further includes: a direction from approaching the P-type collector layer to a direction away from the P-type collector layer
  • An insulating dielectric isolation layer and an emitter metal layer are arranged in sequence, and the insulating dielectric isolation layer covers the N+ emitter layer, the trench-shaped insulating oxide layer, the polysilicon electrode, and the trench-shaped gate oxide layer and the polysilicon gate, the insulating dielectric isolation layer has an opening exposing the polysilicon electrode and the P+ region, and the emitter metal layer covers the insulating dielectric isolation layer and fills the opening.
  • the depth of the first trench is 4um-8um, and the depth of the second trench is 2um-5um.
  • the width of the second trench is 0.6um-1.0um smaller than the width of the first trench, the width of the first trench is 1.4um-2.2um, and the width of the second trench It is 0.8um-1.2um.
  • the doping concentration satisfies at least one of the following conditions:
  • the doping concentration of the P hydrazine region is 1 ⁇ 10 16 cm ⁇ 3 ⁇ 1 ⁇ 10 19 cm ⁇ 3 ;
  • the doping concentration of the P+ region is 1 ⁇ 10 19 cm ⁇ 3 ⁇ 1 ⁇ 10 22 cm ⁇ 3 ;
  • the doping concentration of the N+ emitter layer is 1 ⁇ 10 19 cm ⁇ 3 ⁇ 1 ⁇ 10 23 cm ⁇ 3 .
  • the present disclosure provides a semiconductor structure, comprising a plurality of IGBT cell structures connected in parallel as described above, wherein the depth of the floating P region of the IGBT cell structure is the same as the depth of the first trench, The floating P regions of two adjacent IGBT cell structures are connected to form a floating P region.
  • the present disclosure provides a semiconductor structure, including a plurality of IGBT cell structures connected in parallel as described above;
  • the N-type drift layer is further provided with at least one intermediate trench, the intermediate trench is provided with a trench insulating oxide layer, and the trench insulating An intermediate polysilicon layer is arranged in the oxide layer, the intermediate trench is formed in the same layer as the first trench, the trench insulating oxide layer is formed in the same layer as the trench-shaped insulating oxide layer, and the intermediate polysilicon layer is formed It is formed in the same layer as the polysilicon electrode.
  • At least two intermediate trenches are further provided in the N-type drift layer, and an intermediate P is provided between the two intermediate trenches.
  • a floating area, the intermediate P floating area and the floating P area are formed in the same layer.
  • the present disclosure also provides a method for preparing an IGBT cell structure, including:
  • N-type substrate having opposing front and back surfaces
  • Two first trenches spaced apart are formed in the N-type substrate through deposition, photolithography and etching processes, a trench-shaped insulating oxide layer is formed in the first trenches, and a trench-shaped insulating oxide layer is formed in the trenches.
  • Polysilicon is deposited in the trench-shaped insulating oxide layer to form a polysilicon electrode region, and the opening of the trench-shaped insulating oxide layer faces the front surface;
  • a second trench is formed in the first trench through deposition, photolithography and etching processes, a trench-shaped gate oxide layer is formed in the second trench, and a trench is formed between the second trench and the polysilicon electrodes between the trench-shaped insulating oxide layers;
  • a P hydrazine region is formed between the two trench-shaped insulating oxide layers through Pwell implantation and push junction processes, and floating spaces are respectively formed on the sides of the two trench insulating oxide layers facing away from the P-hydrazine region.
  • the trench gate oxide layers in the two trench-shaped insulating oxide layers are respectively adjacent to the P hydrazine region.
  • the preparation method further includes:
  • An insulating dielectric isolation layer is deposited on the front surface of the N- type substrate, and the insulating dielectric isolation layer covers the N+ emitter layer, the trench-shaped insulating oxide layer, the polysilicon electrode, and the trench-shaped insulating oxide layer.
  • a gate oxide layer and the polysilicon gate, and the insulating dielectric isolation layer has an opening exposing the polysilicon electrode and the P+ region;
  • Metal is sputtered on the side of the insulating dielectric isolation layer facing away from the back surface of the N-type substrate to form an emitter metal layer, and the emitter metal layer fills the opening;
  • An N-type termination layer is formed on the backside of the N-drift layer by ion implantation;
  • a collector metal layer is formed by sputtering metal on the side of the P-type collector facing away from the N-drift layer.
  • the photolithography and etching process are used to form two first trenches arranged at intervals in the N-type substrate, a trench-shaped insulating oxide layer is formed in the first trenches, and a trench-shaped insulating oxide layer is formed in the first trenches.
  • the polysilicon deposited in the trench-shaped insulating oxide layer to form the polysilicon electrode region includes:
  • a first dielectric layer is deposited on the front side of the N-type substrate, photolithography is performed, and the first dielectric layer and the N-type substrate are etched to form two spaced ones located on the N-type substrate a first groove in the bottom;
  • the insulating oxide layer and polysilicon located on the front surface of the N-type substrate are removed by chemical mechanical polishing, and a trench-shaped insulating oxide layer and a trench-shaped insulating oxide layer located in the trench-shaped insulating oxide layer are formed in the first trench.
  • Polysilicon electrode area
  • Deposition of polysilicon in the trench gate oxide layer to form a polysilicon gate includes:
  • a second dielectric layer is deposited on the front side of the N-type substrate, photolithography is performed, the second dielectric layer, the polysilicon electrode region and the trench-shaped insulating oxide layer are etched to form the first dielectric layer located on the first a second groove within the groove;
  • etching back polysilicon to the top of the second trench removing the gate oxide layer on the front side of the N-type substrate, forming a trench-shaped gate oxide layer in the second trench, and forming a trench gate oxide layer in the trench
  • a polysilicon gate is formed in the trench gate oxide layer.
  • the present disclosure further provides a semiconductor cell structure, the semiconductor cell structure includes an N-type drift layer, an N-type termination layer, a P-type collector layer, and a collector metal layer that are stacked in sequence;
  • the semiconductor cell structure includes: two spaced first trenches, forming a trench-shaped insulating oxide layer on the inner wall of the first trench, a polysilicon electrode located in the trench-shaped insulating oxide layer, a second trench formed on the inner wall of the first trench, and a polysilicon electrode located in the inner wall of the first trench a trench gate oxide layer in the trench, a polysilicon gate located in the trench gate oxide layer, a P hydrazine region located between the first trenches, and two spaced floating P regions; wherein ,
  • Both the trench-shaped insulating oxide layer and the polysilicon gate in the first trench are adjacent to the second trench in the first trench, and the trench-shaped gate oxide layer passes through the first trench.
  • the polysilicon electrode is separated from the trench-shaped insulating oxide layer, the depth of the floating P region does not exceed the depth of the first trench, and the floating P region is connected to the trench-shaped insulating oxide layer through the trench-shaped insulating oxide layer.
  • the P hydrazine regions are separated, and the gate oxide layers in the two second trenches are respectively adjacent to the P hydrazine regions.
  • the first trench is a dummy trench (that is, a pseudo trench)
  • the second trench is a gate trench
  • the two second trenches are respectively connected to P
  • the hydrazine region is adjacent to each other. Since most of the second trench is located in the first trench, only a small part of the second trench is adjacent to the N-type drift layer to form a Miller capacitance, which makes the semiconductor cell structure very Small Miller capacitance, so as to achieve the effect of improving the turn-on efficiency of the device and reducing the switching loss of the device.
  • FIG. 1 is a schematic structural diagram of a semiconductor cell structure provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of another semiconductor structure provided by an embodiment of the present disclosure.
  • 4 to 15 are schematic structural diagrams corresponding to a series of processes of a method for fabricating a semiconductor cell structure according to an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a semiconductor cell structure, which includes an N-type drift layer, an N-type termination layer, a P-type collector layer, and a collector metal layer that are stacked in sequence;
  • the semiconductor cell structure includes: two first trenches arranged at intervals, a trench formed on the inner wall of the first trench A trench-shaped insulating oxide layer, a polysilicon electrode in the trench-shaped insulating oxide layer, a second trench formed on the inner wall of the first trench, a trench-shaped gate oxide layer in the second trench, and a trench-shaped gate oxide layer a polysilicon gate in the oxide layer, a P hydrazine region located between the first trenches, and two spaced floating P regions; wherein,
  • the trench-shaped insulating oxide layer and the polysilicon gate in the first trench are both adjacent to the second trench located in the first trench, and the trench-shaped gate oxide layer is separated from the trench-shaped insulating oxide layer by the polysilicon electrode , the depth of the floating P region does not exceed the depth of the first trench, the floating P region is separated from the P hydrazine region by a trench-shaped insulating oxide layer, and the gate oxide layers in the two second trenches are respectively connected to the P hydrazine region. adjoining.
  • the semiconductor cell structure may be an IGBT type semiconductor cell structure, or a MOS (Metal Oxide Semiconductor) type semiconductor cell structure.
  • MOS Metal Oxide Semiconductor
  • the main difference between MOS and IGBT is the backside of the substrate.
  • the backside of the IGBT substrate has an extra layer of P-type substrate than the backside of the MOS substrate.
  • the front-side structure of the IGBT and the MOS substrate is the same.
  • the semiconductor cell structure in the embodiments of the present disclosure may be an IGBT or a MOS.
  • the semiconductor cell structure is an IGBT as an example for description.
  • the existing semiconductor cell structure for example, the IGBT cell structure
  • the switching speed of the device is reduced, the switching loss is increased, and the working performance of the IGBT is seriously affected.
  • the present disclosure provides a semiconductor cell structure, an IGBT cell structure, a semiconductor structure and a method for preparing the IGBT cell structure.
  • an embodiment of the present disclosure provides an IGBT cell structure, including an N-type drift layer 101 , an N-type termination layer 116 , a P-type collector layer 117 and a collector metal layer 118 that are stacked in sequence;
  • the IGBT cell structure On the side of the N-type drift layer 101 facing away from the P-type collector layer 117 and in the N-type drift layer 101, the IGBT cell structure includes: two first trenches 102 arranged at intervals, formed in the first trenches The trench-shaped insulating oxide layer 103 on the inner wall of the trench 102 , the polysilicon electrode 104 located in the trench-shaped insulating oxide layer 103 , the second trench 105 located in the first trench 102 , and the trench formed on the inner wall of the second trench 105 A trench gate oxide layer 106, a polysilicon gate 107 located in the trench gate oxide layer 106, a P hydrazine region 108 located between the first trenches 102, two spaced floating P regions 109, and an N+ emitter layer 110, the N+ emitter layer 110 is formed on the side of the floating P region 109 and the P hydrazine region 108 facing away from the P-type collector layer 117, and the P hydrazine region
  • the IGBT cell structure further includes: insulating layers arranged in sequence from the direction close to the P-type collector layer 117 to the direction away from the P-type collector layer 117 Dielectric isolation layer 112 and emitter metal layer 113, insulating dielectric isolation layer 112 covers N+ emitter layer 110, trench-shaped insulating oxide layer 103, polysilicon electrode 104, trench-shaped gate oxide layer 106 and polysilicon gate 107, insulating dielectric isolation
  • the layer 112 has an opening 114 exposing the polysilicon electrode 104 and the P+ region 111, and the emitter metal layer 113 covers the insulating dielectric isolation layer 112 and fills the opening 114; wherein,
  • the trench-shaped insulating oxide layer 103 and the polysilicon electrode 104 in the first trench are both adjacent to the second trench located in the first trench, and the trench-shaped gate oxide layer 106 is oxidized to the trench-shaped insulating oxide layer through the polysilicon electrode 104
  • the layer 103 is separated, the depth of the floating P region 109 does not exceed the depth of the first trench 102, the floating P region 109 is separated from the P hydrazine region 108 by the trench-shaped insulating oxide layer 103, and the two second trenches 105
  • the inner gate oxide layers 106 are respectively adjacent to the P hydrazine regions 108 .
  • the first trench is a dummytrench (pseudo-trench)
  • the second trench is a gate trench
  • the P hydrazine region is located between the two second trenches (that is, the two gate trenches). Since the second trench is located in the first trench, only a small part of the second trench is adjacent to the N-type drift layer to form Miller capacitance, such as the second trench and the N-type drift layer.
  • the length of the contact part of the type drift layer is 200nm, even 100nm, so that the IGBT cell structure has a small Miller capacitance, thereby improving the turn-on efficiency of the device and reducing the switching loss of the device.
  • the polysilicon electrode is a polysilicon emitter
  • the region inside the second trench is the gate region
  • the periphery of the second trench is basically adjacent to the emitter, so the IGBT cell structure provided in this embodiment has a larger input
  • the capacitance can further reduce the influence of the displacement current caused by the feedback capacitance on the gate voltage, and the gate voltage of the device is not easily affected by the current change.
  • the semiconductor material is polycrystalline silicon, single crystal silicon, silicon carbide, gallium nitride or zinc oxide.
  • the depth of the first trench 102 is 4um-8um, and the depth of the second trench 105 is 2um-5um.
  • the first trench is deeper than the second trench.
  • each first trench is formed with a second trench, the two second trenches are respectively adjacent to the P hydrazine region, and the second trench is located in the first trench In the trench, it is ensured that only a small part of the contact between the gate region and the N-drift region is in contact, so that the device has a small Miller capacitance;
  • the deep first trench forms a floating P region on the outside of the first trench.
  • the first trench and the floating P region can reduce the electric field at the bottom of the trench and improve the reverse voltage withstand capability of the device.
  • the first trench and the floating P region can store a large number of minority carriers on the surface of the device, thereby reducing the turn-on voltage drop of the device.
  • the width of the second trench 105 is 0.6um-1.0um smaller than the width of the first trench 102, the width of the first trench 102 is 1.4um-2.2um, and the width of the second trench 105 is 0.8um- 1.2um to ensure that the first trench can surround the second trench.
  • the doping concentration of the P hydrazine region 108 is 1 ⁇ 10 16 cm ⁇ 3 ⁇ 1 ⁇ 10 19 cm ⁇ 3 ; and/or,
  • the doping concentration of the P+ region 111 is 1 ⁇ 10 19 cm ⁇ 3 ⁇ 1 ⁇ 10 22 cm ⁇ 3 ; and/or,
  • the doping concentration of the N+ emitter layer 110 is 1 ⁇ 10 19 cm ⁇ 3 ⁇ 1 ⁇ 10 23 cm ⁇ 3 .
  • the doping concentration satisfies at least one of the following conditions:
  • the doping concentration of the P hydrazine region is 1 ⁇ 10 16 cm ⁇ 3 ⁇ 1 ⁇ 10 19 cm ⁇ 3 ;
  • the doping concentration of the P+ region is 1 ⁇ 10 19 cm ⁇ 3 ⁇ 1 ⁇ 10 22 cm ⁇ 3 ;
  • the doping concentration of the N+ emitter layer is 1 ⁇ 10 19 cm ⁇ 3 ⁇ 1 ⁇ 10 23 cm ⁇ 3 .
  • an embodiment of the present disclosure provides a semiconductor structure including a plurality of IGBT cell structures shown in FIG. 1 connected in parallel, and the depth of the floating P region of the IGBT cell structure is the same as the depth of the first trench 102 .
  • the depths are similar, and the floating P regions 109 of two adjacent IGBT cell structures are connected to form a floating P region 201 .
  • the depth of the floating P region 201 is the same as or close to that of the first trench.
  • the floating P region can withstand the main electric field, so that the electric field will not be concentrated at the bottom of the first trench, which improves the voltage withstand capability of the device, and the device is less prone to overvoltage damage in application .
  • an embodiment of the present disclosure provides another semiconductor structure, including a plurality of IGBT cell structures shown in FIG. 1 in parallel;
  • At least one intermediate trench 301 is further provided in the N-type drift layer 101 , a trench insulating oxide layer 302 is provided in the intermediate trench 301 , and a trench insulating oxide layer 302 is provided in the intermediate trench 301 .
  • There is an intermediate polysilicon layer 303 the intermediate trench 301 is formed in the same layer as the first trench 103, the trench insulating oxide layer 302 is formed in the same layer as the trench-shaped insulating oxide layer 106, and the intermediate polysilicon layer 303 is formed in the same layer as the polysilicon electrode 104.
  • the insulating dielectric isolation layer 112 also covers the middle trench 301, the trench insulating oxide layer 302 and the intermediate polysilicon layer 303, the insulating dielectric isolation layer 112 also has an opening 304 exposing the intermediate polysilicon layer 303, and the N+ emitter metal layer 113 is also filled with Opening 304 .
  • At least two middle trenches 301 are also arranged in the N-type drift layer 101 , and a middle P floating region is arranged between the two middle trenches 301 .
  • the P floating region and the floating P region 109 are formed in the same layer; the N+ emitter layer 110 is also connected to the middle P floating region.
  • At least one trench portion is provided between adjacent IGBT cell structures, and the depth and width of the trench portion are the same as the first trench.
  • the trench portion and the first trench are formed.
  • a trench is implemented simultaneously without increasing the complexity of the process.
  • the high-density deep trench can reduce the electric field at the bottom of the trench and improve the reverse voltage withstand capability of the device.
  • the deep trench and the floating P region can achieve consistent As a result, a large number of minority carriers can be stored on the surface of the device, and the conduction voltage drop of the device can be reduced.
  • the middle polysilicon electrode in the trench and the polysilicon electrode in the first trench are both connected to the emitter metal layer, adding a larger collector-emitter capacitance, which can absorb to a certain extent Noise generated during device switching operation.
  • the present disclosure provides a preparation method of the IGBT cell structure.
  • N-type substrate 115 having opposite front and back surfaces
  • Two spaced first trenches 102 are formed in the N-type substrate 115 through deposition, photolithography and etching processes, a trench-shaped insulating oxide layer 103 is formed in the first trench 102, and a trench-shaped insulating oxide layer 103 is formed in the trench-shaped substrate 115.
  • Polysilicon is deposited in the insulating oxide layer 103 to form a polysilicon electrode region 123, and the opening of the trench-shaped insulating oxide layer 103 faces the front, referring to FIG. 7;
  • a second trench 105 is formed in the first trench 102 through deposition, photolithography and etching processes, a trench gate oxide layer 106 is formed in the second trench 105, and a trench is formed between the second trench 105 and the trench
  • the polysilicon electrodes 104 between the trench-shaped insulating oxide layers 103;
  • Polysilicon is deposited in the trench gate oxide layer 106 to form a polysilicon gate 107;
  • a P hydrazine region 108 is formed between the two trench-shaped insulating oxide layers 103 through Pwell implantation and push junction processes, and a floating P region is respectively formed on the side of the two trench insulating oxide layers 120 facing away from the P-hydrazine region 108 109, the trench gate oxide layers 106 in the two second trenches 105 are respectively adjacent to the P hydrazine regions 108, referring to FIG. 11;
  • an N+ emitter layer 110 connected to the floating P region 109 and the floating P hydrazine region 108 is formed;
  • a P+ region 111 connected to the N+ emitter is formed in the P hydrazine region 108 through an ion implantation process
  • An insulating dielectric isolation layer 112 is deposited on the front side of the N-type substrate, and the insulating dielectric isolation layer 112 covers the N+ emitter layer 110, the trench-shaped insulating oxide layer 103, the polysilicon electrode 104, the trench-shaped gate oxide layer 106 and the polysilicon gate 107, the insulating dielectric isolation layer 112 has an opening 114 exposing the polysilicon electrode 104 and the P+ region 111;
  • metal is sputtered on the side of the insulating dielectric isolation layer 112 facing away from the back of the N-type substrate 115 to form an emitter metal layer 113 , and the emitter metal layer 113 fills the opening 114 ;
  • the backside of the N-type substrate 115 is thinned to form the N-type drift layer 101;
  • An N-type termination layer 116 is formed on the backside of the N-type drift layer 101 by ion implantation;
  • a P-type collector layer 117 is formed on the side of the N-type termination layer 116 facing away from the N-type drift layer 101;
  • a collector metal layer 118 is formed by sputtering metal on the side of the P-type collector facing away from the N-type drift layer 101 , see FIG. 15 .
  • first trenches 102 are formed in the N-type substrate 115 through photolithography and etching processes, a trench-shaped insulating oxide layer 103 is formed in the first trench 102, and a trench-shaped insulating oxide layer 103 is formed in the trench.
  • Deposition of polysilicon in the insulating oxide layer 103 to form the polysilicon electrode region 123 includes:
  • a first dielectric layer 119 is deposited on the front side of the N-type substrate, photolithography is performed, and the first dielectric layer 119 and the N-type substrate 115 are etched to form two spaced and located the first trench 102 in the N-type substrate;
  • the remaining first dielectric layer 119 is removed, an insulating oxide layer 120 is grown on the front surface of the N-type substrate 115 and in the first trench 102, and polysilicon is deposited;
  • the insulating oxide layer 120 and polysilicon on the front surface of the N-type substrate 115 are removed by chemical mechanical polishing, and a trench-shaped insulating oxide layer 103 and a trench-shaped insulating oxide layer 103 are formed in the first trench 102
  • the polysilicon electrode region 123 in the oxide layer 103 is formed in the first trench 102 .
  • a second trench 105 is formed in the first trench 102 through deposition, photolithography and etching processes, a trench-shaped gate oxide layer 106 is formed in the second trench 105, and a trench-shaped gate oxide layer is formed in the second trench 105
  • Deposition of polysilicon in 106 to form polysilicon gate 107 includes:
  • a second dielectric layer 121 is deposited on the front side of the N-type substrate, and photolithography, etching of the second dielectric layer 121, polysilicon electrode region 123 and trench-shaped insulating oxide layer 103 are performed to form the first dielectric layer 121 in the first trench 102 Two grooves 105;
  • the remaining second dielectric layer 121 is removed, a gate oxide layer 122 is grown on the front surface of the N-type substrate 115 and in the second trench 105 and polysilicon is deposited;
  • polysilicon is etched back to the top of the second trench 105 , and the gate oxide layer 122 located on the front surface of the N-type substrate 115 is removed, and a trench-shaped gate oxide layer 106 is formed in the second trench 105 . And a polysilicon gate 107 is formed in the trench gate oxide layer 106 .
  • the first trench is deeper than the second trench, the second trench is located in the first trench, and the second trench is the gate trench, so that the gate region and the N-type drift layer are located between the gate region and the N-type drift layer.
  • the IGBTs There is only a very small part of the contact between the IGBTs, so that the IGBT has a smaller Miller capacitance, thereby achieving the effect of improving the turn-on efficiency of the device and reducing the switching loss of the device.
  • the present disclosure has strong practicality.

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Abstract

一种半导体元胞结构、IGBT元胞结构、半导体结构及IGBT元胞结构的制备方法，半导体元胞结构包括依次层叠设置的N－型漂移层（101）、N型终止层（116）、P型集电极层（117）以及集电极金属层（118）；在N－型漂移层（101）背向P型集电极层（117）的一侧且在N－型漂移层（101）中，半导体元胞结构包括两个间隔设置的第一沟槽（102）、形成于第一沟槽内壁的沟槽形绝缘氧化层（103）、位于沟槽形绝缘氧化层内的多晶硅电极（104）、形成于第一沟槽内壁的第二沟槽（105）、位于第二沟槽内的沟槽形栅氧化层（106）、位于沟槽形栅氧化层内的多晶硅栅（107）、位于第一沟槽之间的P肼区（108）以及两个间隔设置的浮空P区（109），两个第二沟槽内的栅氧化层（105）与P肼区（108）相邻接。

Description

半导体元胞结构、IGBT元胞结构、半导体结构及其制备方法
本公开要求于2020年09月24日提交中国专利局，申请号为202011017235.3，申请名称为“IGBT元胞结构、半导体结构及IGBT元胞结构的制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开一般涉及半导体制造领域，具体涉及一种半导体元胞结构、IGBT元胞结构、半导体结构及IGBT元胞结构的制备方法。
背景技术
新型半导体功率器件，如新型半导体功率器件为IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极性晶体管)，IGBT具有导通损耗低、输入阻抗高、驱动电路简单、驱动功率小、开启速度快等优点。为了获得更大功率、更高效率的电力控制系统，IGBT一直沿着低导通损耗、低开关损耗的方向在发展。
IGBT经过近四十年的发展，在纵向结构上，IGBT经历了PT—NPT—FS的发展；在表面结构上，IGBT从平面栅发展成沟槽栅结构，极大的降低了IGBT的导通损耗和开关损耗。
浮空P区域的引入极大的降低了Trench(沟槽)IGBT的导通压降，提高了载流子存储效应，在常规TrenchIGBT的基础上极大的改善了器件正向导通压降Vce和关断时间t off之间的矛盾关系。
不过现有浮空P型TrenchIGBT中形成米勒电容的栅极与集电极的接触面占沟槽的大部分面积，而且介质层仅仅为薄薄的栅极氧化层，厚度及其薄，因此现有浮空P型TrenchIGBT的米勒电容很大。在器件开关过程中，在米勒电容的作用下，栅极电流除了栅极驱动的电流 外还增加了位移电流，较大的米勒电容会导致器件栅极中的位移电流很大，栅极电压将受的影响。在器件开通过程中，较大的米勒电容会导致配套使用的续流二极管的反向恢复时将会有较大的电压变化率dv/dt、较高的电流峰值和电磁兼容(EMC)等问题。另外，较大的米勒电容也将会增加器件的开通时间和关断时间，从而器件将会得到较大的开通和关断损耗。
发明内容
鉴于现有技术中的上述缺陷或不足，期望提供一种半导体元胞结构、IGBT元胞结构、半导体结构及IGBT元胞结构的制备方法。
第一方面，本公开实施例提供一种IGBT元胞结构，其特征在于，包括依次层叠设置的N－型漂移层、N型终止层、P型集电极层以及集电极金属层；
在所述N－型漂移层背向所述P型集电极层的一侧且在所述N－型漂移层中，所述IGBT元胞结构包括：两个间隔设置的第一沟槽、形成于所述第一沟槽内壁的沟槽形绝缘氧化层、位于所述沟槽形绝缘氧化层内的多晶硅电极、位于所述第一沟槽内的第二沟槽、位于所述第二沟槽内的沟槽形栅氧化层、位于所述沟槽形栅氧化层内的多晶硅栅、位于所述第一沟槽之间的P肼区以及两个间隔设置的浮空P区；其中，
所述第一沟槽内的所述沟槽形绝缘氧化层和所述多晶硅栅极均与位于该第一沟槽内的所述第二沟槽邻接，所述浮空P区的深度不超过所述第一沟槽的深度，所述浮空P区通过所述沟槽形绝缘氧化层与所述P肼区隔开，所述沟槽形栅氧化层通过所述多晶硅电极与所述沟槽形绝缘氧化层隔开，两个所述沟槽形绝缘氧化层内的栅氧化层分别与所述P肼区相邻接。
优选的，在所述N－型漂移层中，所述IGBT元胞结构还包括：N+发射极层，所述N+发射极层形成于所述浮空P区和所述P肼区背向所述P型集电极层的一侧，所述P肼区内设有与所述N+发射极层连接的P+区；
在所述N－漂移层背向所述P型集电极层的一侧，所述IGBT元胞 结构还包括：自靠近所述P型集电极层至远离所述P型集电极层的方向上顺次设置的绝缘介质隔离层和发射极金属层，所述绝缘介质隔离层覆盖所述N+发射极层、所述沟槽形绝缘氧化层、所述多晶硅电极、所述沟槽形栅氧化层和所述多晶硅栅，所述绝缘介质隔离层具有露出所述多晶硅电极和所述P+区的开口，所述发射极金属层覆盖所述绝缘介质隔离层并填充所述开口。
优选的，所述第一沟槽的深度为4um－8um，所述第二沟槽的深度为2um－5um。
优选的，所述第二沟槽的宽度比所述第一沟槽的宽度小0.6um－1.0um，所述第一沟槽的宽度为1.4um－2.2um，所述第二沟槽的宽度为0.8um－1.2um。
优选的，掺杂浓度满足下列条件至少之一：
所述P肼区的掺杂浓度为1x10 16cm －3－1x10 19cm －3；
所述P+区的掺杂浓度为1x10 19cm －3－1x10 22cm －3；
所述N+发射极层的掺杂浓度为1x10 19cm －3－1x10 23cm －3。
第二方面，本公开提供一种半导体结构，包括多个并联的如上所述的IGBT元胞结构，所述IGBT元胞结构的浮空P区的深度与所述第一沟槽的深度相同，相邻两个所述IGBT元胞结构的浮空P区相连形成浮空P区域。
第三方面，本公开提供一种半导体结构，包括多个并联的如上所述的IGBT元胞结构；
在相邻两个所述IGBT元胞结构之间，所述N－型漂移层内还设有至少一个中间沟槽，所述中间沟槽内设有沟槽绝缘氧化层，所述沟槽绝缘氧化层内设有中间多晶硅层，所述中间沟槽与所述第一沟槽同层形成，所述沟槽绝缘氧化层与所述沟槽形绝缘氧化层同层形成，所述中间多晶硅层与所述多晶硅电极同层形成。
优选的，在相邻两个所述IGBT元胞结构之间，所述N－型漂移层内还设有至少两个所述中间沟槽，两个所述中间沟槽之间设有中间P浮空区，所述中间P浮空区与所述浮空P区同层形成。
第四方面，本公开还提供一种IGBT元胞结构的制备方法，包括：
提供N－型衬底，所述N－型衬底具有相对的正面和背面；
通过沉积、光刻和刻蚀工艺在所述N－型衬底内形成两个间隔设置的第一沟槽，在所述第一沟槽内形成沟槽形绝缘氧化层，并在所述沟槽形绝缘氧化层内沉积多晶硅形成多晶硅电极区，所述沟槽形绝缘氧化层的开口朝向所述正面；
通过沉积、光刻和刻蚀工艺在所述第一沟槽内形成第二沟槽，在所述第二沟槽内形成沟槽形栅氧化层，并形成介于所述第二沟槽和所述沟槽形绝缘氧化层之间的多晶硅电极；
在所述沟槽形栅氧化层内沉积多晶硅形成多晶硅栅；
通过Pwell注入及推结工艺在两个所述沟槽形绝缘氧化层之间形成P肼区，且在两个所述沟槽绝缘氧化层背向所述P肼区的一侧分别形成浮空P区，两个所述沟槽形绝缘氧化层内的沟槽形栅氧化层分别与所述P肼区相邻接。
优选的，在形成所述浮空P区之后，所述制备方法还包括：
形成与所述浮空P区和所述浮空P肼区相连的N+发射极层；
通过离子注入工艺在所述P肼区内形成与所述N+发射极相连的P+区；
在所述N－型衬底的正面沉积形成绝缘介质隔离层，所述绝缘介质隔离层覆盖所述N+发射极层、所述沟槽形绝缘氧化层、所述多晶硅电极、所述沟槽形栅氧化层和所述多晶硅栅，所述绝缘介质隔离层具有露出所述多晶硅电极和所述P+区的开口；
在所述绝缘介质隔离层背向所述N－型衬底背面的一侧溅射金属形成发射极金属层，所述发射极金属层填充所述开口；
对N－型衬底的背面进行减薄处理形成N－漂移层；
在所述N－漂移层的背面采用离子注入方式形成N型终止层；
在N型终止层背向所述N－漂移层的一侧形成P型集电极层；
在所述P型集电极背向所述N－漂移层的一侧溅射金属形成集电极金属层。
优选的，所述通过光刻和刻蚀工艺在所述N－型衬底内形成两个间隔设置的第一沟槽，在所述第一沟槽内形成沟槽形绝缘氧化层，并在 所述沟槽形绝缘氧化层内沉积多晶硅形成多晶硅电极区包括：
在所述N－型衬底的正面沉积第一介质层，进行光刻、刻蚀所述第一介质层和所述N－型衬底，形成两个间隔的且位于所述N－型衬底内的第一沟槽；
去除剩余的第一介质层，在所述N－型衬底正面以及所述第一沟槽内生长一层绝缘氧化层并沉积多晶硅；
通过化学机械研磨的方式去除位于所述N－型衬底正面的绝缘氧化层以及多晶硅，在所述第一沟槽内形成沟槽形绝缘氧化层以及位于所述沟槽形绝缘氧化层内的多晶硅电极区。
优选的，所述通过沉积、光刻和刻蚀工艺在所述第一沟槽内形成第二沟槽，在所述第二沟槽内形成沟槽形栅氧化层，以及所述在所述沟槽形栅氧化层内沉积多晶硅形成多晶硅栅包括：
在所述N－型衬底的正面沉积第二介质层，进行光刻、刻蚀所述第二介质层、所述多晶硅电极区以及所述沟槽形绝缘氧化层，形成位于所述第一沟槽内的第二沟槽；
去除剩余的第二介质层，在所述N－型衬底正面以及所述第二沟槽内生长一层栅氧化层并沉积多晶硅；
将多晶硅回刻至所述第二沟槽顶部，并去除位于所述N－型衬底正面的栅氧化层，在所述第二沟槽内形成沟槽形栅氧化层，并在所述沟槽形栅氧化层内形成多晶硅栅。
第五方面，本公开还提供一种半导体元胞结构，所述半导体元胞结构包括依次层叠设置的N－型漂移层、N型终止层、P型集电极层以及集电极金属层；
在所述N－型漂移层背向所述P型集电极层的一侧且在所述N－型漂移层中，所述半导体元胞结构包括：两个间隔设置的第一沟槽、形成于所述第一沟槽内壁的沟槽形绝缘氧化层、位于所述沟槽形绝缘氧化层内的多晶硅电极、形成于所述第一沟槽内壁的第二沟槽、位于所述第二沟槽内的沟槽形栅氧化层、位于所述沟槽形栅氧化层内的多晶硅栅、位于所述第一沟槽之间的P肼区以及两个间隔设置的浮空P区；其中，
所述第一沟槽内的所述沟槽形绝缘氧化层和所述多晶硅栅极均与位于该第一沟槽内的所述第二沟槽邻接，所述沟槽形栅氧化层通过所述多晶硅电极与所述沟槽形绝缘氧化层隔开，所述浮空P区的深度不超过所述第一沟槽的深度，所述浮空P区通过所述沟槽形绝缘氧化层与所述P肼区隔开，两个所述第二沟槽内的栅氧化层分别与所述P肼区相邻接。
与现有技术相比，本公开提供的半导体元胞结构中，第一沟槽为dummy trench(即赝沟槽)，第二沟槽为栅极沟槽，两个第二沟槽分别与P肼区邻接，由于第二沟槽的绝大部分落在第一沟槽内，第二沟槽仅有很小的一部分与N－型漂移层毗邻形成米勒电容，使得半导体元胞结构具有很小的米勒电容，从而达到提高器件开通效率以及降低器件的开关损耗的效果。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本公开的其它特征、目的和优点将会变得更明显：
图1为本公开实施例提供的半导体元胞结构的结构示意图；
图2为本公开实施例提供的一种半导体结构的结构示意图；
图3为本公开实施例提供的另一种半导体结构的结构示意图；
图4至图15为本公开实施例提供的半导体元胞结构的制备方法的一系列制程对应的结构示意图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释相关发明，而非对该发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与发明相关的部分。
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本公开。
本公开的实施例提供一种半导体元胞结构，半导体元胞结构包括 依次层叠设置的N－型漂移层、N型终止层、P型集电极层以及集电极金属层；
在N－型漂移层背向P型集电极层的一侧且在N－型漂移层中，半导体元胞结构包括：两个间隔设置的第一沟槽、形成于第一沟槽内壁的沟槽形绝缘氧化层、位于沟槽形绝缘氧化层内的多晶硅电极、形成于第一沟槽内壁的第二沟槽、位于第二沟槽内的沟槽形栅氧化层、位于沟槽形栅氧化层内的多晶硅栅、位于第一沟槽之间的P肼区以及两个间隔设置的浮空P区；其中，
第一沟槽内的沟槽形绝缘氧化层和多晶硅栅极均与位于该第一沟槽内的第二沟槽邻接，沟槽形栅氧化层通过多晶硅电极与沟槽形绝缘氧化层隔开，浮空P区的深度不超过第一沟槽的深度，浮空P区通过沟槽形绝缘氧化层与P肼区隔开，两个第二沟槽内的栅氧化层分别与P肼区相邻接。
在本公开的实施例中，半导体元胞结构可以为IGBT型半导体元胞结构，也可以为MOS(Metal Oxide Semiconductor)型半导体元胞结构。MOS与IGBT的主要区别为衬底的背面，IGBT的衬底的背面较MOS的衬底的背面多一层P－型衬底。IGBT与MOS的衬底的正面结构一致。
可以理解的是，本公开的实施例中的半导体元胞结构可以为IGBT，也可以为MOS。下面，以半导体元胞结构为IGBT为例进行说明。
目前，现有的半导体元胞结构，例如，IGBT元胞结构，IGBT在在工作过程中，由于米勒电容的影响，降低器件的开关速度，增加开关损耗，严重影响IGBT的工作性能。基于此，本公开提供一种半导体元胞结构、IGBT元胞结构、半导体结构及IGBT元胞结构的制备方法。
如图1所示，本公开的实施例提供一种IGBT元胞结构，包括依次层叠设置的N－型漂移层101、N型终止层116、P型集电极层117以及集电极金属层118；
在N－型漂移层101背向P型集电极层117的一侧且在N－型漂移层101中，IGBT元胞结构包括：两个间隔设置的第一沟槽102、形成于第一沟槽102内壁的沟槽形绝缘氧化层103、位于沟槽形绝缘氧化层103内的多晶硅电极104、位于第一沟槽102内的第二沟槽105、形成 于第二沟槽105内壁的沟槽形栅氧化层106、位于沟槽形栅氧化层106内的多晶硅栅107、位于第一沟槽102之间的P肼区108、两个间隔设置的浮空P区109以及N+发射极层110，N+发射极层110形成于浮空P区109和P肼区108背向P型集电极层117的一侧，P肼区108内设有与N+发射极层110连接的P+区111；
在N－型漂移层101背向P型集电极层117的一侧，IGBT元胞结构还包括：自靠近P型集电极层117至远离P型集电极层117的方向上顺次设置的绝缘介质隔离层112和发射极金属层113，绝缘介质隔离层112覆盖N+发射极层110、沟槽形绝缘氧化层103、多晶硅电极104、沟槽形栅氧化层106和多晶硅栅107，绝缘介质隔离层112具有露出多晶硅电极104和P+区111的开口114，发射极金属层113覆盖绝缘介质隔离层112并填充开口114；其中，
第一沟槽内的沟槽形绝缘氧化层103和多晶硅电极104均与位于该第一沟槽内的第二沟槽邻接，沟槽形栅氧化层106通过多晶硅电极104与沟槽形绝缘氧化层103隔开，浮空P区109的深度不超过第一沟槽102的深度，浮空P区109通过沟槽形绝缘氧化层103与P肼区108隔开，两个第二沟槽105内的栅氧化层106分别与P肼区108相邻接。
该实施例提供的IGBT元胞结构中，第一沟槽为dummytrench(赝沟槽)，第二沟槽为栅极沟槽，P肼区位于两个第二沟槽之间(即两个栅极沟槽之间)，由于第二沟槽位于第一沟槽内，第二沟槽仅有很小的一部分与N－型漂移层毗邻以形成米勒电容，如第二沟槽与N－型漂移层接触部位的长度为200nm，甚至可以是100nm，使得IGBT元胞结构具有很小的米勒电容，从而达到提高器件的开通效率以及降低器件的开关损耗。
IGBT的集电极与发射极之间等效存在有集电极－发射极电容，即为电容Cce；在发射极与栅极之间等效存在有栅极－发射极电容，即为电容Cge；集电极与栅极之间等效存在有门极－集电极电容，即为电容Cgc，电容Cgc又被称为米勒电容。IGBT的输入电容Cies＝Cge+Cgc。该实施例中多晶硅电极为多晶硅发射极，第二沟槽内部的区域为栅极 区域，第二沟槽四周基本与发射极毗邻，因此该实施例提供的IGBT元胞结构具有一个较大的输入电容，能够进一步降低了因为反馈电容导致的位移电流对栅极电压的影响，器件栅极电压不容易受电流变化的影响。
半导体材料为多晶硅、单晶硅、碳化硅、氮化镓或氧化锌等。
进一步地，第一沟槽102的深度为4um－8um，第二沟槽105的深度为2um－5um。第一沟槽较第二沟槽深一些，一方面各个第一沟槽形成有第二沟槽，两个第二沟槽分别与P肼区相邻接，第二沟槽落在第一沟槽内，确保栅极区域与N－漂移区之间仅有很小的一部分接触，使得器件具有较小的米勒电容；另一方面，通过第一沟槽与N－漂移区接触，利用较深的第一沟槽，在第一沟槽的外侧形成浮空P区，第一沟槽和浮空P区能够降低沟槽底部电场，提高器件的反向耐压能力，在器件导通过程中，第一沟槽与浮空P区能够使得器件表面储存大量的少数载流子，降低器件的导通压降。
进一步地，第二沟槽105的宽度比第一沟槽102的宽度小0.6um－1.0um，第一沟槽102的宽度为1.4um－2.2um，第二沟槽105的宽度为0.8um－1.2um，确保第一沟槽能够包围第二沟槽。
进一步地，P肼区108的掺杂浓度为1x10 16cm －3－1x10 19cm －3；和/或，
P+区111的掺杂浓度为1x10 19cm －3－1x10 22cm －3；和/或，
N+发射极层110的掺杂浓度为1x10 19cm －3－1x10 23cm －3。
具体地，掺杂浓度满足下列条件至少之一：
P肼区的掺杂浓度为1x10 16cm －3－1x10 19cm －3；
P+区的掺杂浓度为1x10 19cm －3－1x10 22cm －3；
N+发射极层的掺杂浓度为1x10 19cm －3－1x10 23cm －3。
如图2所示，本公开的实施例提供一种半导体结构，包括多个并联的图1所示的IGBT元胞结构，IGBT元胞结构的浮空P区的深度与第一沟槽102的深度相仿，相邻两个IGBT元胞结构的浮空P区109相连形成浮空P区域201。
该实施例提供的半导体结构中浮空P区域201与第一沟槽的深度 相同或接近。在器件处于反向阻断状态时，浮空P区域能够承受主要的电场，使得电场不会集中于第一沟槽底部，提高了器件的耐压能力，器件在应用中更加不易发生过压损坏。
如图3所示，本公开的实施例提供另一种半导体结构，包括多个并联的图1所示的IGBT元胞结构；
在相邻两个IGBT元胞结构之间，N－型漂移层101内还设有至少一个中间沟槽301，中间沟槽301内设有沟槽绝缘氧化层302，沟槽绝缘氧化层302内设有中间多晶硅层303，中间沟槽301与第一沟槽103同层形成，沟槽绝缘氧化层302与沟槽形绝缘氧化层106同层形成，中间多晶硅层303与多晶硅电极104同层形成，绝缘介质隔离层112还覆盖中间沟槽301、沟槽绝缘氧化层302和中间多晶硅层303，绝缘介质隔离层112还具有露出中间多晶硅层303的开孔304，N+发射极金属层113还填充开孔304。
进一步地，在相邻两个IGBT元胞结构之间，N－型漂移层101内还设有至少两个中间沟槽301，两个中间沟槽301之间设有中间P浮空区，中间P浮空区与浮空P区109同层形成；N+发射极层110还与中间P浮空区相连。
在图3示意的半导体结构中，在相邻IGBT元胞结构之间设置至少一个沟槽部，该沟槽部的深度和宽度与第一沟槽一致，在生产过程中该沟槽部与第一沟槽同时实现，不会增加工艺的复杂性。在器件处于反向阻断状态，高密度的深沟槽能够降低沟槽底部电场，提高器件的反向耐压能力，在器件导通过程中，深沟槽与浮空P区能够达到一致的效果，能够使得器件表面储存大量的少数载流子，降低器件的导通压降。在开关过程中，沟槽部内的中间多晶硅电极和第一沟槽内的多晶硅电极均与发射极金属层连接，增加了一个较大的集电极－发射极电容，该电容能够在一定程度上吸收器件开关工作中产生的噪声。
基于上述IGBT元胞结构，相应地，本公开提供了该种IGBT元胞结构的制备方法。
结合图4至图15对IGBT元胞结构的制备方法的具体实施方式进行详细说明。
本公开实施例提供的IGBT元胞结构的制备方法，包括：
提供N－型衬底115，N－型衬底115具有相对的正面和背面；
通过沉积、光刻和刻蚀工艺在N－型衬底115内形成两个间隔设置的第一沟槽102，在第一沟槽102内形成沟槽形绝缘氧化层103，并在沟槽形绝缘氧化层103内沉积多晶硅形成多晶硅电极区123，沟槽形绝缘氧化层103的开口朝向正面，参照图7；
通过沉积、光刻和刻蚀工艺在第一沟槽102内形成第二沟槽105，在第二沟槽105内形成沟槽形栅氧化层106，并形成介于第二沟槽105和沟槽形绝缘氧化层103之间的多晶硅电极104；
在沟槽形栅氧化层106内沉积多晶硅形成多晶硅栅107；
通过Pwell注入及推结工艺在两个沟槽形绝缘氧化层103之间形成P肼区108，且在两个沟槽绝缘氧化层120背向P肼区108的一侧分别形成浮空P区109，两个第二沟槽105内的沟槽形栅氧化层106分别与P肼区108相邻接，参照图11；
如图12所示，形成与浮空P区109和浮空P肼区108相连的N+发射极层110；
参照图12和图13，通过离子注入工艺在P肼区108内形成与N+发射极相连的P+区111；
在N－型衬底的正面沉积形成绝缘介质隔离层112，绝缘介质隔离层112覆盖N+发射极层110、沟槽形绝缘氧化层103、多晶硅电极104、沟槽形栅氧化层106和多晶硅栅107，绝缘介质隔离层112具有露出多晶硅电极104和P+区111的开口114；
参照图14，在绝缘介质隔离层112背向N－型衬底115背面的一侧溅射金属形成发射极金属层113，发射极金属层113填充开口114；
对N－型衬底115的背面进行减薄处理形成N－型漂移层101；
在N－型漂移层101的背面采用离子注入方式形成N型终止层116；
在N型终止层116背向N－型漂移层101的一侧形成P型集电极层117；
在P型集电极背向N－型漂移层101的一侧溅射金属形成集电极金属层118，参照图15。
进一步地，通过光刻和刻蚀工艺在N－型衬底115内形成两个间隔设置的第一沟槽102，在第一沟槽102内形成沟槽形绝缘氧化层103，并在沟槽形绝缘氧化层103内沉积多晶硅形成多晶硅电极区123包括：
如图4和图5所示，在N－型衬底的正面沉积第一介质层119，进行光刻、刻蚀第一介质层119和N－型衬底115，形成两个间隔的且位于N－型衬底内的第一沟槽102；
如图6所示，去除剩余的第一介质层119，在N－型衬底115正面以及第一沟槽102内生长一层绝缘氧化层120并沉积多晶硅；
如图7所示，通过化学机械研磨的方式去除位于N－型衬底115正面的绝缘氧化层120以及多晶硅，在第一沟槽102内形成沟槽形绝缘氧化层103以及位于沟槽形绝缘氧化层103内的多晶硅电极区123。
进一步地，通过沉积、光刻和刻蚀工艺在第一沟槽102内形成第二沟槽105，在第二沟槽105内形成沟槽形栅氧化层106，以及在沟槽形栅氧化层106内沉积多晶硅形成多晶硅栅107包括：
在N－型衬底的正面沉积第二介质层121，进行光刻、刻蚀第二介质层121、多晶硅电极区123以及沟槽形绝缘氧化层103，形成位于第一沟槽102内的第二沟槽105；
如图8至图10所示，去除剩余的第二介质层121，在N－型衬底115正面以及第二沟槽105内生长一层栅氧化层122并沉积多晶硅；
如图11所示，将多晶硅回刻至第二沟槽105顶部，并去除位于N－型衬底115正面的栅氧化层122，在第二沟槽105内形成沟槽形栅氧化层106，并在沟槽形栅氧化层106内形成多晶硅栅107。
该制备方法中，第一沟槽较第二沟槽深一些，第二沟槽落在第一沟槽内，第二沟槽为栅极沟槽，使得栅极区域与N－型漂移层之间的仅有极小的一部分接触，使得IGBT具有较小的米勒电容，从而达到提高器件开通效率以及降低器件的开关损耗的效果。
以上描述仅为本公开的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本公开中所涉及的发明范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离发明构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的 其它技术方案。例如上述特征与本公开中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。
工业实用性
通过本公开实施例，可获得具有优异性能的半导体元胞结构，该半导体元胞结构和由该方法获得的半导体元胞结构具有很小的米勒电容，从而达到提高器件开通效率以及降低器件的开关损耗的效果。因此本公开具有很强的实用性。

Claims (13)

  1. 一种IGBT元胞结构，其特征在于，包括依次层叠设置的N－型漂移层、N型终止层、P型集电极层以及集电极金属层；
    在所述N－型漂移层背向所述P型集电极层的一侧且在所述N－型漂移层中，所述IGBT元胞结构包括：两个间隔设置的第一沟槽、形成于所述第一沟槽内壁的沟槽形绝缘氧化层、位于所述沟槽形绝缘氧化层内的多晶硅电极、形成于所述第一沟槽内壁的第二沟槽、位于所述第二沟槽内的沟槽形栅氧化层、位于所述沟槽形栅氧化层内的多晶硅栅、位于所述第一沟槽之间的P肼区以及两个间隔设置的浮空P区；其中，
    所述第一沟槽内的所述沟槽形绝缘氧化层和所述多晶硅栅极均与位于该第一沟槽内的所述第二沟槽邻接，所述沟槽形栅氧化层通过所述多晶硅电极与所述沟槽形绝缘氧化层隔开，所述浮空P区的深度不超过所述第一沟槽的深度，所述浮空P区通过所述沟槽形绝缘氧化层与所述P肼区隔开，两个所述第二沟槽内的栅氧化层分别与所述P肼区相邻接。
  2. 根据权利要求1所述的IGBT元胞结构，其特征在于，在所述N－型漂移层中，所述IGBT元胞结构还包括：N+发射极层，所述N+发射极层形成于所述浮空P区和所述P肼区背向所述P型集电极层的一侧，所述P肼区内设有与所述N+发射极层连接的P+区；
    在所述N－漂移层背向所述P型集电极层的一侧，所述IGBT元胞结构还包括：自靠近所述P型集电极层至远离所述P型集电极层的方向上顺次设置的绝缘介质隔离层和发射极金属层，所述绝缘介质隔离层覆盖所述N+发射极层、所述沟槽形绝缘氧化层、所述多晶硅电极、所述沟槽形栅氧化层和所述多晶硅栅，所述绝缘介质隔离层具有露出所述多晶硅电极和所述P+区的开口，所述发射极金属层覆盖所述绝缘介质隔离层并填充所述开口。
  3. 根据权利要求1所述的IGBT元胞结构，其特征在于，所述第一沟槽的深度为4um－8um，所述第二沟槽的深度为2um－5um。
  4. 根据权利要求1所述的IGBT元胞结构，其特征在于，所述第二沟槽的宽度比所述第一沟槽的宽度小0.6um－1.0um，所述第一沟槽的宽度为1.4um－2.2um，所述第二沟槽的宽度为0.8um－1.2um。
  5. 根据权利要求1所述的IGBT元胞结构，其特征在于，掺杂浓度满足下列条件至少之一：
    所述P肼区的掺杂浓度为1x10 16cm －3－1x10 19cm －3；
    所述P+区的掺杂浓度为1x10 19cm －3－1x10 22cm －3；
    所述N+发射极层的掺杂浓度为1x10 19cm －3－1x10 23cm －3。
  6. 一种半导体结构，其特征在于，包括多个并联的如权利要求1－5任一项所述的IGBT元胞结构，所述IGBT元胞结构的浮空P区的深度与所述第一沟槽的深度相同，相邻两个所述IGBT元胞结构的浮空P区相连形成浮空P区域。
  7. 一种半导体结构，其特征在于，包括多个并联的如权利要求1－5任一项所述的IGBT元胞结构；
    在相邻两个所述IGBT元胞结构之间，所述N－型漂移层内还设有至少一个中间沟槽，所述中间沟槽内设有沟槽绝缘氧化层，所述沟槽绝缘氧化层内设有中间多晶硅层，所述中间沟槽与所述第一沟槽同层形成，所述沟槽绝缘氧化层与所述沟槽形绝缘氧化层同层形成，所述中间多晶硅层与所述多晶硅电极同层形成。
  8. 根据权利要求7所述的半导体结构，其特征在于，在相邻两个所述IGBT元胞结构之间，所述N－型漂移层内还设有至少两个所述中间沟槽，两个所述中间沟槽之间设有中间P浮空区，所述中间P浮空区与所述浮空P区同层形成。
  9. 一种IGBT元胞结构的制备方法，其特征在于，包括：
    提供N－型衬底，所述N－型衬底具有相对的正面和背面；
    通过沉积、光刻和刻蚀工艺在所述N－型衬底内形成两个间隔设置的第一沟槽，在所述第一沟槽内形成沟槽形绝缘氧化层，并在所述沟槽形绝缘氧化层内沉积多晶硅形成多晶硅电极区，所述沟槽形绝缘氧化层的开口朝向所述正面；
    通过沉积、光刻和刻蚀工艺在所述第一沟槽内形成第二沟槽，在所述第二沟槽内形成沟槽形栅氧化层，并形成介于所述第二沟槽和所述沟槽形绝缘氧化层之间的多晶硅电极；
    在所述沟槽形栅氧化层内沉积多晶硅形成多晶硅栅；
    通过Pwell注入及推结工艺在两个所述沟槽形绝缘氧化层之间形成P肼区，且在两个所述沟槽绝缘氧化层背向所述P肼区的一侧分别形成浮空P区，两个所述第二沟槽内的沟槽形栅氧化层分别与所述P肼区相邻接。
  10. 根据权利要求9所述的IGBT元胞结构的制备方法，其特征在于，在形成所述浮空P区之后，所述制备方法还包括：
    形成与所述浮空P区和所述浮空P肼区相连的N+发射极层；
    通过离子注入工艺在所述P肼区内形成与所述N+发射极相连的P+区；
    在所述N－型衬底的正面沉积形成绝缘介质隔离层，所述绝缘介质隔离层覆盖所述N+发射极层、所述沟槽形绝缘氧化层、所述多晶硅电极、所述沟槽形栅氧化层和所述多晶硅栅，所述绝缘介质隔离层具有露出所述多晶硅电极和所述P+区的开口；
    在所述绝缘介质隔离层背向所述N－型衬底背面的一侧溅射金属形成发射极金属层，所述发射极金属层填充所述开口；
    对N－型衬底的背面进行减薄处理形成N－漂移层；
    在所述N－漂移层的背面采用离子注入方式形成N型终止层；
    在N型终止层背向所述N－漂移层的一侧形成P型集电极层；
    在所述P型集电极背向所述N－漂移层的一侧溅射金属形成集电极金属层。
  11. 根据权利要求9所述的IGBT元胞结构的制备方法，其特征在于，所述通过光刻和刻蚀工艺在所述N－型衬底内形成两个间隔设置的第一沟槽， 在所述第一沟槽内形成沟槽形绝缘氧化层，并在所述沟槽形绝缘氧化层内沉积多晶硅形成多晶硅电极区包括：
    在所述N－型衬底的正面沉积第一介质层，进行光刻、刻蚀所述第一介质层和所述N－型衬底，形成两个间隔的且位于所述N－型衬底内的第一沟槽；
    去除剩余的第一介质层，在所述N－型衬底正面以及所述第一沟槽内生长一层绝缘氧化层并沉积多晶硅；
    通过化学机械研磨的方式去除位于所述N－型衬底正面的绝缘氧化层以及多晶硅，在所述第一沟槽内形成沟槽形绝缘氧化层以及位于所述沟槽形绝缘氧化层内的多晶硅电极区。
  12. 根据权利要求9所述的IGBT元胞结构的制备方法，其特征在于，所述通过沉积、光刻和刻蚀工艺在所述第一沟槽内形成第二沟槽，在所述第二沟槽内形成沟槽形栅氧化层，以及所述在所述沟槽形栅氧化层内沉积多晶硅形成多晶硅栅包括：
    在所述N－型衬底的正面沉积第二介质层，进行光刻、刻蚀所述第二介质层、所述多晶硅电极区以及所述沟槽形绝缘氧化层，形成位于所述第一沟槽内的第二沟槽；
    去除剩余的第二介质层，在所述N－型衬底正面以及所述第二沟槽内生长一层栅氧化层并沉积多晶硅；
    将多晶硅回刻至所述第二沟槽顶部，并去除位于所述N－型衬底正面的栅氧化层，在所述第二沟槽内形成沟槽形栅氧化层，并在所述沟槽形栅氧化层内形成多晶硅栅。
  13. 一种半导体元胞结构，其特征在于，包括依次层叠设置的N－型漂移层、N型终止层、P型集电极层以及集电极金属层；
    在所述N－型漂移层背向所述P型集电极层的一侧且在所述N－型漂移层中，所述半导体元胞结构包括：两个间隔设置的第一沟槽、形成于所述第一沟槽内壁的沟槽形绝缘氧化层、位于所述沟槽形绝缘氧化层内的多晶硅电极、形成于所述第一沟槽内壁的第二沟槽、位于所述第二沟槽内的沟槽形栅氧化层、位于所述沟槽形栅氧化层内的多晶硅栅、位于所述第一沟槽之间的P肼区以及两个间隔设置的浮空P区；其中，
    所述第一沟槽内的所述沟槽形绝缘氧化层和所述多晶硅栅极均与位于该第一沟槽内的所述第二沟槽邻接，所述沟槽形栅氧化层通过所述多晶硅电极与所述沟槽形绝缘氧化层隔开，所述浮空P区的深度不超过所述第一沟槽的深度，所述浮空P区通过所述沟槽形绝缘氧化层与所述P肼区隔开，两个所述第二沟槽内的栅氧化层分别与所述P肼区相邻接。
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CN114664929A (zh) * 2022-04-21 2022-06-24 电子科技大学 一种集成异质结二极管的分离栅SiC MOSFET及其制作方法
CN114784108A (zh) * 2022-04-21 2022-07-22 电子科技大学 一种集成结势垒肖特基二极管的平面栅SiC MOSFET及其制作方法
CN115425075A (zh) * 2022-08-24 2022-12-02 中国科学院微电子研究所 一种平面栅igbt器件及其制备方法

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