WO2022047918A1 - 一种传感器组件、传感器组件制程方法及显示面板 - Google Patents

一种传感器组件、传感器组件制程方法及显示面板 Download PDF

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Publication number
WO2022047918A1
WO2022047918A1 PCT/CN2020/122923 CN2020122923W WO2022047918A1 WO 2022047918 A1 WO2022047918 A1 WO 2022047918A1 CN 2020122923 W CN2020122923 W CN 2020122923W WO 2022047918 A1 WO2022047918 A1 WO 2022047918A1
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layer
gate
source
drain electrode
semiconductor layer
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PCT/CN2020/122923
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English (en)
French (fr)
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李金明
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/252,274 priority Critical patent/US12094890B2/en
Publication of WO2022047918A1 publication Critical patent/WO2022047918A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to the field of display technology, and in particular to a sensor component, a method for manufacturing the sensor component, and a display panel.
  • the photosensitive performance of the top-gate TFT sensor in the off-state current (Ioff) segment is significantly better than that of the conventional back-channel etching (BCE, Back Channel Etch) thin film transistor photosensitive sensor, which is mainly due to the improvement of the active layer illuminated area.
  • BCE Back Channel Etch
  • the sensor with bottom lighting has certain limitations when it is integrated with the display panel (Display), and can only be integrated in the liquid crystal display (LCD, Liquid Crystal Display) color filter (CF, color filter) substrate or integrated in the cover plate of the active display, not only increases the thickness of the module, but also increases the cost of development.
  • the invention provides a sensor component, a method for manufacturing the sensor component and a display panel.
  • the sensor component integrates a photosensitive PN junction and a bottom gate structure thin film transistor. When the sensor assembly is applied to a photosensitive display panel, it can avoid increasing the thickness of the display panel and reduce the development cost.
  • the present invention provides a sensor assembly, comprising:
  • the base plate includes a first surface and a second surface arranged oppositely;
  • the gate layer partially covers the first surface, the gate layer includes a first part and a second part, the first part includes a connection part and two or more sub-gate layers, the sub-gate There is a gap between the pole layers, and one end of the sub-gate layer is connected through the connection part;
  • the first semiconductor layer is disposed on a side of the first portion away from the first surface and embedded in the gap;
  • first source-drain electrode layer is disposed on the side of the first semiconductor layer away from the gate layer; wherein, the first part, the first semiconductor layer and the first A source-drain electrode layer forms a photosensitive PN junction;
  • a thin film transistor the thin film transistor is disposed on the first surface adjacent to the photosensitive PN junction, and the second part is the gate of the thin film transistor.
  • the first source-drain electrode layer includes a first P-type material layer and a first electrode material layer, the first P-type material layer is disposed on a side close to the first semiconductor layer, so The first electrode material layer is arranged on the side away from the first semiconductor layer; wherein, the material used in the first P-type material layer is molybdenum oxide compound, tin oxide compound or a combination of the above materials, the first P-type material layer is The material used for the electrode material layer is metal or metal oxide.
  • the thickness of the first source-drain electrode layer is 300 ⁇ to 800 ⁇ .
  • the first source-drain electrode layer is disposed in the orthographic projection region of the first semiconductor layer on the first surface, and the coverage area of the first source-drain electrode layer is smaller than that of the first semiconductor layer. A coverage area of a semiconductor layer.
  • the material used for the gate layer is metal or metal alloy, and the thickness of the gate layer is 3000 ⁇ to 8000 ⁇ .
  • the material used for the first semiconductor layer is a transparent metal oxide, and the thickness of the first semiconductor layer is 300 ⁇ to 800 ⁇ .
  • the thin film transistor further includes a gate insulating layer, a second semiconductor layer, and a second source-drain electrode layer
  • the gate insulating layer is disposed on a portion of the second portion away from the first surface. side and extending to the first side, the second semiconductor layer partially covers the gate insulating layer away from the second side, the second source-drain electrode layer partially covers the second semiconductor layer One side away from the gate insulating layer and extending to the gate insulating layer, a portion of the second source-drain electrode layer covering the second semiconductor layer is provided with a first through hole.
  • the second source-drain electrode layer includes a second P-type material layer and a second electrode material layer, the second P-type material layer is disposed on a side close to the second semiconductor layer, so The second electrode material layer is disposed on a side away from the second semiconductor layer.
  • a passivation layer and a pixel electrode layer are further included, the passivation layer covers the photosensitive PN junction and the thin film transistor, and extends to the first surface, the passivation layer passes through the The first through hole is connected to the second semiconductor layer, the passivation layer is provided with a second through hole, the pixel electrode layer partially covers the side of the passivation layer away from the first surface, and It is connected to the second source-drain electrode layer through the second through hole.
  • the present invention provides a method for manufacturing a sensor assembly, comprising:
  • a substrate is provided, the substrate includes a first surface and a second surface disposed oppositely;
  • a gate layer is provided on the first surface, the gate layer partially covers the first surface, the gate layer includes a first part and a second part, and the first part includes a connection part and two or more sub-sections a gate layer, a gap is provided between the sub-gate layers, and one end of the sub-gate layers is connected by the connection part;
  • a first semiconductor layer is provided on a side of the sub-gate layer away from the first surface, and the first semiconductor layer is embedded in the gap;
  • the first part, the first semiconductor layer and the first source-drain electrode layer form a photosensitive PN junction
  • a thin film transistor is disposed adjacent to the photosensitive PN junction on the first surface, and the second part is the gate of the thin film transistor.
  • the disposing the gate layer on the first surface includes:
  • a gate film layer is arranged on the first surface by a deposition method
  • the gate film layer is subjected to a yellow light process and an etching process to form two or more sub-gate layers with gaps, a connection portion and a patterned gate film layer, and one end of the sub-gate layer passes through the gate layer.
  • the connection part is connected, the sub-gate layer and the connection part form a first part, and the patterned gate film layer forms a second part;
  • the first portion and the second portion form the gate layer.
  • arranging a thin film transistor adjacent to the photosensitive PN junction on the first surface includes:
  • a gate insulating layer is provided on a side of the second portion away from the first surface, and the gate insulating layer extends to the first surface;
  • a second semiconductor layer is disposed on the side of the gate insulating layer far away from the second part;
  • a first source-drain electrode layer is provided on the side of the first semiconductor layer away from the gate layer
  • a second source-drain electrode layer is provided on the side of the second semiconductor layer away from the gate insulating layer, the second source-drain electrode layer extends to the gate insulating layer
  • the second portion, the gate insulating layer, the second semiconductor layer, and the second source-drain electrode layer form the thin film transistor.
  • the present invention provides a display panel, comprising a sensor assembly, the sensor assembly comprising:
  • the base plate includes a first surface and a second surface arranged oppositely;
  • the gate layer partially covers the first surface, the gate layer includes a first part and a second part, the first part includes a connection part and two or more sub-gate layers, the sub-gate There is a gap between the pole layers, and one end of the sub-gate layer is connected through the connection part;
  • the first semiconductor layer is disposed on a side of the first portion away from the first surface and embedded in the gap;
  • first source-drain electrode layer is disposed on the side of the first semiconductor layer away from the gate layer; wherein, the first part, the first semiconductor layer and the first A source-drain electrode layer forms a photosensitive PN junction;
  • a thin film transistor the thin film transistor is disposed on the first surface adjacent to the photosensitive PN junction, and the second part is the gate of the thin film transistor.
  • the first source-drain electrode layer includes a first P-type material layer and a first electrode material layer, the first P-type material layer is disposed on a side close to the first semiconductor layer, so The first electrode material layer is arranged on the side away from the first semiconductor layer; wherein, the material used in the first P-type material layer is molybdenum oxide compound, tin oxide compound or a combination of the above materials, the first P-type material layer is The material used for the electrode material layer is metal or metal oxide.
  • the thickness of the first source-drain electrode layer is 300 ⁇ to 800 ⁇ .
  • the first source-drain electrode layer is disposed in the orthographic projection region of the first semiconductor layer on the first surface, and the coverage area of the first source-drain electrode layer is smaller than that of the first semiconductor layer. A coverage area of a semiconductor layer.
  • the material used for the gate layer is metal or metal alloy, and the thickness of the gate layer is 3000 ⁇ to 8000 ⁇ .
  • the thin film transistor further includes a gate insulating layer, a second semiconductor layer, and a second source-drain electrode layer
  • the gate insulating layer is disposed on a portion of the second portion away from the first surface. side and extending to the first side, the second semiconductor layer partially covers the gate insulating layer away from the second side, the second source-drain electrode layer partially covers the second semiconductor layer One side away from the gate insulating layer and extending to the gate insulating layer, a portion of the second source-drain electrode layer covering the second semiconductor layer is provided with a first through hole.
  • the second source-drain electrode layer includes a second P-type material layer and a second electrode material layer, the second P-type material layer is disposed on a side close to the second semiconductor layer, so The second electrode material layer is disposed on a side away from the second semiconductor layer.
  • a passivation layer and a pixel electrode layer are further included, the passivation layer covers the photosensitive PN junction and the thin film transistor, and extends to the first surface, the passivation layer passes through the The first through hole is connected to the second semiconductor layer, the passivation layer is provided with a second through hole, the pixel electrode layer partially covers the side of the passivation layer away from the first surface, and It is connected to the second source-drain electrode layer through the second through hole.
  • the sensor assembly includes a substrate, a gate layer, a first semiconductor layer, a first source-drain electrode layer and a thin film transistor.
  • the substrate includes a first surface and a second surface disposed opposite to each other.
  • the gate layer partially covers the first surface, the gate layer includes a first part and a second part, the first part includes a connection part and two or more sub-gate layers, and the sub-gate layers are between There is a gap, and one end portion of the sub-gate layer is connected through the connection portion.
  • the first semiconductor layer is disposed on a side of the first portion away from the first surface and embedded in the gap.
  • the first source-drain electrode layer is disposed on a side of the first semiconductor layer away from the gate layer.
  • the first part, the first semiconductor layer and the first source-drain electrode layer form a photosensitive PN junction.
  • the thin film transistor is disposed on the first surface adjacent to the photosensitive PN junction, and the second portion is the gate of the thin film transistor.
  • FIG. 1 is a schematic diagram of the first film layer structure of the sensor assembly provided by the present invention
  • Fig. 2 is a kind of top-view structure schematic diagram of the photosensitive PN junction provided by the present invention.
  • FIG. 3 is a schematic diagram of the second film layer structure of the sensor assembly provided by the present invention.
  • FIG. 4 is a schematic diagram of a third film layer structure of the sensor assembly provided by the present invention.
  • FIG. 5 is a schematic diagram of a first process flow of the sensor component manufacturing method provided by the present invention.
  • FIG. 6 is a schematic diagram of a second process flow of the sensor component manufacturing method provided by the present invention.
  • FIG. 7 to 12 are schematic diagrams of process steps of the method for manufacturing a sensor component provided by the present invention.
  • FIG. 13 is a schematic structural diagram of a display panel provided by the present invention.
  • the present invention provides a sensor assembly, a method for manufacturing the sensor assembly, and a display panel.
  • the sensor assembly is described in detail below.
  • FIG. 1 is a schematic view of the first film layer structure of the sensor assembly 10 in the present invention
  • FIG. 2 is a top-view structure schematic view of the photosensitive PN junction in the present invention.
  • the sensor assembly 10 includes a substrate 101, a gate layer 102, a first semiconductor layer 1041, a first source-drain electrode layer 1051 and a thin film transistor 10b.
  • the substrate 101 includes a first surface 101a and a second surface 101b disposed opposite to each other.
  • the gate layer 102 partially covers the first surface 101a, the gate layer 102 includes a first part 1021 and a second part 1022, the first part 1021 includes a connecting part 1021a and two or more sub-gate layers 1021b, and there is a space between the sub-gate layers 1021b.
  • the gap 1021c and one end of the sub-gate layer 1021b are connected by the connecting portion 1021a.
  • the first semiconductor layer 1041 is disposed on a side of the first portion 1021 away from the first surface 101a and embedded in the gap 1021c.
  • the first source-drain electrode layer 1051 is disposed on the side of the first semiconductor layer 1041 away from the gate layer 102 .
  • the first part 1021, the first semiconductor layer 1041 and the first source-drain electrode layer 1051 form the photosensitive PN junction 10a.
  • the thin film transistor 10b is disposed on the first surface 101a adjacent to the photosensitive PN junction 10a, and the second portion 1022 is the gate of the thin film transistor 10b.
  • the invention develops a photosensitive sensor integrated with a bottom gate structure TFT, which can avoid the problems of increasing module thickness and development cost when the top gate structure photosensitive sensor is integrated in a display device.
  • the invention adopts the form of photosensitive PN junction to generate photodiode (photoelectric cell), and the light generates electromotive force at both ends of the photosensitive PN junction, which is equivalent to adding forward voltage at both ends of the photosensitive PN junction. Under the action of light, the current passes through the circuit to make the photosensitive PN junction 10a function as a photosensitive sensor.
  • first surface 101 a may be the upper surface of the substrate 101
  • second surface 101 b may be the lower surface of the substrate 101
  • first surface 101 a may also be the lower surface of the substrate 101
  • second surface 101 b may be the upper surface of the substrate 101 .
  • first surface 101 a is the upper surface of the substrate 101
  • second surface 101 b is the lower surface of the substrate 101 .
  • the material used for the gate layer 102 is metal or metal alloy, and specifically, may be molybdenum (Mo), aluminum (Al), or molybdenum-aluminum alloy.
  • the thickness of the gate layer 102 is 3000 ⁇ to 8000 ⁇ . Specifically, the thickness of the gate layer 102 is 3000 ⁇ , 4000 ⁇ , 5000 ⁇ , 6000 ⁇ , 7000 ⁇ or 8000 ⁇ .
  • the first part 1021 includes a connecting portion 1021a and two or more sub-gate layers 1021b, a gap 1021c is formed between the sub-gate layers 1021b, and one end of the sub-gate layer 1021b is connected by the connecting portion 1021a. That is, the first part 1021 is hollowed out and set as a comb-like structure as shown in FIG. 2 , which can increase the light-receiving area, improve the sensitivity of the photosensitive PN junction 10a to light, and increase the light utilization efficiency. If it is not hollowed out, the light cannot pass through the gate layer 102 and the first semiconductor layer 1041 and irradiate to the photosensitive PN junction 10a to form an electromotive force.
  • the material used for the first semiconductor layer 1041 is a transparent metal oxide, specifically, indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium gallium zinc tin oxide (IGZTO), indium Any of tin oxide (ITO), indium zinc oxide (IZO), indium aluminum zinc oxide (IAZO), indium gallium tin oxide (IGTO), or antimony tin oxide (ATO).
  • IGZO indium gallium zinc oxide
  • IZTO indium zinc tin oxide
  • IGZTO indium gallium zinc tin oxide
  • ATO antimony tin oxide
  • the above materials have good conductivity and transparency, and the thickness is small, which will not affect the overall thickness of the display panel. At the same time, it can also reduce the harmful electron radiation and ultraviolet and infrared light.
  • the thickness of the first semiconductor layer 1041 is 300 ⁇ to 800 ⁇ , specifically, the thickness of the first semiconductor layer 1041 is 300 ⁇ , 400 ⁇ , 500 ⁇ , 600
  • the thickness of the first source-drain electrode layer 1051 is 300 ⁇ to 800 ⁇ . Specifically, the thickness of the first source-drain electrode layer 1051 is 300 ⁇ , 400 ⁇ , 500 ⁇ , 600 ⁇ , 700 ⁇ or 800 ⁇ .
  • the first source-drain electrode layer 1051 is disposed in the orthographic projection area of the first semiconductor layer 1041 on the first surface 101 a , and the coverage area of the first source-drain electrode layer 1051 is smaller than that of the first semiconductor layer 1041 . Since there is no gate insulating layer in the structure of the photosensitive PN junction 10a, the coverage area of the first semiconductor layer 1041 is set to be slightly larger than the coverage area of the first source-drain electrode layer 1051 to avoid the first source-drain electrode layer. The contact of 1051 with the gate layer 102 causes the device to short circuit.
  • the thin film transistor 10b is a thin film transistor with a bottom gate structure, for example, reverse channel etching (Back Channel Etch, BCE) thin film transistor (Thin Film Transistor, TFT).
  • BCE Back Channel Etch
  • TFT Thin Film Transistor
  • the BCE TFT structure has simple process, low production cost, low contact resistance, high mobility, high stability and high compatibility. BCE TFT can also reduce backlight occlusion and thus reduce power consumption.
  • the thin film transistor 10b further includes a gate insulating layer 103, a second semiconductor layer 1042 and a second source-drain electrode layer 1052.
  • the gate insulating layer 103 is disposed on the side of the second portion 1022 away from the first surface 101a and extends to the second portion 1022.
  • the second semiconductor layer 1042 partially covers the side of the gate insulating layer 103 away from the second portion 1022
  • the second source-drain electrode layer 105 partially covers the side of the second semiconductor layer 1042 away from the gate insulating layer 103, and Extending to the gate insulating layer 103 , a portion of the second source-drain electrode layer 1052 covering the second semiconductor layer 1042 is provided with a first through hole 1052c.
  • the gate insulating layer 103 may have a single-layer or multi-layer structure, and the material used for the gate insulating layer 103 is a silicon oxide compound, a silicon nitride compound or a combination of the above materials.
  • the material used for the gate insulating layer 103 is a silicon oxide compound, a silicon nitride compound or a combination of the above materials.
  • a multi-layer structure of a layer of silicon oxide compound and a layer of silicon nitride compound can be used in the multi-layer structure of the gate insulating layer 103.
  • the thickness of the gate insulating layer 103 is 1500 ⁇ to 4000 ⁇ . Specifically, the thickness of the gate insulating layer 103 is 1500 ⁇ , 2000 ⁇ , 2500 ⁇ , 3000 ⁇ , 3500 ⁇ or 4000 ⁇ .
  • the second semiconductor layer 1042 and the first semiconductor layer 1041 have the same material and thickness, and the second source-drain electrode layer 1052 and the first source-drain electrode layer 1051 have the same material and thickness.
  • FIG. 3 is a schematic diagram of a second film structure of the sensor assembly 10 in the present invention.
  • the first source-drain electrode layer 1051 includes a first P-type material layer 1051a and a first electrode material layer 1051b, the first P-type material layer 1051a is disposed on the side close to the first semiconductor layer 1041, and the first electrode material layer 1051b is disposed on the side of the first semiconductor layer 1041. A side away from the first semiconductor layer 1041 .
  • the material used for the first P-type material layer 1051a is molybdenum oxide compound, tin oxide compound or a combination of the above materials, and the material used for the first electrode material layer 1051b is metal or metal oxide.
  • the second source-drain electrode layer 1052 includes a second P-type material layer 1052a and a second electrode material layer 1052b, the second P-type material layer 1052a is disposed on the side close to the second semiconductor layer 1042, and the second electrode material layer 1052b is disposed on the side of the second semiconductor layer 1042. A side away from the second semiconductor layer 1042 .
  • the material used for the second P-type material layer 1051a is molybdenum oxide compound, tin oxide compound or a combination of the above materials, and the material used for the second electrode material layer 1051b is metal or metal oxide.
  • the materials used for the first electrode material layer 1051b and the second electrode material layer 1051b may be copper (Cu), molybdenum (Mo), or molybdenum oxide (MoO x ).
  • the second source-drain electrode layer 1052 is also provided with a P-type material layer, and the second source-drain electrode layer 1052 and the first source-drain electrode layer 1051 can be fabricated in one step, which can save equipment cost and material cost, save production time, and improve production efficiency .
  • the gate insulating layer 103 is provided in the thin film transistor 10b, the p-type material provided on the bottom layer of the second source-drain electrode layer 1052 will not have much influence on the thin film transistor 10b.
  • FIG. 4 is a schematic diagram of the third film layer structure of the sensor assembly 10 in the present invention.
  • the sensor assembly 10 further includes a passivation layer 106 and a pixel electrode layer 107,
  • the passivation layer covers the photosensitive PN junction 10a and the thin film transistor 10b, and extends to the first surface 101a
  • the passivation layer 106 is connected to the second semiconductor layer 1042 through the first through hole 1052c
  • the passivation layer 106 is provided with a second through hole 1042.
  • the hole 106a, the pixel electrode layer 107 partially covers the side of the passivation layer 106 away from the first surface 101a, and is connected to the second source-drain electrode layer 1052 through the second through hole 106a.
  • the passivation layer 106 may have a single-layer or multi-layer structure, and the material used for the passivation layer 106 is silicon oxide compound, silicon nitride compound or a combination of the above materials.
  • the material used for the passivation layer 106 is silicon oxide compound, silicon nitride compound or a combination of the above materials.
  • a multi-layer structure of a layer of silicon oxide compound and a layer of silicon nitride compound can be used.
  • the thickness of the passivation layer 106 is 100 ⁇ to 2000 ⁇ . Specifically, the thickness of the passivation layer 106 is 100 ⁇ , 500 ⁇ , 1000 ⁇ , 1500 ⁇ or 2000 ⁇ .
  • FIG. 5 is a schematic diagram of a first process flow of the sensor component manufacturing method of the present invention.
  • the present invention provides a method for manufacturing a sensor assembly, which specifically includes the following steps:
  • 201 Provide a substrate, where the substrate includes a first surface and a second surface disposed opposite to each other.
  • a gate layer is provided on the first surface, the gate layer partially covers the first surface, the gate layer includes a first part and a second part, the first part includes a connection part and two or more sub-gate layers, and the sub-gate layer There is a gap therebetween, and one end of the sub-gate layer is connected by a connecting portion.
  • the gate film layer is disposed on the first surface by a deposition method. Then, the gate film layer is subjected to a yellow light process and an etching process to form two or more sub-gate layers with gaps, a connection part and a patterned gate film layer, and one end of the sub-gate layer is connected through the connection part.
  • the sub-gate layer and the connecting portion form a first portion
  • the patterned gate film layer forms a second portion.
  • the first portion and the second portion form a gate layer.
  • the deposition method the speed is fast, the film layer is dense, and the adhesion is good, which is very suitable for large-scale, high-efficiency industrial production.
  • the gate layer may be deposited by a physical vapor deposition method.
  • a semiconductor film layer is disposed on the gate layer by a deposition method, and the semiconductor film layer is embedded in the gap. Then, the semiconductor film layer is annealed at a preset annealing temperature, and after the annealing treatment, the semiconductor film layer is subjected to a yellow light process and an etching process, leaving only the semiconductor film layer above the sub-gate layer to form the first semiconductor layer.
  • the first semiconductor layer may be deposited by a physical vapor deposition method, and the preset annealing temperature is 150°C to 450°C. Further, the preset annealing temperature is 150°C, 200°C, 300°C, 400°C or 450°C.
  • a source-drain electrode film layer is formed on the first semiconductor layer by a deposition method. Then, a yellow light process and an etching process are performed on the source-drain electrode film layer, and only the source-drain electrode film layer above the first semiconductor layer is left, so as to form a first source-drain electrode layer.
  • the first source and drain electrode layers may be deposited by using a physical vapor deposition method.
  • the first part, the first semiconductor layer and the first source-drain electrode layer form a photosensitive PN junction.
  • a gate insulating layer is provided on a side of the second portion away from the first surface, and the gate insulating layer extends to the first surface.
  • the second semiconductor layer is provided on the side of the gate insulating layer away from the second portion.
  • a second source-drain electrode layer is arranged at the side of the second semiconductor layer away from the gate insulating layer, and the second source-drain electrode layer extends to gate insulating layer.
  • the second portion, the gate insulating layer, the second semiconductor layer, and the second source-drain electrode layer form a thin film transistor.
  • This embodiment provides a method for setting a thin film transistor with a BCE structure, but it is not a limitation of the present invention.
  • the integration method provided by the present invention can also be applied to other thin film transistors with a bottom gate structure.
  • the specific setting method of the thin film transistor is a technique in the art. The technical means well known to the personnel will not be repeated here.
  • FIG. 6 is a schematic diagram of a second process flow of the method for manufacturing a sensor device according to the present invention.
  • FIG. 7 to FIG. 12 are schematic diagrams of the process steps of the process method of the sensor device according to the present invention.
  • the present invention provides a method for manufacturing a sensor assembly, which specifically includes the following steps:
  • the substrate includes a first surface and a second surface disposed opposite to each other.
  • a gate layer is provided on the first surface, the gate layer partially covers the first surface, the gate layer includes a first part and a second part, the first part includes a connection part and two or more sub-gate layers, and the sub-gate layer There is a gap therebetween, and one end of the sub-gate layer is connected by a connecting portion.
  • FIG. 7 is a schematic diagram of the process steps of disposing the gate layer in the present invention.
  • physical vapor deposition (Physical Vapor Deposition) Deposition, PVD) process to deposit a gate film layer of 3000 ⁇ to 8000 ⁇ , and then use yellow light process and etching process in turn to obtain a gate layer 102 with a pattern, wherein the photosensitive sensor (ie the photosensitive PN junction in the present invention) )
  • the gate is hollowed out to form two or more sub-gate layers connected together to form the first part 1021 in FIG. 7 .
  • FIG. 8 is a schematic diagram of the process steps of disposing the gate insulating layer in the present invention.
  • the gate insulating layer is deposited by a plasma enhanced chemical vapor deposition process, and then patterned by a yellow light process and an etching process, leaving a portion of the gate insulating layer 103 covering the second portion 1022, and the gate
  • the polar insulating layer 103 extends to the first surface 101a.
  • a second semiconductor layer is provided.
  • FIG. 9 is a schematic diagram of the process steps of disposing the first semiconductor layer and the second semiconductor layer in the present invention.
  • physical vapor deposition (Physical Vapor Deposition) Deposition, PVD) process deposits indium gallium zinc oxide (IGZO) materials with thicknesses ranging from 300 ⁇ to 800 ⁇ .
  • the IGZO material is annealed, and the annealing temperature is 150° C. to 450° C., and then a yellow light process and an etching process are used in turn to obtain a semiconductor layer with a pattern.
  • the IGZO material remaining above the first portion 1021 is the first semiconductor layer 1041
  • the IGZO material remaining above the gate insulating layer 103 is the second semiconductor layer 1042 .
  • FIG. 10 is a schematic diagram of the process steps of disposing the first source-drain electrode layer and the second source-drain electrode layer in the present invention.
  • physical vapor deposition (Physical Vapor Deposition) Deposition, PVD) process deposits source-drain electrode films with a thickness of 300 ⁇ to 800 ⁇ .
  • a layer of P-type material such as molybdenum oxide compound or tin oxide compound, is deposited first.
  • Metal electrode material is then deposited over the P-type material.
  • the metal electrode material remaining above the first semiconductor layer 1041 is the first source-drain electrode layer 1051, and the metal electrode remaining above the second semiconductor layer 1042 and extending to the gate insulating layer 103
  • the material is the second source-drain electrode layer 1052, and the second source-drain electrode layer 1052 is provided with a first through hole 1052c.
  • the specific structure of the thin film transistor 10b can be set according to specific device requirements, and the present invention provides only an example, and is not intended to limit the structure of the thin film transistor 10b of the present invention.
  • FIG. 11 is a schematic diagram of the process steps of disposing the passivation layer in the present invention.
  • a passivation layer with a thickness of 100 ⁇ to 2000 ⁇ is deposited by a plasma-enhanced chemical vapor deposition process, and then a yellow light process and an etching process are sequentially used to form the second through holes 106a.
  • the passivation layer is connected to the second semiconductor layer 1042 through the first through hole 1052c on the second source-drain electrode layer 1052, and isolates two parts of the second source-drain electrode layer 1052, namely the source electrode and the drain electrode (in the accompanying drawings) are not differentiated).
  • the pixel electrode layer Disposing a pixel electrode layer on the passivation layer, the pixel electrode layer partially covers the side of the passivation layer away from the first surface, and is connected to the second source-drain electrode layer through the second through hole 106a.
  • FIG. 12 is a schematic diagram of the process steps of disposing the pixel electrode layer in the present invention. After disposing the pixel electrode layer 107 on the passivation layer, the sensor assembly 10 as shown in FIG. 12 is formed.
  • FIG. 13 is a schematic structural diagram of the display panel 100 in the present invention.
  • the display panel 100 includes the sensor assembly 10 and the light-emitting module 20 described above, and the display panel 100 may also include other devices.
  • the light emitting module 20 and other devices and their assembly in the present invention are related technologies well known to those skilled in the art, and will not be described in detail here.
  • the display panel 100 provided by the present invention by integrating the photosensitive PN junction and the thin film transistor of the bottom gate structure, uses the photosensitive PN junction to replace the photosensitive thin film transistor (photosensitive thin film transistor) in the traditional structure.
  • TFT photosensitive thin film transistor
  • amp TFT signal thin film transistor
  • the display panel 100 provided by the present invention can develop and apply multiple functions such as light-sensitive writing, infrared touch, distance sensing, and remote light interaction.

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Abstract

一种传感器组件（10）、传感器组件制程方法及显示面板，该传感器组件（10）通过集成光感PN结（10a）和底栅结构的薄膜晶体管，避免了顶栅结构薄膜晶体管光敏传感器在集成时存在的局限性，解决了底面照光的光敏传感器与显示面板集成时增加模组厚度和开发成本的问题。

Description

一种传感器组件、传感器组件制程方法及显示面板 技术领域
本发明涉及显示技术领域，具体涉及一种传感器组件、传感器组件制程方法及显示面板。
 背景技术
在弱光条件下，顶栅结构薄膜晶体管光敏传感器（Top-gate TFT sensor）在关态电流（Ioff）段的光敏性能要明显优于顶部照光的常规反向通道蚀刻（BCE, Back Channel Etch）薄膜晶体管光敏传感器，这主要得益于有源层受光照面积的提升。但是底面照光的Sensor在与显示面板（Display）集成时存在一定的局限性，只能集成于液晶显示器（LCD, Liquid Crystal Display）的彩膜（CF, color filter）基板或者集成于主动显示的盖板，不仅增加了模组的厚度，还增加了开发的成本。
 技术问题
本发明提供一种传感器组件、传感器组件制程方法及显示面板，该传感器组件集成光感PN结与底栅结构薄膜晶体管。将该传感器组件应用于光敏传感显示面板时，能够避免增加显示面板的厚度，降低了开发成本。
 技术解决方案
本发明提供一种传感器组件，包括：
基板，所述基板包括相对设置的第一面和第二面；
栅极层，所述栅极层部分覆盖所述第一面，所述栅极层包括第一部分和第二部分，所述第一部分包括连接部和两个以上子栅极层，所述子栅极层之间具有间隙，所述子栅极层的一端部通过所述连接部连接；
第一半导体层，所述第一半导体层设置在所述第一部分远离所述第一面的一侧且嵌入所述间隙；
第一源漏电极层，所述第一源漏电极层设置在所述第一半导体层远离所述栅极层的一侧；其中，所述第一部分、所述第一半导体层及所述第一源漏电极层形成光感PN结；
薄膜晶体管，所述薄膜晶体管与所述光感PN结相邻设置在所述第一面上，所述第二部分为所述薄膜晶体管的栅极。
在一些实施例中，所述第一源漏电极层包括第一P型材料层和第一电极材料层，所述第一P型材料层设置在靠近所述第一半导体层的一侧，所述第一电极材料层设置在远离所述第一半导体层的一侧；其中，所述第一P型材料层采用的材料为钼氧化合物、锡氧化合物或以上材料的组合，所述第一电极材料层采用的材料为金属或金属氧化物。
在一些实施例中，所述第一源漏电极层的厚度为300 Å至800 Å。
在一些实施例中，所述第一源漏电极层设置在所述第一半导体层在所述第一面的正投影区域内，且所述第一源漏电极层的覆盖面积小于所述第一半导体层的覆盖面积。
在一些实施例中，所述栅极层采用的材料为金属或金属合金，所述栅极层的厚度为3000Å至8000 Å。
在一些实施例中，所述第一半导体层采用的材料为透明金属氧化物，所述第一半导体层的厚度为300Å至800 Å。
在一些实施例中，所述薄膜晶体管还包括栅极绝缘层、第二半导体层以及第二源漏电极层，所述栅极绝缘层设置在所述第二部分远离所述第一面的一侧并延伸至所述第一面，所述第二半导体层部分覆盖所述栅极绝缘层远离所述第二部分的一侧，所述第二源漏电极层部分覆盖所述第二半导体层远离所述栅极绝缘层的一侧，并延伸至所述栅极绝缘层，所述第二源漏电极层覆盖所述第二半导体层的部分设置有第一通孔。
在一些实施例中，所述第二源漏电极层包括第二P型材料层和第二电极材料层，所述第二P型材料层设置在靠近所述第二半导体层的一侧，所述第二电极材料层设置在远离所述第二半导体层的一侧。
在一些实施例中，还包括钝化层和像素电极层，所述钝化层覆盖所述光感PN结和所述薄膜晶体管，并延伸至所述第一面，所述钝化层通过所述第一通孔与所述第二半导体层连接，所述钝化层上设置有第二通孔，所述像素电极层部分覆盖所述钝化层远离所述第一面的一侧，且通过所述第二通孔与所述第二源漏电极层连接。
本发明提供一种传感器组件制程方法，包括：
提供一基板，所述基板包括相对设置的第一面和第二面；
在所述第一面上设置栅极层，所述栅极层部分覆盖所述第一面，所述栅极层包括第一部分和第二部分，所述第一部分包括连接部和两个以上子栅极层，所述子栅极层之间具有间隙，所述子栅极层的一端部通过所述连接部连接；
在所述子栅极层远离所述第一面的一侧设置第一半导体层，所述第一半导体层嵌入所述间隙；
在所述第一半导体层远离所述栅极层的一侧设置第一源漏电极层；
所述第一部分、所述第一半导体层及所述第一源漏电极层形成光感PN结；
在所述第一面上与所述光感PN结相邻设置薄膜晶体管，所述第二部分为所述薄膜晶体管的栅极。
在一些实施例中，所述在所述第一面上设置栅极层，包括：
在所述第一面上采用沉积的方法设置栅极膜层；
对所述栅极膜层进行黄光工艺和刻蚀工艺，形成两个以上具有间隙的子栅极层、连接部和图案化的栅极膜层，所述子栅极层的一端部通过所述连接部连接，所述子栅极层与所述连接部形成第一部分，所述图案化的栅极膜层形成第二部分；
所述第一部分和所述第二部分形成所述栅极层。
在一些实施例中，所述在所述第一面上与所述光感PN结相邻设置薄膜晶体管，包括：
在所述第二部分远离所述第一面的一侧设置栅极绝缘层，所述栅极绝缘层延伸至所述第一面；
在所述子栅极层远离所述第一面的一侧设置第一半导体层时，在所述栅极绝缘层远离所述第二部分的一侧设置第二半导体层；
在所述第一半导体层远离所述栅极层的一侧设置第一源漏电极层时，在所述第二半导体层远离所述栅极绝缘层的一侧设置第二源漏电极层，所述第二源漏电极层延伸至所述栅极绝缘层；
所述第二部分、所述栅极绝缘层、所述第二半导体层以及所述第二源漏电极层形成所述薄膜晶体管。
本发明提供一种显示面板，包括一种传感器组件，所述传感器组件包括:
基板，所述基板包括相对设置的第一面和第二面；
栅极层，所述栅极层部分覆盖所述第一面，所述栅极层包括第一部分和第二部分，所述第一部分包括连接部和两个以上子栅极层，所述子栅极层之间具有间隙，所述子栅极层的一端部通过所述连接部连接；
第一半导体层，所述第一半导体层设置在所述第一部分远离所述第一面的一侧且嵌入所述间隙；
第一源漏电极层，所述第一源漏电极层设置在所述第一半导体层远离所述栅极层的一侧；其中，所述第一部分、所述第一半导体层及所述第一源漏电极层形成光感PN结；
薄膜晶体管，所述薄膜晶体管与所述光感PN结相邻设置在所述第一面上，所述第二部分为所述薄膜晶体管的栅极。
在一些实施例中，所述第一源漏电极层包括第一P型材料层和第一电极材料层，所述第一P型材料层设置在靠近所述第一半导体层的一侧，所述第一电极材料层设置在远离所述第一半导体层的一侧；其中，所述第一P型材料层采用的材料为钼氧化合物、锡氧化合物或以上材料的组合，所述第一电极材料层采用的材料为金属或金属氧化物。
在一些实施例中，所述第一源漏电极层的厚度为300 Å至800 Å。
在一些实施例中，所述第一源漏电极层设置在所述第一半导体层在所述第一面的正投影区域内，且所述第一源漏电极层的覆盖面积小于所述第一半导体层的覆盖面积。
在一些实施例中，所述栅极层采用的材料为金属或金属合金，所述栅极层的厚度为3000Å至8000 Å。
在一些实施例中，所述薄膜晶体管还包括栅极绝缘层、第二半导体层以及第二源漏电极层，所述栅极绝缘层设置在所述第二部分远离所述第一面的一侧并延伸至所述第一面，所述第二半导体层部分覆盖所述栅极绝缘层远离所述第二部分的一侧，所述第二源漏电极层部分覆盖所述第二半导体层远离所述栅极绝缘层的一侧，并延伸至所述栅极绝缘层，所述第二源漏电极层覆盖所述第二半导体层的部分设置有第一通孔。
在一些实施例中，所述第二源漏电极层包括第二P型材料层和第二电极材料层，所述第二P型材料层设置在靠近所述第二半导体层的一侧，所述第二电极材料层设置在远离所述第二半导体层的一侧。
在一些实施例中，还包括钝化层和像素电极层，所述钝化层覆盖所述光感PN结和所述薄膜晶体管，并延伸至所述第一面，所述钝化层通过所述第一通孔与所述第二半导体层连接，所述钝化层上设置有第二通孔，所述像素电极层部分覆盖所述钝化层远离所述第一面的一侧，且通过所述第二通孔与所述第二源漏电极层连接。
 有益效果
本发明所提供的传感器组件，包括基板、栅极层、第一半导体层、第一源漏电极层和薄膜晶体管。基板包括相对设置的第一面和第二面。所述栅极层部分覆盖所述第一面，所述栅极层包括第一部分和第二部分，所述第一部分包括连接部和两个以上子栅极层，所述子栅极层之间具有间隙，所述子栅极层的一端部通过所述连接部连接。所述第一半导体层设置在所述第一部分远离所述第一面的一侧且嵌入所述间隙。所述第一源漏电极层设置在所述第一半导体层远离所述栅极层的一侧。其中，所述第一部分、所述第一半导体层及所述第一源漏电极层形成光感PN结。所述薄膜晶体管与所述光感PN结相邻设置在所述第一面上，所述第二部分为所述薄膜晶体管的栅极。该传感器组件通过集成光感PN结和底栅结构的薄膜晶体管，避免了顶栅结构薄膜晶体管光敏传感器在集成时存在的局限性，解决了底面照光的光敏传感器与显示面板集成时增加模组厚度和开发成本的问题。
 附图说明
为了更清楚地说明本发明中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明提供的传感器组件的第一种膜层结构示意图；
图2为本发明提供的光感PN结的一种俯视结构示意图；
图3为本发明提供的传感器组件的第二种膜层结构示意图；
图4为本发明提供的传感器组件的第三种膜层结构示意图；
图5为本发明提供的传感器组件制程方法的第一种工艺流程示意图；
图6为本发明提供的传感器组件制程方法的第二种工艺流程示意图；
图7至图12为本发明提供的传感器组件制程方法的制程步骤示意图；
图13为本发明提供的显示面板的一种结构示意图。
 本发明的实施方式
下面将结合本发明中的附图，对本发明中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
需要说明的是，在本发明的描述中，术语“上”、“下”、“前”、“后”、“左”、“右”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
本发明提供一种传感器组件、传感器组件制程方法及显示面板，以下对传感器组件做详细介绍。
请参阅图1和图2，图1是本发明中的传感器组件10的第一种膜层结构示意图，图2是本发明中的光感PN结的一种俯视结构示意图。其中，传感器组件10包括基板101、栅极层102、第一半导体层1041、第一源漏电极层1051和薄膜晶体管10b。基板101包括相对设置的第一面101a和第二面101b。栅极层102部分覆盖第一面101a，栅极层102包括第一部分1021和第二部分1022，第一部分1021包括连接部1021a和两个以上子栅极层1021b，子栅极层1021b之间具有间隙1021c，子栅极层1021b的一端部通过连接部1021a连接。第一半导体层1041设置在第一部分1021远离第一面101a的一侧且嵌入间隙1021c。第一源漏电极层1051设置在第一半导体层1041远离栅极层102的一侧。其中，第一部分1021、第一半导体层1041及第一源漏电极层1051形成光感PN结10a。薄膜晶体管10b与光感PN结10a相邻设置在第一面101a上，第二部分1022为薄膜晶体管10b的栅极。
本发明开发了一种与底栅结构TFT集成的光敏传感器，可以避免顶栅结构光敏传感器在集成于显示装置时增加模组厚度和开发成本的问题。本发明采用光感PN结的形式产生光电二级管（光电池），光照在光感PN结两端产生电动势，相当于在光感PN结两端加正向电压。在光照的作用下，电流通过电路使光感PN结10a起到光敏传感器的作用。
需要说明的是，第一面101a可以为基板101的上表面，第二面101b可以为基板101的下表面。当然，第一面101a也可以为基板101的下表面，第二面101b可以为基板101的上表面。本发明中不做特殊说明的情况下，默认为第一面101a为基板101的上表面，第二面101b为基板101的下表面。
其中，栅极层102采用的材料为金属或金属合金，具体地，可以为钼（Mo）、铝（Al）或钼铝合金。其中，栅极层102的厚度为3000Å至8000 Å。具体地，栅极层102的厚度为3000Å、4000Å、5000Å、6000Å、7000Å或8000 Å。
其中，第一部分1021包括连接部1021a和两个以上子栅极层1021b，子栅极层1021b之间具有间隙1021c，子栅极层1021b的一端部通过连接部1021a连接。即，第一部分1021掏空制作，设置为如图2所示的梳状结构，这样设置可以增大受光面积，提高光感PN结10a对光线的敏感性，增大光线利用效率。如不掏空，则光线无法透过栅极层102和第一半导体层1041照射至光感PN结10a形成电动势。
其中，第一半导体层1041采用的材料为透明金属氧化物，具体地，可以为铟镓锌氧化物(IGZO)、铟锌锡氧化物（IZTO）、铟镓锌锡氧化物（IGZTO）、铟锡氧化物（ITO）、铟锌氧化物（IZO）、铟铝锌氧化物（IAZO）、铟镓锡氧化物（IGTO）或锑锡氧化物（ATO）中的任一种。以上材料具有很好的导电性和透明性，并且厚度较小，不会影响显示面板的整体厚度。同时，还可以减少对人体有害的电子辐射及紫外、红外光。第一半导体层1041的厚度为300Å至800 Å，具体地，第一半导体层1041的厚度为300Å、400Å、500Å、600Å、700Å或800 Å。
其中，第一源漏电极层1051的厚度为300Å至800Å。具体地，第一源漏电极层1051的厚度为300 Å、400 Å、500 Å、600 Å、700 Å或800 Å。
其中，第一源漏电极层1051设置在第一半导体层1041在第一面101a的正投影区域内，且第一源漏电极层1051的覆盖面积小于第一半导体层1041的覆盖面积。由于光感PN结10a的结构中没有设置栅极绝缘层，因此将第一半导体层1041的覆盖面积设置为比第一源漏电极层1051的覆盖面积稍大，可以避免第一源漏电极层1051与栅极层102接触造成器件短路。
其中，薄膜晶体管10b为底栅结构的薄膜晶体管，例如，反向通道刻蚀（Back Channel Etch, BCE）薄膜晶体管（Thin Film Transistor, TFT）。BCE TFT结构工艺制程简单，生产成本低，接触电阻低，并且具有高迁移率、高稳定性和高兼容性。BCE TFT还可以减少背光遮挡进而降低功耗。
其中，薄膜晶体管10b还包括栅极绝缘层103、第二半导体层1042以及第二源漏电极层1052，栅极绝缘层103设置在第二部分1022远离第一面101a的一侧并延伸至第一面101a，第二半导体层1042部分覆盖栅极绝缘层103远离第二部分1022的一侧，第二源漏电极层105部分覆盖第二半导体层1042远离栅极绝缘层103的一侧，并延伸至栅极绝缘层103，第二源漏电极层1052覆盖第二半导体层1042的部分设置有第一通孔1052c。
其中，栅极绝缘层103可以为单层或多层结构，栅极绝缘层103采用的材料为硅氧化合物、硅氮化合物或以上材料的组合。例如在栅极绝缘层103多层结构中，可以采用一层硅氧化合物与一层硅氮化合物的多层结构。栅极绝缘层103的厚度为1500Å至4000Å。具体地，栅极绝缘层103的厚度为1500 Å、2000 Å、2500 Å、3000 Å、3500 Å或4000 Å。
其中，第二半导体层1042与第一半导体层1041的材料和厚度相同，第二源漏电极层1052与第一源漏电极层1051的材料和厚度相同。
请参阅图3，图3是本发明中的传感器组件10的第二种膜层结构示意图。第一源漏电极层1051包括第一P型材料层1051a和第一电极材料层1051b，第一P型材料层1051a设置在靠近第一半导体层1041的一侧，第一电极材料层1051b设置在远离第一半导体层1041的一侧。其中，第一P型材料层1051a采用的材料为钼氧化合物、锡氧化合物或以上材料的组合，第一电极材料层1051b采用的材料为金属或金属氧化物。第二源漏电极层1052包括第二P型材料层1052a和第二电极材料层1052b，第二P型材料层1052a设置在靠近第二半导体层1042的一侧，第二电极材料层1052b设置在远离第二半导体层1042的一侧。其中，第二P型材料层1051a采用的材料为钼氧化合物、锡氧化合物或以上材料的组合，第二电极材料层1051b采用的材料为金属或金属氧化物。具体地，第一电极材料层1051b和第二电极材料层1051b采用的材料可以为铜（Cu）、钼（Mo）或钼氧化合物（MoO x）。
第二源漏电极层1052也设置P型材料层可以将第二源漏电极层1052与第一源漏电极层1051采用一步制程制作，能够节约设备成本和材料成本，节省生产时间，提高生产效率。并且，由于薄膜晶体管10b中设置有栅极绝缘层103，因此，在第二源漏电极层1052的底层设置P型材料不会对薄膜晶体管10b产生太大影响。
请参阅图4，图4是本发明中的传感器组件10的第三种膜层结构示意图。其中，图4所示的传感器组件10的膜层结构与图1、图3两种实施例中传感器组件10膜层结构的区别是，传感器组件10还包括钝化层106和像素电极层107，钝化层覆盖光感PN结10a和薄膜晶体管10b，并延伸至第一面101a，钝化层106通过第一通孔1052c与第二半导体层1042连接，钝化层106上设置有第二通孔106a，像素电极层107部分覆盖钝化层106远离第一面101a的一侧，且通过第二通孔106a与所述第二源漏电极层1052连接。
其中，钝化层106可以为单层或多层结构，钝化层106采用的材料为硅氧化合物、硅氮化合物或以上材料的组合。例如在钝化层106多层结构中，可以采用一层硅氧化合物与一层硅氮化合物的多层结构。钝化层106的厚度为100Å至2000Å。具体地，钝化层106的厚度为100 Å、500 Å、1000 Å、1500 Å或2000 Å。
请参阅图5，图5是本发明中的传感器组件制程方法的第一种工艺流程示意图。其中，本发明提供一种传感器组件制程方法，具体包括如下步骤：
201、提供一基板，基板包括相对设置的第一面和第二面。
202、在第一面上设置栅极层，栅极层部分覆盖第一面，栅极层包括第一部分和第二部分，第一部分包括连接部和两个以上子栅极层，子栅极层之间具有间隙，子栅极层的一端部通过连接部连接。
具体地，在第一面上采用沉积的方法设置栅极膜层。然后对栅极膜层进行黄光工艺和刻蚀工艺，形成两个以上具有间隙的子栅极层、连接部和图案化的栅极膜层，子栅极层的一端部通过连接部连接，子栅极层与连接部形成第一部分，图案化的栅极膜层形成第二部分。第一部分和第二部分形成栅极层。采用沉积的方法，速度快，膜层致密，附着性好，很适合于大批量，高效率工业生产。进一步地，可以采用物理气相沉积的方法沉积栅极层。
203、在子栅极层远离第一面的一侧设置第一半导体层，第一半导体层嵌入间隙。
具体地，在栅极层上采用沉积的方法设置半导体膜层，半导体膜层嵌入间隙。然后对半导体膜层在预设退火温度下进行退火处理，退火处理之后对半导体膜层进行黄光工艺和刻蚀工艺，只留下在子栅极层上方的半导体膜层，以形成第一半导体层。具体地，可以采用物理气相沉积的方法沉积第一半导体层，预设退火温度为150℃至450℃。进一步地，预设退火温度为150℃、200℃、300℃、400℃或450℃。
204、在第一半导体层远离栅极层的一侧设置第一源漏电极层。
具体地，在第一半导体层上采用沉积的方法设置源漏电极膜层。然后对源漏电极膜层进行黄光工艺和刻蚀工艺，只留下在第一半导体层上方的源漏电极膜层，以形成第一源漏电极层。具体地，可以采用物理气相沉积的方法沉积第一源漏电极层。
205、第一部分、第一半导体层及第一源漏电极层形成光感PN结。
206、在第一面上与光感PN结相邻设置薄膜晶体管，第二部分为薄膜晶体管的栅极。
具体地，在第二部分远离第一面的一侧设置栅极绝缘层，栅极绝缘层延伸至第一面。在第一部分远离第一面的一侧设置第一半导体层时，在栅极绝缘层远离所述第二部分的一侧设置第二半导体层。在第一半导体层远离栅极层的一侧设置第一源漏电极层时，在第二半导体层远离栅极绝缘层的一侧设置第二源漏电极层，第二源漏电极层延伸至栅极绝缘层。第二部分、栅极绝缘层、第二半导体层以及第二源漏电极层形成薄膜晶体管。
本实施例提供的是BCE结构薄膜晶体管的设置方法，但不作为对本发明的限制，本发明提供的集成方法还可适用于其他底栅结构的薄膜晶体管，具体的薄膜晶体管设置方式为本领域技术人员所熟知的技术手段，在此不再赘述。
请参阅图6至图12，图6是本发明中的传感器组件制程方法的第二种工艺流程示意图。图7至图12是本发明中的传感器组件制程方法的制程步骤示意图。其中，本发明提供一种传感器组件制程方法，具体包括如下步骤：
301、提供一基板，基板包括相对设置第一面和第二面。
302、在第一面上设置栅极层，栅极层部分覆盖第一面，栅极层包括第一部分和第二部分，第一部分包括连接部和两个以上子栅极层，子栅极层之间具有间隙，子栅极层的一端部通过连接部连接。
请参阅图7，图7是本发明中设置栅极层的制程步骤示意图。在一种实施例中，采用物理气相沉积（Physical Vapor Deposition, PVD）工艺沉积形成3000Å至8000 Å的栅极膜层，再依次利用黄光工艺和刻蚀工艺制得具有图形的栅极层102，其中光敏传感器（即本发明中的光感PN结）栅极掏空制作，形成两块或两块以上子栅极层连接一起组成图7中第一部分1021。
303、在第二部分上设置栅极绝缘层，栅极远离第一面的一侧设置栅极绝缘层，栅极绝缘层延伸至第一面。
请参阅图8，图8是本发明中设置栅极绝缘层的制程步骤示意图。在一种实施例中，通过等离子增强化学气相沉积工艺沉积栅极绝缘层，然后利用黄光工艺和刻蚀工艺进行图案化，留下部分覆盖第二部分1022的栅极绝缘层103，且栅极绝缘层103延伸至第一面101a。
304、在子栅极层远离所述第一面的一侧设置第一半导体层，所述第一半导体层嵌入所述间隙，同时在所述栅极绝缘层远离所述第二部分的一侧设置第二半导体层。
请参阅图9，图9是本发明中设置第一半导体层和第二半导体层的制程步骤示意图。在一种实施例中，通过物理气相沉积（Physical Vapor Deposition, PVD）工艺沉积厚度为300Å至800 Å的铟镓锌氧化物(IGZO)材料。然后对IGZO材料进行退火处理，退火温度为150℃至450℃，再依次利用黄光工艺和刻蚀工艺制得具有图形的半导体层。其中，保留在第一部分1021上方的IGZO材料为第一半导体层1041，保留在栅极绝缘层103上方的IGZO材料为第二半导体层1042。
305、在所述第一半导体层远离所述栅极层的一侧设置第一源漏电极层，同时在所述第二半导体层远离所述第二半导体层的一侧设置第二源漏电极层，所述第二源漏电极层延伸至所述栅极绝缘层。
请参阅图10，图10是本发明中设置第一源漏电极层和第二源漏电极层的制程步骤示意图。在一种实施例中，通过物理气相沉积（Physical Vapor Deposition, PVD）工艺沉积厚度为300Å至800 Å的源漏电极膜层。其中，先沉积一层P型材料，例如钼氧化合物或锡氧化合物。然后在P型材料上方沉积金属电极材料。沉积完成后进行黄光刻蚀工艺，保留在第一半导体层1041上方的金属电极材料为第一源漏电极层1051，保留在第二半导体层1042上方且延伸至栅极绝缘层103的金属电极材料为第二源漏电极层1052，并且第二源漏电极层1052上设置有第一通孔1052c。另外，薄膜晶体管10b的具体结构可以根据具体的器件需求设置，本发明提供的只是一种示例，不作为对本发明薄膜晶体管10b结构的限制。
306、在光感PN结和薄膜晶体管上设置钝化层，钝化层延伸至第一面。
请参阅图11，图11是本发明中设置钝化层的制程步骤示意图。在一种实施例中，通过等离子增强化学气相沉积工艺沉积厚度为100Å至2000 Å的钝化层，再依次利用黄光工艺和刻蚀工艺制进行设置第二通孔106a。钝化层通过第二源漏电极层1052上的第一通孔1052c与第二半导体层1042连接，并隔绝第二源漏电极层1052的两个部分，即源极和漏极（附图中均未做区分）。
307、在钝化层上设置像素电极层，像素电极层部分覆盖钝化层远离第一面的一侧，且通过第二通孔106a与第二源漏电极层连接。
请参阅图12，图12是本发明中设置像素电极层的制程步骤示意图。在钝化层上设置像素电极层107之后，形成如图12的传感器组件10。
本发明提供一种显示面板100，图13为本发明中显示面板100的一种结构示意图。其中，显示面板100包括以上所述的传感器组件10和发光模块20，显示面板100还可以包括其他装置。本发明中发光模块20和其他装置及其装配是本领域技术人员所熟知的相关技术，在此不做过多赘述。
本发明提供的显示面板100，通过集成光感PN结和底栅结构的薄膜晶体管，由于采用光感PN结替代了传统结构中的光敏薄膜晶体管（photo TFT）、信号薄膜晶体管（amp TFT），能够减少一个薄膜晶体管的设置，因此，简化了器件结构，节省了像素结构中的布局空间，增大了开口率。还可避免顶栅结构薄膜晶体管光敏传感器在集成时存在的局限性，并解决了底面照光的光敏传感器与显示面板集成时增加模组厚度和开发成本的问题。本发明提供的显示面板100可以开发应用光感书写、红外触控、距离感应以及远程光互动等多项功能。
以上对本发明提供的传感器组件、传感器组件制程方法及显示面板进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明。同时，对于本领域的技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种传感器组件，其中，包括：
    基板，所述基板包括相对设置的第一面和第二面；
    栅极层，所述栅极层部分覆盖所述第一面，所述栅极层包括第一部分和第二部分，所述第一部分包括连接部和两个以上子栅极层，所述子栅极层之间具有间隙，所述子栅极层的一端部通过所述连接部连接；
    第一半导体层，所述第一半导体层设置在所述第一部分远离所述第一面的一侧且嵌入所述间隙；
    第一源漏电极层，所述第一源漏电极层设置在所述第一半导体层远离所述栅极层的一侧；其中，所述第一部分、所述第一半导体层及所述第一源漏电极层形成光感PN结；
    薄膜晶体管，所述薄膜晶体管与所述光感PN结相邻设置在所述第一面上，所述第二部分为所述薄膜晶体管的栅极。
  2. 根据权利要求1所述的传感器组件，其中，所述第一源漏电极层包括第一P型材料层和第一电极材料层，所述第一P型材料层设置在靠近所述第一半导体层的一侧，所述第一电极材料层设置在远离所述第一半导体层的一侧；其中，所述第一P型材料层采用的材料为钼氧化合物、锡氧化合物或以上材料的组合，所述第一电极材料层采用的材料为金属或金属氧化物。
  3. 根据权利要求2所述的传感器组件，其中，所述第一源漏电极层的厚度为300 Å至800 Å。
  4. 根据权利要求1所述的传感器组件，其中，所述第一源漏电极层设置在所述第一半导体层在所述第一面的正投影区域内，且所述第一源漏电极层的覆盖面积小于所述第一半导体层的覆盖面积。
  5. 根据权利要求1所述的传感器组件，其中，所述栅极层采用的材料为金属或金属合金，所述栅极层的厚度为3000Å至8000 Å。
  6. 根据权利要求1所述的传感器组件，其中，所述第一半导体层采用的材料为透明金属氧化物，所述第一半导体层的厚度为300Å至800 Å。
  7. 根据权利要求1所述的传感器组件，其中，所述薄膜晶体管还包括栅极绝缘层、第二半导体层以及第二源漏电极层，所述栅极绝缘层设置在所述第二部分远离所述第一面的一侧并延伸至所述第一面，所述第二半导体层部分覆盖所述栅极绝缘层远离所述第二部分的一侧，所述第二源漏电极层部分覆盖所述第二半导体层远离所述栅极绝缘层的一侧，并延伸至所述栅极绝缘层，所述第二源漏电极层覆盖所述第二半导体层的部分设置有第一通孔。
  8. 根据权利要求7所述的传感器组件，其中，所述第二源漏电极层包括第二P型材料层和第二电极材料层，所述第二P型材料层设置在靠近所述第二半导体层的一侧，所述第二电极材料层设置在远离所述第二半导体层的一侧。
  9. 根据权利要求7所述的传感器组件，其中，还包括钝化层和像素电极层，所述钝化层覆盖所述光感PN结和所述薄膜晶体管，并延伸至所述第一面，所述钝化层通过所述第一通孔与所述第二半导体层连接，所述钝化层上设置有第二通孔，所述像素电极层部分覆盖所述钝化层远离所述第一面的一侧，且通过所述第二通孔与所述第二源漏电极层连接。
  10. 一种传感器组件制程方法，其中，包括：
    提供一基板，所述基板包括相对设置的第一面和第二面；
    在所述第一面上设置栅极层，所述栅极层部分覆盖所述第一面，所述栅极层包括第一部分和第二部分，所述第一部分包括连接部和两个以上子栅极层，所述子栅极层之间具有间隙，所述子栅极层的一端部通过所述连接部连接；
    在所述子栅极层远离所述第一面的一侧设置第一半导体层，所述第一半导体层嵌入所述间隙；
    在所述第一半导体层远离所述栅极层的一侧设置第一源漏电极层；
    所述第一部分、所述第一半导体层及所述第一源漏电极层形成光感PN结；
    在所述第一面上与所述光感PN结相邻设置薄膜晶体管，所述第二部分为所述薄膜晶体管的栅极。
  11. 根据权利要求10所述的传感器组件制程方法，其中，所述在所述第一面上设置栅极层，包括：
    在所述第一面上采用沉积的方法设置栅极膜层；
    对所述栅极膜层进行黄光工艺和刻蚀工艺，形成两个以上具有间隙的子栅极层、连接部和图案化的栅极膜层，所述子栅极层的一端部通过所述连接部连接，所述子栅极层与所述连接部形成第一部分，所述图案化的栅极膜层形成第二部分；
    所述第一部分和所述第二部分形成所述栅极层。
  12. 根据权利要求10所述的传感器组件制程方法，其中，所述在所述第一面上与所述光感PN结相邻设置薄膜晶体管，包括：
    在所述第二部分远离所述第一面的一侧设置栅极绝缘层，所述栅极绝缘层延伸至所述第一面；
    在所述子栅极层远离所述第一面的一侧设置第一半导体层时，在所述栅极绝缘层远离所述第二部分的一侧设置第二半导体层；
    在所述第一半导体层远离所述栅极层的一侧设置第一源漏电极层时，在所述第二半导体层远离所述栅极绝缘层的一侧设置第二源漏电极层，所述第二源漏电极层延伸至所述栅极绝缘层；
    所述第二部分、所述栅极绝缘层、所述第二半导体层以及所述第二源漏电极层形成所述薄膜晶体管。
  13. 一种显示面板，其中，包括传感器组件，所述传感器组件包括：
    基板，所述基板包括相对设置的第一面和第二面；
    栅极层，所述栅极层部分覆盖所述第一面，所述栅极层包括第一部分和第二部分，所述第一部分包括连接部和两个以上子栅极层，所述子栅极层之间具有间隙，所述子栅极层的一端部通过所述连接部连接；
    第一半导体层，所述第一半导体层设置在所述第一部分远离所述第一面的一侧且嵌入所述间隙；
    第一源漏电极层，所述第一源漏电极层设置在所述第一半导体层远离所述栅极层的一侧；其中，所述第一部分、所述第一半导体层及所述第一源漏电极层形成光感PN结；
    薄膜晶体管，所述薄膜晶体管与所述光感PN结相邻设置在所述第一面上，所述第二部分为所述薄膜晶体管的栅极。
  14. 根据权利要求13所述的显示面板，其中，所述第一源漏电极层包括第一P型材料层和第一电极材料层，所述第一P型材料层设置在靠近所述第一半导体层的一侧，所述第一电极材料层设置在远离所述第一半导体层的一侧；其中，所述第一P型材料层采用的材料为钼氧化合物、锡氧化合物或以上材料的组合，所述第一电极材料层采用的材料为金属或金属氧化物。
  15. 根据权利要求14所述的显示面板，其中，所述第一源漏电极层的厚度为300 Å至800 Å。
  16. 根据权利要求13所述的显示面板，其中，所述第一源漏电极层设置在所述第一半导体层在所述第一面的正投影区域内，且所述第一源漏电极层的覆盖面积小于所述第一半导体层的覆盖面积。
  17. 根据权利要求13所述的显示面板，其中，所述栅极层采用的材料为金属或金属合金，所述栅极层的厚度为3000 Å至8000 Å。
  18. 根据权利要求13所述的显示面板，其中，所述薄膜晶体管还包括栅极绝缘层、第二半导体层以及第二源漏电极层，所述栅极绝缘层设置在所述第二部分远离所述第一面的一侧并延伸至所述第一面，所述第二半导体层部分覆盖所述栅极绝缘层远离所述第二部分的一侧，所述第二源漏电极层部分覆盖所述第二半导体层远离所述栅极绝缘层的一侧，并延伸至所述栅极绝缘层，所述第二源漏电极层覆盖所述第二半导体层的部分设置有第一通孔。
  19. 根据权利要求18所述的显示面板，其中，所述第二源漏电极层包括第二P型材料层和第二电极材料层，所述第二P型材料层设置在靠近所述第二半导体层的一侧，所述第二电极材料层设置在远离所述第二半导体层的一侧。
  20. 根据权利要求18所述的显示面板，其中，还包括钝化层和像素电极层，所述钝化层覆盖所述光感PN结和所述薄膜晶体管，并延伸至所述第一面，所述钝化层通过所述第一通孔与所述第二半导体层连接，所述钝化层上设置有第二通孔，所述像素电极层部分覆盖所述钝化层远离所述第一面的一侧，且通过所述第二通孔与所述第二源漏电极层连接。
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