WO2022047896A1 - 阵列基板及其制作方法、显示面板 - Google Patents

阵列基板及其制作方法、显示面板 Download PDF

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Publication number
WO2022047896A1
WO2022047896A1 PCT/CN2020/120825 CN2020120825W WO2022047896A1 WO 2022047896 A1 WO2022047896 A1 WO 2022047896A1 CN 2020120825 W CN2020120825 W CN 2020120825W WO 2022047896 A1 WO2022047896 A1 WO 2022047896A1
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WIPO (PCT)
Prior art keywords
layer
via hole
metal layer
insulating layer
array substrate
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Application number
PCT/CN2020/120825
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English (en)
French (fr)
Inventor
肖邦清
许森
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/052,579 priority Critical patent/US11749687B2/en
Publication of WO2022047896A1 publication Critical patent/WO2022047896A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a manufacturing method thereof, and a display panel.
  • the ultra-narrow frame display panel can realize the seamless splicing of the panel.
  • the existing ultra-narrow frame mainly adopts the structure of GOA (Gate driver in COF). Realization, that is, the scanning line signal output function is designed on the same COF (Chip On Film) side as the data line, thereby reducing the width of the borders on both sides of the display panel and realizing the "three narrow and one wide" display effect. Under this structure, the density of lines such as scan lines and data lines increases. In order not to affect the pixel aperture ratio, the scan lines and data lines are designed to be narrower, and the scan lines and data lines are added. resistance-capacitance, prone to signal propagation delay (RC loading) and insufficient pixel charging.
  • RC loading signal propagation delay
  • metal layer one 12 includes scanning horizontal lines 121
  • metal layer two 14 includes scanning vertical lines one 141 and data Line one 142
  • the metal layer three 16 is a new metal layer for reducing resistance in parallel with the scan vertical line one 141 and the data line one 142
  • the metal layer three 16 includes a scan vertical line in parallel with the scan vertical line one 141
  • the third 161, and the second data line 162 connected in parallel with the first data line 142 obviously, it is necessary to form a via hole one 131 on the insulating layer one 13 and a via hole two 151 on the insulating layer two 15, respectively, to achieve
  • the connection between the above-mentioned metal layers not only increases the complexity of the array substrate structure, but also increases the manufacturing process of
  • the present application provides an array substrate, a manufacturing method thereof, and a display panel to solve the problem of adding a layer of metal wiring in parallel with the original data lines and scan lines to reduce the resistance in the existing ultra-narrow bezel display panel, and adding a process more, which increases the technical problems of production cost and production time.
  • the present application provides an array substrate, comprising a substrate, a first metal layer disposed on the substrate, a first metal layer disposed on the substrate and the first metal layer and covering the first metal layer an insulating layer, a second metal layer disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and the second metal layer and covering the second metal layer, a third metal layer on the second insulating layer;
  • the first metal layer includes first data traces and first vertical scan lines
  • the second metal layer includes horizontal scan lines
  • the third metal layer includes second data traces and second vertical scan lines
  • a first via hole and a second via hole passing through the first insulating layer and the second insulating layer are arranged above the first metal layer
  • a third via hole is arranged on the second insulating layer
  • the A second data line passes through the first via hole in parallel with the first data line
  • the second vertical scan line passes through the second via hole in parallel with the first vertical scan line
  • the second vertical scan line is connected to the horizontal scan line through the third via hole, wherein the first via hole, the second via hole and the third via hole are integrally formed through the same process.
  • the array substrate includes a plurality of sub-pixel regions, the first via hole and the second via hole are located between the sub-pixel regions, and the third via hole is located in the sub-pixel region. within the sub-pixel area.
  • the second metal layer further includes a common electrode and a gate connected to the horizontal scan line.
  • an active layer corresponding to the position of the gate is disposed on the second insulating layer, and the third metal layer further includes a source disposed on the active layer pole and drain.
  • the array substrate further comprises a layer disposed on the second insulating layer, the third metal layer and the active layer and covering the third metal layer and the active layer
  • the passivation protection layer is provided on the passivation protection layer, a color resist layer is provided on the color resist layer, a flat insulating layer is provided on the color resist layer, a pixel electrode layer is provided on the flat insulating layer, and a through-hole is provided on the drain electrode passing through the passivation protection layer, the color resist layer and the fourth via hole of the flat insulating layer, the pixel electrode layer is connected to the drain electrode through the fourth via hole.
  • the present application also provides a method for fabricating an array substrate, comprising the following steps:
  • the substrate providing a substrate, and forming a first metal layer on the substrate, the first metal layer including a first data trace and a first vertical scan line formed on the substrate;
  • a first insulating layer covering the first metal layer is formed on the substrate and the first metal layer, a second metal layer is formed on the first insulating layer, and the second metal layer includes a horizontal scan line on the first insulating layer, and a second insulating layer covering the second metal layer is formed on the first insulating layer and the second metal layer;
  • a first via hole and a second via hole are formed over the first metal layer through the first insulating layer and the second insulating layer, and a third via hole is formed over the second insulating layer, wherein , the first via hole, the second via hole and the third via hole are integrally formed through the same process;
  • a third metal layer is formed on the second insulating layer, the third metal layer includes a second data wiring and a second vertical scan line formed on the second insulating layer, the second data wiring Passing through the first via hole in parallel with the first data trace, the second vertical scan line passing through the second via hole in parallel with the first vertical scan line, and the second vertical scan line in parallel Connect to the horizontal scan line through the third via hole.
  • the first via hole, the second via hole and the third via hole are integrally formed by a grayscale mask.
  • the second metal layer further includes a common electrode formed on the first insulating layer, and a gate electrode connected to the horizontal scan line.
  • the first via hole and the second via hole are formed above the first metal layer and pass through the first insulating layer and the second insulating layer, Before forming the third via hole on the second insulating layer, the method further includes forming an active layer corresponding to the gate position on the second insulating layer;
  • the third metal layer further includes source and drain electrodes formed on the active layer.
  • the present application further provides a display panel, the display panel includes a color filter substrate and the array substrate as described in the previous embodiments, and a liquid crystal layer is disposed between the color filter substrate and the array substrate.
  • the beneficial effects of the present application are: in the present application, the first metal layer is configured to include the first data wiring and the first vertical scan line, the second metal layer is configured to include the horizontal scan line, and the third metal layer is configured to include the horizontal scan line.
  • the layer is set to include a second data line and a second vertical scan line; the first via hole, the second vertical scan line and all the required first data lines and the first data line in parallel
  • the second via hole required for the parallel connection of the first vertical scan line and the third via hole required for the connection between the second vertical scan line and the horizontal scan line can be integrally formed through the same process, ensuring that the Under the condition that the resistance of the first data wiring and the first vertical scan line is reduced by adding a third metal layer, the preparation steps of the array substrate are reduced, and the production cost and production time of the display panel are reduced as a whole.
  • FIG. 1 is a schematic diagram of a hierarchical structure of a conventional array substrate
  • FIG. 2 is a schematic diagram of a hierarchical structure of an array substrate according to an embodiment of the present application
  • FIG. 3 is a top view of an array substrate in an embodiment of the present application.
  • 4A to 4K are hierarchical structure flowcharts of a manufacturing process of an array substrate according to an embodiment of the present application.
  • 5A-5E are top-view structural flow charts of a manufacturing process of an array substrate in an embodiment of the present application.
  • FIG. 6 is a schematic block diagram of a process flow of a first method for fabricating an array substrate according to an embodiment of the present application
  • FIG. 7 is a schematic flowchart of a method for fabricating a second array substrate according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • the present application provides an array substrate 20, as shown in FIG. 2 to FIG. 3, comprising a substrate 21, a first metal layer 22 disposed on the substrate 21, a first metal layer 22 disposed on the substrate 21 and the first metal layer 22.
  • the first metal layer 22 includes first data lines 221 and first vertical scan lines 222
  • the second metal layer 24 includes horizontal scan lines 241
  • the third metal layer 26 includes second data lines 261 and
  • a first via hole 201 and a second via hole 202 are arranged above the first metal layer 22 and pass through the first insulating layer 23 and the second insulating layer 25 .
  • a third via hole 203 is formed on the two insulating layers 25 , the second data line 261 is connected in parallel with the first data line 221 through the first via hole 201 , and the second vertical scan line 262 passes through The second vertical scan line 262 is connected in parallel with the first vertical scan line 222 through the second via hole 202, and the second vertical scan line 262 is connected to the horizontal scan line 241 through the third via hole 203.
  • a via hole 201 , a second via hole 202 and the third via hole 203 are integrally formed through the same process.
  • a layer of metal wiring is added to the array substrate in parallel with the original data lines and scan lines to reduce resistance; specifically, as shown in Figure 1, the sequence includes stacking The substrate 11, the metal layer 1 12, the insulating layer 1 13, the metal layer 2 14, the insulating layer 2 15, and the metal layer 3 16 are provided.
  • the metal layer three 16 is a new metal layer used to reduce resistance in parallel with the scan vertical line one 141 and the data line one 142, the metal layer three 16 includes the scan vertical line one 141 in parallel.
  • this structure not only increases the complexity of the structure of the array substrate 20, but also increases the manufacturing process of forming the metal layer 3 16 and forming the via hole 2 151 in the insulating layer 2 15, The production cost and production time are improved; in this embodiment, by setting the first metal layer 22 to include the first data traces 221 and the first vertical scan lines 222, the second metal layer 24 is configured to include horizontal scan lines Line 241, the third metal layer 26 is set to include a second data line 261 and a second vertical scan line
  • the required third vias 203 can be integrally formed through the same process, and the array is reduced on the condition that the resistance of the first data traces 221 and the first vertical scan lines 222 is reduced by adding a third metal layer 26.
  • the preparation steps of the substrate 20 reduce the production cost and production time of the display panel as a whole.
  • the orthographic projection of the second data trace 261 on the substrate 21 may coincide with the orthographic projection of the first data trace 221 on the substrate 21
  • the orthographic projection of the second vertical scan line 262 on the substrate 21 may coincide with the orthographic projection of the first vertical scan line 222 on the substrate 21;
  • the effect is better.
  • the thickness and/or width of the second data line 261 can be set to be larger.
  • the The thickness and/or width of the second vertical scan line 262 may be set to be larger.
  • the array substrate 20 includes a plurality of sub-pixel regions 200 , and the first via hole 201 and the second via hole 202 are located between the sub-pixel regions 200 .
  • the third via hole 203 is located in the sub-pixel region 200; it can be understood that the first via hole 201 and the second via hole 202 are located between the sub-pixel regions 200, that is, The first via hole 201 and the second via hole 202 are located in the non-transparent non-effective display area, specifically, the first via hole 201 and the second via hole 202 In the area covered by the black matrix, the overall transmittance of the array substrate 20 is not affected.
  • the first data traces 221 are connected in parallel in the non-effective display area, and the second vertical scan lines 262 and the first vertical scan lines 222 are connected in parallel in the non-effective display area, in order to reduce the penetration of the array substrate 20.
  • Influence of transmittance in this embodiment, the first via hole 201 and the second via hole 202 are arranged between each of the sub-pixel regions 200, and the functional structures in the sub-pixel region 200 are also avoided. Too dense, the overall structure layout is more reasonable.
  • the second metal layer 24 further includes a common electrode 242 and a gate electrode 243 connected to the horizontal scan line 241 ; it can be understood that in this embodiment, the , the gate 243 and the horizontal scanning line 241 are arranged in the same layer between the first insulating layer 23 and the second insulating layer 25 to avoid the gate 243 and the horizontal scanning.
  • the lines 241 are disposed in different layers, additional via holes are required when the gate electrodes 243 and the horizontal scan lines 241 are connected, thereby increasing the process steps for the fabrication of the array substrate 20 .
  • the second insulating layer 25 is provided with an active layer 27 corresponding to the position of the gate electrode 243
  • the third metal layer 26 further includes an active layer 27 .
  • the metal layer 26 further includes a source electrode 263 and a drain electrode 264 disposed on the active layer 27 , so that the source electrode 263 , the drain electrode 264 and the gate electrode 243 in the array substrate 20 are farther away from the
  • the substrate 21 is arranged to avoid the need to make via holes in the first insulating layer 23 before the second insulating layer 25 is fabricated, which reduces the complexity of fabrication.
  • the array substrate 20 further includes a layer disposed on the second insulating layer 25 , the third metal layer 26 and the active layer 27 and covering the third metal layer 26 and the passivation protective layer 281 of the active layer 27, a color resist layer 282 is provided on the passivation protective layer 281, a flat insulating layer 283 is provided on the color resist layer 282, and a flat insulating layer 283 is provided on the color resist layer 282.
  • a pixel electrode layer 284 is provided, a fourth via hole 204 passing through the passivation protection layer 281 , the color resist layer 282 and the flat insulating layer 283 is provided above the drain electrode 264 , and the pixel electrode layer 284 passes through It is connected to the drain electrode 264 through the fourth via hole 204;
  • the material of the flat insulating layer 283 is an organic insulating material
  • the flat insulating layer 283 is PFA (Polymer Film Specifically, since the active layer 27 is disposed on the second insulating layer 25, and the third metal layer 26 also includes an organic film disposed on the active layer The source electrode 263 and the drain electrode 264 on the 27, so that the source electrode 263 and the drain electrode 264 in the array substrate 20 are closer to the pixel electrode layer 284, reducing the fourth via hole 204 to pass through Therefore, the hole depth of the fourth via hole 204 is reduced, and it is also convenient to reduce the manufacturing time and manufacturing difficulty of the process.
  • the present application also provides a method for fabricating the array substrate 20, as shown in FIG. 6, including the following steps:
  • Step S10 As shown in FIG. 4A and FIG. 5A , a substrate 21 is provided, and a first metal layer 22 is formed on the substrate 21 , and the first metal layer 22 includes the first metal layer 22 formed on the substrate 21 . a data trace 221 and a first vertical scan line 222;
  • Step S20 As shown in FIG. 4B to FIG. 4D and FIG. 5B, forming a first insulating layer 23 covering the first metal layer 22 on the substrate 21 and the first metal layer 22, and forming a first insulating layer 23 on the substrate 21 and the first metal layer 22.
  • a second metal layer 24 is formed on the first insulating layer 23, the second metal layer 24 includes horizontal scan lines 241 formed on the first insulating layer 23, and the first insulating layer 23 and the second metal layer
  • a second insulating layer 25 covering the second metal layer 24 is formed on the layer 24;
  • Step S30 as shown in FIGS. 4E to 4F and FIGS. 5C to 5D , forming a first pass through the first insulating layer 23 and the second insulating layer 25 over the first metal layer 22 .
  • the hole 201 and the second via hole 202, the third via hole 203 is formed on the second insulating layer 25, wherein the first via hole 201, the second via hole 202 and the third via hole 203 pass through the same Integrated molding process;
  • Step S40 as shown in FIG. 4G and FIG. 5E , a third metal layer 26 is formed on the second insulating layer 25 , and the third metal layer 26 includes the second data formed on the second insulating layer 25 A trace 261 and a second vertical scan line 262, the second data trace 261 is connected in parallel with the first data trace 221 through the first via hole 201, and the second vertical scan line 262 passes through the The second via hole 202 is connected in parallel with the first vertical scan line 222 , and the second vertical scan line 262 is connected to the horizontal scan line 241 through the third via hole 203 .
  • the substrate 21 may be a glass substrate, and the first data traces 221 and the first vertical scan lines 222 in the first metal layer 22 are integrally formed by the same process.
  • the second data traces 261 and the second vertical scan lines 262 in the third metal layer 26 are integrally formed using the same process.
  • the first metal layer 22 is first fabricated and formed on the substrate 21, and a first insulating layer 23 covering the first metal layer 22 is formed on the substrate 21 and the first metal layer 22, and then A second metal layer 24 including the horizontal scan lines 241 is fabricated and formed on the first insulating layer 23 , and a second metal layer covering the first insulating layer 23 and the second metal layer 24 is formed
  • the second insulating layer 25 of the The first via hole 201 required for the parallel connection of the first data trace 221, the second via hole 202 required for the parallel connection between the second vertical scan line 262 and the first vertical scan line 222, and the second vertical scan line
  • the third via hole 203 required for connection between 262 and the horizontal scan line 241 can be integrally formed by the same process, which ensures that the first data line 221 and the first vertical scan line 221 and the first vertical scan line are reduced by adding a third metal layer 26.
  • the preparation steps of the array substrate 20 are reduced, and the production cost and production time of the display panel are reduced as a whole.
  • the first via hole 201 , the second via hole 202 and the third via hole 203 are integrally formed by a grayscale mask.
  • the second metal layer 24 further includes a common electrode 242 formed on the first insulating layer 23 and the horizontal scan line. 241 connected to the gate 243; it can be understood that the common electrode 242, the gate 243 and the horizontal scan line 241 are disposed in the same layer, and are integrally formed by the same process.
  • the first insulating layer 23 and the second insulating layer 25 are formed above the first metal layer 22 .
  • the method further includes forming on the second insulating layer 25 corresponding to the position of the gate electrode 243 . active layer 27;
  • the third metal layer 26 further includes a source electrode 263 and a drain electrode 264 formed on the active layer 27 .
  • the manufacturing method of the array substrate 20 further includes step S50 : as shown in FIGS. 4H to 4K , in the second insulating layer 25 , the third metal layer 26 and the A passivation protection layer 281 covering the third metal layer 26 and the active layer 27 is formed on the active layer 27, a color resist layer 282 is formed on the passivation protection layer 281, and a color resist layer is formed on the color resist layer A flat insulating layer 283 is formed on 282 , a fourth via hole 204 is formed over the drain 264 through the passivation protection layer 281 , the color resist layer 282 and the flat insulating layer 283 , and a fourth via hole 204 is formed on the flat insulating layer A pixel electrode layer 284 is formed on the 283 , and the pixel electrode layer 284 is connected to the drain electrode 264 through the fourth via hole 204 .
  • the present application also provides a display panel.
  • the display panel includes a color filter substrate 30 and the array substrate 20 described in the previous embodiment, and the color filter substrate 30 and the array substrate 20 are located between the color filter substrate 30 and the array substrate 20 .
  • a liquid crystal layer 40 is provided.
  • the The third metal layer 26 is configured to include second data traces 261 and second vertical scan lines 262; the first vias 201, The second via hole 202 required for the parallel connection between the second vertical scan line 262 and the first vertical scan line 222 , and the third via hole 202 required for the connection between the second vertical scan line 262 and the horizontal scan line 241
  • the via hole 203 can be integrally formed by the same process, and the fabrication steps of the array substrate 20 are reduced under the condition that the resistance of the first data trace 221 and the first vertical scan line 222 is reduced by adding the third metal layer 26 . The overall production cost and production time of the display panel are reduced.

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Abstract

本申请提出了一种阵列基板及其制作方法、显示面板，所述阵列基板包括衬底、第一金属层、第二金属层、及第三金属层；第一金属层包括第一数据走线和第一垂直扫描线，第二金属层包括水平扫描线，第三金属层包括第二数据走线和第二垂直扫描线，所述第一金属层上方设有第一过孔和第二过孔，所述第二绝缘层上设有第三过孔。

Description

阵列基板及其制作方法、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示面板。
 背景技术
随着显示技术的发展，显示面板的窄边框化已成为行业关注的焦点，超窄边框的显示面板可以实现面板的无缝拼接，现有超窄边框主要通过GOA（Gate driver in COF）的结构实现，也即是把扫描线信号输出功能设计在与数据线同一COF（Chip On Film，覆晶薄膜）侧，从而减小显示面板两侧边框宽度，实现“三窄一宽”的显示效果，此种结构下，诸如扫描线、数据线等走线的密度增加，而为了不影响像素开口率，使扫描线和数据线等走线设计得较窄，增加了扫描线和数据线等走线的电阻电容，容易产生信号传输延迟（RC loading）和像素充电不足的问题。
 技术问题
目前，为解决上述问题，一般采用在所述阵列基板中增加一层金属走线与原有的数据线和扫描线并联以减小电阻；具体的，如图1所示，依次包括层叠设置的基底11、金属层一12、绝缘层一13、金属层二14、绝缘层二15、金属层三16，金属层一12包括扫描横线121，金属层二14包括扫描纵线一141和数据线一142，所述金属层三16为用于与扫描纵线一141和数据线一142并联减少电阻新增金属层，所述金属层三16包括与扫描纵线一141并联的扫描纵线三161、以及与数据线一142并联的数据线二162；显然，需要分别在所述绝缘层一13上形成过孔一131、以及在所述绝缘层二15形成过孔二151，以实现上述各金属层之间的连接，该结构不仅增加了阵列基板结构的复杂度，还增加了形成金属层三16和在所述绝缘层二15形成过孔二151的制作工艺，提高了生产成本和生产时间。
 技术解决方案
本申请提供一种阵列基板及其制作方法、显示面板，以解决现有超窄边框显示面板中通过增加一层金属走线与原有的数据线和扫描线并联以减小电阻后，增加工序较多，提高了生产成本和生产时间的技术问题。
为解决上述问题，本申请提供的技术方案如下：
本申请提供了一种阵列基板，包括衬底、设置于所述衬底上的第一金属层、设置于所述衬底和所述第一金属层上且覆盖所述第一金属层的第一绝缘层、设置于所述第一绝缘层上的第二金属层、设置于所述第一绝缘层和所述第二金属层上且覆盖所述第二金属层的第二绝缘层、设置于所述第二绝缘层上的第三金属层；
所述第一金属层包括第一数据走线和第一垂直扫描线，所述第二金属层包括水平扫描线，所述第三金属层包括第二数据走线和第二垂直扫描线，所述第一金属层上方设有穿过所述第一绝缘层和所述第二绝缘层的第一过孔和第二过孔，所述第二绝缘层上设有第三过孔，所述第二数据走线穿过所述第一过孔与所述第一数据走线并联，所述第二垂直扫描线穿过所述第二过孔与所述第一垂直扫描线并联，所述第二垂直扫描线穿过所述第三过孔与所述水平扫描线连接，其中，所述第一过孔、第二过孔和所述第三过孔通过同一道制程一体成型。
在本申请所提供的阵列基板中，所述阵列基板包括多个子像素区，所述第一过孔和所述第二过孔位于各所述子像素区之间，所述第三过孔位于所述子像素区内。
在本申请所提供的阵列基板中，所述第二金属层还包括公共电极、及与所述水平扫描线连接的栅极。
在本申请所提供的阵列基板中，所述第二绝缘层上设有与所述栅极位置相对应的有源层，所述第三金属层还包括设置于所述有源层上的源极和漏极。
在本申请所提供的阵列基板中，所述阵列基板还包括设置于所述第二绝缘层、第三金属层和所述有源层上且覆盖所述第三金属层和所述有源层的钝化保护层，所述钝化保护层上设有色阻层，所述色阻层上设有平坦绝缘层，所述平坦绝缘层上设有像素电极层，所述漏极上方设有穿过所述钝化保护层、色阻层和所述平坦绝缘层的第四过孔，所述像素电极层穿过所述第四过孔与所述漏极连接。
本申请还提供一种阵列基板的制作方法，包括以下步骤：
提供一衬底，在所述衬底上形成第一金属层，所述第一金属层包括形成于所述衬底上的第一数据走线和第一垂直扫描线；
在所述衬底和所述第一金属层上形成覆盖所述第一金属层的第一绝缘层，在所述第一绝缘层上形成第二金属层，所述第二金属层包括形成于所述第一绝缘层上水平扫描线，在所述第一绝缘层和所述第二金属层上形成覆盖所述第二金属层的第二绝缘层；
在所述第一金属层上方形成穿过所述第一绝缘层和所述第二绝缘层的第一过孔和第二过孔，在所述第二绝缘层上形成第三过孔，其中，所述第一过孔、第二过孔和所述第三过孔通过同一道制程一体成型；及
在所述第二绝缘层上形成第三金属层，所述第三金属层包括形成于所述第二绝缘层上的第二数据走线和第二垂直扫描线，所述第二数据走线穿过所述第一过孔与所述第一数据走线并联，所述第二垂直扫描线穿过所述第二过孔与所述第一垂直扫描线并联，所述第二垂直扫描线穿过所述第三过孔与所述水平扫描线连接。
在本申请所提供阵列基板的制作方法中，所述第一过孔、第二过孔和所述第三过孔采用灰阶光罩的方式一体成型。
在本申请所提供阵列基板的制作方法中，所述第二金属层还包括形成于所述第一绝缘层上的公共电极、及与所述水平扫描线连接的栅极。
在本申请所提供阵列基板的制作方法中，所述在所述第一金属层上方形成穿过所述第一绝缘层和所述第二绝缘层的第一过孔和第二过孔，在所述第二绝缘层上形成第三过孔之前，还包括在所述第二绝缘层上形成与所述栅极位置相对应的有源层；
所述第三金属层还包括形成于所述有源层上的源极和漏极。
本申请还提供一种显示面板，所述显示面板包括彩膜基板和如前实施例所述的阵列基板，所述彩膜基板与所述阵列基板之间设置有液晶层。
 有益效果
本申请的有益效果为：本申请通过将第一金属层设置为包括第一数据走线和第一垂直扫描线，将所述第二金属层设置为包括水平扫描线，将所述第三金属层设置为包括第二数据走线和第二垂直扫描线；使得所述第二数据走线与所述第一数据走线并联所需的第一过孔、所述第二垂直扫描线与所述第一垂直扫描线并联所需的第二过孔、所述第二垂直扫描线与所述水平扫描线连接所需的所述第三过孔可以通过同一道制程一体成型，在保证了通过新增第三金属层减少第一数据走线和第一垂直扫描线电阻的条件下，减少了阵列基板的制备步骤，整体降低了显示面板的生产成本和生产时间。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为现有阵列基板的层级结构示意图；
图2为本申请实施例中阵列基板的层级结构示意图；
图3为本申请实施例中阵列基板的俯视图；
图4A-图4K为本申请实施例中阵列基板制作过程的层级结构流程图；
图5A-图5E为本申请实施例中阵列基板制作过程的俯视结构流程图；
图6为本申请实施例中第一种阵列基板的制作方法的流程示意框图；
图7为本申请实施例中第二种阵列基板的制作方法的流程示意框图；及
图8为本申请实施例中显示面板的结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
现结合具体实施例对本申请的技术方案进行描述。
本申请提供了一种阵列基板20，如图2至图3所示，包括衬底21、设置于所述衬底21上的第一金属层22、设置于所述衬底21和所述第一金属层22上且覆盖所述第一金属层22的第一绝缘层23、设置于所述第一绝缘层23上的第二金属层24、设置于所述第一绝缘层23和所述第二金属层24上且覆盖所述第二金属层24的第二绝缘层25、设置于所述第二绝缘层25上的第三金属层26；
所述第一金属层22包括第一数据走线221和第一垂直扫描线222，所述第二金属层24包括水平扫描线241，所述第三金属层26包括第二数据走线261和第二垂直扫描线262，所述第一金属层22上方设有穿过所述第一绝缘层23和所述第二绝缘层25的第一过孔201和第二过孔202，所述第二绝缘层25上设有第三过孔203，所述第二数据走线261穿过所述第一过孔201与所述第一数据走线221并联，所述第二垂直扫描线262穿过所述第二过孔202与所述第一垂直扫描线222并联，所述第二垂直扫描线262穿过所述第三过孔203与所述水平扫描线241连接，其中，所述第一过孔201、第二过孔202和所述第三过孔203通过同一道制程一体成型。
可以理解的是，目前，为解决窄边框显示面板中扫描线和数据线等走线设计得较窄，增加了扫描线和数据线等走线的电阻电容，容易产生信号传输延迟（RC loading）和像素充电不足的问题，一般采用在所述阵列基板中增加一层金属走线与原有的数据线和扫描线并联以减小电阻；具体的，如图1所示，依次包括层叠设置的基底11、金属层一12、绝缘层一13、金属层二14、绝缘层二15、金属层三16，金属层一12包括扫描横线121，金属层二14包括扫描纵线一141和数据线一142，所述金属层三16为用于与扫描纵线一141和数据线一142并联减少电阻新增金属层，所述金属层三16包括与扫描纵线一141并联的扫描纵线三161、以及与数据线一142并联的数据线二162；显然，需要分别在所述绝缘层一13上形成过孔一131、以及在所述绝缘层二15形成过孔二151，以实现上述各金属层之间的连接，该结构不仅增加了阵列基板20结构的复杂度，还增加了形成金属层三16和在所述绝缘层二15形成过孔二151的制做工艺，提高了生产成本和生产时间；本实施例中，通过将第一金属层22设置为包括第一数据走线221和第一垂直扫描线222，将所述第二金属层24设置为包括水平扫描线241，将所述第三金属层26设置为包括第二数据走线261和第二垂直扫描线262；使得所述第二数据走线261与所述第一数据走线221并联所需的第一过孔201、所述第二垂直扫描线262与所述第一垂直扫描线222并联所需的第二过孔202、所述第二垂直扫描线262与所述水平扫描线241连接所需的所述第三过孔203可以通过同一道制程一体成型，在保证了通过新增第三金属层26减少第一数据走线221和第一垂直扫描线222电阻的条件下，减少了阵列基板20的制备步骤，整体降低了显示面板的生产成本和生产时间。
值得注意的是，如图3所示，所述第二数据走线261在所述衬底21上的正投影可以与所述第一数据走线221在所述衬底21上的正投影重合，所述第二垂直扫描线262在所述衬底21上的正投影可以与所述第一垂直扫描线222在所述衬底21上的正投影重合；当然，为使得并联减小电阻的效果更好，相较于所述第一数据走线221，所述第二数据走线261的厚度和/或宽度可以设置的更大，相较于所述第一垂直扫描线222，所述第二垂直扫描线262的厚度和/或宽度可以设置的更大。
在一实施例中，如图5D所示，所述阵列基板20包括多个子像素区200，所述第一过孔201和所述第二过孔202位于各所述子像素区200之间，所述第三过孔203位于所述子像素区200内；可以理解的是，将所述第一过孔201和所述第二过孔202位于各所述子像素区200之间，也即是将所述第一过孔201和所述第二过孔202位于不透光的非有效显示区内，具体的，所述第一过孔201和所述第二过孔202设置于被诸如黑色矩阵所覆盖的区域内，不影响阵列基板20整体的穿透率，此外，所述第一过孔201和所述第二过孔202用于使所述第二数据走线261与所述第一数据走线221在非有效显示区内并联、以及使所述第二垂直扫描线262与所述第一垂直扫描线222在非有效显示区内并联，为减少对所述阵列基板20穿透率的影响，本实施例中，将所述第一过孔201和所述第二过孔202设置于各所述子像素区200之间，也避免所述子像素区200内各功能结构太过密集，整体结构布局更加合理。
在一实施例中，如图5B至图5E所示，所述第二金属层24还包括公共电极242、及与所述水平扫描线241连接的栅极243；可以理解的是，本实施例中，将所述栅极243与所述水平扫描线241同层设置于所述第一绝缘层23与所述第二绝缘层25之间的位置，避免所述栅极243与所述水平扫描线241异层设置时，在所述栅极243与所述水平扫描线241连接时需要额外的过孔，而增加所述阵列基板20制作的工艺步骤。
在一实施例中，如图2至图3所示，所述第二绝缘层25上设有与所述栅极243位置相对应的有源层27，所述第三金属层26还包括设置于所述有源层27上的源极263和漏极264；可以理解的是，本实施例中，所述有源层27设置于所述第二绝缘层25上，并且，所述第三金属层26还包括设置于所述有源层27上的源极263和漏极264，使得所述阵列基板20中的所述源极263、漏极264和所述栅极243更远离所述衬底21进行设置，避免在制作所述第二绝缘层25之前必须对所述第一绝缘层23进行过孔的制作，降低了制作的复杂度。
在一实施例中，如图2所示，所述阵列基板20还包括设置于所述第二绝缘层25、第三金属层26和所述有源层27上且覆盖所述第三金属层26和所述有源层27的钝化保护层281，所述钝化保护层281上设有色阻层282，所述色阻层282上设有平坦绝缘层283，所述平坦绝缘层283上设有像素电极层284，所述漏极264上方设有穿过所述钝化保护层281、色阻层282和所述平坦绝缘层283的第四过孔204，所述像素电极层284穿过所述第四过孔204与所述漏极264连接；可以理解的是，本实施例中，所述平坦绝缘层283的材料为有机绝缘材料，所述平坦绝缘层283为PFA(Polymer Film on Array，阵列基板侧有机膜)；具体的，由于将所述有源层27设置于所述第二绝缘层25上，并且，所述第三金属层26还包括设置于所述有源层27上的源极263和漏极264，使得所述阵列基板20中的所述源极263和所述漏极264更靠近所述像素电极层284，减少了所述第四过孔204所要穿过的膜层数量，从而降低了所述第四过孔204的孔深，也便于降低工艺的制作时间和制作难度。
本申请还提供一种阵列基板20的制作方法，如图6所示，包括以下步骤：
步骤S10：如图4A和图5A所示，提供一衬底21，在所述衬底21上形成第一金属层22，所述第一金属层22包括形成于所述衬底21上的第一数据走线221和第一垂直扫描线222；
步骤S20：如图4B至图4D、以及图5B所示，在所述衬底21和所述第一金属层22上形成覆盖所述第一金属层22的第一绝缘层23，在所述第一绝缘层23上形成第二金属层24，所述第二金属层24包括形成于所述第一绝缘层23上水平扫描线241，在所述第一绝缘层23和所述第二金属层24上形成覆盖所述第二金属层24的第二绝缘层25；
步骤S30：如图4E至图4F、以及图5C至图5D所示，在所述第一金属层22上方形成穿过所述第一绝缘层23和所述第二绝缘层25的第一过孔201和第二过孔202，在所述第二绝缘层25上形成第三过孔203，其中，所述第一过孔201、第二过孔202和所述第三过孔203通过同一道制程一体成型；及
步骤S40：如图4G和图5E所示，在所述第二绝缘层25上形成第三金属层26，所述第三金属层26包括形成于所述第二绝缘层25上的第二数据走线261和第二垂直扫描线262，所述第二数据走线261穿过所述第一过孔201与所述第一数据走线221并联，所述第二垂直扫描线262穿过所述第二过孔202与所述第一垂直扫描线222并联，所述第二垂直扫描线262穿过所述第三过孔203与所述水平扫描线241连接。
可以理解的是，所述衬底21可以是玻璃基板，所述第一金属层22中的所述第一数据走线221和所述第一垂直扫描线222采用同一道制程一体成型，所述第三金属层26中的第二数据走线261和第二垂直扫描线262采用同一道制程一体成型，在制作过程中，通过将包括第一数据走线221和第一垂直扫描线222的所述第一金属层22先制作形成于所述衬底21上，并在所述衬底21和所述第一金属层22上形成覆盖所述第一金属层22的第一绝缘层23，然后将包括所述水平扫描线241的第二金属层24制作形成于第一绝缘层23上，并在所述第一绝缘层23和所述第二金属层24上形成覆盖所述第二金属层24的第二绝缘层25，最后将包括所述第二数据走线261和所述第二垂直扫描线262制作形成于第二绝缘层25上，使得所述第二数据走线261与所述第一数据走线221并联所需的第一过孔201、所述第二垂直扫描线262与所述第一垂直扫描线222并联所需的第二过孔202、所述第二垂直扫描线262与所述水平扫描线241连接所需的所述第三过孔203可以通过同一道制程一体成型，在保证了通过新增第三金属层26减少第一数据走线221和第一垂直扫描线222电阻的条件下，减少了阵列基板20的制备步骤，整体降低了显示面板的生产成本和生产时间。本实施例中，所述第一过孔201、第二过孔202和所述第三过孔203采用灰阶光罩的方式一体成型。
在一实施例中，如图5B至图5D、以及图2所示，所述第二金属层24还包括形成于所述第一绝缘层23上的公共电极242、及与所述水平扫描线241连接的栅极243；可以理解的是，所述公共电极242、栅极243和所述水平扫描线241同层设置，并且采用同一道制程一体成型。
在一实施例中，如图4D至图4F、以及图5C所示，所述在所述第一金属层22上方形成穿过所述第一绝缘层23和所述第二绝缘层25的第一过孔201和第二过孔202，在所述第二绝缘层25上形成第三过孔203之前，还包括在所述第二绝缘层25上形成与所述栅极243位置相对应的有源层27；
所述第三金属层26还包括形成于所述有源层27上的源极263和漏极264。
在一实施例中，如图7所示，所述阵列基板20的制作方法还包括步骤S50：如图4H至图4K所示，在所述第二绝缘层25、第三金属层26和所述有源层27上形成覆盖所述第三金属层26和所述有源层27的钝化保护层281，在所述钝化保护层281上形成色阻层282，在所述色阻层282上形成平坦绝缘层283，在所述漏极264上方形成穿过所述钝化保护层281、色阻层282和所述平坦绝缘层283的第四过孔204，在所述平坦绝缘层283上形成像素电极层284，所述像素电极层284穿过所述第四过孔204与所述漏极264连接。
本申请还提供一种显示面板，如图8所示，所述显示面板包括彩膜基板30和如前实施例所述的阵列基板20，所述彩膜基板30与所述阵列基板20之间设置有液晶层40。
综上所述，本申请通过将第一金属层22设置为包括第一数据走线221和第一垂直扫描线222，将所述第二金属层24设置为包括水平扫描线241，将所述第三金属层26设置为包括第二数据走线261和第二垂直扫描线262；使得所述第二数据走线261与所述第一数据走线221并联所需的第一过孔201、所述第二垂直扫描线262与所述第一垂直扫描线222并联所需的第二过孔202、所述第二垂直扫描线262与所述水平扫描线241连接所需的所述第三过孔203可以通过同一道制程一体成型，在保证了通过新增第三金属层26减少第一数据走线221和第一垂直扫描线222电阻的条件下，减少了阵列基板20的制备步骤，整体降低了显示面板的生产成本和生产时间。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (16)

  1. 一种阵列基板，包括衬底、设置于所述衬底上的第一金属层、设置于所述衬底和所述第一金属层上且覆盖所述第一金属层的第一绝缘层、设置于所述第一绝缘层上的第二金属层、设置于所述第一绝缘层和所述第二金属层上且覆盖所述第二金属层的第二绝缘层、设置于所述第二绝缘层上的第三金属层；
    所述第一金属层包括第一数据走线和第一垂直扫描线，所述第二金属层包括水平扫描线，所述第三金属层包括第二数据走线和第二垂直扫描线，所述第一金属层上方设有穿过所述第一绝缘层和所述第二绝缘层的第一过孔和第二过孔，所述第二绝缘层上设有第三过孔，所述第二数据走线穿过所述第一过孔与所述第一数据走线并联，所述第二垂直扫描线穿过所述第二过孔与所述第一垂直扫描线并联，所述第二垂直扫描线穿过所述第三过孔与所述水平扫描线连接，其中，所述第一过孔、第二过孔和所述第三过孔通过同一道制程一体成型。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板包括多个子像素区，所述第一过孔和所述第二过孔位于各所述子像素区之间，所述第三过孔位于所述子像素区内。
  3. 根据权利要求1所述的阵列基板，其中，所述第二金属层还包括公共电极、及与所述水平扫描线连接的栅极。
  4. 根据权利要求3所述的阵列基板，其中，所述第二绝缘层上设有与所述栅极位置相对应的有源层，所述第三金属层还包括设置于所述有源层上的源极和漏极。
  5. 根据权利要求4所述的阵列基板，其中，所述阵列基板还包括设置于所述第二绝缘层、第三金属层和所述有源层上且覆盖所述第三金属层和所述有源层的钝化保护层，所述钝化保护层上设有色阻层，所述色阻层上设有平坦绝缘层，所述平坦绝缘层上设有像素电极层，所述漏极上方设有穿过所述钝化保护层、色阻层和所述平坦绝缘层的第四过孔，所述像素电极层穿过所述第四过孔与所述漏极连接。
  6. 一种阵列基板的制作方法，包括以下步骤：
    提供一衬底，在所述衬底上形成第一金属层，所述第一金属层包括形成于所述衬底上的第一数据走线和第一垂直扫描线；
    在所述衬底和所述第一金属层上形成覆盖所述第一金属层的第一绝缘层，在所述第一绝缘层上形成第二金属层，所述第二金属层包括形成于所述第一绝缘层上水平扫描线，在所述第一绝缘层和所述第二金属层上形成覆盖所述第二金属层的第二绝缘层；
    在所述第一金属层上方形成穿过所述第一绝缘层和所述第二绝缘层的第一过孔和第二过孔，在所述第二绝缘层上形成第三过孔，其中，所述第一过孔、第二过孔和所述第三过孔通过同一道制程一体成型；及
    在所述第二绝缘层上形成第三金属层，所述第三金属层包括形成于所述第二绝缘层上的第二数据走线和第二垂直扫描线，所述第二数据走线穿过所述第一过孔与所述第一数据走线并联，所述第二垂直扫描线穿过所述第二过孔与所述第一垂直扫描线并联，所述第二垂直扫描线穿过所述第三过孔与所述水平扫描线连接。
  7. 根据权利要求6所述阵列基板的制作方法，其中，所述第一过孔、第二过孔和所述第三过孔采用灰阶光罩的方式一体成型。
  8. 根据权利要求7所述阵列基板的制作方法，其中，所述阵列基板包括多个子像素区，所述第一过孔和所述第二过孔形成于各所述子像素区之间，所述第三过孔形成于所述子像素区内。
  9. 根据权利要求6所述阵列基板的制作方法，其中，所述第二金属层还包括形成于所述第一绝缘层上的公共电极、及与所述水平扫描线连接的栅极。
  10. 根据权利要求9所述阵列基板的制作方法，其中，所述在所述第一金属层上方形成穿过所述第一绝缘层和所述第二绝缘层的第一过孔和第二过孔，在所述第二绝缘层上形成第三过孔之前，还包括在所述第二绝缘层上形成与所述栅极位置相对应的有源层；
    所述第三金属层还包括形成于所述有源层上的源极和漏极。
  11. 根据权利要求10所述阵列基板的制作方法，其中，还包括：
    在所述第二绝缘层、第三金属层和所述有源层上形成覆盖所述第三金属层和所述有源层的钝化保护层，在所述钝化保护层上形成色阻层，在所述色阻层上形成平坦绝缘层，在所述漏极上方形成穿过所述钝化保护层、色阻层和所述平坦绝缘层的第四过孔，在所述平坦绝缘层上形成像素电极层，所述像素电极层穿过所述第四过孔与所述漏极连接。
  12. 一种显示面板，所述显示面板包括彩膜基板和阵列基板，所述彩膜基板与所述阵列基板之间设置有液晶层；
    所述阵列基板包括衬底、设置于所述衬底上的第一金属层、设置于所述衬底和所述第一金属层上且覆盖所述第一金属层的第一绝缘层、设置于所述第一绝缘层上的第二金属层、设置于所述第一绝缘层和所述第二金属层上且覆盖所述第二金属层的第二绝缘层、设置于所述第二绝缘层上的第三金属层；
    所述第一金属层包括第一数据走线和第一垂直扫描线，所述第二金属层包括水平扫描线，所述第三金属层包括第二数据走线和第二垂直扫描线，所述第一金属层上方设有穿过所述第一绝缘层和所述第二绝缘层的第一过孔和第二过孔，所述第二绝缘层上设有第三过孔，所述第二数据走线穿过所述第一过孔与所述第一数据走线并联，所述第二垂直扫描线穿过所述第二过孔与所述第一垂直扫描线并联，所述第二垂直扫描线穿过所述第三过孔与所述水平扫描线连接，其中，所述第一过孔、第二过孔和所述第三过孔通过同一道制程一体成型。
  13. 根据权利要求12所述的显示面板，其中，所述阵列基板包括多个子像素区，所述第一过孔和所述第二过孔位于各所述子像素区之间，所述第三过孔位于所述子像素区内。
  14. 根据权利要求12所述的显示面板，其中，所述第二金属层还包括公共电极、及与所述水平扫描线连接的栅极。
  15. 根据权利要求14所述的显示面板，其中，所述第二绝缘层上设有与所述栅极位置相对应的有源层，所述第三金属层还包括设置于所述有源层上的源极和漏极。
  16. 根据权利要求15所述的显示面板，其中，所述阵列基板还包括设置于所述第二绝缘层、第三金属层和所述有源层上且覆盖所述第三金属层和所述有源层的钝化保护层，所述钝化保护层上设有色阻层，所述色阻层上设有平坦绝缘层，所述平坦绝缘层上设有像素电极层，所述漏极上方设有穿过所述钝化保护层、色阻层和所述平坦绝缘层的第四过孔，所述像素电极层穿过所述第四过孔与所述漏极连接。
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