WO2022040967A1 - 一种透射电镜高分辨原位温差芯片及其制备方法 - Google Patents

一种透射电镜高分辨原位温差芯片及其制备方法 Download PDF

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WO2022040967A1
WO2022040967A1 PCT/CN2020/111296 CN2020111296W WO2022040967A1 WO 2022040967 A1 WO2022040967 A1 WO 2022040967A1 CN 2020111296 W CN2020111296 W CN 2020111296W WO 2022040967 A1 WO2022040967 A1 WO 2022040967A1
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heating
wafer
resolution
chip
situ
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PCT/CN2020/111296
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French (fr)
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廖洪钢
江友红
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厦门超新芯科技有限公司
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Publication of WO2022040967A1 publication Critical patent/WO2022040967A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
    • G01N23/02—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by transmitting the radiation through the material
    • G01N23/04—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by transmitting the radiation through the material and forming images of the material
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01Q—SCANNING-PROBE TECHNIQUES OR APPARATUS; APPLICATIONS OF SCANNING-PROBE TECHNIQUES, e.g. SCANNING PROBE MICROSCOPY [SPM]
    • G01Q30/00—Auxiliary means serving to assist or improve the scanning probe techniques or apparatus, e.g. display or data processing devices
    • G01Q30/08—Means for establishing or regulating a desired environmental condition within a sample chamber
    • G01Q30/10—Thermal environment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/02—Details
    • H01J37/20—Means for supporting or positioning the objects or the material; Means for adjusting diaphragms or lenses associated with the support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/26—Electron or ion microscopes; Electron or ion diffraction tubes

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  • the invention relates to the field of in-situ characterization, in particular to a transmission electron microscope high-resolution in-situ thermodifference chip and a preparation method thereof.
  • In situ TEM technology is widely used in various scientific fields due to its advantages of ultra-high spatial resolution (atomic level) and ultra-fast temporal resolution (millisecond level), which provides researchers with the opportunity to explore the microstructure of new materials. New ideas and research methods.
  • the main performance is to build a visualization window in the electron microscope, introduce external fields such as thermal field, optical field, electrochemical field, etc., to conduct real-time dynamic in-situ testing of the sample morphology, so as to obtain a direct correlation between material properties and its structure.
  • researchers can capture the dynamic sensing of samples to the environment through in situ testing techniques, including important information such as size, morphology, crystal structure, atomic structure, chemical bonds, and thermal energy changes.
  • the in-situ chip still has the defects of low heating and cooling rate, insufficient temperature measurement and temperature control accuracy, low resolution, and high sample drift rate, and there is no chip structure that can achieve continuous and accurate temperature difference for micron-scale samples.
  • the invention aims to provide a high-resolution in-situ temperature difference chip for transmission electron microscopy with rapid temperature rise and fall, precise temperature measurement and temperature control, continuous maintenance of precise temperature difference, high resolution, and low sample drift rate.
  • a transmission electron microscope high-resolution in-situ thermodifference chip comprising a substrate covered with insulating layers on both sides, a heating layer is arranged on the front side of the substrate, the heating layer includes two symmetrically arranged heating units, each heating unit is It includes a heating area formed by a heating wire, two contact electrodes, and a connection line connecting the heating wire and the contact electrode, wherein the heating wire is arranged to form a roughly square heating area, and the heating wires have a certain distance between each other and do not contact each other.
  • a contact electrode is located on the same side edge of the substrate; there is a gap for carrying the sample between the heating areas of the two heating units; the area of the substrate except the heating unit is etched and hollowed out, thereby forming a first space for supporting the heating area. a support area and a second support area for supporting the connection lines.
  • the substrate is a silicon substrate
  • the insulating layer is a silicon nitride or silicon oxide insulating layer.
  • the external dimension of the high-resolution in-situ thermodifference chip for TEM is 2*2-10*10mm, preferably 4*8mm.
  • the size of the first support area is 0.2*0.2mm-0.8*0.8mm; the size of the second support area is 0.5*0.2mm-2.5*0.8mm; the size of the gap between the two heating zones It is 0.01*0.2mm-0.05*0.8mm.
  • the thickness of the insulating layer is 5-200nm; the thickness of the substrate is 50-500um.
  • each of the heating zones is provided with a set of equivalent circuits, and the equivalent circuits can simultaneously realize power supply and heat generation and real-time monitoring of the resistance value of the heating wire after heating.
  • the heating zone formed by the heating wire has a side length of 0.15-0.5 mm and a thickness of 50 nm-500 nm.
  • the heating wire is made of gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metal molybdenum carbide.
  • the invention also provides a preparation method of a high-resolution in-situ thermodifference chip for a transmission electron microscope, comprising the following steps:
  • the photolithography process is exposed in the hard contact mode of an ultraviolet lithography machine;
  • the photoresist in the photolithography process is AZ5214E;
  • the development time is 50s;
  • the exposure time is 15s
  • the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metal molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;
  • the thickness of the protective layer is 30-150 nm;
  • the lithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the photoresist used in the lithography process is AZ5214E; the development time is 65s;
  • the exposure time is 20s;
  • wafer A-7 Put the back of wafer A-6 into potassium hydroxide solution for wet etching until the exposed base silicon is completely etched, take out the wafer, rinse it with a large amount of deionized water, and dry it to obtain a wafer A-7; preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70-90°C, and the etching time is 1.5-4h;
  • the etching temperature is 80°C; the etching time is 2h;
  • the size of the silicon support layer of the heating wire is 0.3*0.3mm-0.5*0.5mm; the size of the silicon support layer between the contact electrode and the heating wire is 1.0*0.2mm-2.0*0.4mm; The size of the gap between them is 0.01*0.3mm-0.02*0.5mm;
  • the high-resolution in-situ thermodifference chip for transmission electron microscopy provided by the present invention has the following advantages: the high-resolution in-situ thermodifference chip for transmission electron microscopy provided by the present invention has a large thermal insulation area around the heating zone, and the two heating units have micron-level The distance can realize the loading of micron-sized samples, and the temperature can be controlled by program to achieve precise temperature difference control and rapid temperature rise and fall.
  • Figure 1 Top view of the high-resolution in-situ thermodifference chip for transmission electron microscopy.
  • Figure 2 shows an enlarged view of the heating zone.
  • FIG. 3 shows a cross-sectional view at A-A in FIG. 1 .
  • FIG. 4 shows a cross-sectional view at B-B in FIG. 2 .
  • the present embodiment provides a high-resolution in-situ thermodifference chip for transmission electron microscopy, including a substrate 1 , and an insulating layer 10 is covered on the front and back of the substrate 1 .
  • the substrate in this embodiment is a silicon substrate, and the insulating layer is a silicon nitride or silicon oxide insulating layer.
  • the front surface of the substrate 1 is provided with a heating layer 11, the heating layer 11 includes two symmetrically arranged heating units, each heating unit includes a heating area composed of a heating wire 111, two contact electrodes 112 and connecting the heating wire 111 and the contact The connection lines 113 of the electrodes 112, wherein the heating wires 111 are arranged to form a substantially square heating area, the heating wires 111 have a certain distance from each other and do not contact each other, and the two contact electrodes 112 are located on the same side edge of the substrate 1 .
  • the middle part of the substrate 1 is used to support the heating wire 111 and the connecting line 113.
  • Hollow-out arrangement that is, the area in the middle of the substrate 1 except for supporting the heating wire 111 and the connecting line 113 is etched and hollowed out, so as to form the first supporting area 101 for supporting the heating area and the first supporting area for supporting the connecting line 113.
  • the second support area 102 is etched and hollowed out, so as to form the first supporting area 101 for supporting the heating area and the first supporting area for supporting the connecting line 113.
  • the external dimensions of the high-resolution in-situ thermodifference chip of the transmission electron microscope are preferably 2*2-10*10mm; more preferably 4*8mm.
  • the size of the first support area 101 is preferably 0.2*0.2mm-0.8*0.8mm; the size of the second support area 102 is preferably 0.5*0.2mm-2.5*0.8mm; two heating The size of the gap between the zones is 0.01*0.2mm—0.05*0.8mm.
  • the thickness of the insulating layer 10 is 5-200 nm; the thickness of the substrate 1 is 50-500 ⁇ m.
  • each heating unit is set as a set of equivalent circuits, and the equivalent circuits can simultaneously realize power supply and heat generation and real-time monitoring of the resistance value of the heating wire after heating.
  • the side length of the heating zone formed by the heating wire is 0.15-0.5 mm, and the thickness is 50-500 nm.
  • the heating wire is made of metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metallic molybdenum carbide.
  • the present embodiment provides a preparation method of a high-resolution in-situ thermodifference chip for transmission electron microscopy, and the preparation method includes the following steps:
  • the photolithography process is exposed in the hard contact mode of an ultraviolet lithography machine;
  • the photoresist in the photolithography process is AZ5214E;
  • the development time is 50s;
  • the exposure time is 15s
  • the metal of the metal heating wire is metal gold, platinum, palladium, rhodium, molybdenum, tungsten, platinum-rhodium alloy or non-metal molybdenum carbide; the thickness of the metal heating wire is 50nm-500nm;
  • the thickness of the protective layer is 30-150 nm;
  • the lithography process is exposure in the hard contact mode of an ultraviolet lithography machine; the photoresist used in the lithography process is AZ5214E; the development time is 65s;
  • the exposure time is 20s;
  • wafer A-7 Put the back of wafer A-6 into potassium hydroxide solution for wet etching until the exposed base silicon is completely etched, take out the wafer, rinse it with a large amount of deionized water, and dry it to obtain a wafer A-7; preferably, the mass percentage concentration of the potassium hydroxide solution is 20%; the etching temperature is 70-90°C, and the etching time is 1.5-4h;
  • the etching temperature is 80°C; the etching time is 2h;
  • the size of the silicon support layer of the heating wire is 0.3*0.3mm-0.5*0.5mm; the size of the silicon support layer between the contact electrode and the heating wire is 1.0*0.2mm-2.0*0.4mm; The size of the gap between them is 0.01*0.3mm-0.02*0.5mm;

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Abstract

一种透射电镜高分辨原位温差芯片及其制备方法，原位温差芯片包括双面覆盖有绝缘层（10）的基片（1），基片（1）的正面上设置有加热层（11），加热层（11）包括两对称设置的加热单元，每一加热单元都包括由加热丝（111）构成的加热区、两接触电极（112）以及连接加热丝（111）和接触电极（112）的连接线路（113），其中，加热丝（111）布设形成大致方形的加热区，两个接触电极（112）位于基片（1）的同侧边缘；两加热单元的加热区之间具有用来搭载样品的缝隙；基片（1）除加热单元外的区域被腐蚀镂空，从而形成用于支撑加热区的第一支撑区域（101）和用于支撑连接线路（113）的第二支撑区域（102），芯片具有快速升降温、精准测温控温、持续维持精准温差、分辨率高、样品漂移率低的优点。

Description

一种透射电镜高分辨原位温差芯片及其制备方法 技术领域
本发明涉及原位表征领域，具体是涉及一种透射电镜高分辨原位温差芯片及其制备方法。
背景技术
原位透射电镜技术以其超高空间分辨率(原子级)以及超快时间分辨率(毫秒级)的优势而被广泛应用于各个科学领域中，这为研究人员对新型材料微观结构的探索提供全新的思路和研究方法。主要表现为在电镜中搭建可视化的窗口，引入比如热场、光场、电化学场等外场作用，对样品形貌进行实时动态的原位测试，从而得到材料性质和其结构的直接关联。研究学者可以通过原位测试技术捕获样品对环境的动态感应，包括尺寸、形态、晶体结构、原子结构、化学健、热能变化等重要信息。外场作用下材料在原子尺度的形态变化成为了材料研究和开发的根本。可以广泛用于显微结构分析、纳米材料研究的观测等，在生物、材料、半导体电子材料方面具有极高的应用价值。
目前原位芯片还存在升降温速率低、测温控温准确性不足、分辨率较低、样品漂移率高等缺陷，且没有可以对微米级样品实现持续精准温差的芯片结构。
发明内容
本发明旨在提供一种具有快速升降温、精准测温控温、持续维持精准温差、分辨率高、样品漂移率低的透射电镜高分辨原位温差芯片。
具体方案如下：
一种透射电镜高分辨原位温差芯片，包括双面覆盖有绝缘层的基片，该基片的正面上设置有加热层，所述加热层包括两对称设置的加热单元，每一加热 单元都包括由加热丝构成的加热区、两接触电极以及连接加热丝和接触电极的连接线路，其中，加热丝布设形成大致方形的加热区，加热丝相互之间具有一定的间距，互不接触，两个接触电极位于基片的同侧边缘；两加热单元的加热区之间具有用来搭载样品的缝隙；所述基片除加热单元外的区域被腐蚀镂空，从而形成用于支撑加热区的第一支撑区域和用于支撑连接线路的第二支撑区域。
进一步的，所述基片为硅基片，所述绝缘层为氮化硅或者氧化硅绝缘层。
进一步的，该透射电镜高分辨原位温差芯片的外形尺寸为2*2-10*10mm，优选为4*8mm。
进一步的，所述第一支撑区域的尺寸为0.2*0.2mm-0.8*0.8mm；所述第二支撑区域的尺寸为0.5*0.2mm-2.5*0.8mm；两个加热区之间缝隙的尺寸为0.01*0.2mm-0.05*0.8mm。
进一步的，所述绝缘层的厚度为5-200nm；所述基片的厚度为50-500um。
进一步的，每一所述加热区均设置有一组等效电路，该等效电路可同时实现供电产热以及实时监控加热丝发热后的电阻值。
进一步的，所述加热丝组成的加热区的边长为0.15-0.5mm，厚度为50nm-500nm。
进一步的，所述加热丝采用的是材料金、铂、钯、铑、钼、钨、铂铑合金或非金属的碳化钼。
本发明还提供了一种透射电镜高分辨原位温差芯片的制备方法，包括以下步骤：
S1.准备双面具有低压化学气相沉积的氮化硅或氧化硅绝缘层的Si(100) 晶圆A，绝缘层的厚度为5-200nm，以晶圆A的两面分别定义为正面和背面；
S2.通过光刻工艺，将加热区、接触电极以及两者之间的连接线路从光刻掩模版转移到上述晶圆的正面，然后在正交显影液中显影，再用去离子水清洗表面得到晶圆A-1；
优选的，所述光刻工艺在紫外光刻机的hard contact模式下曝光；光刻工艺中的光刻胶为AZ5214E；显影的时间为50s；
更优选的，曝光时间为15s；
S3.通过反应离子刻蚀工艺，将在晶圆A-1的正面加热单元图案处的绝缘层刻蚀掉，得到晶圆A-2；
S4.利用热蒸发镀膜工艺，在晶圆A-2正面蒸镀金属材料形成加热电极，然后将晶圆正面朝上放入丙酮中浸泡，最后用丙酮冲洗，去掉光刻胶，得到晶圆A-3；
优选的，所述金属加热丝的金属为金属金、铂、钯、铑、钼、钨、铂铑合金或非金属的碳化钼；所述金属加热丝的厚度为50nm-500nm；
S5.利用PECVD工艺，在晶圆A-3正面支撑加热丝的硅区域上生长一层氮化硅或氧化硅或氧化铝作为保护层，得到晶圆A-4；
优选的，保护层的厚度为30-150nm；
S6.利用光刻工艺，将待腐蚀区域从光刻掩膜版转移到上述晶圆的背面，然后在正胶显影液中显影，再用去离子水清洗表面得到晶圆A-5；
优选的，所述光刻工艺为在紫外光刻机的hard contact模式下曝光；光刻工艺中使用的光刻胶为AZ5214E；显影的时间为65s；
更优选的，曝光的时间为20s；
S7.利用反应离子刻蚀工艺，将晶圆A-5背面待腐蚀区域上的氮化硅或氧化硅或氧化铝刻蚀掉，然后将晶圆背面朝上先后放入丙酮中浸泡，最后用丙酮冲洗，去掉光刻胶，得到晶圆A-6；
S8.将晶圆A-6的背面朝上放入氢氧化钾溶液中进行湿法刻蚀，直至裸露的基底硅完全腐蚀完，取出晶圆用大量去离子水冲洗后吹干，得到晶圆A-7；优选的，所述氢氧化钾溶液的质量百分比浓度为20％；刻蚀的温度为70-90℃，刻蚀的时间为1.5-4h；
更优选的，刻蚀的温度为80℃；刻蚀的时间为2h；
优选的，加热丝的硅支撑层尺寸为0.3*0.3mm-0.5*0.5mm；接触电极与加热丝之间的硅支撑层尺寸为1.0*0.2mm-2.0*0.4mm；两个微型加热器之间的缝隙尺寸为0.01*0.3mm-0.02*0.5mm；
S9.将晶圆A-7进行激光划片，分成独立芯片。
本发明提供的透射电镜高分辨原位温差芯片与现有技术相比较具有以下优点：本发明提供的透射电镜高分辨原位温差芯片的加热区周围隔热面积大、两个加热单元有微米级间距，可实现微米尺寸样品搭载，而且可通过程序控温，实现精准的温差控制和快速的升降温。
附图说明
图1透射电镜高分辨原位温差芯片的俯视图。
图2示出了加热区的放大图。
图3示出了图1中A-A处的剖视图。
图4示出了图2中B-B处的剖视图。
具体实施方式
为进一步说明各实施例，本发明提供有附图。这些附图为本发明揭露内容的一部分，其主要用以说明实施例，并可配合说明书的相关描述来解释实施例的运作原理。配合参考这些内容，本领域普通技术人员应能理解其他可能的实施方式以及本发明的优点。图中的组件并未按比例绘制，而类似的组件符号通常用来表示类似的组件。
现结合附图和具体实施方式对本发明进一步说明。
实施例1
如图1-图4所示的，本实施例提供了一种透射电镜高分辨原位温差芯片，包括一基片1，该基片1的正面和背面上均覆盖有一绝缘层10。其中本实施例中的基片为硅基片，绝缘层为氮化硅或者氧化硅绝缘层。
基片1的正面上设置有加热层11，该加热层11包括两对称设置的加热单元，每一加热单元都包括由加热丝111构成的加热区、两接触电极112以及连接加热丝111和接触电极112的连接线路113，其中，加热丝111布设形成大致方形的加热区，加热丝111相互之间具有一定的间距，互不接触，两个接触电极112位于基片1的同侧边缘。
两加热单元的加热区之间有适当的缝隙、互不接触，以用来搭载样品；以样品搭载区为中心，基片1的中部上除用于支撑加热丝111和连接线路113外的区域镂空设置，即该基片1的中部上除用于支撑加热丝111和连接线路113外的区域被腐蚀镂空，从而形成用于支撑加热区的第一支撑区域101和用于支撑连接线路113的第二支撑区域102。
其中，作为本实施例的一优选方案，该透射电镜高分辨原位温差芯片的外形尺寸优选为2*2—10*10mm；更优选为4*8mm。
作为本实施例的一优选方案，第一支撑区域101的尺寸优选为0.2*0.2mm—0.8*0.8mm；第二支撑区域102的尺寸优选为0.5*0.2mm—2.5*0.8mm；两个加热区之间的缝隙尺寸为0.01*0.2mm—0.05*0.8mm。
作为本实施例的一优选方案，绝缘层10的厚度为5-200nm；基片1的厚度为50-500um。
作为本实施例的一优选方案，每一加热单元设置为一组等效电路，所述等效电路可同时实现供电产热以及实时监控加热丝发热后的电阻值。
优选的，加热丝组成的加热区的边长为0.15-0.5mm，厚度为50nm-500nm。
优选的，加热丝采用的是金属金、铂、钯、铑、钼、钨、铂铑合金或非金属的碳化钼。
实施例2
本实施例提供了一种透射电镜高分辨原位温差芯片的制备方法，该制备方法包括以下步骤：
S1.准备双面具有低压化学气相沉积的氮化硅或氧化硅绝缘层的Si(100)晶圆A，绝缘层的厚度为5-200nm，以晶圆A的两面分别定义为正面和背面；
S2.通过光刻工艺，将加热区、接触电极以及两者之间的连接线路从光刻掩模版转移到上述晶圆的正面，然后在正交显影液中显影，再用去离子水清洗表面得到晶圆A-1；
优选的，所述光刻工艺在紫外光刻机的hard contact模式下曝光；光刻工艺中的光刻胶为AZ5214E；显影的时间为50s；
更优选的，曝光时间为15s；
S3.通过反应离子刻蚀工艺，将在晶圆A-1的正面加热单元图案处的绝缘层 刻蚀掉，得到晶圆A-2；
S4.利用热蒸发镀膜工艺，在晶圆A-2正面蒸镀金属材料形成加热电极，然后将晶圆正面朝上放入丙酮中浸泡，最后用丙酮冲洗，去掉光刻胶，得到晶圆A-3；
优选的，所述金属加热丝的金属为金属金、铂、钯、铑、钼、钨、铂铑合金或非金属的碳化钼；所述金属加热丝的厚度为50nm-500nm；
S5.利用PECVD工艺，在晶圆A-3正面支撑加热丝的硅区域上生长一层氮化硅或氧化硅或氧化铝作为保护层，得到晶圆A-4；
优选的，保护层的厚度为30-150nm；
S6.利用光刻工艺，将待腐蚀区域从光刻掩膜版转移到上述晶圆的背面，然后在正胶显影液中显影，再用去离子水清洗表面得到晶圆A-5；
优选的，所述光刻工艺为在紫外光刻机的hard contact模式下曝光；光刻工艺中使用的光刻胶为AZ5214E；显影的时间为65s；
更优选的，曝光的时间为20s；
S7.利用反应离子刻蚀工艺，将晶圆A-5背面待腐蚀区域上的氮化硅或氧化硅或氧化铝刻蚀掉，然后将晶圆背面朝上先后放入丙酮中浸泡，最后用丙酮冲洗，去掉光刻胶，得到晶圆A-6；
S8.将晶圆A-6的背面朝上放入氢氧化钾溶液中进行湿法刻蚀，直至裸露的基底硅完全腐蚀完，取出晶圆用大量去离子水冲洗后吹干，得到晶圆A-7；优选的，所述氢氧化钾溶液的质量百分比浓度为20％；刻蚀的温度为70-90℃，刻蚀的时间为1.5-4h；
更优选的，刻蚀的温度为80℃；刻蚀的时间为2h；
优选的，加热丝的硅支撑层尺寸为0.3*0.3mm-0.5*0.5mm；接触电极与加热丝之间的硅支撑层尺寸为1.0*0.2mm-2.0*0.4mm；两个微型加热器之间的缝隙尺寸为0.01*0.3mm-0.02*0.5mm；
S9.将晶圆A-7进行激光划片，分成独立芯片。
尽管结合优选实施方案具体展示和介绍了本发明，但所属领域的技术人员应该明白，在不脱离所附权利要求书所限定的本发明的精神和范围内，在形式上和细节上可以对本发明做出各种变化，均为本发明的保护范围。

Claims (9)

  1. 一种透射电镜高分辨原位温差芯片，其特征在于：包括双面覆盖有绝缘层的基片，该基片的正面上设置有加热层，所述加热层包括两对称设置的加热单元，每一加热单元都包括由加热丝构成的加热区、两接触电极以及连接加热丝和接触电极的连接线路，其中，加热丝布设形成大致方形的加热区，加热丝相互之间具有一定的间距，互不接触，两个接触电极位于基片的同侧边缘；两加热单元的加热区之间具有用来搭载样品的缝隙；所述基片除加热单元外的区域被腐蚀镂空，从而形成用于支撑加热区的第一支撑区域和用于支撑连接线路的第二支撑区域。
  2. 根据权利要求1所述的透射电镜高分辨原位温差芯片，其特征在于：所述基片为硅基片，所述绝缘层为氮化硅或者氧化硅绝缘层。
  3. 根据权利要求1所述的透射电镜高分辨原位温差芯片，其特征在于：该透射电镜高分辨原位温差芯片的外形尺寸为2*2-10*10mm，优选为4*8mm。
  4. 根据权利要求1所述的透射电镜高分辨原位温差芯片，其特征在于：所述第一支撑区域的尺寸为0.2*0.2mm-0.8*0.8mm；所述第二支撑区域的尺寸为0.5*0.2mm-2.5*0.8mm；两个加热区之间缝隙的尺寸为0.01*0.2mm-0.05*0.8mm。
  5. 根据权利要求1所述的透射电镜高分辨原位温差芯片，其特征在于：所述绝缘层的厚度为5-200nm；所述基片的厚度为50-500um。
  6. 根据权利要求1所述的透射电镜高分辨原位温差芯片，其特征在于：每一所述加热区均设置有一组等效电路，该等效电路可同时实现供电产热以及实时监控加热丝发热后的电阻值。
  7. 根据权利要求1所述的透射电镜高分辨原位温差芯片，其特征在于：所述加热丝组成的加热区的边长为0.15-0.5mm，厚度为50nm-500nm。
  8. 根据权利要求1所述的透射电镜高分辨原位温差芯片，其特征在于：所述加热丝采用的是材料金、铂、钯、铑、钼、钨、铂铑合金或非金属的碳化钼。
  9. 一种透射电镜高分辨原位温差芯片的制备方法，其特征在于，包括以下步骤：
    S1.准备双面具有低压化学气相沉积的氮化硅或氧化硅绝缘层的Si(100)晶圆A，绝缘层的厚度为5-200nm，以晶圆A的两面分别定义为正面和背面；
    S2.通过光刻工艺，将加热区、接触电极以及两者之间的连接线路从光刻掩模版转移到上述晶圆的正面，然后在正交显影液中显影，再用去离子水清洗表面得到晶圆A-1；
    优选的，所述光刻工艺在紫外光刻机的hard contact模式下曝光；光刻工艺中的光刻胶为AZ5214E；显影的时间为50s；
    更优选的，曝光时间为15s；
    S3.通过反应离子刻蚀工艺，将在晶圆A-1的正面加热单元图案处的绝缘层刻蚀掉，得到晶圆A-2；
    S4.利用热蒸发镀膜工艺，在晶圆A-2正面蒸镀金属材料形成加热电极，然后将晶圆正面朝上放入丙酮中浸泡，最后用丙酮冲洗，去掉光刻胶，得到晶圆A-3；
    优选的，所述金属加热丝的金属为金属金、铂、钯、铑、钼、钨、铂铑合金或非金属的碳化钼；所述金属加热丝的厚度为50nm-500nm；
    S5.利用PECVD工艺，在晶圆A-3正面支撑加热丝的硅区域上生长一层氮化硅或氧化硅或氧化铝作为保护层，得到晶圆A-4；
    优选的，保护层的厚度为30-150nm；
    S6.利用光刻工艺，将待腐蚀区域从光刻掩膜版转移到上述晶圆的背面，然 后在正胶显影液中显影，再用去离子水清洗表面得到晶圆A-5；
    优选的，所述光刻工艺为在紫外光刻机的hard contact模式下曝光；光刻工艺中使用的光刻胶为AZ5214E；显影的时间为65s；
    更优选的，曝光的时间为20s；
    S7.利用反应离子刻蚀工艺，将晶圆A-5背面待腐蚀区域上的氮化硅或氧化硅或氧化铝刻蚀掉，然后将晶圆背面朝上先后放入丙酮中浸泡，最后用丙酮冲洗，去掉光刻胶，得到晶圆A-6；
    S8.将晶圆A-6的背面朝上放入氢氧化钾溶液中进行湿法刻蚀，直至裸露的基底硅完全腐蚀完，取出晶圆用大量去离子水冲洗后吹干，得到晶圆A-7；
    优选的，所述氢氧化钾溶液的质量百分比浓度为20％；刻蚀的温度为70-90℃，刻蚀的时间为1.5-4h；
    更优选的，刻蚀的温度为80℃；刻蚀的时间为2h；
    优选的，加热丝的硅支撑层尺寸为0.3*0.3mm-0.5*0.5mm；接触电极与加热丝之间的硅支撑层尺寸为1.0*0.2mm-2.0*0.4mm；两个微型加热器之间的缝隙尺寸为0.01*0.3mm-0.02*0.5mm；
    S9.将晶圆A-7进行激光划片，分成独立芯片。
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