WO2022033161A1 - 半导体器件及半导体器件的形成方法 - Google Patents

半导体器件及半导体器件的形成方法 Download PDF

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WO2022033161A1
WO2022033161A1 PCT/CN2021/099989 CN2021099989W WO2022033161A1 WO 2022033161 A1 WO2022033161 A1 WO 2022033161A1 CN 2021099989 W CN2021099989 W CN 2021099989W WO 2022033161 A1 WO2022033161 A1 WO 2022033161A1
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layer
metal layer
insulating layer
height
region
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French (fr)
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刘忠明
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/411,127 priority Critical patent/US12100657B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance

Definitions

  • the present application relates to the field of semiconductor preparation, in particular to a semiconductor device and a method for forming a semiconductor device.
  • a contact window is formed in the peripheral area of the memory, close to the device area, to expose the conductive metal in the memory, so as to form a peripheral contact landing that is electrically connected to the bit line and the like. pad.
  • the distance between adjacent two-bit lines is also gradually reduced.
  • a trench with a high aspect ratio is formed downward from the upper surface of the mask structure in a direction perpendicular to the upper surface of the mask structure, so as to form a required bit line structure with a smaller critical dimension.
  • the present application proposes a semiconductor device and a method for forming the semiconductor device, which can solve the problems of poor shape and poor conductivity of the peripheral contact landing pad, and improve the production yield of the memory.
  • a method for forming a semiconductor device includes the following steps: providing a substrate, the substrate has a peripheral area, a bonding area and a device area adjacent to each other in sequence; forming on the upper surface of the substrate a metal layer; forming a dielectric layer over the metal layer; forming an opening in the dielectric layer over at least one of the peripheral region or the bonding region to expose the metal layer A contact window is formed, and the height of the upper surface of the metal layer exposed to the contact window is lower than the height of the upper surface of the metal layer located in the device region.
  • forming the metal layer includes the following steps: forming a first insulating layer on the upper surface of the substrate; partially removing the first insulating layer to form a stepped first insulating layer, and The height of the upper surface of the first insulating layer located in the peripheral region is lower than the height of the upper surface of the first insulating layer located in the device region; the step-shaped metal is formed on the upper surface of the first insulating layer layer, and the height of the upper surface of the metal layer in the peripheral region is lower than the height of the upper surface of the metal layer in the device region.
  • the partially removing the first insulating layer includes the following steps: forming a patterned first mask layer on the upper surface of the first insulating layer, the peripheral region and part of the bonding region exposing to the first mask layer, the first mask layer covering the device area and the remaining bonding area; removing the first insulating layer by using the first mask layer as a mask; removing the first mask layer.
  • the first insulating layer includes a nitride layer.
  • the following steps are further included: forming a second insulating layer on the upper surface of the substrate; partially removing the second insulating layer to form a groove at a position corresponding to the contact window, the concave The bottom surface of the groove is also located in the second insulating layer; the metal layer is formed on the upper surface of the second insulating layer, and the height of the upper surface of the metal layer formed in the groove is lower than that of the device region The height of the top surface of the metal layer.
  • partially removing the second insulating layer includes the following steps: forming a patterned second mask layer on the upper surface of the second insulating layer, and the second mask layer is in contact with the second insulating layer.
  • a through hole is formed at a position corresponding to the contact window; the second insulating layer is etched downward from the through hole in a direction perpendicular to the upper surface of the substrate to form the groove on the surface of the second insulating layer ; removing the second mask layer.
  • the step of etching the metal layer to form a bit line structure having a portion extending over the peripheral region is further included.
  • etching the metal layer to form the bit line structure includes the steps of: forming a patterned third mask layer over the metal layer, the third mask layer covering the a device area, a bonding area and a part of a peripheral area; using the third mask layer as a mask to pattern the metal layer to form a bit line structure, and one end of the third mask layer covers the peripheral area ; removing the third mask layer.
  • a semiconductor device comprising: a substrate formed with a peripheral region, a device region and a bonding region; a metal layer formed on the substrate; a dielectric layer formed on the Above the metal layer, a contact window is formed on the surface of the dielectric layer to expose the metal layer, and the height of the upper surface of the metal layer exposed to the contact window is lower than the height of the metal layer located in the device region. Top surface height.
  • the method further includes: a first insulating layer formed on the upper surface of the substrate and located under the metal layer, and the height of the upper surface of the first insulating layer under the peripheral region is lower than that under the peripheral region. The height of the upper surface of the first insulating layer below the device region.
  • the method further includes: a second insulating layer formed on the upper surface of the substrate and located under the metal layer, and the height of the upper surface of the second insulating layer under the contact window is lower than The height of the upper surface of the second insulating layer below the device region.
  • the semiconductor device includes a bit line structure composed of the metal layer and having a portion extending over the peripheral region.
  • the height of the upper surface of the metal layer exposed to the contact window according to the semiconductor device and the method for forming the semiconductor device of the present application is lower than the height of the upper surface of the metal layer located in the device region, which can effectively prevent During etching, the etching gas first contacts the upper surface of the metal layer located in the contact window area, so as to avoid affecting the conductivity of the peripheral contact landing pad formed based on the contact window.
  • FIG. 1 is a schematic diagram of the morphological structure of a metal layer used for preparing a bit line structure of a memory in the prior art.
  • FIG. 2 is a schematic flowchart of steps of a preparation method in a specific embodiment of the present application.
  • 3 to 9 are schematic structural diagrams of a semiconductor device corresponding to each step of a manufacturing method in an embodiment of the present application.
  • 10 to 13 are schematic structural diagrams of the semiconductor device corresponding to each step of the preparation method in the preparation of the bit line structure.
  • 14 to 16 are schematic structural diagrams of the semiconductor device corresponding to each step when the second insulating layer is partially removed.
  • the upper surface of the metal layer at the position where the contact window is expected to be formed is higher than the upper surface of the metal layer located in the device area. Height, the entire metal layer, from the peripheral area to the device area, presents a zigzag distribution, and the metal layer located in the peripheral area is overall higher than the metal layer located in the device area.
  • FIG. 1 there is also a bonding region 102 between the device region 103 and the peripheral region 101 , the position of the contact window is located in the bonding region 102 , and the metal layer 104 is at the height of the bonding region 102 and the peripheral region 101 . higher than the height in the device region 103 .
  • the etching gas will first contact the metal layer at the preset contact window position, etch it first, and then Then, the metal layer located in the device region is contacted, and the metal layer belonging to the device region is etched.
  • the etching gas will first contact the metal layer located at the preset contact window position, etch it first, and then contact the metal layer located in the device area.
  • the metal layer in the device area is etched. In this way, the metal layer located at the preset contact window position is exposed to the etching gas first, and its morphology is more etched than the metal layer located in the device area.
  • the phenomenon of necking (Necking) or even cracking (Broken) occurs, which affects the conductivity of the final formed peripheral contact landing pad.
  • FIG. 2 is a schematic flowchart of the steps of the preparation method in a specific embodiment of the application
  • FIGS. 3 to 9 are the steps of the preparation method in a specific embodiment of the application.
  • a method for forming a semiconductor device includes the following steps: S21 providing a substrate 201, the substrate 201 having a peripheral region 101, a bonding region 102 and a device region 103 adjacent in sequence, here Please refer to FIG. 3; S22 forms a metal layer 104 on the upper surface of the substrate 201, please refer to FIG. 7 here; S23 forms a dielectric layer 204 above the metal layer 104, please refer to FIG. 8 here; An opening is formed in the dielectric layer 204 , please refer to FIG.
  • the opening is located above at least one of the peripheral region 101 or the bonding region 102 to expose the metal layer 104 to form a contact window 205 , and the height of the upper surface of the metal layer 104 exposed to the contact window 205 is lower than the height of the upper surface of the metal layer 104 located in the device region 103 .
  • the height of the upper surface of the metal layer 104 exposed to the contact window 205 is lower than the height of the upper surface of the metal layer 104 located in the device region 103 , which can effectively prevent damage to the metal layer 104 During etching, the etching gas first contacts the upper surface of the metal layer 104 located in the contact window 205 area, so as to avoid affecting the conductivity of the peripheral contact landing pad formed based on the contact window 205 .
  • the formation of the metal layer 104 includes the following steps: forming a first insulating layer 202 on the upper surface of the substrate 201; partially removing the first insulating layer 202 to form a stepped The first insulating layer 202, and the height of the upper surface of the first insulating layer 202 in the peripheral region 101 is lower than the height of the upper surface of the first insulating layer 202 in the device region 103;
  • the upper surface of the layer 202 forms the stepped metal layer 104 , and the height of the upper surface of the metal layer 104 in the peripheral region 101 is lower than the height of the upper surface of the metal layer 104 in the device region 103 .
  • this step is also consistent with the flow of steps for preparing the memory.
  • this step may correspond to the step of peripheral region nitride removal (Periphery nitride remove).
  • the first insulating layer 202 includes a nitride layer.
  • a silicon nitride layer needs to be formed under the metal layer 104 , and this layer can be used as the first insulating layer 202 .
  • the partially removing the first insulating layer 202 includes the following steps: forming a patterned first mask on the upper surface of the first insulating layer 202 layer 210, the peripheral region 101 and a part of the bonding region 102 are exposed to the first mask layer 210, the first mask layer 210 covers the device region 103 and the rest of the bonding region 102, see FIG. 4 ; using the first mask layer 210 as a mask to partially remove the first insulating layer 202 , please refer to FIG. 5 ; to remove the first mask layer 210 , please refer to FIG. 6 .
  • the peripheral region 101 and part of the bonding region exposed to the first mask layer 210 can be 102 parts removed.
  • the area exposed outside the first mask layer 210 is fully etched to expose the surface of the substrate 201, and in some other embodiments, exposed to the first mask layer The area outside 210 is only etched to a certain depth and does not penetrate through the first insulating layer 202 .
  • the etching depth of the first insulating layer 202 can be set as required.
  • the required minimum thickness of the first insulating layer 202 is used to set the removal depth when the first insulating layer 202 is partially removed.
  • At least one of dry etching or wet etching is used to partially remove the first insulating layer 202 .
  • the partially removed first insulating layer 202 is in a stepped shape. Afterwards, if other material layers are grown on the upper surface of the first insulating layer 202, When the thicknesses of the material layers are equal, the other material layers grown on the upper surface of the first insulating layer 202 are also stepped. Even if the metal layer 104 is formed above these subsequently generated material layers, the A stepped metal layer 104 is obtained, and it is ensured that the height of the upper surface of the metal layer 104 exposed to the contact window 205 is lower than the height of the upper surface of the metal layer 104 located in the device region 103 .
  • the method further includes the following steps: forming a second insulating layer 203 on the upper surface of the substrate 201 ; partially removing the second insulating layer 203 to form a position corresponding to the contact window 205 a groove, the bottom surface of the groove is also located in the second insulating layer 203; the metal layer 104 is formed on the upper surface of the second insulating layer 203, and the metal layer 104 formed in the groove is The height of the upper surface is lower than the height of the upper surface of the metal layer 104 of the device region 103 .
  • this step may correspond to the formation process of the bit line contact plug in the bit line structure, that is, the step of patterning the polysilicon layer under the metal layer 104 in the bit line structure middle.
  • the morphological structure of the nitride layer under the polysilicon layer there is no requirement for the morphological structure of the nitride layer under the polysilicon layer, but the morphological structure of the polysilicon layer is directly modified, so that the polysilicon layer presents a stepped shape.
  • the metal layer 104 on the upper surface of the layer is also stepped, and the upper surface of the metal layer 104 exposed to the contact window 205 is lower than the upper surface of the metal layer 104 located in the device region 103 .
  • a polysilicon layer is also formed on the upper surface of the nitride layer, which is consistent with the preparation process of the memory. Therefore, in addition to patterning the nitride layer to change the height of the surface on which the metal layer 104 is formed, the polysilicon layer can also be patterned to change the height of the surface on which the metal layer 104 is formed .
  • the polysilicon layer as the second insulating layer 203 is patterned, and the groove is formed in a predetermined area, so that the metal layer 104 is formed on the upper surface of the polysilicon layer , the height of the upper surface of the metal layer 104 in the groove is lower than the height of the upper surface of the metal layer 104 outside the groove.
  • the height of the upper surface of the metal layer 104 exposed to the contact window 205 can be restricted to be lower than the height of the upper surface of the metal layer 104 located in the device region 103 , and the corresponding height can be reached. Effect.
  • partially removing the second insulating layer 203 includes the following steps: forming a patterned second mask layer 208 on the upper surface of the second insulating layer 203, the second mask A through hole 209 is formed in the layer 208 at a position corresponding to the contact window 205, please see FIG. 14, the through hole 209 in FIG. 14 includes the position where the contact window 205 is to be formed; from the through hole 209
  • the second insulating layer 203 is etched downward along the direction perpendicular to the upper surface of the substrate 201 to form the grooves on the surface of the second insulating layer 203, please refer to FIG. 15 here;
  • Two mask layers 208 are two mask layers 208 .
  • the position of the groove is limited by limiting the exposed area of the patterned second mask layer 208 , please refer to FIG. 16 here.
  • the second insulating layer 203 is penetrated by the groove.
  • the bottom surface of the groove should be located in the groove.
  • the inside of the second insulating layer 203 is related to the minimum thickness of the second insulating layer 203 (ie, the polysilicon layer) required to form the memory.
  • the through holes 209 formed after the second mask layer 208 is patterned do not have the first patterned through holes 209 in FIGS. 4 to 6 .
  • a mask layer 210 all the peripheral regions 101 are exposed, but only the position of the contact window 205 and the surrounding area of the position of the contact window 205 are exposed.
  • the second mask layer 208 is exposed after patterning
  • the resulting area can also be as shown in FIG. 4 to FIG. 6 , exposing all the peripheral regions 101 to form a step-shaped second mask layer 208 .
  • the following step is further included: etching the metal layer 104 to form a bit line structure, and the bit line structure has a portion extending above the peripheral region 101 .
  • the length of the bit line structure is extended, and the bit line structure is extended to a predetermined distance in the peripheral region 101, so that the The end of the bit line structure close to the contact window 205 also has a higher height, and the height of the upper surface of the metal layer 104 exposed by the contact window 205 is basically the same, which can also prevent the contact window 205 Poor contact with the bit line structure.
  • etching the metal layer 104 to form the bit line structure includes the following steps: forming a patterned third mask over the metal layer 104 layer 206, please refer to FIG. 10, the third mask layer 206 covers the device region 103, the bonding region 102 and part of the peripheral region 101; the third mask layer 206 is used as a mask to pattern the metal layer 104 to form a bit line structure, and one end of the third mask layer 206 covers the peripheral region 101 , please refer to FIG. 11 ; remove the third mask layer 206 , please refer to FIG. 12 .
  • FIGS. 10 the specific embodiments shown in FIGS.
  • a large aspect ratio of the trench 207 formed after the third mask layer is patterned in the process of forming the bit line structure is also shown.
  • the ratio between the depth D of the trench 207 and the width W of the trench is the aspect ratio of the trench 207 .
  • the etching uniformity of the etching gas when etching the metal layer under the trench 207 is difficult to control.
  • the end of the third mask layer 206 extends into the peripheral area 101, and the bit line structure formed based on the third mask layer 206 shown in FIG. 13 also extends to the peripheral area in area 101.
  • This structure can be applied not only to the case where the upper surface of the metal layer 104 in the area where the contact window 205 is located is lower than the upper surface of the metal layer 104 located in the device region 103 , but also applicable to the case where the upper surface of the metal layer 104 in the area where the contact window 205 is located The surface is not lower than the case where the upper surface of the metal layer 104 in the device region 103 is located.
  • the metal layer 104 includes a conductive metal material layer such as a tungsten layer.
  • a TiN layer or the like is further provided between the polysilicon layer and the metal layer 104, and the TiN layer and the like also follow at least one of a stepped polysilicon layer or a nitride layer. The undulations form steps to ensure that the metal layer 104 formed on the upper surface of the material layers such as the TiN layer has a stepped upper surface.
  • a semiconductor device comprising: a substrate 201 formed with a peripheral region 101, a device region 103 and a bonding region 102; a metal layer 104 formed over the substrate 201; a dielectric A layer 204 is formed over the metal layer 104 , and a contact window 205 is formed on the surface of the dielectric layer 204 to expose the metal layer 104 , and the height of the upper surface of the metal layer 104 exposed to the contact window 205 lower than the height of the upper surface of the metal layer 104 located in the device region 103 .
  • the height of the upper surface of the metal layer 104 exposed to the contact window 205 is lower than the height of the upper surface of the metal layer 104 located in the device region 103 , which can effectively prevent damage to the metal layer 104 During etching, the etching gas first contacts the upper surface of the metal layer 104 located in the contact window 205 area, so as to avoid affecting the conductivity of the peripheral contact landing pad formed based on the contact window 205 .
  • the method further includes: a first insulating layer 202 , formed on the upper surface of the substrate 201 , located below the metal layer 104 , and located below the peripheral region 101 of the first insulating layer 202 .
  • the height of the upper surface is lower than the height of the upper surface of the first insulating layer 202 under the device region 103 .
  • the first insulating layer 202 includes a nitride layer. In the process of preparing the memory, in order to be consistent with the manufacturing process of the memory, the first insulating layer 202 here refers to the silicon nitride layer located under the metal layer 104 .
  • it further includes: a second insulating layer 203 , formed on the upper surface of the substrate 201 , located under the metal layer 104 and located under the contact window 205 , the second insulating layer The height of the upper surface of the second insulating layer 203 is lower than the height of the upper surface of the second insulating layer 203 under the device region 103 .
  • the second insulating layer 203 here refers to the polysilicon layer located under the metal layer 104 and above the silicon nitride layer.
  • a polysilicon layer is also formed on the upper surface of the nitride layer, which is consistent with the preparation process of the memory. Therefore, in addition to patterning the nitride layer to change the height of the surface on which the metal layer 104 is formed, the polysilicon layer can also be patterned to change the height of the surface on which the metal layer 104 is formed .
  • the polysilicon layer is used as the second insulating layer 203 and is patterned, and the groove is formed in a predetermined area, so that the metal layer 104 can be formed on the upper surface of the polysilicon layer.
  • the height of the upper surface of the metal layer 104 in the groove is lower than the height of the upper surface of the metal layer 104 outside the groove. In this way, by presetting the position of the groove, the height of the upper surface of the metal layer 104 exposed to the contact window 205 can be restricted to be lower than the height of the upper surface of the metal layer 104 located in the device region 103 , and the corresponding height can be reached. Effect.
  • the semiconductor device includes a bit line structure formed by the metal layer 104 and having a portion extending above the peripheral region 101 . This is an operation after the metal layer 104 is formed.
  • the length of the bit line structure is extended to a predetermined distance in the peripheral region 101 , so that the end of the bit line structure close to the contact window 205 also has a higher height , which is substantially the same as the height of the upper surface of the metal layer 104 exposed by the contact window 205 , which can also prevent the contact window 205 from being in poor contact with the bit line structure.
  • the substrate has a peripheral area, a bonding area and a device area adjacent to each other in sequence; a metal layer is formed on the upper surface of the substrate; and a dielectric layer is formed above the metal layer ; forming an opening in the dielectric layer, the opening is located above at least one of the peripheral area or the bonding area, to expose the metal layer to form a contact window, and to expose the metal of the contact window
  • the upper surface height of the layer is lower than the upper surface height of the metal layer located in the device region.

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Abstract

一种半导体器件及半导体器件的形成方法，能够解决外围接触着陆焊盘的形态不好、导电性不佳的问题，提高存储器的制备良率。所述半导体器件的形成方法，包括以下步骤：提供衬底，所述衬底具有依次邻接的外围区、接合区和器件区；在所述衬底的上表面形成金属层；在所述金属层上方形成介电层；在所述介电层中形成开孔，所述开孔位于所述外围区或接合区中至少一处的上方，以暴露所述金属层形成接触窗，且暴露于所述接触窗的金属层的上表面高度低于位于所述器件区的金属层的上表面高度。

Description

半导体器件及半导体器件的形成方法
相关申请的交叉引用
本申请要求在2020年08月12日提交中国专利局、申请号为202010805989.9、申请名称为“半导体器件及半导体器件的形成方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制备领域，尤其涉及半导体器件及半导体器件的形成方法。
背景技术
现有技术中，在进行存储器的制备时，会在存储器的外围区内，靠近器件区的区域形成接触窗，用于暴露存储器中的导电金属，以便形成与位线等电连接的外围接触着陆焊盘。随着存储器关键尺寸的逐渐缩小，相邻两位线之间的距离也在逐渐缩小，在形成位线结构前，就需要先在用于形成位线结构的金属层上表面形成掩膜结构，并从所述掩膜结构的上表面，沿垂直所述掩膜结构上表面的方向向下形成高深宽比的沟槽，以形成所需的关键尺寸较小的位线结构。
现有技术中在形成接触窗、制备外围接触着陆焊盘时，经常会存在外围接触着陆焊盘的形态不好、导电性不佳的问题，影响存储器的制备良率。
发明内容
本申请提出了一种半导体器件及半导体器件的形成方法，能够解决外围接触着陆焊盘的形态不好、导电性不佳的问题，提高存储器的制备良率。
为了解决上述问题，以下提供了一种半导体器件的形成方法，包括以下步骤：提供衬底，所述衬底具有依次邻接的外围区、接合区和器件区；在所述衬底的上表面形成金属层；在所述金属层上方形成介电层；在所述介电层中形成 开孔，所述开孔位于所述外围区或接合区中至少一处的上方，以暴露所述金属层形成接触窗，且暴露于所述接触窗的金属层的上表面高度低于位于所述器件区的金属层的上表面高度。
在一些实施例中，形成所述金属层时，包括以下步骤：在所述衬底上表面形成第一绝缘层；部分去除所述第一绝缘层，以形成台阶状的第一绝缘层，且位于外围区的所述第一绝缘层的上表面高度低于位于所述器件区的所述第一绝缘层的上表面高度；在所述第一绝缘层的上表面形成台阶状的所述金属层，且位于外围区的所述金属层的上表面高度低于位于所述器件区的所述金属层的上表面高度。
在一些实施例中，所述部分去除所述第一绝缘层，包括以下步骤：在所述第一绝缘层上表面形成图形化的第一掩膜层，所述外围区以及部分所述接合区暴露于所述第一掩膜层，所述第一掩膜层覆盖所述器件区以及剩余所述接合区；以所述第一掩膜层为掩膜部分去除所述第一绝缘层；去除所述第一掩膜层。
在一些实施例中，所述第一绝缘层包括氮化物层。
在一些实施例中，还包括以下步骤：在所述衬底上表面形成第二绝缘层；部分去除所述第二绝缘层，以在与所述接触窗对应的位置形成凹槽，所述凹槽的底面也位于所述第二绝缘层内；在所述第二绝缘层上表面形成所述金属层，且形成于所述凹槽内的金属层的上表面高度低于所述器件区的金属层的上表面高度。
在一些实施例中，在部分去除所述第二绝缘层，包括以下步骤：在所述第二绝缘层上表面形成图形化的第二掩膜层，所述第二掩膜层在与所述接触窗对应的位置形成有通孔；从所述通孔沿垂直所述衬底上表面的方向向下刻蚀所述第二绝缘层，以在所述第二绝缘层表面形成所述凹槽；去除所述第二掩膜层。
在一些实施例中，还包括以下步骤：刻蚀所述金属层以形成位线结构，且所述位线结构具有伸入至所述外围区上方的部分。
在一些实施例中，刻蚀所述金属层以形成所述位线结构，包括以下步骤：在所述金属层上方形成图形化的第三掩膜层，所述第三掩膜层覆盖所述器件区、 接合区和部分外围区；以所述第三掩膜层为掩膜以图形化所述金属层以形成位线结构，且所述第三掩膜层的一端覆盖至所述外围区；去除所述第三掩膜层。
为解决上述技术问题，以下还提供了一种半导体器件，包括：衬底，形成有外围区、器件区和接合区；金属层，形成于所述衬底上方；介电层，形成于所述金属层上方，且所述介电层表面形成有接触窗，以暴露所述金属层，且暴露于所述接触窗的金属层的上表面高度低于位于所述器件区的所述金属层的上表面高度。
在一些实施例中，还包括：第一绝缘层，形成于所述衬底上表面，位于所述金属层下方，且位于外围区下方的所述第一绝缘层的上表面高度低于位于所述器件区下方的所述第一绝缘层的上表面高度。
在一些实施例中，还包括：第二绝缘层，形成于所述衬底上表面，位于所述金属层下方，且位于所述接触窗下方的所述第二绝缘层的上表面高度低于所述器件区下方的所述第二绝缘层的上表面高度。
在一些实施例中，所述半导体器件包括位线结构，所述位线结构由所述金属层构成，并具有伸入至所述外围区上方的部分。
本申请的半导体器件及半导体器件的形成方法暴露于所述接触窗的金属层的上表面高度低于位于所述器件区的金属层的上表面高度，能够有效的防止在对所述金属层进行刻蚀时，刻蚀气体先接触到位于所述接触窗区域的金属层的上表面，避免影响基于所述接触窗形成的外围接触着陆焊盘的导电性。
附图说明
图1为现有技术中存储器的用于制备位线结构的金属层的形态结构示意图。
图2为本申请的一种具体实施方式中的制备方法的步骤流程示意图。
图3至图9为本申请的一种具体实施方式中的制备方法的各步骤对应的半导体器件的结构示意图。
图10至图13为制备位线结构时制备方法的各步骤对应的半导体器件的结 构示意图。
图14至图16为部分去除所述第二绝缘层时各步骤对应的半导体器件的结构示意图。
具体实施方式
研究发现，外围接触着陆焊盘的形态不好、导电性不佳在于，现有技术中，预计要形成接触窗的位置的金属层，其上表面高度高于位于器件区的金属层的上表面高度，整个金属层，从外围区到器件区，呈现Z字分布，位于外围区的金属层整体高于位于器件区的金属层。此处可参阅图1，器件区103和外围区101之间还具有一接合区102，所述接触窗的位置位于所述接合区102内，金属层104在接合区102和外围区101的高度高于在器件区103的高度。
这样，在基于所述高深宽比的沟槽来刻蚀金属层、形成位线结构时，刻蚀气体会率先接触到位于预设的接触窗位置的金属层，先对其进行刻蚀，之后再接触到位于器件区的金属层，对该属于器件区的金属层进行刻蚀。这就导致，在形成位线结构时，刻蚀气体会率先接触到位于预设的接触窗位置的金属层，先对其进行刻蚀，之后再接触到位于器件区的金属层，对该属于器件区的金属层进行刻蚀，这样，位于预设的接触窗位置的金属层先接触到刻蚀气体，其形貌相较于位于器件区的金属层，被蚀刻的更多，很容易就发生颈化现象(Necking)甚至发生破裂(Broken)，影响最终形成的外围接触着陆焊盘的导电性。
以下结合图示对半导体器件及半导体器件的形成方法进行了进一步的解释和阐述。
请看图2至图9，其中图2为本申请的一种具体实施方式中的制备方法的步骤流程示意图，图3至图9为本申请的一种具体实施方式中的制备方法的各步骤对应的半导体器件的结构示意图。
在该具体实施方式中，提出了一种半导体器件的形成方法，包括以下步骤：S21提供衬底201，所述衬底201具有依次邻接的外围区101、接合区102和器 件区103，此处请参阅图3；S22在所述衬底201的上表面形成金属层104，此处请参阅图7；S23在所述金属层104上方形成介电层204，此处请参阅图8；S24在所述介电层204中形成开孔，此处请参阅图9，所述开孔位于所述外围区101或接合区102中至少一处的上方，以暴露所述金属层104形成接触窗205，且暴露于所述接触窗205的金属层104的上表面高度低于位于所述器件区103的金属层104的上表面高度。
在该具体实施方式中，暴露于所述接触窗205的金属层104的上表面高度低于位于所述器件区103的金属层104的上表面高度，能够有效的防止在对所述金属层104进行刻蚀时，刻蚀气体先接触到位于所述接触窗205区域的金属层104的上表面，避免影响基于所述接触窗205形成的外围接触着陆焊盘的导电性。
在一种具体实施方式中，形成所述金属层104时，包括以下步骤：在所述衬底201上表面形成第一绝缘层202；部分去除所述第一绝缘层202，以形成台阶状的第一绝缘层202，且位于外围区101的所述第一绝缘层202的上表面高度低于位于所述器件区103的所述第一绝缘层202的上表面高度；在所述第一绝缘层202的上表面形成台阶状的所述金属层104，且位于外围区101的所述金属层104的上表面高度低于位于所述器件区103的所述金属层104的上表面高度。
该具体实施方式中，可以在生成厚度均等的金属层104时保证位于所述接触窗205的金属层104的上表面高度低于位于所述器件区103的金属层104的上表面高度，并且，该步骤也与制备存储器的步骤流程相一致。在将该制备方法应用到存储器的制备中时，该步骤可以对应到外围区氮化物去除(Periphery nitride remove)的步骤中。
在一种具体实施方式中，所述第一绝缘层202包括氮化物层。在制备存储器的过程中，需要在金属层104下方形成一层氮化硅层，该层可以作为所述第一绝缘层202。
请参阅图4至图6，在一种具体实施方式中，所述部分去除所述第一绝缘 层202，包括以下步骤：在所述第一绝缘层202上表面形成图形化的第一掩膜层210，所述外围区101以及部分所述接合区102暴露于所述第一掩膜层210，所述第一掩膜层210覆盖所述器件区103以及剩余所述接合区102，请参阅图4；以所述第一掩膜层210为掩膜部分去除所述第一绝缘层202，请参阅图5；去除所述第一掩膜层210，请参阅图6。
这样，就可以在基于所述第一掩膜层210对所述第一绝缘层202进行部分去除时，将暴露于所述第一掩膜层210的所述外围区101以及部分所述接合区102部分去除。在一种具体实施方式中，暴露在所述第一掩膜层210外的区域被完全刻蚀至暴露所述衬底201表面，在一些其他的具体实施方式中，暴露于第一掩膜层210外的区域只是被刻蚀至一定深度，并不贯穿所述第一绝缘层202。
在一种具体实施方式中，在进行第一绝缘层202的部分去除时，可根据需要设置所述第一绝缘层202的刻蚀深度，如需要采用该种半导体器件制备存储器，则需要根据存储器需要的第一绝缘层202的最小厚度，来设置所述第一绝缘层202被部分去除时的去除深度。
在一种具体实施方式中，采用干法刻蚀或湿法刻蚀中的至少一种来实现所述第一绝缘层202的部分去除。
在图4至图6所示的具体实施方式中，部分去除后的第一绝缘层202呈台阶状，之后，若还有其他的材料层生长在所述第一绝缘层202的上表面，在所述材料层的厚度均等的情况下，该生长在所述第一绝缘层202上表面的其他材料层也呈台阶状，即使在这些后续生成的材料层上方形成所述金属层104，也可以得到台阶状的金属层104，保证暴露于所述接触窗205的金属层104的上表面高度低于位于器件区103的金属层104的上表面高度。
在一种具体实施方式中，还包括以下步骤：在所述衬底201上表面形成第二绝缘层203；部分去除所述第二绝缘层203，以在与所述接触窗205对应的位置形成凹槽，所述凹槽的底面也位于所述第二绝缘层203内；在所述第二绝缘层203上表面形成所述金属层104，且形成于所述凹槽内的金属层104的上表 面高度低于所述器件区103的金属层104的上表面高度。
在将该制备方法应用到存储器的制备中时，该步骤可以对应到位线结构中位线接触插塞的形成过程，即对所述位线结构中金属层104下方的多晶硅层的图形化的步骤中。在该具体实施方式时，没有对所述多晶硅层下方的氮化物层的形态结构做要求，而是直接修改多晶硅层的形态结构，使得所述多晶硅层呈现台阶状，这样，生长在所述多晶硅层上表面的金属层104也会呈台阶状，并且暴露于接触窗205的金属层104的上表面低于位于器件区103的金属层104的上表面。
在具有氮化物层作为第一绝缘层202的基础上，在所述氮化物层的上表面还形成有多晶硅层，这是与存储器的制备流程相一致的。因此，除了对所述氮化物层进行图形化处理，改变金属层104所形成到的表面的高度，还可以对所述多晶硅层进行图形化处理，来改变金属层104所形成到的表面的高度。
在该具体实施方式中，所述多晶硅层作为所述第二绝缘层203，被图形化处理，在预设区域形成了所述凹槽，以使得在所述多晶硅层的上表面形成金属层104时，凹槽内的金属层104其上表面的高度低于位于所述凹槽外的金属层104的上表面高度。这样，通过预设所述凹槽的位置，就可以限制暴露于所述接触窗205的金属层104的上表面高度低于位于所述器件区103的金属层104的上表面高度，并达到相应的效果。
在一种具体实施方式中，在部分去除所述第二绝缘层203，包括以下步骤：在所述第二绝缘层203上表面形成图形化的第二掩膜层208，所述第二掩膜层208在与所述接触窗205对应的位置形成有通孔209，请看图14，图14中的通孔209将所述接触窗205要形成到的位置包含进去；从所述通孔209沿垂直所述衬底201上表面的方向向下刻蚀所述第二绝缘层203，以在所述第二绝缘层203表面形成所述凹槽，此处请参阅图15；去除所述第二掩膜层208。这里通过限制图形化的第二掩膜层208的暴露区域，来限制凹槽的位置，此处请参阅图16。
在图15所示的具体实施方式中，所述第二绝缘层203被所述凹槽贯穿，实 际上，在将所述制备方法应用到存储器的制备时，所述凹槽的底面应当位于所述第二绝缘层203内部，与形成存储器所需的第二绝缘层203(即多晶硅层)的最小厚度相关。
另外，还需要注意的是，在图14至图16所示的具体实施方式中，所述第二掩膜层208图形化后形成的通孔209没有如图4至图6中图形化的第一掩膜层210一样，将所有的外围区101都暴露在外，而是只暴露了接触窗205的位置以及接触窗205的位置的周围区域，实际上，第二掩膜层208图形化后暴露出来的面积也可以如图4至图6中所示的，将所有的外围区101都暴露在外，以形成台阶状的第二掩膜层208。
在一种具体实施方式中，还包括以下步骤：刻蚀所述金属层104以形成位线结构，且所述位线结构具有伸入至所述外围区101上方的部分。
这是形成了金属层104之后的操作。在该操作中，在刻蚀所述金属层104形成位线结构的过程中，延长所述位线结构的长度，将所述位线结构延伸至外围区101内一预设距离，使得所述位线结构靠近所述接触窗205一侧的端头也具有较高的高度，并且与所述接触窗205所暴露的金属层104的上表面高度基本一致，这也可以防止所述接触窗205与所述位线结构的接触不良。
请参阅图10至图13，在一种具体实施方式中，刻蚀所述金属层104以形成所述位线结构，包括以下步骤：在所述金属层104上方形成图形化的第三掩膜层206，请参阅图10，所述第三掩膜层206覆盖所述器件区103、接合区102和部分外围区101；以所述第三掩膜层206为掩膜以图形化所述金属层104以形成位线结构，且所述第三掩膜层206的一端覆盖至所述外围区101，请参阅图11；去除所述第三掩膜层206，请参阅图12。在图10至图13所示的具体实施方式中，还展现了形成位线结构过程中，第三掩膜层图形化后形成的沟槽207的大深宽比。在图10至图13中，沟槽207的深度D与沟槽的宽度W之间的比值即为所述沟槽207的深宽比。当该值较大时，刻蚀气体在刻蚀该沟槽207下方的金属层时刻蚀的均匀度难以控制。
由图13可以看出，所述第三掩膜层206的端头延伸到了外围区101内，基 于该图13中所示的第三掩膜层206形成的位线结构也延伸到所述外围区101内。
这种结构既可以适用于位于接触窗205所在区域内的金属层104上表面低于位于器件区103的金属层104上表面的情况，也适用于位于接触窗205所在区域内的金属层104上表面不低于位于器件区103的金属层104上表面的情况。
在一种具体实施方式中，所述金属层104包括钨层等导电金属材料层。在使用所述制备方法制备存储器时，所述多晶硅层与所述金属层104之间还设置有TiN层等，所述TiN层等也跟随台阶状的多晶硅层或氮化物层中的至少一种起伏，形成台阶，以保证形成在这些TiN层等材料层上表面的金属层104具有台阶状的上表面。
在该具体实施方式中，还提供了一种半导体器件，包括：衬底201，形成有外围区101、器件区103和接合区102；金属层104，形成于所述衬底201上方；介电层204，形成于所述金属层104上方，且所述介电层204表面形成有接触窗205，以暴露所述金属层104，且暴露于所述接触窗205的金属层104的上表面高度低于位于所述器件区103的所述金属层104的上表面高度。
在该具体实施方式中，暴露于所述接触窗205的金属层104的上表面高度低于位于所述器件区103的金属层104的上表面高度，能够有效的防止在对所述金属层104进行刻蚀时，刻蚀气体先接触到位于所述接触窗205区域的金属层104的上表面，避免影响基于所述接触窗205形成的外围接触着陆焊盘的导电性。
在一种具体实施方式中，还包括：第一绝缘层202，形成于所述衬底201上表面，位于所述金属层104下方，且位于外围区101下方的所述第一绝缘层202的上表面高度低于位于所述器件区103下方的所述第一绝缘层202的上表面高度。在一种具体实施方式中，所述第一绝缘层202包括氮化物层。在制备存储器的过程中，为了与存储器的制备流程相一致，这里的第一绝缘层202指的是位于金属层104下方的氮化硅层。
在一种具体实施方式中，还包括：第二绝缘层203，形成于所述衬底201 上表面，位于所述金属层104下方，且位于所述接触窗205下方的所述第二绝缘层203的上表面高度低于所述器件区103下方的所述第二绝缘层203的上表面高度。
在制备存储器的过程中，为了与存储器的制备流程相一致，这里的第二绝缘层203指的是位于金属层104下方、氮化硅层上方的多晶硅层。
在具有氮化物层作为第一绝缘层202的基础上，在所述氮化物层的上表面还形成有多晶硅层，这是与存储器的制备流程相一致的。因此，除了对所述氮化物层进行图形化处理，改变金属层104所形成到的表面的高度，还可以对所述多晶硅层进行图形化处理，来改变金属层104所形成到的表面的高度。
在该具体实施方式中，所述多晶硅层作为所述第二绝缘层203，被图形化处理，在预设区域形成了所述凹槽，能够使得在所述多晶硅层的上表面形成金属层104时，凹槽内的金属层104其上表面的高度低于位于所述凹槽外的金属层104的上表面高度。这样，通过预设所述凹槽的位置，就可以限制暴露于所述接触窗205的金属层104的上表面高度低于位于所述器件区103的金属层104的上表面高度，并达到相应的效果。
在一种具体实施方式中，所述半导体器件包括位线结构，所述位线结构由所述金属层104构成，并具有伸入至所述外围区101上方的部分。这是形成了金属层104之后的操作。在该具体实施方式中，所述位线结构的长度被延长延伸至外围区101内一预设距离，使得所述位线结构靠近所述接触窗205一侧的端头也具有较高的高度，与所述接触窗205所暴露的金属层104的上表面高度基本一致，这也可以防止所述接触窗205与所述位线结构的接触不良。
本申请虽然已以较佳实施例公开如上，但其并不是用来限定本申请，任何本领域技术人员在不脱离本申请的精神和范围内，都可以利用上述揭示的方法和技术内容对本申请技术方案做出可能的变动和修改，因此，凡是未脱离本申请技术方案的内容，依据本申请的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本申请技术方案的保护范围。
工业实用性：
本申请实施例中，通过提供衬底，所述衬底具有依次邻接的外围区、接合区和器件区；在所述衬底的上表面形成金属层；在所述金属层上方形成介电层；在所述介电层中形成开孔，所述开孔位于所述外围区或接合区中至少一处的上方，以暴露所述金属层形成接触窗，且暴露于所述接触窗的金属层的上表面高度低于位于所述器件区的金属层的上表面高度。这样，能够解决外围接触着陆焊盘的形态不好、导电性不佳的问题，提高存储器的制备良率。

Claims (12)

  1. 一种半导体器件的形成方法，包括以下步骤：
    提供衬底，所述衬底具有依次邻接的外围区、接合区和器件区；
    在所述衬底的上表面形成金属层；
    在所述金属层上方形成介电层；
    在所述介电层中形成开孔，所述开孔位于所述外围区或接合区中至少一处的上方，以暴露所述金属层形成接触窗，且暴露于所述接触窗的金属层的上表面高度低于位于所述器件区的金属层的上表面高度。
  2. 根据权利要求1所述的半导体器件的形成方法，其中，形成所述金属层时，包括以下步骤：
    在所述衬底上表面形成第一绝缘层；
    部分去除所述第一绝缘层，以形成台阶状的第一绝缘层，且位于外围区的所述第一绝缘层的上表面高度低于位于所述器件区的所述第一绝缘层的上表面高度；
    在所述第一绝缘层的上表面形成台阶状的所述金属层，且位于外围区的所述金属层的上表面高度低于位于所述器件区的所述金属层的上表面高度。
  3. 根据权利要求2所述的半导体器件的形成方法，其中，所述部分去除所述第一绝缘层，包括以下步骤：
    在所述第一绝缘层上表面形成图形化的第一掩膜层，所述外围区以及部分所述接合区暴露于所述第一掩膜层，所述第一掩膜层覆盖所述器件区以及剩余所述接合区；
    以所述第一掩膜层为掩膜部分去除所述第一绝缘层；
    去除所述第一掩膜层。
  4. 根据权利要求2所述的半导体器件的形成方法，其中，所述第一绝缘层包括氮化物层。
  5. 根据权利要求1所述的半导体器件的形成方法，其中，还包括以下步骤：
    在所述衬底上表面形成第二绝缘层；
    部分去除所述第二绝缘层，以在与所述接触窗对应的位置形成凹槽，所述凹槽的底面也位于所述第二绝缘层内；
    在所述第二绝缘层上表面形成所述金属层，且形成于所述凹槽内的金属层的上表面高度低于所述器件区的金属层的上表面高度。
  6. 根据权利要求5所述的半导体器件的形成方法，其中，在部分去除所述第二绝缘层，包括以下步骤：
    在所述第二绝缘层上表面形成图形化的第二掩膜层，所述第二掩膜层在与所述接触窗对应的位置形成有通孔；
    从所述通孔沿垂直所述衬底上表面的方向向下刻蚀所述第二绝缘层，以在所述第二绝缘层表面形成所述凹槽；
    去除所述第二掩膜层。
  7. 根据权利要求1所述的半导体器件的形成方法，其中，还包括以下步骤：
    刻蚀所述金属层以形成位线结构，且所述位线结构具有伸入至所述外围区上方的部分。
  8. 根据权利要求7所述的半导体器件的形成方法，其中，刻蚀所述金属层以形成所述位线结构，包括以下步骤：
    在所述金属层上方形成图形化的第三掩膜层，所述第三掩膜层覆盖所述器件区、接合区和部分外围区；
    以所述第三掩膜层为掩膜以图形化所述金属层以形成位线结构，且所述第三掩膜层的一端覆盖至所述外围区；
    去除所述第三掩膜层。
  9. 一种半导体器件，包括：
    衬底，形成有外围区、器件区和接合区；
    金属层，形成于所述衬底上方；
    介电层，形成于所述金属层上方，且所述介电层表面形成有接触窗，以暴露所述金属层，且暴露于所述接触窗的金属层的上表面高度低于位于所述器件 区的所述金属层的上表面高度。
  10. 根据权利要求9所述的半导体器件，其中，还包括：第一绝缘层，形成于所述衬底上表面，位于所述金属层下方，且位于外围区下方的所述第一绝缘层的上表面高度低于位于所述器件区下方的所述第一绝缘层的上表面高度。
  11. 根据权利要求9所述的半导体器件，其中，还包括：第二绝缘层，形成于所述衬底上表面，位于所述金属层下方，且位于所述接触窗下方的所述第二绝缘层的上表面高度低于所述器件区下方的所述第二绝缘层的上表面高度。
  12. 根据权利要求9所述的半导体器件，其中，所述半导体器件包括位线结构，所述位线结构由所述金属层构成，并具有伸入至所述外围区上方的部分。
PCT/CN2021/099989 2020-08-12 2021-06-15 半导体器件及半导体器件的形成方法 Ceased WO2022033161A1 (zh)

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