WO2022028163A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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WO2022028163A1
WO2022028163A1 PCT/CN2021/103703 CN2021103703W WO2022028163A1 WO 2022028163 A1 WO2022028163 A1 WO 2022028163A1 CN 2021103703 W CN2021103703 W CN 2021103703W WO 2022028163 A1 WO2022028163 A1 WO 2022028163A1
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region
isolation
corner
substrate
regions
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PCT/CN2021/103703
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English (en)
French (fr)
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朱柄宇
洪海涵
卢经文
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长鑫存储技术有限公司
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Priority to US17/471,256 priority Critical patent/US12002707B2/en
Publication of WO2022028163A1 publication Critical patent/WO2022028163A1/zh

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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material

Definitions

  • Embodiments of the present application relate to a semiconductor structure and a manufacturing method thereof.
  • the semiconductor structure usually includes an array area and a peripheral area surrounding the array area.
  • the underlying substrate When etching and cleaning the underlying substrate of the array area and the peripheral area, the underlying substrate will be partially consumed or even the film will come off. , the consumption of substrate material can lead to performance defects in the substrate, such as leakage.
  • An embodiment of the present application provides a method for fabricating a semiconductor structure, including: providing a substrate, the substrate includes an active region and an isolation region located between adjacent active regions, the active region includes the corner region adjacent to the isolation region; performing a doping process, implanting dopant ions into the corner region, and the doping ions are used to slow down the oxidation rate of the corner region; after performing the doping process,
  • the substrate is subjected to a removal process, which can remove the oxidized substrate. During the removal process, the structures in the isolation regions expose the sidewalls of the corner regions.
  • an embodiment of the present application further provides a semiconductor structure, including: a substrate, the substrate includes an active region and an isolation region located between adjacent active regions, the active region The region includes a corner region adjacent to the isolation region, the structure in the isolation region exposes the sidewall of the corner region; the corner region contains dopant ions for slowing the corner Oxidation rate of the region.
  • 1 to 5 are schematic cross-sectional structural diagrams corresponding to each step of a method for forming a semiconductor structure
  • 6 to 15 are schematic cross-sectional structural diagrams corresponding to each step of the method for forming a semiconductor structure according to an embodiment of the present application.
  • a substrate 100 is provided that includes active regions 101 and isolation regions 102 between adjacent active regions 101 , the active regions 101 including corner regions adjoining the isolation regions 102 .
  • the material of the substrate 100 includes polysilicon, and subsequent removal processes for the substrate 100 are mostly performed in an atmospheric environment, and the polysilicon will be naturally oxidized in an atmospheric environment.
  • the dividing line used to divide the active region 101 and the isolation region 102 in the illustration is only for illustration. In fact, the dividing line is not necessarily perpendicular to the surface of the substrate 100, and the dividing line may also have a certain inclination angle. , the inclination angle of the dividing line can be equal to the inclination angle of the sidewall of the trench formed by subsequent etching.
  • an etching process is performed on the isolation region 102 to form a trench 120 , and the trench 120 is used to form an isolation structure.
  • the sidewalls of the corner regions of the active region 101 will be exposed, and the exposed sidewalls of the corner regions will be oxidized, and the oxide layer formed after oxidation is relatively opposite to the substrate 100 .
  • the material is more easily removed by the etching process.
  • the etching process of etching to form the trench 120 is a continuous process, and the etchant of the etching process will be in contact with the exposed sidewall of the corner region, the oxide formed by natural oxidation at the sidewall of the corner region will be removed by etching in a short period of time.
  • the substrate 100 at the sidewall of the corner region is always exposed to the atmospheric environment, and the oxide layer formed by oxidation cannot effectively isolate oxygen in the air.
  • the sidewalls of the corner regions of the substrate 100 will always be oxidized at a faster oxidation rate, that is, the oxidation rate when the substrate 100 is in direct contact with air, so that the substrate 100 will be consumed at a faster rate, and finally the formation of Larger chamfer 103.
  • the chamfer 103 has a first width d1 in a direction parallel to the surface of the substrate 100 and a first thickness d2 in a direction perpendicular to the surface of the substrate 100, and there is no necessary size between the first width d1 and the first thickness d2
  • the magnitudes of the first width d1 and the first thickness d2 are related to the etching time of the trench 120 and the oxidation rate of the substrate 100 when the substrate 100 is in direct contact with air. Specifically, the faster the oxidation rate of the substrate 100 when it is in direct contact with air, the larger the first width d1 and the first thickness d2.
  • a first cleaning process is performed on the bottom surface and sidewalls of the trench 120 , and the first cleaning process is used to remove residual etchant and debris of the substrate 100 .
  • the cleaning agent in the first cleaning process will contact the substrate 100 at the chamfer 103 and remove the oxide layer formed by natural oxidation, thereby causing further consumption to the substrate 100 .
  • the first width d1 and the first thickness d2 of the chamfer 103 are further increased to form the chamfer 103 having a larger size.
  • isolation structures 12 are formed within trenches 120 (refer to FIG. 3).
  • the isolation structure 12 generally includes a first isolation layer 121 covering the bottom surface and sidewalls of the trench 120 , a second isolation layer 122 covering the bottom surface and sidewalls of the first isolation layer 121 , and a third isolation layer 123 filling the trench 120 .
  • the material of the isolation layer 121 and the third isolation layer 123 is generally silicon oxide
  • the material of the second isolation layer 122 is generally silicon nitride, that is, a commonly used "ONO" isolation structure.
  • the first isolation layer 121 is usually over-etched and cannot completely cover the surface of the chamfer 103 That is, the isolation structure 12 will have a recessed portion 124 located at the top of the first isolation layer 121 , and the recessed portion 124 will expose at least part of the sidewall of the corner region. In this way, the size of the chamfer 103 will be further enlarged in other subsequent removal processes.
  • a second cleaning process is performed on the top surface of the active region 101 , and the second cleaning process is used to remove impurities on the top surface of the active region 101 .
  • the second cleaning process is a pre-step of depositing and forming a gate dielectric layer on the top surface of the active region 101 .
  • the cleaning agent will contact the exposed sidewalls of the corner regions, and etch and remove oxides on the sidewalls of the corner regions, further enlarging the size of the chamfer 103 , thereby making the corners of the active region 101 .
  • the integrity of the area is poor.
  • the present application provides a semiconductor structure and a manufacturing method thereof.
  • the oxidation rate of the corner regions is slowed down, so that solvents such as etchants or cleaning agents in the process are removed.
  • the oxide film layer is thinner when it touches the side wall of the corner area; since the size of the chamfer is positively related to the thickness of the oxide film layer, by suppressing the oxidation of the corner area, the size of the chamfer can be effectively reduced, which is beneficial to ensure the The corner regions of the source region have better structural integrity.
  • 6 to 14 are schematic cross-sectional structural diagrams corresponding to each step of the method for forming a semiconductor structure according to an embodiment of the present application.
  • a substrate 200 and a mask layer 220 and a shielding film 211 sequentially stacked on the substrate 200 are provided.
  • the substrate 200 includes an active region 201 and an isolation region 202 located between adjacent active regions 201 ; in the direction perpendicular to the surface of the substrate 200 , the orthographic projection of the top surface of the active region 201 and the mask The orthographic projections of the film layer 220 are coincident.
  • the mask layer 220 can be directly used to etch the subsequent trenches without forming different mask layers for the subsequent doping of doping ions and the etching of the trenches, which is beneficial to reduce process steps and shorten the substrate length.
  • the exposure time of the top surface of the substrate 200 reduces the consumption of the substrate 200 .
  • the mask layer 220 is a hard mask layer, and the material of the mask layer 220 includes polysilicon; the shielding film 211 is used to form a shielding layer, and the shielding layer plays the role of shielding ion implantation, and the material of the shielding film 211 includes oxide silicon.
  • the substrate 200 can generally be divided into an array area and a peripheral area surrounding the array area. In this embodiment, the area where the substrate 200 is located is taken as an example of the peripheral area.
  • the mask layer 220 may be formed together with the polysilicon layer of the array region.
  • the shielding film 211 is etched to form the shielding layer 210, and the masking layer 220 is removed.
  • the active region 201 includes a corner region 212 adjacent to the isolation region 202 , and the shielding layer 210 covers the top surface of the corner region 212 ; in other embodiments, the shielding layer exposes the top surface of the corner region.
  • a doping process is performed.
  • an ion implantation process with an implantation angle is used to perform ion implantation on the corner region 212 and the top of the isolation region 202; in other embodiments, ion implantation is performed only on the corner region.
  • the type of dopant ion is related to the cause of oxidation of the sidewalls of the corner region 212 .
  • the sidewall of the corner region 212 may be either naturally oxidized, that is, oxidized by oxygen contained in the air in the atmospheric environment, or oxidized by an oxidizing component in a solvent such as an etchant or a cleaning agent. Since the oxidation components in different solvents may be different, the type of dopant ions can be adjusted according to the type of solvent used in the subsequent process steps and the time period for which the substrate 200 is exposed to the atmospheric environment; A variety of doping ions are simultaneously doped to slow down the oxidation rate of the corner region 212 under different oxidation environments.
  • the doping ions include nitrogen ions
  • the implantation dose of the doping ions is 1e12-1e16 atoms/cm2, for example, 1e13 atoms/cm2, 1e14 atoms/cm2 or 1e15 atoms/cm2. If the implantation dose of dopant ions is too small, the effect of slowing down the oxidation rate will not be obvious, and a large chamfer will still be formed later; if the implantation dose of dopant ions is too large, the effect of slowing down the oxidation rate will not be significantly improved, and may The damage to the corner region 212 is not conducive to the subsequent doping of P-type or N-type doping ions to form a doped region.
  • the implantation energy of the ion implantation process ranges from 1KV to 60KV, such as 20KV, 30KV or 40KV. If the implantation energy is too low, the implantation depth of the dopant ions will be shallow, and the corner region which can reduce consumption is thin; if the implantation energy is too high, the substrate 200 may be damaged due to the deep injection range.
  • the injection angle is 5° ⁇ 60°, for example, 20°, 30° or 40°. If the implantation angle is too small, the doping effect of the top region of the corner region 212 is likely to be poor; if the implantation angle is too large, a large implantation energy is required to implant the doping ions to the preset depth, and the adjacent corner regions are easy to be implanted. The intermediate regions between 212 cause unnecessary doping that may affect the performance of subsequently formed semiconductor structures.
  • the substrate 200 is subjected to a removal process, and the removal process can remove the oxidized substrate 200.
  • the removal process includes an etching process, a cleaning process, and the like.
  • the removal process performed after the doping process may include the following process steps:
  • an etching process is performed on the substrate 200 of the isolation region 202 (refer to FIG. 8 ) to form trenches 230 exposing the sidewalls of the corner regions 212 , and the trenches 230 are used to form isolation structures.
  • the corner region 212 is doped with doping ions, the rate of natural oxidation of the sidewall of the corner region 212 when exposed and the rate of oxidation by the oxidizing components in the etchant are relatively slow. In the process, the total thickness of the oxide film layer that can be etched and removed by the etchant is relatively thin.
  • a first cleaning process is performed on the trench 230 , and the cleaning solution of the first cleaning process is in contact with the sidewall of the corner region 212 .
  • the corner region 212 is doped with doping ions that slow down the doping rate, the doping ions can inhibit the natural oxidation of the substrate 200 between the etching process and the first cleaning process, and inhibit the cleaning solution
  • the oxidizing component oxidizes the substrate 200 to ensure that the total thickness of the oxide film that can be removed by the first cleaning process is relatively thin. In this way, it is beneficial to suppress further consumption of the material in the corner region 212 by the first cleaning process, and ensure that the corner region 212 has good structural integrity.
  • isolation structures 240 are formed.
  • the isolation structure 240 is a three-layer structure of a silicon oxide layer-silicon nitride layer-silicon oxide layer, and the isolation structure 240 has a recessed portion 241, and the recessed portion 241 exposes the sidewall of the corner region 212; in other embodiments Among them, the isolation structure may also be a double-layer stack structure including a silicon oxide layer and a silicon nitride layer.
  • the structure and material of the isolation structure 240 are not limited herein, but only to emphasize that the isolation structure 240 has certain defects, and the defects include the presence of the recessed portion 241 exposing the sidewall of the corner region 212 .
  • the corner region 212 may only be equal to the thickness of recess 241 . In this way, it is beneficial to reduce the number of doping ions to be implanted and shorten the range of ion implantation, so that the ion implantation process causes less damage to the corner region 212 and ensures that the active region 201 has good electrical performance.
  • a second cleaning process is performed on the top surface of the active region 201 , and the cleaning solution of the second cleaning process is in contact with the side walls of the corner region 212 .
  • the doping ions can also suppress the natural oxidation from the formation of the isolation structure 240 to the second cleaning process, as well as the natural oxidation of the sidewall of the corner region 212 and the oxidation of the cleaning agent during the second cleaning process, so as to further ensure the corners Structural integrity of region 212.
  • a deposition process is performed on the top surface of the active region 201 to form a gate dielectric layer 250 .
  • the gate dielectric layer 250 only covers the top surface of the active region 201 . Because the formation process of the gate dielectric layer 250 is usually to form a whole layer of gate dielectric film on the substrate 200 first, and then pattern and etch the gate dielectric film. When the gate dielectric layer 250 does not cover the sidewall of the corner region 212 , the etching process may remove the oxide film layer on the sidewall of the corner region 212 .
  • the doping ions can inhibit the natural oxidation of the substrate 200 during the etching process, and inhibit the oxidation components in the etchant from oxidizing the substrate 200 to ensure the etching process.
  • the total thickness of the oxide film that can be removed by the process is relatively thin. In this way, it is beneficial to suppress further consumption of the material of the corner region 212 by the etching process, and to ensure that the corner region 212 has good structural integrity.
  • the gate dielectric layer 350 also covers the sidewall of the corner region 212 , that is, covers the surface of the chamfer 303 .
  • the gate dielectric layer 350 can isolate the corner region 312 , which is beneficial to avoid further oxidation of the corner region 312 and further consumption of the material of the corner region 312 .
  • an isolation part 260 and a gate electrode 270 are formed.
  • the isolation portion 260 covers the corner region.
  • the sidewalls of 212 serve the purpose of isolating the corner region 212 and the gate electrode 270 , which is beneficial to ensure that the transistor formed by the gate electrode 270 , the gate dielectric layer 250 and the active region 201 has good electrical performance.
  • the material of the isolation portion 260 may be the same as or different from that of the gate dielectric layer 250 .
  • the method of implanting dopant ions into the corner region is used to slow down the oxidation rate of the corner region, avoid the formation of a thicker oxide layer, and avoid the removal process to remove the oxide layer at a faster rate and gradually form larger chamfers , to ensure that the corner region of the active region has good structural integrity, thereby ensuring that the active region and the semiconductor structure including the active region, such as field effect transistors, have good electrical performance.
  • the embodiments of the present application further provide a semiconductor structure, and the semiconductor structure can be manufactured by the above-mentioned manufacturing method of the semiconductor structure.
  • the semiconductor structure includes: a substrate 200, the substrate 200 includes an active region 201 and an isolation region between adjacent active regions 201, the active region 201 includes a corner region 212 adjacent to the isolation region, the isolation region
  • the inner structure exposes the sidewalls of the corner region 212 ; the corner region 212 contains dopant ions, and the dopant ions are used to slow down the oxidation rate of the corner region 212 .
  • the isolation region has an isolation structure 240
  • the isolation structure 240 has a recessed portion 241 (refer to FIG. 12 ), and the recessed portion 241 exposes the sidewall of the corner region 212 .
  • the semiconductor structure further includes: a gate dielectric layer 250 and an isolation portion 260, the gate dielectric layer 250 covers the top surface of the active region 201, and the isolation portion 260 covers the sidewall of the corner region 212; in other embodiments, the gate dielectric layer Covers the top surface of the active region and covers the sidewalls of the corner regions.
  • the trench is formed after the doping process, which is beneficial to suppress the oxidation of the substrate during the etching process, avoid etching the thick oxide layer by the etching process, and ensure the chamfer formed by the etching process. smaller.

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Abstract

本申请实施例提供一种半导体结构及其制作方法，半导体结构的制作方法包括：提供衬底，衬底包括有源区和位于相邻有源区之间的隔离区，有源区包括与隔离区邻接的拐角区域；进行掺杂工艺，向拐角区域内注入掺杂离子，掺杂离子用于减缓拐角区域的氧化速率；在进行掺杂工艺之后，对衬底进行去除工艺，去除工艺可去除氧化后的衬底，在进行去除工艺的过程中，隔离区内的结构暴露拐角区域侧壁。

Description

半导体结构及其制作方法
交叉引用
本申请要求于2020年8月6日递交的名称为“半导体结构及其制作方法”、申请号为202010784644.X的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本申请实施例涉及一种半导体结构及其制作方法。
背景技术
随着半导体结构尺寸的微缩，在制作半导体结构过程中，膜层材料的额外消耗可能会导致较大的性能缺陷。
具体来说，半导体结构通常包括阵列区和包围阵列区的外围区，在对阵列区和外围区的底层衬底进行刻蚀、清洗等工艺时，底层衬底会被部分消耗甚至产生膜层脱落，衬底材料的消耗会导致衬底出现性能缺陷，例如漏电等。
发明内容
本申请实施例提供一种半导体结构的制作方法，包括：提供衬底，所述衬底包括有源区和位于相邻所述有源区之间的隔离区，所述有源区包括与所述隔离区邻接的拐角区域；进行掺杂工艺，向所述拐角区域内注入掺杂离子，所述掺杂离子用于减缓所述拐角区域的氧化速率；在进行所述掺杂工艺之后，对所述衬底进行去除工艺，所述去除工艺可去除氧化后的所述衬底，在进行所述去除工艺的过程中，所述隔离区内的结构暴露所述拐角区域侧壁。
根据本申请实施例，本申请实施例还提供了一种半导体结构，包括：衬底，所述衬底包括有源区和位于相邻所述有源区之间的隔离区，所述有源区包括与所述隔离区邻接的拐角区域，所述隔离区内的结构暴露出所述拐角区域侧壁；所述拐角区域内包含有掺杂离子，所述掺杂离子用于减缓所述拐角区域的氧化速率。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1至图5为半导体结构的形成方法各步骤对应的剖面结构示意图；
图6至图15为本申请实施例提供的半导体结构的形成方法各步骤对应的剖面结构示意图。
具体实施方式
参考图1，提供衬底100，衬底100包括有源区101和位于相邻有源区101之间的隔离区102，有源区101包括与隔离区102邻接的拐角区域。
衬底100的材料包括多晶硅，后续针对衬底100进行的去除工艺大多在大气环境下进行，多晶硅在大气环境下会发生自然氧化。
需要说明的是，本文图示中用于分割有源区101和隔离区102的分割线仅作为示意使用，实际上分割线不一定垂直于衬底100表面，分割线也可以具有一定的倾斜角度，分割线的倾斜角度可与后续刻蚀形成的沟槽侧壁的倾斜角度相等。
参考图2，对隔离区102进行刻蚀工艺，形成沟槽120，沟槽120用于形成隔离结构。
在刻蚀形成沟槽120的过程中，有源区101的拐角区域侧壁会被暴露出来，而被暴露出的拐角区域侧壁处会发生氧化，氧化后形成的氧化层相对于衬底100材料更容易被刻蚀工艺去除。
由于刻蚀形成沟槽120的刻蚀工艺是一个持续过程，且刻蚀工艺的刻蚀剂会与暴露出的拐角区域侧壁接触，因此，拐角区域侧壁处自然氧化形成的氧化物会在较短的时间内被刻蚀去除。这导致拐角区域侧壁处的衬底100会始终暴露在大气环境下，氧化形成的氧化物层无法对空气中的氧气进行有效隔离。如此，衬底100的拐角区域侧壁会始终以较快的氧化速率，即衬底100与空气直接接触时的氧化速率发生氧化，进而导致衬底100会以较快的速率被消耗，最终形成较大的倒角103。
倒角103具有在平行于衬底100表面方向上的第一宽度d1和在垂直于与衬底100表面方向上的第一厚度d2，第一宽度d1与第一厚度d2之间没有必然的大小关系，第一宽度d1和第一厚度d2的大小都与沟槽120的刻蚀时间以及衬底100与空气直接接触时的氧化速率有关。具体地，衬底100与空气直接接触时的氧化速率越快，第一宽度d1和第一厚度d2就越大。
参考图3，在形成沟槽120之后，对沟槽120底面和侧壁进行第一清洗工艺，第一清洗工艺用于去除残留的刻蚀剂和衬底100的碎屑。
第一清洗工艺的清洗剂会与倒角103处的衬底100接触，并去除自然氧化形成的氧化物层，从而对衬底100造成进一步的消耗。具体可表现为倒角103的第一宽度d1和第一厚度d2会进一步增大，形成具有更大尺寸的倒角103。
参考图4，在进行第一清洁工艺之后，在沟槽120(参考图3)内形成隔离结构12。
隔离结构12通常包括覆盖沟槽120底面和侧壁的第一隔离层121，覆盖第一隔离层121底面和侧壁的第二隔离层122以及填充沟槽120的第三隔离层123，第一隔离层121和第三隔离层123的材料通常为氧化硅，第二隔离层122的材料通常为氮化硅，即常用的“ONO”隔离结构。
由于氮化硅具有较高的硬度，在对氮化硅和氧化硅进行刻蚀时，由于刻蚀选择比的原因，第一隔离层121通常会发生过刻蚀，无法完全覆盖倒角103表面，即隔离结构12会具有位于第一隔离层121顶部的凹陷部124，凹陷部124会暴露出至少部分拐角区域侧壁。如此，倒角103的尺寸在后续的其他去除工艺中会被进一步放大。
参考图5，形成隔离结构12之后，对有源区101顶面进行第二清洗工艺，第二清洗工艺用于去除有源区101顶面的杂质。
第二清洗工艺是在有源区101顶面沉积形成栅介质层的前置步骤。在进行第二清洗工艺的过程中，清洗剂会与暴露出的拐角区域侧壁接触，并刻蚀去除拐角区域侧壁的氧化物，进一步放大倒角103的尺寸，进而使得有源区101拐角区域的完整性较差。
为解决上述问题，本申请实施提供一种半导体结构及其制作方法，通过 向有源区的拐角区域注入掺杂离子，减缓拐角区域的氧化速率，使得去除工艺的刻蚀剂或清洗剂等溶剂在接触到拐角区域侧壁时氧化物膜层较薄；由于倒角的大小与氧化物膜层的厚度正相关，通过抑制拐角区域的氧化，能够有效减小倒角的尺寸，有利于保证有源区的拐角区域具有较好的结构完整性。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图6至图14为本申请实施例提供的半导体结构的形成方法各步骤对应的剖面结构示意图。
参考图6，提供衬底200和在衬底200上依次层叠的掩膜层220和屏蔽膜211。
本实施例中，衬底200包括有源区201和位于相邻有源区201之间的隔离区202；在垂直于衬底200表面的方向上，有源区201顶面的正投影与掩膜层220的正投影重合。如此，可直接利用掩膜层220进行后续沟槽的刻蚀，无需形成不同的掩膜层以分别进行后续掺杂离子的掺杂和沟槽的刻蚀，有利于减少工艺步骤以及缩短衬底200顶面暴露的时间，减少衬底200的消耗。
本实施例中，掩膜层220为硬掩膜层，掩膜层220的材料包括多晶硅；屏蔽膜211用于形成屏蔽层，屏蔽层起到屏蔽离子注入的作用，屏蔽膜211的材料包括氧化硅。
衬底200通常可以分为阵列区和包围阵列区的外围区，本实施例中，以衬底200所在区域为外围区为例。掩膜层220可与阵列区的多晶硅层一同形成。
参考图7，刻蚀屏蔽膜211形成屏蔽层210，并去除掩膜层220。
本实施例中，有源区201包括与隔离区202邻接的拐角区域212，屏蔽层210覆盖拐角区域212顶面；在其他实施例中，屏蔽层暴露出拐角区域顶面。
参考图8，进行掺杂工艺。
本实施例中，采用具有注入角度的离子注入工艺对拐角区域212以及隔 离区202顶部进行离子注入；在其他实施例中，仅对拐角区域进行离子注入。
掺杂离子的类型与拐角区域212侧壁的氧化原因有关。具体地，拐角区域212侧壁既可能是自然氧化，即被大气环境中空气所包含的氧气所氧化，也可能是被刻蚀剂或清洗剂等溶剂内的氧化成分所氧化。由于不同溶剂内的氧化成分可能不同，因此，可根据后续进行的工艺步骤所使用的溶剂类型以及衬底200暴露在大气环境下的时长调整掺杂离子的类型；此外，可在拐角区域212内同时掺杂多种掺杂离子，以减缓拐角区域212在不同氧化环境下的氧化速率。
本实施例中，掺杂离子包括氮离子，掺杂离子的注入剂量为1e12～1e16atoms/cm2，例如为1e13atoms/cm2、1e14atoms/cm2或1e15atoms/cm2。掺杂离子的注入剂量过小，则减缓氧化速率的效果不明显，后续依然会形成较大的倒角；掺杂离子的注入剂量过大，则对减缓氧化速率的效果提升不明显，且可能对拐角区域212造成损伤，不利于后续掺杂P型或N型掺杂离子以形成掺杂区。
本实施例中，离子注入工艺的注入能量范围为1KV～60KV，例如20KV、30KV或40KV。注入能量过低，则掺杂离子的注入深度较浅，可减少消耗的拐角区域较薄；注入能量过高，则可能因为射程过深而对衬底200造成损伤。
本实施例中，注入角度为5°～60°，例如20°、30°或40°。注入角度过小，则容易导致拐角区域212的顶部区域掺杂效果较差；注入角度过大，则需要较大的注入能量才能将掺杂离子注入到预设深度，且容易对相邻拐角区域212之间的中间区域造成不必要的掺杂，该不必要的掺杂可能会影响后续形成的半导体结构的性能。
本实施例中，在进行掺杂工艺之后，对衬底200进行去除工艺，去除工艺可去除氧化后的衬底200，在进行去除工艺的过程中，隔离区202内的结构暴露拐角区域212侧壁。其中，去除工艺包括刻蚀工艺和清洗工艺等。
具体地，在掺杂工艺之后进行的去除工艺可包括以下工艺步骤：
参考图9，对隔离区202(参考图8)的衬底200进行刻蚀工艺，形成暴露拐角区域212侧壁的沟槽230，沟槽230用于形成隔离结构。
本实施例中，由于拐角区域212内掺杂有掺杂离子，拐角区域212侧壁 在暴露的情况自然氧化的速率以及被刻蚀剂内的氧化成分氧化的速率较慢，在整个刻蚀工艺的过程中，刻蚀剂所能刻蚀去除的氧化物膜层总厚度较薄。
如此，有利于避免因拐角区域212侧壁材料消耗过多而导致的膜层剥落，以及避免因膜层剥落或其他原因形成的倒角203尺寸过大，即保证倒角203的第二宽度d3和第二厚度d4较小，使得拐角区域212具有较好的结构完整性，进而避免因结构缺失而导致的漏电风险。
参考图10，在进行刻蚀工艺之后，对沟槽230进行第一清洗工艺，第一清洗工艺的清洗液与拐角区域212侧壁相接触。
本实施例中，由于拐角区域212内掺杂有减缓掺杂速率的掺杂离子，掺杂离子能够抑制从刻蚀工艺到第一清洗工艺之间的衬底200自然氧化，以及抑制清洗液中的氧化成分氧化衬底200，保证第一清洗工艺所能去除的氧化物膜层总厚度较薄。如此，有利于抑制第一清洗工艺对拐角区域212材料的进一步消耗，保证拐角区域212具有良好的结构完整性。
参考图11，形成隔离结构240。
本实施例中，隔离结构240为氧化硅层-氮化硅层-氧化硅层的三层叠层结构，隔离结构240具有凹陷部241，凹陷部241暴露出拐角区域212侧壁；在其他实施例中，隔离结构还可以是包括氧化硅层和氮化硅层的双层叠层结构。本文不对隔离结构240的结构和材料进行限定，仅在于强调隔离结构240存在一定缺陷，缺陷包括存在暴露拐角区域212侧壁的凹陷部241。
需要说明的是，如果在形成隔离结构240之后对拐角区域212进行离子掺杂，以抑制倒角203的形成或者减小倒角203的尺寸，在垂直于衬底200表面的方向上，拐角区域212的厚度可仅等于凹陷部241的厚度。如此，有利于减少需注入的掺杂离子数量以及缩短离子注入的射程，使得离子注入工艺对拐角区域212的损伤较小，保证有源区201具有良好的电学性能。
参考图12，对有源区201顶面进行第二清洗工艺，第二清洗工艺的清洗液与拐角区域212侧壁相接触。
本实施例中，掺杂离子还可以抑制从形成隔离结构240到进行第二清洗工艺的自然氧化，以及抑制第二清洗工艺过程中的拐角区域212侧壁自然氧化 和清洗剂氧化，进一步保证拐角区域212的结构完整性。
参考图13，对有源区201顶面进行沉积工艺，形成栅介质层250。
本实施例中，栅介质层250仅覆盖有源区201的顶部表面。由于栅介质层250的形成工艺通常是先在衬底200上形成整层栅介质膜，再对栅介质膜进行图形化刻蚀。在栅介质层250不覆盖拐角区域212的侧壁时，刻蚀工艺会去除拐角区域212侧壁的氧化物膜层。
由于拐角区域212内掺杂有减缓掺杂速率的掺杂离子，掺杂离子能够抑制刻蚀过程中的衬底200自然氧化，以及抑制刻蚀剂中的氧化成分氧化衬底200，保证刻蚀工艺所能去除的氧化物膜层总厚度较薄。如此，有利于抑制刻蚀工艺对拐角区域212材料的进一步消耗，保证拐角区域212具有良好的结构完整性。
在其他实施例中，参考图14，栅介质层350还覆盖拐角区域212侧壁，即覆盖倒角303表面。栅介质层350能够对拐角区域312起到隔离作用，有利于避免拐角区域312的进一步氧化以及避免拐角区域312材料的进一步消耗。
参考图15，形成隔离部260和栅极270。
本实施例中，由于拐角区域212的侧壁被暴露，为避免后续形成的栅极270与拐角区域212侧壁相接触等问题，因此，需要形成额外形成隔离部260，隔离部260覆盖拐角区域212侧壁，起到隔离拐角区域212和栅极270的目的，有利于保证由栅极270、栅介质层250和有源区201构成的晶体管具有良好的电学性能。
隔离部260的材料可以与栅介质层250的材料相同或不同。
本实施例中，采用向拐角区域注入掺杂离子的方法减缓拐角区域的氧化速率，避免形成较厚的氧化层，以及避免去除工艺以较快的速率去除氧化层而逐渐形成较大的倒角，保证有源区的拐角区域具有较好的结构完整性，进而保证有源区以及包含有源区的半导体结构，例如场效应管，具有良好的电学性能。
相应地，本申请实施例还提供一种半导体结构，该半导体结构可由上述半导体结构的制作方法制成。
参考图15，半导体结构包括：衬底200，衬底200包括有源区201以及位于相邻有源区201之间的隔离区，有源区201包括与隔离区邻接的拐角区域 212，隔离区内的结构暴露出拐角区域212侧壁；拐角区域212内包含有掺杂离子，掺杂离子用于减缓拐角区域212的氧化速率。
本实施例中，隔离区内具有隔离结构240，隔离结构240内具有凹陷部241(参考图12)，凹陷部241暴露出拐角区域212侧壁。
本实施例中，半导体结构还包括：栅介质层250和隔离部260，栅介质层250覆盖有源区201顶面，隔离部260覆盖拐角区域212侧壁；在其他实施例中，栅介质层覆盖有源区顶面以及覆盖拐角区域侧壁。
本实施例中，拐角区域内具有可减缓氧化速率的掺杂离子，有利于避免拐角区域在经历去除工艺时被刻蚀消耗较多的材料，进而保证拐角区域具有较好的结构完整性。
本实施例中，在进行掺杂工艺之后形成沟槽，有利于抑制刻蚀工艺过程中的衬底氧化，避免刻蚀工艺对较厚的氧化层进行刻蚀，保证刻蚀工艺形成的倒角较小。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (13)

  1. 一种半导体结构的制作方法，包括：
    提供衬底，所述衬底包括有源区和位于相邻所述有源区之间的隔离区，所述有源区包括与所述隔离区邻接的拐角区域；
    进行掺杂工艺，向所述拐角区域内注入掺杂离子，所述掺杂离子用于减缓所述拐角区域的氧化速率；
    在进行所述掺杂工艺之后，对所述衬底进行去除工艺，所述去除工艺可去除氧化后的所述衬底，在进行所述去除工艺的过程中，所述隔离区内的结构暴露所述拐角区域侧壁。
  2. 根据权利要求1所述的半导体结构的制作方法，其中，所述对所述衬底进行去除工艺，包括：对所述隔离区的所述衬底进行刻蚀工艺，形成暴露所述拐角区域侧壁的沟槽，所述沟槽用于形成隔离结构。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，所述去除工艺还包括：在进行所述刻蚀工艺之后，对所述沟槽进行第一清洗工艺，所述第一清洗工艺的清洗液与所述拐角区域侧壁相接触。
  4. 根据权利要求1或2所述的半导体结构的制作方法，其中，所述隔离区内具有隔离结构，所述隔离结构具有凹陷部，所述凹陷部暴露所述拐角区域侧壁；所述去除工艺包括：在进行所述掺杂工艺之后，对所述有源区顶面进行第二清洗工艺，所述第二清洗工艺的清洗液与所述拐角区域侧壁相接触。
  5. 根据权利要求4所述的半导体结构的制作方法，其中，在进行所述第二清洗工艺之后，对所述有源区进行沉积工艺，形成覆盖所述有源区顶面的栅氧化层，所述栅氧化层和所述隔离结构暴露所述拐角区域侧壁。
  6. 根据权利要求1所述的半导体结构的制作方法，其中，所述掺杂离子包括氮离子，所述掺杂离子的注入剂量为1e12～1e16atoms/cm 2。
  7. 根据权利要求1或6所述的半导体结构的制作方法，其中，注入所述掺杂离子的工艺步骤包括：提供所述衬底和位于所述衬底上的屏蔽层，所述有源区还包括位于相邻所述拐角区域之间的中间区域，所述屏蔽层覆盖所述中间区域顶面，所述屏蔽层用于屏蔽所述掺杂离子的注入；对所述衬底进行离子注 入工艺。
  8. 根据权利要求7所述的半导体结构的制作方法，其中，所述离子注入工艺的注入能量范围为1KV～60KV。
  9. 根据权利要求7所述的半导体结构的制作方法，其中，所述屏蔽层还覆盖所述拐角区域并暴露出所述隔离区；对所述衬底进行具有注入角度的所述离子注入工艺。
  10. 根据权利要求9所述的半导体结构的制作方法，其中，所述注入角度为5°～60°。
  11. 一种半导体结构，包括：
    衬底，所述衬底包括有源区和位于相邻所述有源区之间的隔离区，所述有源区包括与所述隔离区邻接的拐角区域，所述隔离区内的结构暴露出所述拐角区域侧壁；
    所述拐角区域内包含有掺杂离子，所述掺杂离子用于减缓所述拐角区域的氧化速率。
  12. 根据权利要求11所述的半导体结构，其中，所述隔离区内具有隔离结构，所述隔离结构具有凹陷部，所述凹陷部暴露出所述拐角区域侧壁。
  13. 根据权利要求12所述的半导体结构，其中，还包括：栅介质层和隔离部，所述栅介质层覆盖所述有源区顶面，所述隔离部覆盖所述拐角区域的侧壁。
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