WO2022022095A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2022022095A1
WO2022022095A1 PCT/CN2021/099278 CN2021099278W WO2022022095A1 WO 2022022095 A1 WO2022022095 A1 WO 2022022095A1 CN 2021099278 W CN2021099278 W CN 2021099278W WO 2022022095 A1 WO2022022095 A1 WO 2022022095A1
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Prior art keywords
shift register
signal
redundant
register unit
pull
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PCT/CN2021/099278
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English (en)
French (fr)
Inventor
赵重阳
缪应蒙
孙志华
曲峰
许晓春
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/796,660 priority Critical patent/US20230335029A1/en
Publication of WO2022022095A1 publication Critical patent/WO2022022095A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the invention belongs to the field of display technology, and in particular relates to a display panel and a display device.
  • GOA Gate Driver on Array, array substrate row drive
  • TFT Thin Film Transistor, thin film field effect transistor
  • the gate switch circuit integrated on the array substrate using the GOA technology is also called a GOA circuit or a shift register circuit.
  • the present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display panel and a display device.
  • an embodiment of the present disclosure provides a display panel, which includes p groups of pixel units, each of the p groups of pixel units includes q rows of the pixel units, and p and q are both integers greater than or equal to 2 wherein, the pixel units located in the same group are provided with gate scanning signals simultaneously by the same shift register; the pixel units located in the same group and in the same column are provided with data voltage signals by different data lines.
  • N is an even number greater than or 4
  • p is greater than or equal to 2N
  • each of the shift registers is connected to one of the clock signal lines, and different clock signal lines are connected to the connected of the shift register is different.
  • each of the shift registers includes q shift register units, and the shift register units are connected to the gate lines in a one-to-one correspondence.
  • each of the shift register units is connected to the clock signal line through a signal connection line, and different shift register units are connected to different signal connection lines.
  • a plurality of the shift register units included in each of the shift registers are connected to the clock signal line through the same signal connection line, and a plurality of the shift register units included in different shift registers are connected to the clock signal line.
  • the shift register units are connected to different signal connection lines.
  • each of the shift register units includes at least an input sub-circuit, an output sub-circuit, and a pull-up reset sub-circuit; wherein, the input sub-circuit responds to the input signal input from the signal input terminal, and inputs the input signal to the pull-up node; the output sub-circuit responds to the potential of the pull-up node, and outputs the clock signal input by the clock signal line through the signal output terminal; the pull-up reset sub-circuit responds to the pull-up the pull-up reset signal input by the reset signal terminal, and reset the potential of the pull-up node through the non-working level signal;
  • Each of the N adjacent shift registers is connected to the N clock signal lines in a one-to-one correspondence, and the i-th shift register and the i+N-th shift register are connected to the same clock Signal line; i takes 1 to pN.
  • the signal input terminal of each of the shift register units in the 1st to (N-4)/2th shift registers is responsive to the frame start signal
  • the signal output end of the jth shift register unit in the Mth shift register is connected to the jth shift register in the M+(N-4)/2 shift register
  • the pull-up reset signal terminal of the jth shift register unit in the Lth shift register is connected to the jth shift register in the L+(N/2-1)th shift register
  • the display panel further includes N-2 redundant shift registers, the N-2 redundant shift registers are respectively connected to N-2 clock signal lines, and each redundant shift register includes q a redundant shift register unit; the redundant shift register unit has the same structure as the shift register unit; wherein,
  • the signal output terminals of the j-th redundant shift register unit in the 1-th to N/2-1 redundant shift registers are respectively connected to the p-(N/2-2) to p-th redundant shift register units.
  • the signal output terminals of the jth redundant shift register unit in the N/2 to N-2 redundant shift registers are respectively connected to the 1 to N/2-1 redundant shift registers.
  • the pull-up reset signal terminal of the jth redundant shift register unit in the register is respectively connected to the 1 to N/2-1 redundant shift registers.
  • a signal input terminal of each of the shift register units in the first to (N-2)/2 shift registers responds to a frame start signal
  • the signal output terminal of the jth shift register unit in the Mth shift register is connected to the jth shift register unit in the M+(N-2)/2 shift register the signal input terminal;
  • the pull-up reset signal terminal of the jth shift register unit in the Lth shift register is connected to the pull-up reset signal terminal of the jth shift register unit in the L+N/2th shift register.
  • Signal output terminal; M takes 1 to p-(N-2)/2; L takes 1 to pN/2; j takes 1 to q.
  • the display panel further includes N redundant shift registers, and the N shift registers are respectively connected to N clock signal lines; each of the redundant shift registers includes q redundant shift register units; the The redundant shift register unit has the same structure as the shift register unit; wherein,
  • the signal output terminals of the jth redundant shift register unit in the first to N/2 redundant shift registers are respectively connected to the pN/2+1 to pth redundant shift registers
  • the pull-up reset signal terminals of the j shift register units; the signal output terminals of the jth redundant shift register unit in the N/2+1 to N redundant shift registers are respectively connected
  • the signal input terminal of each of the shift register units in the 1st to N/2th shift registers is responsive to a frame start signal
  • the signal output terminal of the jth shift register unit in the Mth shift register is connected to the signal input of the jth shift register unit in the M+N/2th shift register end;
  • the pull-up reset signal terminal of the jth shift register unit in the Lth shift register is connected to the jth shift register in the L+(N/2+1)th shift register
  • the display panel further includes N+2 redundant shift registers, the first to N of the N+2 redundant shift registers are respectively connected to the N clock signal lines, and the N+1 and N +2 are respectively connected to the first and second clock signal lines; each of the redundant shift registers includes q redundant shift register units; the redundant shift register unit has the same structure as the shift register unit ;in,
  • the signal output terminals of the jth redundant shift register units in the 1st to N/2+1th redundant shift registers are respectively connected to the pN/2 to pth ones of the shift registers. j pull-up reset signal terminals of the shift register units;
  • the signal output terminals of the jth redundant shift register unit in the N/2+2 to N+2 redundant shift registers are respectively connected to the first to N/2+1 redundant shift registers.
  • the pull-up reset signal terminal of the jth redundant shift register unit in the shift register is respectively connected to the first to N/2+1 redundant shift registers.
  • each of the shift registers includes a shift register unit and q sub-signal output ends connected to the signal output ends of the shift register unit, the The sub-signal output terminals are connected to the gate lines in a one-to-one correspondence.
  • each of the shift register units includes at least an input sub-circuit, an output sub-circuit, and a pull-up reset sub-circuit; wherein, the input sub-circuit responds to the input signal input from the signal input terminal, and inputs the input signal to the pull-up node; the output sub-circuit responds to the potential of the pull-up node, and inputs the clock signal input from the clock signal line to the signal output end, so that the signal output end passes through the q sub-circuits the signal output terminal outputs; the pull-up reset subcircuit is responsive to the pull-up reset signal input from the pull-up reset signal terminal, and resets the potential of the pull-up node through a non-working level signal;
  • Each adjacent N of the shift register units is connected to the N of the clock signal lines in a one-to-one correspondence, and the i-th shift register unit is connected to the i+N-th shift register unit in the same way
  • the clock signal line; i takes 1 to pN.
  • the signal input terminals of the first to (N-4)/2 of the shift register units respond to the frame start signal
  • the signal output terminal of the M-th said shift register unit is connected to the signal input terminal of the M+(N-4)/2-th said shift register unit;
  • the pull-up reset signal terminal of the Lth shift register unit is connected to the signal output terminal of the L+(N/2-1)th shift register unit; M takes 1 to p-(N-4)/2 ; L takes 1 to p-(N/2-1).
  • the display panel further includes N-2 redundant shift registers, the N-2 redundant shift registers are respectively connected to N-2 clock signal lines, and each redundant shift register includes 1 a redundant shift register unit; the redundant shift register unit has the same structure as the shift register unit; wherein,
  • the signal output terminals of the first to N/2-1 redundant shift register units are respectively connected to the pull-up reset signal terminals of the p-(N/2-2) to p-th shift register units;
  • the signal output terminals of the N/2th to N-2th redundant shift register units are respectively connected to the pull-up reset signal terminals of the 1st to N/2-1th redundant shift register units.
  • the signal input terminals of the first to (N-2)/2 of the shift register units are responsive to the frame start signal
  • the signal output terminal of the Mth said shift register unit is connected to the signal input terminal of the M+(N-2)/2th said shift register unit;
  • the pull-up reset signal terminal of the Lth shift register unit is connected to the signal output terminal of the L+N/2th shift register unit; M takes 1 to p-(N-2)/2; L takes 1 to pN/2.
  • the display panel further includes N redundant shift registers, and the N redundant shift registers are respectively connected to N clock signal lines; each of the redundant shift registers includes one redundant shift register unit;
  • the redundant shift register unit has the same structure as the shift register unit;
  • the signal output terminals of the 1st to N/2th redundant shift register units are respectively connected to the pull-up reset signal terminals of the p-N/2+1th to pth said shift register units;
  • the signal output terminals of the N/2+1 to Nth redundant shift register units are respectively connected to the pull-up reset signal terminals of the first to N/2 redundant shift register units.
  • the signal input terminals of the 1st to N/2th said shift register units are responsive to the frame start signal
  • the signal output end of the Mth described shift register unit is connected to the signal input end of the M+N/2th described shift register unit;
  • the pull-up reset signal terminal of the Lth shift register unit is connected to the signal output terminal of the L+(N/2+1)th shift register unit; M takes 1 to pN/2; L takes 1 to p -(N/2+1).
  • the display panel further includes N+2 redundant shift registers, the first to N of the N+2 redundant shift registers are respectively connected to the N clock signal lines, and the N+1 and N+2 are respectively connected to the first and second clock signal lines; each of the redundant shift registers includes a redundant shift register unit; the redundant shift register unit and the shift register unit have the same structure;
  • the signal output terminals of the 1st to N/2+1th redundant shift register units are respectively connected to the pull-up reset signal terminals of the p-N/2th to pth said shift register units;
  • the signal output terminals of the N/2+2 to N+2 redundant shift register units are respectively connected to the pull-up reset signal terminals of the first to N/2+1 redundant shift register units.
  • the pixel units in q rows in each group are arranged adjacently.
  • an embodiment of the present disclosure provides a display device including the above-mentioned display panel.
  • 1 is a circuit diagram of a shift register unit
  • FIG. 2 is a schematic diagram of a cascade connection of a gate drive circuit
  • Fig. 3 is the circuit diagram of another kind of shift register unit
  • FIG. 4 is a schematic structural diagram of a display panel according to an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a connection between a shift register and a clock signal line according to an embodiment of the disclosure
  • FIG. 6 is a schematic diagram of the connection between another shift register and a clock signal line according to an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of a cascade connection of shift registers when the number of clock signal lines is 6 and the duty cycle of the clock signal is 30% according to an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of a cascade connection of shift registers when the number of clock signal lines is 8 and the duty cycle of the clock signal is 30% according to an embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of a cascade connection of shift registers when the clock signal line is 10 and the duty cycle of the clock signal is 30% according to an embodiment of the present disclosure
  • FIG. 10 is a schematic diagram of a cascade connection of shift registers when the number of clock signal lines is 4 and the duty cycle of the clock signal is 40% according to an embodiment of the present disclosure
  • 11 is a schematic diagram of a cascade connection of shift registers when the number of clock signal lines is 6 and the duty cycle of the clock signal is 40% according to an embodiment of the present disclosure
  • FIG. 12 is a schematic diagram of a cascade of shift registers when the number of clock signal lines is 8 and the duty cycle of the clock signal is 40% according to an embodiment of the present disclosure
  • FIG. 13 is a schematic diagram of a cascade connection of shift registers when the clock signal line is 10 and the duty cycle of the clock signal is 40% according to an embodiment of the present disclosure
  • FIG. 14 is a schematic diagram of a cascade of shift registers when the number of clock signal lines is 4 and the duty cycle of the clock signal is 50% according to an embodiment of the present disclosure
  • 15 is a schematic diagram of a cascade connection of shift registers when the number of clock signal lines is 6 and the duty cycle of the clock signal is 50% according to an embodiment of the present disclosure
  • 16 is a schematic diagram of a cascade of shift registers when the number of clock signal lines is 8 and the duty cycle of the clock signal is 50% according to an embodiment of the present disclosure
  • 17 is a schematic diagram of a cascade of shift registers when the clock signal line is 10 and the duty cycle of the clock signal is 50% according to an embodiment of the present disclosure
  • FIG. 18 is a schematic diagram of connection between still another shift register and a clock signal line according to an embodiment of the disclosure.
  • 19 is a schematic diagram of another cascade connection of shift registers when the number of clock signal lines in the embodiment of the disclosure is 6 and the duty cycle of the clock signal is 30%;
  • 20 is a schematic diagram of another cascade connection of shift registers when the number of clock signal lines in the embodiment of the disclosure is 8 and the duty cycle of the clock signal is 30%;
  • 21 is a schematic diagram of a cascade of another shift register when the clock signal line is 10 and the duty cycle of the clock signal is 30% according to an embodiment of the present disclosure
  • 22 is a schematic diagram of a cascade connection of another shift register when the number of clock signal lines is 4 and the duty cycle of the clock signal is 40% according to an embodiment of the present disclosure
  • 23 is a schematic diagram of another cascade connection of shift registers when the number of clock signal lines in the embodiment of the present disclosure is 6 and the duty cycle of the clock signal is 40%;
  • 24 is a schematic diagram of another cascade connection of shift registers when the number of clock signal lines is 8 and the duty cycle of the clock signal is 40% according to an embodiment of the present disclosure
  • 25 is a schematic diagram of another cascade connection of shift registers when the clock signal line is 10 and the duty cycle of the clock signal is 40% according to an embodiment of the present disclosure
  • 26 is a schematic diagram of another cascade connection of shift registers when the number of clock signal lines in the embodiment of the disclosure is 4 and the duty cycle of the clock signal is 50%;
  • 27 is a schematic diagram of another cascade connection of shift registers when the number of clock signal lines in the embodiment of the disclosure is 6 and the duty cycle of the clock signal is 50%;
  • 28 is a schematic diagram of another cascade connection of shift registers when the number of clock signal lines is 8 and the duty cycle of the clock signal is 50% according to an embodiment of the present disclosure
  • FIG. 29 is a schematic diagram of another cascade connection of shift registers when the clock signal line is 10 and the duty cycle of the clock signal is 50% according to an embodiment of the present disclosure.
  • the transistors used in the embodiments of the present invention may be thin film transistors or field effect transistors or other devices with the same characteristics. , Drain is no difference.
  • one electrode is called the first electrode
  • the other electrode is called the second electrode
  • the gate electrode is called the control electrode.
  • transistors can be divided into N-type and P-type according to their characteristics. In the following embodiments, N-type transistors are used for description. When N-type transistors are used, the first pole is the source of the N-type transistor, and the second pole is the source of the N-type transistor.
  • the working level signal in the embodiment of the present invention refers to a high-level signal
  • the non-working level signal is a low-level signal
  • the working level terminal is the high-level signal terminal
  • the non-working level terminal is the low-level signal terminal.
  • a display panel includes a plurality of gate lines and a plurality of data lines.
  • the intersection of the gate lines and the data lines defines a plurality of pixel regions, and each pixel region is provided with a pixel unit.
  • the structure of the display panel will be described by taking the extension direction of each gate line as the row direction and the extension direction of each data line as the column direction as an example.
  • the gate scanning signal is provided by the gate driving circuit, and the data voltage signal is provided by the source driving circuit; in the related art, the gate driving circuit can be integrated in the gate driving chip, and the source driving circuit can be integrated in the source driving circuit
  • the gate drive circuit includes A plurality of cascaded shift register units are integrated on the array substrate, and each shift register unit is connected to a gate line in a one-to-one correspondence, and is used to provide a gate scan signal for the gate line connected to it.
  • the pull-up reset subcircuit 3 responds to the pull-up reset signal output by the pull-up reset signal terminal RESET_PU, and resets the pull-up node PU through a low-level signal; the output reset module responds to the output reset signal , the signal output terminal OUTPUT is reset by a low level signal.
  • the output subcircuit 2 includes a first transistor M1; the pull-up reset subcircuit 3 includes a second transistor M2; the output subcircuit 2 includes a third transistor M3 and a storage capacitor C; the output reset subcircuit 4 It includes a fourth transistor M4; wherein the gate and source of M1 are connected to the signal input terminal INPUT, the drain of M1 is connected to the pull-up node PUPU; the gate of M2 is connected to the pull-up reset signal terminal RESET_PU, and the source of M2 is connected to the pull-up node Node PU, the drain of M2 is connected to the low-level signal terminal; the gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal, the drain of M3 is connected to the signal output terminal OUTPUT; the first terminal of C is connected to the The second end of the pull node PU and C is connected to the signal output terminal OUTPUT; the gate of M
  • the signal input terminal INPUT writes a high-level signal
  • M1 is turned on
  • the PU point is pulled up through the high-level signal
  • C is charged.
  • the output reset signal terminal RESET_OUTPUT inputs a high-level signal
  • M4 is turned on, and the output of the signal output terminal OUTPUT is pulled down through the low-level signal input at the low-level signal terminal
  • the pull-up reset signal terminal RESET_PU inputs a high-level signal
  • M2 turns on the low-level signal input through the low-level signal terminal and pulls down the potential of the pull-up node PU, thus completing the reset of the pull-up node PU and the signal output terminal OUTPUT.
  • the output reset subcircuit 4 may not be set in the shift register unit. After resetting the pull-up node PU in the reset stage, the pull-up node PU is at a low level, and M3 is turned off at this time. The signal output terminal OUTPUT is no longer output to complete the reset of the signal output terminal OUTPUT.
  • the cascade relationship of the first to fourth shift register units (GOA1-GOA4) is taken as an example;
  • the signal output terminal OUTPUT of the bit register unit is connected to the pull-up reset signal terminal RESET_PU of the shift register unit of the previous stage, and the signal input terminal INPUT of the shift register unit of the next stage.
  • a device that not only includes the above-mentioned input sub-circuit 1, output sub-circuit 2, and pull-up reset sub-circuit 3, but also includes a first pull-down Control sub-circuit, second pull-down control sub-circuit, first pull-down sub-circuit, second pull-down sub-circuit, first noise reduction sub-circuit, second noise-reduction sub-circuit, cascade sub-circuit, discharge sub-circuit, first auxiliary circuit subcircuit and a second auxiliary subcircuit.
  • the discharge sub-circuit discharges the pull-up node PU through the low level input from the low-level signal terminal in response to the pre-frame open signal input by the pre-frame open signal terminal STV0; the first pull-down control sub-circuit and the second pull-down control sub-circuit
  • the structure and function of the pull-down control sub-circuit are the same, and the two only work in time-sharing; for the same reason, the structure and function of the first pull-down sub-circuit and the second pull-down sub-circuit are the same; the structure of the first auxiliary sub-circuit and the second auxiliary sub-circuit and functions are the same; the structures and functions of the first noise reduction sub-circuit and the second noise reduction sub-circuit are the same.
  • Both the first auxiliary sub-circuit and the second auxiliary sub-circuit are in response to the input signal input from the signal input terminal INPUT, and respectively pull down the first pull-down node PD1 and the second pull-down node PD2 through a low-level signal;
  • the control sub-circuit controls the potential of the first pull-down node PD1 in response to the first power supply voltage input from the first power supply voltage signal terminal;
  • the second pull-down control sub-circuit responds to the second power supply input from the second power supply voltage signal terminal voltage to control the potential of the second pull-down node PD2;
  • the first pull-down subcircuit responds to the pull-up node PU, and pulls down the first pull-down node PD1 and the first pull-down control through the level signal input from the low-level signal terminal Node PD_CN1
  • the signals output by the cascaded signal output terminal OUT_C and the signal output terminal OUTPUT are the same, except that two output terminals are set in the shift register unit, one is the signal output terminal OUTPUT connected to the gate line , and the other is the cascade signal output terminal OUT_C for cascade.
  • the reason why the cascaded sub-circuits are separately arranged is to reduce the load of the signal output terminal OUTPUT, so as to avoid affecting the gate scan signal output by the signal output terminal OUTPUT.
  • the cascade signal output terminal OUT_C of the shift register unit of this stage is connected to the pull-up reset signal terminal RESET_PU of the shift register of the previous stage , and the signal input terminal INPUT of the next stage shift register unit.
  • the above-mentioned shift register unit may not be provided with a cascaded sub-circuit.
  • the signal output terminal OUTPUT of the shift register unit of this stage is connected to the pull-up reset signal terminal RESET_PU of the shift register of the previous stage, And the signal input terminal INPUT of the next stage shift register unit.
  • the first pull-down control sub-circuit and the second pull-down control sub-circuit both include a fifth transistor and a ninth transistor; wherein, in the first pull-down control sub-circuit and in the second pull-down control sub-circuit
  • the fifth transistors are represented by M5 and M5', respectively
  • the ninth transistors are represented by M9 and M9', respectively.
  • Both the first pull-down sub-circuit and the second pull-down sub-circuit include a sixth transistor and an eighth transistor; wherein, the sixth transistor in the first pull-down sub-circuit and the second pull-down sub-circuit is represented by M6 and M6' respectively,
  • the eight transistors are denoted by M8 and M8', respectively.
  • the first noise reduction sub-circuit and the second noise reduction sub-circuit each include a tenth transistor, an eleventh transistor and a twelfth transistor; wherein, the tenth transistor in the first noise reduction sub-circuit and the second noise reduction sub-circuit are respectively It is represented by M10 and M10', the eleventh transistor is represented by M11 and M11', respectively, and the twelfth transistor is represented by M12 and M12', respectively.
  • the discharge sub-circuit includes a seventh transistor M7; the cascaded sub-circuit includes a thirteenth transistor M13.
  • Both the first auxiliary sub-circuit and the second auxiliary sub-circuit include sixth transistors, which are represented by M16 and M16', respectively.
  • the gate and source of M1 are connected to the signal input terminal INPUT, the drain of M1 is connected to the pull-up node PUPU; the gate of M2 is connected to the pull-up reset signal terminal RESET_PU, the source of M2 is connected to the pull-up node PU, The drain of M2 is connected to the low-level signal terminal; the gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal, the drain of M3 is connected to the signal output terminal OUTPUT; the first terminal of C is connected to the pull-up node PU , the second terminal of C is connected to the signal output terminal OUTPUT; the gate and source of M5 are connected to the first power supply voltage terminal, the drain of M5 is connected to the first pull-down control node PD_CN1; the gate of M9 is connected to the first pull-down control node Node PD_CN1, the source of M9 is connected to the first power supply voltage terminal, the drain of M9 is connected
  • the gate of M16 is connected to the signal input terminal INPUT, the source of M16 is connected to the first pull-down node PD1, and the drain of M16 is connected to the low-level signal terminal.
  • the gate of M16' is connected to the signal input terminal INPUT, the source of M16' is connected to the second pull-down node PD2, and the drain of M16' is connected to the low-level signal terminal.
  • M5 and M9 form the first pull-down control sub-circuit
  • M5' and M9' form the first pull-down control sub-circuit to work in time-sharing (that is, to work in turn)
  • a noise reduction sub-circuit and a second noise reduction sub-circuit composed of M10', M11', and M12' are controlled by the first pull-down control sub-circuit and the second pull-down control sub-circuit, respectively, so the first noise-reduction sub-circuit and the third
  • the second noise reduction sub-circuit also works time-sharing.
  • the working principles of the first pull-down control sub-circuit and the second pull-down control sub-circuit are the same, and the working principles of the first and second noise-reduction sub-circuits are the same; therefore, only the first pull-down control sub-circuit and the second pull-down control sub-circuit work in the same way; When the first noise reduction sub-circuit works, the working principle of the shift register unit will be described.
  • the high-level signal is input to the open signal terminal before the frame, and the pull-up node PU is discharged through the low-level signal input from the low-level signal terminal to prevent the pull-up.
  • the display is abnormal due to the residual charge of the node PU.
  • the signal input terminal INPUT inputs a high-level signal
  • M1 is turned on
  • the pull-up node PU is pulled up by the high-level signal
  • C is charged.
  • M16 and M16' are both turned on, and the first The pull-down node PD1 and the second pull-down node PD2 are pulled low to avoid affecting the potential of the pull-up node PU.
  • the pull-up node PU is pulled high in the input stage, M3 and M13 are turned on, and the high-level signal input from the clock signal terminal is output to the gate line connected to it through the signal output terminal OUTPUT.
  • the connected signal output terminal OUT_C is the same as the signal output by the signal output terminal OUTPUT, that is, it outputs a high level signal to the pull-up reset signal terminal RESET_PU of the shift register unit of the previous stage, and the signal input of the shift register unit of the next stage. terminal INPUT.
  • the pull-up reset signal terminal RESET_PU inputs a high-level signal
  • M2 turns on the low-level signal input through the low-level signal terminal to pull down the potential of the pull-up node PU to reset the pull-up node PU.
  • the pull node PU is pulled low, M3 and M13 are turned off, and both the signal output terminal OUTPUT and the cascaded signal output terminal OUT_C no longer output high-level signals.
  • the first pull-down control node PD_CN1 and the pull-down node are both high-level signals, and M10, M11, and M12 are turned on, respectively lowering the outputs of the pull-up node PU, the signal output terminal OUTPUT, and the cascaded signal output terminal OUT_C. noise, until the next frame scan starts, the pull-up node PU potential is pulled high.
  • the signal output by the signal output terminal OUTPUT is only used to control the gate line and the gate line, while the cascaded signal output terminal OUT_C only It is used for the cascading of the shift register unit of the current stage and the shift register unit of the previous stage and the next stage.
  • the signals output by the signal output terminal OUTPUT and the cascaded signal output terminal OUT_C are synchronized. In practical applications, the setting of the cascaded sub-circuit can also be omitted.
  • one shift register unit in the gate driving circuit only provides a gate scan signal for one gate line, but with the continuous increase of the size of the display panel, from 65 inches, 75 inches to 98 inches, 110 inches, resolution
  • the rate has also been continuously improved, from FHD, UHD to 8K products, the refresh rate has been increased from 60HZ to 120HZ.
  • the charging time of each row of pixels is only 1.85us, and the charging time and charging rate of the product cannot meet the design requirements.
  • the product size is too large, and the delay of displaying the remote signal is also very large, and the risk of serialization is high.
  • an embodiment of the present disclosure provides a display panel, which includes p groups of pixel units, each of the p groups of pixel units includes q rows of pixel units, and both p and q are greater than or equal to 2 An integer of ; wherein, the pixel units in the same group are provided with gate scanning signals simultaneously by the same shift register; the pixel units in the same group and in the same column are provided with data voltage signals by different data lines.
  • the display panel includes P groups of pixel units, correspondingly including P shift registers and 2P gate lines; if there are h columns of pixel units, correspondingly includes 2h data line.
  • a group of pixel units is provided with gate scan signals by the same shift register, and the pixel units in the same group and in the same column are provided with data voltage signals by different data lines;
  • the refresh frequency can be effectively increased, thereby avoiding the problem of insufficient charging time and/or charging rate for the display panel, let alone a large-size display panel.
  • each group of pixel units includes two rows of pixel units, and each column of pixel units needs at least two data lines to provide data voltage signals.
  • each shift register it is not appropriate for each shift register to provide gate scan signals for too many rows of pixel units.
  • each group of pixel units includes two rows of pixel units, and each shift register simultaneously provides raster scan signals for two rows of pixel units in a group of pixel units; and located in different groups of pixel units
  • the gate scan signals are provided by different shift registers.
  • the two pixel units located in the same group and in the same column are provided with data voltage signals by two data lines.
  • each column of pixel units can consist of two pieces of data. line provides the data voltage. For example, two rows of pixel units in each group are arranged adjacent to each other.
  • the first pixel unit in each column in the same group can be connected to a data line
  • the second pixel unit in each column can be connected to another data line.
  • this connection method does not limit the protection scope of this embodiment, as long as the data lines connected to the two pixel units in the same group and in the same column are different.
  • the two rows of pixel units in each group may also be arranged non-adjacent, for example, the pixel units located in the first row and the third row are a group.
  • every two rows of pixel units are a group, and each column of pixel units is provided with data data voltages by two data lines as an example.
  • the display panel includes not only the above structure but also N clock signal lines, where N is an even number greater than or 4, and the number p of pixel units is greater than or equal to 2N;
  • the shift register is connected to the N clock signal lines in a one-to-one correspondence, and the i-th shift register and the i+N-th shift register are connected to the same clock signal line; i takes 1 to pN.
  • the clock signal line is used to provide a clock signal to the clock signal terminal of the shift register.
  • each shift register includes as many shift register cells as there are rows of pixel cells in each group. That is, each group includes two rows of pixel units, and each shift register includes two shift register units, and since the gate scan signals output by the two shift register units are the same, the two can use the same structure.
  • Each shift register unit may use any one of the aforementioned FIG. 1 or FIG. 3 .
  • the two shift register units in each shift register are connected to the same clock signal line. The following takes a 110-inch display panel using the 21T1C shift register unit and 10 clock signal lines shown in FIG. 3 as an example to describe the connection between the shift register unit in each shift register and the clock signal.
  • the 10 clock signal lines are respectively represented by clk1, clk2...clk10.
  • every 10 shift registers from top to bottom are respectively connected to clk1, clk2...clk10.
  • the first shift register goa1 includes two shift register units denoted as GOA1 and GOA1' respectively, wherein the clock signal terminal of GOA1 and the clock signal terminal of GOA1' are respectively connected to clk1 through a signal connection line. That is to say, there is a one-to-one correspondence between the signal connection lines and the shift register units. In this way, the currents of the clock signal lines of the two shift register units of each shift register are evenly distributed, which can effectively avoid signal connection. A large current occurs at the transfer hole connected to the line clock signal line, causing the transfer hole to burn out.
  • the second connection method also takes the number of clock signal lines of the first connection method as an example.
  • the first shift register goa1 includes two shift register units, which are respectively denoted as GOA1 and GOA1' , wherein the clock signal terminal of GOA1 and the clock signal terminal of GOA1' are respectively connected to clk1 through the same signal connection line. That is to say, there is a one-to-one correspondence between signal connection lines and shift registers.
  • this connection method reduces the number of signal connection lines by half, and avoids a large number of signal connection lines crossing the clock signal line to generate a large amount of parasitic capacitance, which can effectively improve the charging rate of the display panel.
  • each shift register includes q shift register units
  • the number N of clock signal lines is greater than or equal to an even number of 4, and the duty cycles of the clock signals are 30%, 40%, and 50%, respectively, for each shift register
  • the cascading relationship between register unit units is described. It should be noted here that in the following description, when the shift register includes the cascaded signal output terminal OUT_C, the signal output terminal OUTPUT of the current stage and the register is connected to the shift register unit of other stages through the cascaded signal output terminal OUT_C. cascade.
  • each shift in the first to (N-4)/2 shift registers The signal input terminal INPUT of the register unit responds to the frame open signal; the signal output terminal OUTPUT of the jth shift register unit in the Mth shift register is connected to the M+(N-4)/2th shift register.
  • the signal input terminal INPUT of the j shift register units; the pull-up reset signal terminal RESET_PU of the jth shift register unit in the Lth shift register is connected to the L+(N/2-1)th shift register.
  • the signal output terminal OUTPUT of the p-th shift register (the last stage shift register) is connected to the pull-up reset signal terminal RESET_PU of the p-(N/2-1)-th shift register unit; -(N/2-2) to the pull-up node PU of each shift register unit of the p shift registers has no shift register for which the reset signal is provided.
  • the pull-up node PU reset signal terminal of the jth shift register unit of the pth shift register needs the jth shift register unit of the pth + (N/2-1) shift register.
  • N-2 redundant shift registers are further provided in the display panel, the N-2 redundant shift registers are respectively connected to N-2 clock signal lines, and each redundant shift register is connected to N-2 clock signal lines.
  • the bit register includes q redundant shift register units (the same as the shift register units in the shift register), wherein the j-th redundant shift register in the 1-th to N/2-1 redundant shift registers
  • the signal output terminal OUTPUT of the register unit is respectively connected to the pull-up reset signal terminal RESET_PU of the jth shift register unit in the p-(N/2-2)th to pth shift registers; N/2th to N-2th
  • the signal output terminal OUTPUT of the j-th redundant shift register unit in the redundant shift registers is respectively connected to the j-th redundant shift register in the first to N/2-1 redundant shift registers.
  • the pull-up reset signal terminal RESET_PU of the unit; j takes 1 to q.
  • the following example illustrates the cascade relationship of each shift register when the number N of clock signal lines is an even number greater than or 6 and the duty cycle of the clock signal is 30%.
  • the number N of clock signal lines is equal to 6, and the 6 clock signal lines are clk1, clk2...clk6 respectively, each group includes two rows of pixel units, at this time j takes 1, 2, ie each of the p shift registers includes two shift register cells. At this time, every adjacent six shift registers are respectively connected to clk1, clk2...clk6, and the two shift register units in each shift register are connected to the same clock signal line; of course, this kind of The display panel also includes 4 redundant shift registers, each redundant shift register also includes two shift register units; the first to fourth of the 4 redundant shift registers are respectively connected to clk1, clk2...
  • the two shift register units of each redundant shift register are connected to the same clock signal line.
  • the signal input terminals INPUT of the two shift register units in the first shift register are both connected to the frame start signal line, that is, the two shift register units of the first shift register respond to the frame start signal.
  • the signal output terminal OUTPUT of the first shift register unit in the Mth shift register is connected to the signal input terminal INPUT of the first shift register unit in the M+1th shift register; the Mth shift register
  • the signal output terminal OUTPUT of the second shift register unit in the M+1 shift register is connected to the signal input terminal INPUT of the second shift register unit in the M+1th shift register; M takes 1 to p-1.
  • the pull-up reset signal of the first shift register unit in the Lth shift register is connected to the signal output terminal OUTPUT of the first shift register unit in the L+2th shift register; the Lth shift register The pull-up reset signal of the second shift register unit in the L+2 shift register is connected to the signal output terminal OUTPUT of the second shift register unit in the L+2th shift register; L takes 1 to p-2.
  • the signal output terminal OUTPUT of the first shift register unit in the pth shift register is connected to the signal input terminal INPUT of the first redundant shift register unit in the first redundant shift register;
  • the signal output terminal OUTPUT of the second shift register unit in the first redundant shift register is connected to the signal input terminal INPUT of the second redundant shift register unit in the first redundant shift register;
  • the Kth redundant shift register The signal output terminal OUTPUT of the first redundant shift register unit in the bit register is respectively connected to the signal input terminal INPUT of the first redundant shift register unit in the K+1 redundant shift registers;
  • the signal output terminal OUTPUT of the second redundant shift register unit in the remaining shift registers is respectively connected to the signal input terminal INPUT of the second redundant shift register unit in the K+1 redundant shift registers;
  • K takes 1 to 3.
  • the signal output terminal OUTPUT of the first redundant shift register unit in the first and second redundant shift registers is connected to the pull-up of the first shift register unit in the p-1 and p shift registers, respectively.
  • the reset signal terminal RESET_PU; the signal output terminal OUTPUT of the second redundant shift register unit in the first and second redundant shift registers is respectively connected to the second shift register in the p-1 to pth shift registers
  • the pull-up reset signal terminal RESET_PU of the register unit; the signal output terminal OUTPUT of the first redundant shift register unit in the third and fourth redundant shift registers is connected to the first and second redundant shift registers respectively.
  • the pull-up reset signal terminal RESET_PU of the first redundant shift register unit; the signal output terminals OUTPUT of the second redundant shift register unit in the third and fourth redundant shift registers are connected to the first and second redundant shift registers respectively.
  • the pull-up reset signal terminal RESET_PU of the second redundant shift register unit in the redundant shift register is connected to the first and second redundant shift registers respectively.
  • the number of clock signal lines N is equal to 8
  • the 8 clock signal lines are clk1, clk2...clk8 respectively, each group includes two rows of pixel units, at this time j is 1, 2, ie each of the p shift registers includes two shift register cells.
  • each redundant shift register also includes two shift register units; the 6 redundant shift registers are respectively connected to clk1, clk2...clk6, each redundant The two shift register units of the remaining shift register are connected to the same clock signal line.
  • the signal input terminals INPUT of the two shift register units in the first and second shift registers are connected to the frame start signal line, that is, the two shift register units of the first and second shift registers respond to the frame Turn on the signal.
  • the signal output terminal OUTPUT of the first shift register unit in the Mth shift register is connected to the signal input terminal INPUT of the first shift register unit in the M+2th shift register;
  • the signal output terminal OUTPUT of the second shift register unit in the bit register is connected to the signal input terminal INPUT of the second shift register unit in the M+2th shift register;
  • M takes 1 to p-2.
  • the pull-up reset signal terminal RESET_PU of the first shift register unit in the Lth shift register is connected to the signal output terminal OUTPUT of the first shift register unit in the L+3th shift register;
  • the pull-up reset signal of the second shift register unit in the bit register is connected to the signal output terminal OUTPUT of the second shift register unit in the L+3th shift register;
  • L takes 1 to p-3.
  • the signal output terminal OUTPUT of the first shift register unit in the p-1th and pth shift registers is connected to the signal output terminal OUTPUT of the first redundant shift register unit in the first and second redundant shift registers, respectively.
  • the signal input terminal INPUT; the signal output terminal OUTPUT of the second shift register unit in the p-1 and pth shift registers is connected to the second redundant shift register in the first and second redundant shift registers.
  • the signal input terminal INPUT of the unit; the signal output terminal OUTPUT of the first redundant shift register unit in the Kth redundant shift register is respectively connected to the first redundant shift register in the K+2 redundant shift registers.
  • the signal input terminal INPUT of the bit register unit; the signal output terminal OUTPUT of the second redundant shift register unit in the Kth redundant shift register is respectively connected to the second redundant shift register in the K+2 redundant shift registers.
  • the signal input terminal INPUT of the remaining shift register unit; K takes 1 to 4.
  • the signal output terminal OUTPUT of the first redundant shift register unit in the first to third redundant shift registers is respectively connected to the pull-up of the first shift register unit in the p-2 to p-th shift registers
  • the reset signal terminal RESET_PU; the signal output terminal OUTPUT of the second redundant shift register unit in the 1-3 redundant shift registers is connected to the second shift register in the p-2 to p shift registers respectively
  • the pull-up reset signal terminal RESET_PU of the register unit; the signal output terminal OUTPUT of the first redundant shift register unit in the fourth to sixth redundant shift registers is respectively connected to the first to third redundant shift registers.
  • the pull-up reset signal terminal RESET_PU of the first redundant shift register unit; the signal output terminals OUTPUT of the second redundant shift register unit in the fourth to sixth redundant shift register units are respectively connected to the first to third The pull-up reset signal terminal RESET_PU of the second redundant shift register unit in the redundant shift register.
  • the number N of clock signal lines is equal to 10, and the 10 clock signal lines are clk1, clk2...clk10 respectively, each group includes two rows of pixel units, at this time j is 1, 2, ie each of the p shift registers includes two shift register cells.
  • each redundant shift register also includes two shift register units; the 1st to 8th redundant shift registers are respectively connected to clk1, clk2...clk8,
  • the two shift register cells of each redundant shift register are connected to the same clock signal line.
  • the signal input terminals INPUT of the two shift register units in the first to third shift registers are connected to the frame start signal line, that is, the two shift register units of the first to third shift registers respond to the frame Turn on the signal.
  • the signal output terminal OUTPUT of the first shift register unit in the Mth shift register is connected to the signal input terminal INPUT of the first shift register unit in the M+3th shift register; the Mth shift register The signal output terminal OUTPUT of the second shift register unit in the bit register is connected to the signal input terminal INPUT of the second shift register unit in the M+3th shift register; M takes 1 to p-3.
  • the pull-up reset signal terminal RESET_PU of the first shift register unit in the Lth shift register is connected to the signal output terminal OUTPUT of the first shift register unit in the L+4th shift register;
  • the pull-up reset signal of the second shift register unit in the bit register is connected to the signal output terminal OUTPUT of the second shift register unit in the L+4th shift register;
  • L takes 1 to p-4.
  • the signal output terminal OUTPUT of the first shift register unit in the p-2 to pth shift registers is respectively connected to the signal output terminal OUTPUT of the first redundant shift register unit in the first to third redundant shift registers.
  • the signal input terminal INPUT; the signal output terminal OUTPUT of the first shift register unit in the p-2 to pth shift registers is connected to the second redundant shift register in the first to third redundant shift registers.
  • the signal input terminal INPUT of the unit; the signal output terminal OUTPUT of the first redundant shift register unit in the Kth redundant shift register is connected to the first redundant shift register in the K+3 redundant shift register respectively.
  • the signal input terminal INPUT of the shift register unit; the signal output terminal OUTPUT of the second redundant shift register unit in the Kth redundant shift register is respectively connected to the second redundant shift register in the K+3 redundant shift register.
  • Signal input terminal INPUT of each redundant shift register unit; K takes 1 to 5.
  • the signal output terminal OUTPUT of the first redundant shift register unit in the first to fourth redundant shift registers is respectively connected to the pull-up of the first shift register unit in the p-3 to p-th shift registers
  • the reset signal terminal RESET_PU; the signal output terminal OUTPUT of the second redundant shift register unit in the first to fourth redundant shift registers is connected to the second shift register in the p-3 to p shift registers respectively
  • the pull-up reset signal terminal RESET_PU of the register unit; the signal output terminal OUTPUT of the first redundant shift register unit in the fifth to eighth redundant shift registers is respectively connected to the first to fourth redundant shift registers.
  • the pull-up reset signal terminal RESET_PU of the first redundant shift register unit; the signal output terminals OUTPUT of the second redundant shift register unit in the fifth to eighth redundant shift register units are respectively connected to the first to fourth The pull-up reset signal terminal RESET_PU of the second redundant shift register unit in the redundant shift register.
  • each shift register in the first to (N-2)/2 shift registers The signal input terminal INPUT of the bit register unit responds to the frame start signal; the signal output terminal OUTPUT of the jth shift register unit in the Mth shift register is connected to the M+(N-2)/2th shift register.
  • the signal input terminal INPUT of the jth shift register unit; the pull-up reset signal terminal RESET_PU of the jth shift register unit in the Lth shift register is connected to the jth shift register in the L+N/2th shift register.
  • the signal output terminal OUTPUT of the pth shift register (the last stage shift register) is connected to the pull-up reset signal terminal RESET_PU of the pN/2th shift register unit; therefore, from the pN/2+1 to P
  • the pull-up node PU of each shift register unit of the two shift registers has no shift register for which a reset signal is provided.
  • the signal terminal of the pull-up node PU of the jth shift register unit of the pth shift register needs to be output by the signal output of the jth shift register unit of the p+N/2th shift register.
  • N redundant shift registers are further provided in the display panel, the N shift registers are respectively connected to N clock signal lines, and each redundant shift register includes q redundant shift registers.
  • Bit register unit (same as shift register unit in shift register). Among them, the signal output terminal OUTPUT of the jth redundant shift register unit in the 1st to N/2th redundant shift registers is connected to the jth shift register in the pN/2+1 to pth shift registers respectively.
  • the pull-up reset signal terminal RESET_PU of the bit register unit; the signal output terminal OUTPUT of the jth redundant shift register unit in the N/2+1 to N redundant shift registers are respectively connected to the first to N/2
  • the pull-up reset signal terminal RESET_PU of the jth redundant shift register unit in the redundant shift register; j takes 1 to q.
  • the following example illustrates the cascade relationship of each shift register when the number N of clock signal lines is an even number greater than or 4 and the duty cycle of the clock signal is 40%.
  • the number N of clock signal lines is equal to 4, the four clock signal lines are clk1, clk2...clk4, each group includes two rows of pixel units, at this time j is 1, 2, ie each of the P shift registers includes two shift register units. At this time, every adjacent 4 shift registers are respectively connected to clk1, clk2...clk4, and the two shift register units in each shift register are connected to the same clock signal line; of course, this kind of The display panel also includes 4 redundant shift registers, each redundant shift register also includes two shift register units; the first to fourth of the 4 redundant shift registers are respectively connected to clk1, clk2...
  • the two shift register units of each redundant shift register are connected to the same clock signal line.
  • the signal input terminals INPUT of the two shift register units in the first shift register are both connected to the frame start signal line, that is, the two shift register units of the first shift register respond to the frame start signal.
  • the signal output terminal OUTPUT of the first shift register unit in the Mth shift register is connected to the signal input terminal INPUT of the first shift register unit in the M+1th shift register;
  • the signal output terminal OUTPUT of the second shift register unit in the bit register is connected to the signal input terminal INPUT of the second shift register unit in the M+1th shift register; M takes 1 to p-1.
  • the pull-up reset signal terminal RESET_PU of the first shift register unit in the Lth shift register is connected to the signal output terminal OUTPUT of the first shift register unit in the L+2th shift register;
  • the pull-up reset signal terminal RESET_PU of the second shift register unit in the bit register is connected to the signal output terminal OUTPUT of the second shift register unit in the L+2th shift register;
  • L takes 1 to p-2.
  • the signal output terminal OUTPUT of the first shift register unit in the pth shift register is connected to the signal input terminal INPUT of the first redundant shift register unit in the first redundant shift register;
  • the signal output terminal OUTPUT of the second shift register unit in the first redundant shift register is connected to the signal input terminal INPUT of the second redundant shift register unit in the first redundant shift register;
  • the Kth redundant shift register The signal output terminal OUTPUT of the first redundant shift register unit in the bit register is respectively connected to the signal input terminal INPUT of the first redundant shift register unit in the K+1 redundant shift registers;
  • the signal output terminal OUTPUT of the second redundant shift register unit in the remaining shift registers is respectively connected to the signal input terminal INPUT of the second redundant shift register unit in the K+1 redundant shift registers;
  • K takes 1 to 3.
  • the signal output terminal OUTPUT of the first redundant shift register unit in the first and second redundant shift registers is connected to the pull-up of the first shift register unit in the p-1 and p shift registers, respectively.
  • the reset signal terminal RESET_PU; the signal output terminal OUTPUT of the second redundant shift register unit in the first and second redundant shift registers is respectively connected to the second shift register in the p-1 to pth shift registers
  • the pull-up reset signal terminal RESET_PU of the register unit; the signal output terminal OUTPUT of the first redundant shift register unit in the third and fourth redundant shift registers is connected to the first and second redundant shift registers respectively.
  • the pull-up reset signal terminal RESET_PU of the first redundant shift register unit; the signal output terminals OUTPUT of the second redundant shift register unit in the third and fourth redundant shift registers are connected to the first and second redundant shift registers respectively.
  • the pull-up reset signal terminal RESET_PU of the second redundant shift register unit in the redundant shift register is connected to the first and second redundant shift registers respectively.
  • the number N of clock signal lines is equal to 6, the 6 clock signal lines are clk1, clk2...clk6 respectively, each group includes two rows of pixel units, at this time j is 1, 2, ie each of the P shift registers includes two shift register units. At this time, every adjacent six shift registers are respectively connected to clk1, clk2...clk6, and the two shift register units in each shift register are connected to the same clock signal line; of course, this kind of The display panel also includes 6 redundant shift registers, and each redundant shift register also includes two shift register units; the first to sixth of the 6 redundant shift registers are respectively connected to clk1, clk2...
  • the two shift register units of each redundant shift register are connected to the same clock signal line.
  • the signal input terminals INPUT of the two shift register units in the first and second shift registers are connected to the frame start signal line, that is, the two shift register units of the first and second shift registers respond to the frame Turn on the signal.
  • the signal output terminal OUTPUT of the first shift register unit in the Mth shift register is connected to the signal input terminal INPUT of the first shift register unit in the M+2th shift register;
  • the signal output terminal OUTPUT of the second shift register unit in the bit register is connected to the signal input terminal INPUT of the second shift register unit in the M+2th shift register;
  • M takes 1 to p-2.
  • the pull-up reset signal terminal RESET_PU of the first shift register unit in the Lth shift register is connected to the signal output terminal OUTPUT of the first shift register unit in the L+3th shift register;
  • the pull-up reset signal terminal RESET_PU of the second shift register unit in the bit register is connected to the signal output terminal OUTPUT of the second shift register unit in the L+3th shift register;
  • L takes 1 to p-3.
  • the signal output terminal OUTPUT of the first shift register unit in the p-1th and pth shift registers is connected to the signal output terminal OUTPUT of the first redundant shift register unit in the first and second redundant shift registers, respectively.
  • the signal input terminal INPUT; the signal output terminal OUTPUT of the second shift register unit in the p-1 and pth shift registers is connected to the second redundant shift register in the first and second redundant shift registers respectively.
  • the signal input terminal INPUT of the register unit; the signal output terminal OUTPUT of the first redundant shift register unit in the Kth redundant shift register is respectively connected to the first redundant shift register in the K+2 redundant shift registers.
  • the signal input terminal INPUT of the shift register unit; the signal output terminal OUTPUT of the second redundant shift register unit in the Kth redundant shift register is respectively connected to the second one of the K+2 redundant shift registers
  • the signal input terminal INPUT of the redundant shift register unit; K takes 1 and 2.
  • the signal output terminal OUTPUT of the first redundant shift register unit in the first to third redundant shift registers is respectively connected to the pull-up of the first shift register unit in the p-2 to p-th shift registers
  • the reset signal terminal RESET_PU; the signal output terminal OUTPUT of the second redundant shift register unit in the first to third redundant shift registers is connected to the second shift register in the p-2 to p shift registers respectively
  • the pull-up reset signal terminal RESET_PU of the register unit; the signal output terminal OUTPUT of the first redundant shift register unit in the fourth to sixth redundant shift registers is respectively connected to the first to third redundant shift registers.
  • the pull-up reset signal terminal RESET_PU of the first redundant shift register unit; the signal output terminals OUTPUT of the second redundant shift register unit in the fourth to sixth redundant shift register units are respectively connected to the first to third The pull-up reset signal terminal RESET_PU of the second redundant shift register unit in the redundant shift register.
  • the number of clock signal lines N is equal to 8
  • the 8 clock signal lines are clk1, clk2...clk8 respectively
  • each group includes two rows of pixel units, at this time j is 1, 2, ie each of the p shift registers includes two shift register cells.
  • each redundant shift register also includes two shift register units; the 8 redundant shift registers are respectively connected to clk1, clk2...clk8, each redundant The two shift register units of the remaining shift register are connected to the same clock signal line.
  • the signal input terminals INPUT of the two shift register units in the first to third shift registers are connected to the frame start signal line, that is, the two shift register units of the first to third shift registers respond to the frame Turn on the signal.
  • the signal output terminal OUTPUT of the first shift register unit in the Mth shift register is connected to the signal input terminal INPUT of the first shift register unit in the M+3th shift register; the Mth shift register The signal output terminal OUTPUT of the second shift register unit in the bit register is connected to the signal input terminal INPUT of the second shift register unit in the M+3th shift register; M takes 1 to p-3.
  • the pull-up reset signal terminal RESET_PU of the first shift register unit in the Lth shift register is connected to the signal output terminal OUTPUT of the first shift register unit in the L+4th shift register;
  • the pull-up reset signal terminal RESET_PU of the second shift register unit in the bit register is connected to the signal output terminal OUTPUT of the second shift register unit in the L+4th shift register;
  • L takes 1 to p-4.
  • the signal output terminal OUTPUT of the first shift register unit in the p-2 to pth shift registers is respectively connected to the signal output terminal OUTPUT of the first redundant shift register unit in the first to third redundant shift registers.
  • the signal input terminal INPUT; the signal output terminal OUTPUT of the second shift register unit in the p-2 to pth shift registers is connected to the second redundant shift register in the first to third redundant shift registers.
  • the signal input terminal INPUT of the unit; the signal output terminal OUTPUT of the first redundant shift register unit in the Kth redundant shift register is connected to the first redundant shift register in the K+3 redundant shift register respectively.
  • the signal input terminal INPUT of the shift register unit; the signal output terminal OUTPUT of the second redundant shift register unit in the Kth redundant shift register is respectively connected to the second redundant shift register in the K+3 redundant shift register.
  • Signal input terminal INPUT of each redundant shift register unit; K takes 1 to 5.
  • the signal output terminal OUTPUT of the first redundant shift register unit in the first to fourth redundant shift registers is respectively connected to the pull-up of the first shift register unit in the p-3 to p-th shift registers
  • the reset signal terminal RESET_PU; the signal output terminal OUTPUT of the first redundant shift register unit in the fifth to eight redundant shift registers is respectively connected to the first redundant shift register in the first to fourth redundant shift registers.
  • the pull-up reset signal terminal RESET_PU of the shift register unit; the signal output terminal OUTPUT of the second redundant shift register unit in the first to fourth redundant shift registers is connected to the p-3 to pth shift registers respectively
  • the pull-up reset signal terminal RESET_PU of the second shift register unit in the The pull-up reset signal terminal RESET_PU of the second redundant shift register unit in the redundant shift register.
  • the number N of clock signal lines is equal to 10
  • the 10 clock signal lines are clk1, clk2...clk10 respectively, each group includes two rows of pixel units, at this time j is 1, 2, ie each of the p shift registers includes two shift register cells.
  • each redundant shift register also includes two shift register units; the 1st to 10th redundant shift registers are respectively connected to clk1, clk2...clk10,
  • the two shift register cells of each redundant shift register are connected to the same clock signal line.
  • the signal input terminals INPUT of the two shift register units in the first to fourth shift registers are connected to the frame start signal line, that is, the two shift register units of the first to fourth shift registers respond to the frame Turn on the signal.
  • the signal output terminal OUTPUT of the first shift register unit in the Mth shift register is connected to the signal input terminal INPUT of the first shift register unit in the M+4th shift register;
  • the signal output terminal OUTPUT of the second shift register unit in the bit register is connected to the signal input terminal INPUT of the second shift register unit in the M+4th shift register;
  • M takes 1 to p-4.
  • the pull-up reset signal terminal RESET_PU of the first shift register unit in the Lth shift register is connected to the signal output terminal OUTPUT of the first shift register unit in the L+5th shift register;
  • the pull-up reset signal terminal RESET_PU of the second shift register unit in the bit register is connected to the signal output terminal OUTPUT of the second shift register unit in the L+5th shift register;
  • L takes 1 to p-5.
  • the signal output terminal OUTPUT of the first shift register unit in the p-3 to pth shift registers is respectively connected to the signal output terminal OUTPUT of the first redundant shift register unit in the first to fourth redundant shift registers.
  • the signal input terminal INPUT; the signal output terminal OUTPUT of the first shift register unit in the p-3 to pth shift registers is connected to the second redundant shift register in the first to fourth redundant shift registers.
  • the signal input terminal INPUT of the unit; the signal output terminal OUTPUT of the first redundant shift register unit in the Kth redundant shift register unit is respectively connected to the first redundant shift register in the K+4 redundant shift registers.
  • the signal input terminal INPUT of the bit register unit; the signal output terminal OUTPUT of the second redundant shift register unit in the Kth redundant shift register is respectively connected to the second redundant shift register in the K+4 redundant shift registers.
  • the signal input terminal INPUT of the remaining shift register unit; K takes 1 to 6.
  • the signal output terminal OUTPUT of the first redundant shift register unit in the first to fifth redundant shift registers is respectively connected to the pull-up of the first shift register unit in the p-4 to p-th shift registers
  • the reset signal terminal RESET_PU; the signal output terminal OUTPUT of the second redundant shift register unit in the 1st to 5th redundant shift registers is connected to the second shift register in the p-4th to pth shift registers respectively
  • the pull-up reset signal terminal RESET_PU of the register unit; the signal output terminal OUTPUT of the first redundant shift register unit in the 6-10 redundant shift registers is connected to the 1 to 5 redundant shift registers respectively.
  • the pull-up reset signal terminal RESET_PU of the first redundant shift register unit; the signal output terminals OUTPUT of the second redundant shift register unit in the sixth to tenth redundant shift register units are respectively connected to the first to fifth The pull-up reset signal terminal RESET_PU of the second redundant shift register unit in the redundant shift register.
  • the number N of clock signal lines is an even number greater than or 4, and the duty cycle of the clock signal is 50%;
  • the signal input terminal INPUT responds to the frame opening signal;
  • the signal output terminal OUTPUT of the jth shift register unit in the Mth shift register is connected to the jth shift register unit in the M+N/2th shift register
  • the pull-up reset signal terminal RESET_PU of the jth shift register unit in the Lth shift register is connected to the jth shift register in the L+(N/2+1)th shift register
  • L takes 1 to p-(N/2+1);
  • j takes 1 to q.
  • the signal output terminal OUTPUT of the p-th shift register (the last stage shift register) is connected to the pull-up reset signal terminal RESET_PU of the p-(N/2+1)-th shift register unit;
  • the pull-up node PU of each shift register unit of the /2 to P shift registers has no shift register for which a reset signal is provided.
  • the pull-up node PU of the jth shift register unit of the pth shift register needs to reset the signal terminal of the jth shift register unit of the p+N/2+1th shift register.
  • N+2 redundant shift registers are also provided in the display panel, and the first to N of the N+2 redundant shift registers are respectively connected to N clock signals. Lines, N+1 and N+2 connect the 1st and 2nd clock signal lines respectively, and each redundant shift register includes q shift register units (the same as the shift register units in the shift register).
  • the signal output terminal OUTPUT of the jth redundant shift register unit in the 1st to N/2+1 redundant shift registers is respectively connected to the jth shift register in the pN/2 to pth shift registers.
  • the pull-up reset signal terminal RESET_PU of the bit register unit; the signal output terminal OUTPUT of the jth redundant shift register unit in the N/2+2 to N+2 redundant shift registers are respectively connected to the 1st to N/
  • the following example illustrates the cascade relationship of each shift register when the number N of clock signal lines is an even number greater than or 4 and the duty cycle of the clock signal is 50%.
  • the number N of clock signal lines is equal to 4, the four clock signal lines are clk1, clk2...clk4, each group includes two rows of pixel units, at this time j is 1, 2, ie each of the P shift registers includes two shift register units. At this time, every adjacent 4 shift registers are respectively connected to clk1, clk2...clk4, and the two shift register units in each shift register are connected to the same clock signal line; of course, this kind of The display panel also includes 6 redundant shift registers, each redundant shift register also includes two shift register units; the first to fourth of the 6 redundant shift registers are respectively connected to clk1, clk2...
  • the fifth and sixth are respectively connected to clk1 and clk2; the two shift register units of each redundant shift register are connected to the same clock signal line.
  • the signal input terminals INPUT of the two shift register units in the first and second shift registers are connected to the frame start signal line, that is, the two shift register units of the first and second shift registers respond to the frame Turn on the signal.
  • the signal output terminal OUTPUT of the first shift register unit in the Mth shift register is connected to the signal input terminal INPUT of the first shift register unit in the M+2th shift register;
  • the signal output terminal OUTPUT of the second shift register unit in the bit register is connected to the signal input terminal INPUT of the second shift register unit in the M+2th shift register;
  • M takes 1 to p-2.
  • the pull-up reset signal terminal RESET_PU of the first shift register unit in the Lth shift register is connected to the signal output terminal OUTPUT of the first shift register unit in the L+3th shift register;
  • the pull-up reset signal terminal RESET_PU of the second shift register unit in the bit register is connected to the signal output terminal OUTPUT of the second shift register unit in the L+3th shift register;
  • L takes 1 to p-3.
  • the signal output terminal OUTPUT of the first shift register unit in the p-1 and pth shift registers is connected to the signal of the first redundant shift register unit in the first and second redundant shift registers
  • the input terminal INPUT; the signal output terminal OUTPUT of the second shift register unit in the p-1 and pth shift registers is connected to the second redundant shift register unit in the first and second redundant shift registers
  • the signal input terminal INPUT; the signal output terminal OUTPUT of the first redundant shift register unit in the Kth redundant shift register is connected to the first redundant shift register in the K+2 redundant shift registers respectively.
  • the signal input terminal INPUT of the register unit; the signal output terminal OUTPUT of the second redundant shift register unit in the Kth redundant shift register is respectively connected to the second redundant shift register in the K+2 redundant shift registers.
  • the signal input terminal INPUT of the shift register unit; K takes 1 to 4.
  • the signal output terminal OUTPUT of the first redundant shift register unit in the first to third redundant shift registers is respectively connected to the pull-up of the first shift register unit in the p-2 to p-th shift registers
  • the reset signal terminal RESET_PU; the signal output terminal OUTPUT of the second redundant shift register unit in the first to third redundant shift registers is connected to the second shift register in the p-2 to p shift registers respectively
  • the pull-up reset signal terminal RESET_PU of the register unit; the signal output terminal OUTPUT of the first redundant shift register unit in the fourth to sixth redundant shift registers is respectively connected to the first to third redundant shift registers.
  • the pull-up reset signal terminal RESET_PU of the first redundant shift register unit; the signal output terminals OUTPUT of the second redundant shift register unit in the fourth to sixth redundant shift register units are respectively connected to the first to third The pull-up reset signal terminal RESET_PU of the second redundant shift register unit in the redundant shift register.
  • the number of clock signal lines N is equal to 6, the 6 clock signal lines are clk1, clk2...clk6 respectively, each group includes two rows of pixel units, at this time j is 1, 2, ie each of the P shift registers includes two shift register units. At this time, every adjacent six shift registers are respectively connected to clk1, clk2...clk6, and the two shift register units in each shift register are connected to the same clock signal line; of course, this kind of The display panel also includes 8 redundant shift registers, and each redundant shift register also includes two shift register units; the first to sixth of the 8 redundant shift registers are respectively connected to clk1, clk2...
  • the seventh and eighth are respectively connected to clk1 and clk2; the two shift register units of each redundant shift register are connected to the same clock signal line.
  • the signal input terminals INPUT of the two shift register units in the first and second shift registers are connected to the frame start signal line, that is, the two shift register units of the first and second shift registers respond to the frame Turn on the signal.
  • the signal output terminal OUTPUT of the first shift register unit in the Mth shift register is connected to the signal input terminal INPUT of the first shift register unit in the M+3th shift register; the Mth shift register The signal output terminal OUTPUT of the second shift register unit in the bit register is connected to the signal input terminal INPUT of the second shift register unit in the M+3th shift register; M takes 1 to p-3.
  • the pull-up reset signal terminal RESET_PU of the first shift register unit in the Lth shift register is connected to the signal output terminal OUTPUT of the first shift register unit in the L+4th shift register;
  • the pull-up reset signal terminal RESET_PU of the second shift register unit in the bit register is connected to the signal output terminal OUTPUT of the second shift register unit in the L+4th shift register;
  • L takes 1 to p-4.
  • the signal output terminal OUTPUT of the first shift register unit in the p-2 to pth shift registers is respectively connected to the signal output terminal OUTPUT of the first redundant shift register unit in the first to third redundant shift registers.
  • the signal input terminal INPUT; the signal output terminal OUTPUT of the second shift register unit in the p-2 to pth shift registers is connected to the second redundant shift register in the first to third redundant shift registers respectively.
  • the signal input terminal INPUT of the register unit; the signal output terminal OUTPUT of the first redundant shift register unit in the Kth redundant shift register is respectively connected to the first redundant shift register in the K+3 redundant shift register.
  • the signal input terminal INPUT of the redundant shift register unit; the signal output terminal OUTPUT of the second redundant shift register unit in the Kth redundant shift register is respectively connected to the Kth redundant shift register in the K+3 redundant shift register.
  • Signal input terminal INPUT of 2 redundant shift register units; K takes 1 to 3.
  • the signal output terminal OUTPUT of the first redundant shift register unit in the first to fourth redundant shift registers is respectively connected to the pull-up of the first shift register unit in the p-3 to p-th shift registers
  • the reset signal terminal RESET_PU; the signal output terminal OUTPUT of the second redundant shift register unit in the first to fourth redundant shift registers is connected to the second shift register in the p-3 to p shift registers respectively
  • the pull-up reset signal terminal RESET_PU of the register unit; the signal output terminal OUTPUT of the first redundant shift register unit in the fifth to eighth redundant shift registers is respectively connected to the first to fourth redundant shift registers.
  • the pull-up reset signal terminal RESET_PU of the first redundant shift register unit; the signal output terminals OUTPUT of the second redundant shift register unit in the fifth to eighth redundant shift register units are respectively connected to the first to fourth The pull-up reset signal terminal RESET_PU of the second redundant shift register unit in the redundant shift register.
  • the number of clock signal lines N is equal to 8
  • the 8 clock signal lines are clk1, clk2...clk8 respectively
  • each group includes two rows of pixel units
  • j is 1, 2
  • each of the p shift registers includes two shift register cells.
  • every adjacent 8 shift registers are respectively connected to clk1, clk2...clk8, and the two shift register units in each shift register are connected to the same clock signal line; of course, this kind of display
  • the panel also includes 10 redundant shift registers, each redundant shift register also includes two shift register units; the 1st to 8th of the 8 redundant shift registers are respectively connected to clk1, clk2....
  • the 9th and 10th are connected to clk1 and clk2 respectively; the two shift register units of each redundant shift register are connected to the same clock signal line.
  • the signal input terminals INPUT of the two shift register units in the first to fourth shift registers are connected to the frame start signal line, that is, the two shift register units of the first to fourth shift registers respond to the frame Turn on the signal.
  • the signal output terminal OUTPUT of the first shift register unit in the Mth shift register is connected to the signal input terminal INPUT of the first shift register unit in the M+4th shift register;
  • the signal output terminal OUTPUT of the second shift register unit in the bit register is connected to the signal input terminal INPUT of the second shift register unit in the M+4th shift register;
  • M takes 1 to p-4.
  • the pull-up reset signal terminal RESET_PU of the first shift register unit in the Lth shift register is connected to the signal output terminal OUTPUT of the first shift register unit in the L+5th shift register;
  • the pull-up reset signal terminal RESET_PU of the second shift register unit in the bit register is connected to the signal output terminal OUTPUT of the second shift register unit in the L+5th shift register;
  • L takes 1 to p-5.
  • the signal output terminal OUTPUT of the first shift register unit in the p-3 to pth shift registers is respectively connected to the signal output terminal OUTPUT of the first redundant shift register unit in the first to fourth redundant shift registers.
  • Signal input terminal INPUT; the signal output terminal OUTPUT of the second shift register unit in the p-3 to pth shift registers is connected to the second redundant shift register in the first to fourth redundant shift registers.
  • the signal input terminal INPUT of the unit; the signal output terminal OUTPUT of the first redundant shift register unit in the Kth redundant shift register unit is respectively connected to the first redundant shift register in the K+4 redundant shift registers.
  • the signal input terminal INPUT of the bit register unit; the signal output terminal OUTPUT of the second redundant shift register unit in the Kth redundant shift register is respectively connected to the second redundant shift register in the K+4 redundant shift registers.
  • the signal input terminal INPUT of the remaining shift register unit; K takes 1 to 6.
  • the signal output terminal OUTPUT of the second redundant shift register unit in the 1st to 5th redundant shift registers is connected to the pull-up of the second shift register unit in the p-4th to pth shift registers respectively
  • the reset signal terminal RESET_PU; the signal output terminal OUTPUT of the first redundant shift register unit in the 1st to 5th redundant shift registers is connected to the first shift register in the p-4th to pth shift registers respectively
  • the pull-up reset signal terminal RESET_PU of the register unit; the signal output terminal OUTPUT of the first redundant shift register unit in the 6th to 10th redundant shift registers is respectively connected to the 1st to 5th redundant shift registers.
  • the pull-up reset signal terminal RESET_PU of the first redundant shift register unit; the signal output terminals OUTPUT of the second redundant shift register unit in the sixth to tenth redundant shift register units are respectively connected to the first to fifth The pull-up reset signal terminal RESET_PU of the second redundant shift register unit in the redundant shift register.
  • the number N of clock signal lines is equal to 10
  • the 10 clock signal lines are clk1, clk2...clk10 respectively
  • each group includes two rows of pixel units
  • j takes 1, 2
  • each of the p shift registers includes two shift register cells.
  • every adjacent 10 shift registers are respectively connected to clk1, clk2...clk10, and the two shift register units in each shift register are connected to the same clock signal line; of course, this kind of display
  • the panel also includes 12 redundant shift registers, each redundant shift register also includes two shift register units; the 1st to 10th of the 12 redundant shift registers are respectively connected to clk1, clk2...
  • the signal input terminals INPUT of the two shift register units in the first to fifth shift registers are connected to the frame start signal line, that is, the two shift register units of the first to fifth shift registers respond to the frame Turn on the signal.
  • the signal output terminal OUTPUT of the first shift register unit in the Mth shift register is connected to the signal input terminal INPUT of the first shift register unit in the M+5th shift register;
  • the signal output terminal OUTPUT of the second shift register unit in the bit register is connected to the signal input terminal INPUT of the second shift register unit in the M+5th shift register;
  • M takes 1 to p-5.
  • the pull-up reset signal terminal RESET_PU of the first shift register unit in the Lth shift register is connected to the signal output terminal OUTPUT of the first shift register unit in the L+6th shift register;
  • the pull-up reset signal terminal RESET_PU of the second shift register unit in the bit register is connected to the signal output terminal OUTPUT of the second shift register unit in the L+6th shift register;
  • L takes 1 to p-6.
  • the signal output terminal OUTPUT of the first shift register unit in the p-4th to pth shift registers is respectively connected to the signal output terminal OUTPUT of the first redundant shift register unit in the first to fifth redundant shift registers.
  • the signal input terminal INPUT; the signal output terminal OUTPUT of the first shift register unit in the p-4th to pth shift registers is connected to the second redundant shift register in the first to fifth redundant shift registers.
  • the signal input terminal INPUT of the unit; the signal output terminal OUTPUT of the first redundant shift register unit in the Kth redundant shift register is respectively connected to the first redundant shift register in the K+5 redundant shift registers.
  • the signal input terminal INPUT of the bit register unit; the signal output terminal OUTPUT of the second redundant shift register unit in the Kth redundant shift register is respectively connected to the second redundant shift register in the K+5 redundant shift registers.
  • the signal input terminal INPUT of the remaining shift register unit; K takes 1 to 7.
  • the signal output terminal OUTPUT of the first redundant shift register unit in the 1st to 6th redundant shift registers is connected to the pull-up of the first shift register unit in the p-5th to pth shift registers, respectively
  • the reset signal terminal RESET_PU; the signal output terminal OUTPUT of the second redundant shift register unit in the 1st to 6th redundant shift registers is connected to the second shift register in the p-5th to pth shift registers respectively.
  • the pull-up reset signal terminal RESET_PU of the register unit; the signal output terminal OUTPUT of the first redundant shift register unit in the 7th to 12th redundant shift registers is connected to the 1st to 6th redundant shift registers respectively.
  • the pull-up reset signal terminal RESET_PU of the first redundant shift register unit; the signal output terminals OUTPUT of the second redundant shift register unit in the seventh to twelfth redundant shift register units are respectively connected to the first to sixth
  • each shift register includes 1 shift register unit and q sub-signal output terminals OUTPUT
  • the number N of clock signal lines is greater than or equal to an even number of 4
  • the duty cycle of the clock signal is 30%, 40%, 50%
  • the cascading relationship between each shift register unit unit will be described.
  • q is 2, that is, each shift register includes one shift register unit and two signal output terminals OUTPUT as an example.
  • a certain shift register unit involved in the following description refers to the shift register unit of the shift register to which it belongs.
  • the signal input terminals of the first to (N-4)/2 shift register units INPUT responds to the frame open signal;
  • the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+(N-4)/2th shift register unit;
  • the pull-up of the Lth shift register unit The reset signal terminal RESET_PU is connected to the signal output terminal OUTPUT of the L+(N/2-1)th shift register unit;
  • M takes 1 to p-(N-4)/2;
  • L takes 1 to p-(N/2- 1);
  • j takes 1 to q.
  • the signal output terminal OUTPUT of the p-th shift register unit (the last stage shift register unit) is connected to the pull-up reset signal terminal RESET_PU of the p-(N/2-1)-th shift register unit;
  • the pull-up node PU of each shift register unit of the p-(N/2-2)th to Pth shift register units has no shift register for which a reset signal is provided.
  • N-2 redundant shift registers are further provided in the display panel, the N-2 shift registers are respectively connected to N-2 clock signal lines, and each redundant shift register is It includes 1 shift register unit (same as the shift register unit in the shift register, in order to distinguish it from the above shift register unit, the redundant shift register is called a redundant shift register unit), wherein the first The signal output terminals OUTPUT of 1 to N/2-1 redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the pN/2 to pth shift register units; the N/2 to N-2 redundant The signal output terminals OUTPUT of the redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the first to N/2-1 redundant shift register units; j takes 1 to q.
  • the p-(N/2-2) to p-th shift register units are reset through the signals output by the 1-th to N/2-1 redundant shift register units;
  • the 1st to N/2-1th redundant shift register units are reset through the signals output by the N/2th to N-2th redundant shift register units to ensure that the 1st to N/2-1th redundant shift register units are reset.
  • the redundant shift register cells work normally.
  • the following example illustrates the cascade relationship of each shift register when the number N of clock signal lines is an even number greater than or 6 and the duty cycle of the clock signal is 30%.
  • the number N of clock signal lines is equal to 6, the 6 clock signal lines are clk1, clk2...clk6 respectively, each group includes two rows of pixel units, at this time j takes 1, 2, that is, each shift register includes one shift register unit.
  • every adjacent 6 shift register units are respectively connected to clk1, clk2...clk6; of course, this kind of display panel also includes 4 redundant shift registers, and each redundant shift register is the same All include 1 shift register unit, which is called a redundant shift register unit; 4 redundant shift register units are respectively connected to clk1, clk2...clk4.
  • the signal input terminal INPUT of the first shift register unit is connected to the frame start signal line, that is, the first shift register unit responds to the frame start signal.
  • the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+1th shift register unit; M takes 1 to p-1.
  • the pull-up reset signal of the Lth shift register unit is connected to the signal output terminal OUTPUT of the L+2th shift register unit; L takes 1 to p-2.
  • the signal output terminal OUTPUT of the p-th shift register unit is connected to the signal input terminal INPUT of the first redundant shift register unit; the signal output terminal OUTPUT of the K-th redundant shift register unit is respectively connected to K+1 Signal input terminal INPUT of the redundant shift register unit; K takes 1 to 3.
  • the signal output terminals OUTPUT of the first and second redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the p-1 and p-th shift register units; the signals of the third and fourth redundant shift register units The output terminal OUTPUT is respectively connected to the pull-up reset signal terminals RESET_PU of the first and second redundant shift register units.
  • the number of clock signal lines N is equal to 8
  • the 8 clock signal lines are clk1, clk2...clk8 respectively
  • each group includes two rows of pixel units
  • j is 1, 2 that is, each of the p shift registers includes 1 shift register unit and 2 sub-signal output terminals OUTPUT.
  • every adjacent 8 shift register units are respectively connected to clk1, clk2...clk8; of course, this kind of display panel also includes 6 redundant shift registers, each redundant shift register includes 1 redundant shift register unit; 6 redundant shift register units are respectively connected to clk1, clk2...clk6.
  • the signal input terminals INPUT of the first and second shift register units are both connected to the frame start signal line, that is, the first and second shift register units respond to the frame start signal.
  • the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+2th shift register unit; M takes 1 to p-2.
  • the pull-up reset signal terminal RESET_PU of the Lth shift register unit is connected to the signal output terminal OUTPUT of the L+3th shift register unit; the pull-up reset signal of the Lth shift register unit is connected to the L+3th shift register unit
  • the signal output terminal OUTPUT of the register unit; L takes 1 to p-3.
  • the signal output terminals OUTPUT of the p-1th and pth shift register units are respectively connected to the signal input terminals INPUT of the first and second redundant shift register units; the signal output terminals of the Kth redundant shift register unit OUTPUT is respectively connected to the signal input terminals INPUT of K+2 redundant shift register units; K takes 1 to 4.
  • the signal output terminals OUTPUT of the first to third redundant shift register units are respectively connected to the pull-up reset signals of the p-2 to pth shift register units; the signal output terminals of the fourth to sixth redundant shift register units OUTPUT is respectively connected to the pull-up reset signal terminals RESET_PU of the first to third redundant shift register units.
  • the number N of clock signal lines is equal to 10, and the 10 clock signal lines are clk1, clk2...clk10 respectively, each group includes two rows of pixel units, at this time j takes 1, 2, that is, each of the p shift registers includes 1 shift register unit and 2 sub-signal output terminals OUTPUT.
  • every adjacent 10 shift register units are respectively connected to clk1, clk2...clk10; of course, the display panel also includes 8 redundant shift registers, and each redundant shift register includes 1 redundant shift register unit; the 1st to 8th redundant shift register units are respectively connected to clk1, clk2...clk8.
  • the signal input terminals INPUT of the first to third shift register units are all connected to the frame start signal line, that is, the first to third shift register units respond to the frame start signal.
  • the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+3th shift register unit; M takes 1 to p-3.
  • the pull-up reset signal terminal RESET_PU of the Lth shift register unit is connected to the signal output terminal OUTPUT of the L+4th shift register unit; L takes 1 to p-4.
  • the signal output terminals OUTPUT of the p-2th to pth shift register units are respectively connected to the signal input terminals INPUT of the 1st to 3rd redundant shift register units; the signal output terminals of the Kth redundant shift register unit are respectively connected.
  • OUTPUT is respectively connected to the signal input terminal INPUT of the K+3 redundant shift register unit; K takes 1 to 5.
  • the signal output terminals OUTPUT of the 1st to 4th redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the p-3 to pth shift register units; the signals of the 5th to 8th redundant shift register units The output terminals OUTPUT are respectively connected to the pull-up reset signal terminals RESET_PU of the first to fourth redundant shift register units.
  • the shift in the 1st to (N-2)/2th shift registers The signal input terminal INPUT of the register unit responds to the frame opening signal; the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+(N-2)/2 shift register unit; The pull-up reset signal terminal RESET_PU of the bit register unit is connected to the signal output terminal OUTPUT of the L+N/2th shift register unit; M takes 1 to p-(N-2)/2; L takes 1 to pN/2.
  • the signal output terminal OUTPUT of the pth shift register unit (the last stage shift register unit) is connected to the pull-up reset signal terminal RESET_PU of the pN/2th shift register unit;
  • the pull-up node PU to the P shift register units has no shift register unit for which a reset signal is provided. According to the above derivation, to reset the signal terminal of the pull-up node PU of the p-th shift register unit, the signal output terminal OUTPUT of the p+N/2-th shift register unit is required;
  • the shift register unit can work normally, so it is necessary to add N shift registers.
  • N redundant shift registers are further provided in the display panel, the N redundant shift registers are respectively connected to N clock signal lines, and each redundant shift register includes one redundant shift register.
  • the remainder of the shift register unit (same as the shift register unit in the shift register).
  • the signal output terminals OUTPUT of the 1st to N/2th redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the pN/2+1th to pth shift register units;
  • the signal output terminals OUTPUT of the N redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the first to N/2 redundant shift register units.
  • the following example illustrates the cascade relationship of each shift register when the number N of clock signal lines is an even number greater than or 4 and the duty cycle of the clock signal is 40%.
  • the number of clock signal lines N is equal to 4, the four clock signal lines are clk1, clk2...clk4, each group includes two rows of pixel units, at this time j is 1, 2, that is, each shift register includes one shift register unit and two sub-signal output terminals OUTPUT.
  • every adjacent 4 shift registers are respectively connected to clk1, clk2...clk4, and the two shift register units in each shift register are connected to the same clock signal line; of course, this kind of The display panel also includes 4 redundant shift registers, each of which includes a redundant shift register unit; the 4 redundant shift register units are respectively connected to clk1, clk2...clk4 .
  • the signal input terminals INPUT of the two shift register units in the first shift register are both connected to the frame start signal line, that is, the first shift register unit responds to the frame start signal.
  • the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+1th shift register unit; M takes 1 to p-1.
  • the pull-up reset signal terminal RESET_PU of the Lth shift register unit is connected to the signal output terminal OUTPUT of the L+2th shift register unit; L takes 1 to p-2.
  • the signal output terminal OUTPUT of the p-th shift register unit is connected to the signal input terminal INPUT of the first redundant shift register unit; the signal output terminal OUTPUT of the K-th redundant shift register unit is respectively connected to K+1 Signal input terminal INPUT of the redundant shift register unit; K takes 1 to 3.
  • the signal output terminals OUTPUT of the first and second redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the p-1 and p-th shift register units; the signals of the third and fourth redundant shift register units The output terminal OUTPUT is respectively connected to the pull-up reset signal terminals RESET_PU of the first and second redundant shift register units.
  • the number of clock signal lines N is equal to 6, the 6 clock signal lines are clk1, clk2...clk6 respectively, each group includes two rows of pixel units, at this time j takes 1, 2, that is, each shift register includes one shift register unit and two sub-signal output terminals OUTPUT.
  • every adjacent 6 shift register units are respectively connected to clk1, clk2...clk6; of course, this kind of display panel also includes 6 redundant shift registers, each redundant shift register is Including 1 redundant shift register unit; 6 redundant shift register units are respectively connected to clk1, clk2...clk6.
  • the signal input terminals INPUT of the first and second shift register units are both connected to the frame start signal line, that is, the first and second shift register units respond to the frame start signal.
  • the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+2th shift register unit; M takes 1 to p-2.
  • the pull-up reset signal terminal RESET_PU of the Lth shift register unit is connected to the signal output terminal OUTPUT of the L+3th shift register unit; L takes 1 to p-3.
  • the signal output terminals OUTPUT of the p-1th and pth shift register units are respectively connected to the signal input terminals INPUT of the first and second redundant shift register units; the signal output terminals of the Kth redundant shift register unit OUTPUT is respectively connected to the signal input terminals INPUT of K+2 redundant shift register units; K takes 1 and 2.
  • the signal output terminals OUTPUT of the 1st to 3rd redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the p-2 to pth shift register units; the signals of the 4th to 6th redundant shift register units
  • the output terminals OUTPUT are respectively connected to the pull-up reset signal terminals RESET_PU of the first to third redundant shift register units.
  • the number of clock signal lines N is equal to 8
  • the 8 clock signal lines are clk1, clk2...clk8 respectively, each group includes two rows of pixel units, at this time j is 1, 2, that is, each shift register includes one shift register unit and two sub-signal output terminals OUTPUT.
  • every adjacent 8 shift register units are respectively connected to clk1, clk2...clk8; of course, the display panel also includes 8 redundant shift registers, and each redundant shift register includes 1 redundant shift register unit; 8 redundant redundant shift register units are respectively connected to clk1, clk2...clk8, and the two shift register units of each redundant shift register unit are connected to the same clock signal line.
  • the signal input terminals INPUT of the first to third shift register units are all connected to the frame start signal line, that is, the first to third shift register units respond to the frame start signal.
  • the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+3th shift register unit; M takes 1 to p-3.
  • the pull-up reset signal terminal RESET_PU of the Lth shift register unit is connected to the signal output terminal OUTPUT of the L+4th shift register unit; L takes 1 to p-4.
  • the signal output terminals OUTPUT of the p-2th to pth shift register units are respectively connected to the signal input terminals INPUT of the 1st to 3rd redundant shift register units; the signal output terminals of the Kth redundant shift register unit are respectively connected.
  • OUTPUT is respectively connected to the signal input terminal INPUT of the K+3 redundant shift register unit; K takes 1 to 5.
  • the signal output terminals OUTPUT of the 1st to 4th redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the p-3 to pth shift register units; the signals of the 5th to 8th redundant shift register units The output terminals OUTPUT are respectively connected to the pull-up reset signal terminals RESET_PU of the first to fourth redundant shift register units;
  • the number N of clock signal lines is equal to 10
  • the 10 clock signal lines are clk1, clk2...clk10 respectively
  • each group includes two rows of pixel units
  • j takes 1, 2, that is, each shift register includes one shift register unit and two sub-signal output terminals OUTPUT.
  • every adjacent 10 shift register units are respectively connected to clk1, clk2...clk10; of course, the display panel also includes 10 redundant shift registers, and each redundant shift register includes 1 shift register units; the 1st to 10th redundant shift register units are respectively connected to clk1, clk2...clk10.
  • the signal input terminals INPUT of the first to fourth shift register units are all connected to the frame start signal line, that is, the first to fourth shift register units respond to the frame start signal.
  • the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+4th shift register unit; M takes 1 to p-4.
  • the pull-up reset signal terminal RESET_PU of the Lth shift register unit is connected to the signal output terminal OUTPUT of the L+5th shift register unit; L takes 1 to p-5.
  • the signal output terminals OUTPUT of the p-3th to pth shift register units are respectively connected to the signal input terminals INPUT of the 1st to 4th redundant shift register units; the signal output terminals of the Kth redundant shift register unit are respectively connected.
  • OUTPUT is respectively connected to the signal input terminals INPUT of K+4 redundant shift register units; K takes 1 to 6.
  • the signal output terminals OUTPUT of the 1st to 5th redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the p-4th to pth shift register units;
  • the signal output terminals OUTPUT are respectively connected to the pull-up reset signal terminals RESET_PU of the first to fifth redundant shift register units.
  • the signals of the shift register units in the 1st to N/2th shift registers The input terminal INPUT responds to the frame start signal; the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+N/2th shift register unit; the pull-up reset of the Lth shift register unit
  • the signal terminal RESET_PU is connected to the signal output terminal OUTPUT of the L+(N/2+1)th shift register unit; M takes 1 to pN/2; L takes 1 to p-(N/2+1).
  • the signal output terminal OUTPUT of the p-th shift register unit (the last stage shift register unit) is connected to the pull-up reset signal terminal RESET_PU of the p-(N/2+1)-th shift register unit;
  • the pull-up nodes PU of the pN/2 to Pth shift register units have no shift register units for which reset signals are provided. According to the above derivation, to reset the signal terminal of the pull-up node PU of the p-th shift register unit, the signal output terminal OUTPUT of the p+N/2+1-th shift register unit is required; 2+1 shift register units can work normally, so it is necessary to add N+2 shift register units.
  • N+2 redundant shift registers are further provided in the display panel, and each redundant shift register includes 1 redundant shift register unit (compared to the one in the shift register).
  • the shift register units are the same), the 1st to Nth of the N+2 redundant shift register units are respectively connected to the N clock signal lines, and the N+1th and N+2th are respectively connected to the 1st and 2nd clock signals String.
  • the signal output terminals OUTPUT of the 1st to N/2+1 redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the pN/2 to pth shift register units;
  • the signal output terminals OUTPUT of the N+2 redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the first to N/2+1 redundant shift register units.
  • the following example illustrates the cascade relationship of each shift register when the number N of clock signal lines is an even number greater than or 4 and the duty cycle of the clock signal is 50%.
  • the number N of clock signal lines is equal to 4, the four clock signal lines are clk1, clk2...clk4 respectively, each group includes two rows of pixel units, at this time j is 1, 2, that is, each shift register includes one shift register unit.
  • every adjacent 4 shift register units are respectively connected to clk1, clk2...clk4; of course, this kind of display panel also includes 6 redundant shift registers, each redundant shift register is It includes 1 redundant shift register unit; the 1st to 4th of the 6 redundant shift register units are respectively connected to clk1, clk2...clk4, and the 5th and 6th are connected to clk1 and clk2 respectively.
  • the signal input terminals INPUT of the first and second shift register units are both connected to the frame start signal line, that is, the first and second shift register units respond to the frame start signal.
  • the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+2th shift register unit; M takes 1 to p-2.
  • the pull-up reset signal terminal RESET_PU of the Lth shift register unit is connected to the signal output terminal OUTPUT of the L+3th shift register unit; L takes 1 to p-3.
  • the signal output terminals OUTPUT of the p-1 and p-th shift register units are connected to the signal input terminals INPUT of the first and second redundant shift register units; the signal output terminal OUTPUT of the K-th redundant shift register unit
  • the signal input terminals INPUT of K+2 redundant shift register units are respectively connected; K takes 1 to 4.
  • the signal output terminals OUTPUT of the 1st to 3rd redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the p-2 to pth shift register units; the signals of the 4th to 6th redundant shift register units
  • the output terminals OUTPUT are respectively connected to the pull-up reset signal terminals RESET_PU of the first to third redundant shift register units.
  • the number N of clock signal lines is equal to 6, and the 6 clock signal lines are clk1, clk2...clk6 respectively, each group includes two rows of pixel units, at this time j is 1, 2, that is, each shift register includes one shift register unit and two sub-signal output terminals OUTPUT.
  • every adjacent 6 shift register units are respectively connected to clk1, clk2...clk6; of course, this kind of display panel also includes 8 redundant shift registers, each redundant shift register is Including 1 redundant shift register unit; the 1st to 6th of the 8 redundant shift registers are respectively connected to clk1, clk2...clk6, and the 7th and 8th are respectively connected to clk1, clk2.
  • the signal input terminals INPUT of the first and second shift register units are both connected to the frame start signal line, that is, the first and second shift register units respond to the frame start signal.
  • the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+3th shift register unit; M takes 1 to p-3.
  • the pull-up reset signal terminal RESET_PU of the Lth shift register unit is connected to the signal output terminal OUTPUT of the L+4th shift register unit; L takes 1 to p-4.
  • the signal output terminals OUTPUT of the p-2th to pth shift register units are respectively connected to the signal input terminals INPUT of the 1st to 3rd redundant shift register units; the first one in the Kth redundant shift register The signal output terminal OUTPUT of the redundant shift register unit is respectively connected to the signal input terminal INPUT of the first redundant shift register unit in the K+3 redundant shift register unit; K takes 1 to 3.
  • the signal output terminals OUTPUT of the 1st to 4th redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the p-3 to pth shift register units; the signals of the 5th to 8th redundant shift register units The output terminals OUTPUT are respectively connected to the pull-up reset signal terminals RESET_PU of the first to fourth redundant shift register units.
  • each group includes two rows of pixel units, at this time j is 1, 2, that is, each shift register includes one shift register unit and two sub-signal output terminals OUTPUT.
  • every adjacent 8 shift register units are respectively connected to clk1, clk2...clk8; of course, the display panel also includes 10 redundant shift registers, and each redundant shift register includes 1 redundant shift register unit; the 1st to 8th of the 10 redundant shift register units are respectively connected to clk1, clk2...clk8, and the 9th and 10th are connected to clk1, clk2 respectively.
  • the signal input terminals INPUT of the first to fourth shift register units are all connected to the frame start signal line, that is, the first to fourth shift register units respond to the frame start signal.
  • the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+4th shift register unit; M takes 1 to p-4.
  • the pull-up reset signal terminal RESET_PU of the Lth shift register unit is connected to the signal output terminal OUTPUT of the L+5th shift register unit; L takes 1 to p-5.
  • the signal output terminals OUTPUT of the p-3th to pth shift register units are respectively connected to the signal input terminals INPUT of the 1st to 4th redundant shift register units; the signal output terminals of the Kth redundant shift register unit are respectively connected.
  • OUTPUT is respectively connected to the signal input terminals INPUT of K+4 redundant shift register units; K takes 1 to 6.
  • the signal output terminals OUTPUT of the 1st to 5th redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the p-4th to pth shift register units; the signals of the 6th to 10th redundant shift register units The output terminals OUTPUT are respectively connected to the pull-up reset signal terminals RESET_PU of the first to fifth redundant shift register units.
  • the number N of clock signal lines is equal to 10
  • the 10 clock signal lines are clk1, clk2...clk10 respectively
  • each group includes two rows of pixel units
  • j is 1, 2 that is, each shift register includes one shift register unit and two sub-signal output terminals OUTPUT.
  • every adjacent 10 shift register units are respectively connected to clk1, clk2...clk10; of course, the display panel also includes 12 redundant shift registers, each redundant shift register includes 1 redundant shift register unit; 12 redundant shift register units 1 to 10 are respectively connected to clk1, clk2...clk10, and 11 to 12 are connected to clk1, clk2 respectively.
  • the signal input terminals INPUT of the first to fifth shift register units are all connected to the frame start signal line, that is, the first to fifth shift register units respond to the frame start signal.
  • the signal output terminal OUTPUT of the Mth shift register unit is connected to the signal input terminal INPUT of the M+5th shift register unit; M takes 1 to p-5.
  • the pull-up reset signal terminal RESET_PU of the Lth shift register unit is connected to the signal output terminal OUTPUT of the L+6th shift register unit; L takes 1 to p-6.
  • the signal output terminals OUTPUT of the p-4th to pth shift register units are respectively connected to the signal input terminals INPUT of the 1st to 5th redundant shift register units; the signal output terminals of the Kth redundant shift register unit are respectively connected.
  • OUTPUT is respectively connected to the signal input terminals INPUT of K+5 redundant shift register units; K takes 1 to 7.
  • the signal output terminals OUTPUT of the 1st to 6th redundant shift register units are respectively connected to the pull-up reset signal terminals RESET_PU of the p-5th to pth shift register units; the signals of the 7th to 12th redundant shift register units The output terminals OUTPUT are respectively connected to the pull-up reset signal terminals RESET_PU of the first to sixth redundant shift register units.
  • an embodiment of the present disclosure provides a display device including any one of the above-mentioned display panels.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device of this embodiment may also include other conventional structures, such as a power supply unit, a display driving unit, and the like.

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Abstract

本公开提供一种显示面板及显示装置，属于显示技术领域。本公开的显示面板，其包括p组像素单元，所述p组像素单元中的每组包括q行所述像素单元，p、q均为大于或者等于2的整数；其中，位于同一组的所述像素单元由同一移位寄存器同时提供栅扫描信号；位于同一组、且处于同一列的所述像素单元由不同的数据线提供数据电压信号。

Description

显示面板及显示装置 技术领域
本发明属于显示技术领域，具体涉及一种显示面板及显示装置。
背景技术
随着显示技术的不断发展,近些年的显示器发展逐渐呈现出了高集成度，低成本的发展趋势。其中一项非常重要的技术就是GOA(Gate Driver on Array,阵列基板行驱动)技术的量产化的实现。利用GOA技术将TFT(Thin Film Transistor,薄膜场效应晶体管)栅极开关电路集成在显示面板的阵列基板上以形成对显示面板的扫描驱动，从而可以省掉栅极驱动集成电路部分，其不仅可以从材料成本和制作工艺两方面降低产品成本，而且显示面板可以做到两边对称和窄边框的美观设计。同时由于可以省去Gate方向绑定Bonding的工艺，对产能和良率提升也较有利。这种利用GOA技术集成在阵列基板上的栅极开关电路也称为GOA电路或移位寄存器电路。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种显示面板及显示装置。
第一方面，本公开实施例提供一种显示面板，其包括p组像素单元，所述p组像素单元中的每组包括q行所述像素单元，p、q均为大于或者等于2的整数；其中，位于同一组的所述像素单元由同一移位寄存器同时提供栅扫描信号；位于同一组、且处于同一列的所述像素单元由不同的数据线提供数据电压信号。
其中，还包括N条时钟信号线，N为大于或者4的偶数，p大于或者等于2N；每个所述移位寄存器连接一条所述时钟信号线，且不同的所述时钟信号线连接所连接的所述移位寄存器不同。
其中，位于同一行的所述像素单元连接同一栅线；每个所述移位寄存器 包括q个移位寄存器单元，所述移位寄存器单元与所述栅线一一对应连接。
其中，每一个所述移位寄存器单元通过一条信号连接线与所述时钟信号线连接，且不同的所述移位寄存器单元连接不同的所述信号连接线。
其中，每个所述移位寄存器所包括的多个所述移位寄存器单元通过同一所述信号连接线与所述时钟信号线连接，且不同的所述移位寄存器所包括的多个所述移位寄存器单元连接不同的信号连接线。
其中，所述移位寄存器单元均至少包括输入子电路、输出子电路、上拉复位子电路；其中，所述输入子电路响应于信号输入端所输入的输入信号，并将所述输入信号输入至上拉节点；所述输出子电路响应于所述上拉节点的电位，并将所述时钟信号线所输入的时钟信号通过信号输出端输出；所述上拉复位子电路响应于所述上拉复位信号端所输入的上拉复位信号，并通过非工作电平信号对所述上拉节点的电位进行复位；
每相邻设置的N个所述移位寄存器与N条所述时钟信号线一一对应连接，且第i个所述移位寄存器与第i+N个所述移位寄存器连接同一所述时钟信号线；i取1至p-N。
其中，当所述时钟信号的占空比为30％，N为大于或者等于6的偶数时；
第1至(N-4)/2个所述移位寄存器中的各所述移位寄存器单元的信号输入端响应于帧开启信号；
第M个所述移位寄存器中的第j个所述移位寄存器单元的信号输出端连接第M+(N-4)/2个所述移位寄存器中的所述第j个所述移位寄存器单元的信号输入端；
第L个所述移位寄存器中的第j个所述移位寄存器单元的上拉复位信号端连接第L+(N/2-1)个所述移位寄存器中的第j个所述移位寄存器单元的信号输出端；M取1至p-(N-4)/2；L取1至p-(N/2-1)；j取1至q。
其中，所述显示面板还包括N-2个冗余移位寄存器，N-2个所述冗余移位寄存器分别连接N-2条时钟信号线，每个所述冗余移位寄存器包括q个冗 余移位寄存器单元；所述冗余移位寄存器单元与所述移位寄存器单元结构相同；其中，
第1至N/2-1个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的信号输出端分别连接第p-(N/2-2)至p个所述移位寄存器中的第j个所述移位寄存器单元的上拉复位信号端；
第N/2至N-2个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的信号输出端分别连接第1至N/2-1个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的上拉复位信号端。
其中，当所述时钟信号的占空比为40％，N为大于或者等于4的偶数时；
第1至(N-2)/2个所述移位寄存器中的各所述移位寄存器单元的信号输入端响应于帧开启信号；
第M个所述移位寄存器中的第j个所述移位寄存器单元的信号输出端连接第M+(N-2)/2个所述移位寄存器中的第j个所述移位寄存器单元的信号输入端；
第L个所述移位寄存器中的第j个所述移位寄存器单元的上拉复位信号端连接第L+N/2个所述移位寄存器中的第j个所述移位寄存器单元的信号输出端；M取1至p-(N-2)/2；L取1至p-N/2；j取1至q。
其中，所述显示面板还包括N个冗余移位寄存器，N个移位寄存器分别连接N条时钟信号线；每个所述冗余移位寄存器包括q个冗余移位寄存器单元；所述冗余移位寄存器单元与所述移位寄存器单元结构相同；其中，
第1至N/2个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的信号输出端分别连接第p-N/2+1至p个所述移位寄存器中的第j个所述移位寄存器单元的上拉复位信号端；第N/2+1至N个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的信号输出端分别连接第1至N/2个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的上拉复位信号端。
其中，当所述时钟信号的占空比为50％，N为大于或者等于4的偶数时；
第1至N/2个所述移位寄存器中的各所述移位寄存器单元的信号输入端响应于帧开启信号；
第M个所述移位寄存器中的第j个所述移位寄存器单元的信号输出端连接第M+N/2个所述移位寄存器中的第j个所述移位寄存器单元的信号输入端；
第L个所述移位寄存器中的第j个所述移位寄存器单元的上拉复位信号端连接第L+(N/2+1)个所述移位寄存器中的第j个所述移位寄存器单元的信号输出端；M取1至p-N/2；L取1至p-(N/2+1)；j取1至q。
其中，所述显示面板还包括N+2个冗余移位寄存器，N+2个冗余移位寄存器中的第1至N个分别连接N条所述时钟信号线，第N+1和N+2个分别连接第1和2条时钟信号线；每个所述冗余移位寄存器包括q个冗余移位寄存器单元；所述冗余移位寄存器单元与所述移位寄存器单元结构相同；其中，
第1至N/2+1个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的信号输出端分别连接第p-N/2至p个所述移位寄存器中的第j个所述移位寄存器单元的上拉复位信号端；
第N/2+2至N+2个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的信号输出端分别连接第1至N/2+1个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的上拉复位信号端。
其中，位于同一行的所述像素单元连接同一栅线；每个所述移位寄存器包括一个移位寄存器单元以及与所述移位寄存器单元的信号输出端连接的q个子信号输出端，所述子信号输出端与所述栅线一一对应连接。
其中，所述移位寄存器单元均至少包括输入子电路、输出子电路、上拉复位子电路；其中，所述输入子电路响应于信号输入端所输入的输入信号，并将所述输入信号输入至上拉节点；所述输出子电路响应于所述上拉节点的电位，并将所述时钟信号线所输入的时钟信号输入至信号输出端，以使所述信号输出端通过q个所述子信号输出端输出；所述上拉复位子电路响应于所 述上拉复位信号端所输入的上拉复位信号，并通过非工作电平信号对所述上拉节点的电位进行复位；
每相邻设置的N个所述移位寄存器单元与N条所述时钟信号线一一对应连接，且第i个所述移位寄存器单元与第i+N个所述移位寄存器单元连接同一所述时钟信号线；i取1至p-N。
其中，当所述时钟信号的占空比为30％，N为大于或者等于6的偶数时；
第1至(N-4)/2个所述移位寄存器单元的信号输入端响应于帧开启信号；
第M个所述移位寄存器单元的信号输出端连接第M+(N-4)/2个所述移位寄存器单元的信号输入端；
第L个所述移位寄存器单元的上拉复位信号端连接第L+(N/2-1)个所述移位寄存器单元的信号输出端；M取1至p-(N-4)/2；L取1至p-(N/2-1)。
其中，所述显示面板还包括N-2个冗余移位寄存器，N-2个所述冗余移位寄存器分别连接N-2条时钟信号线，每个所述冗余移位寄存器包括1个冗余移位寄存器单元；所述冗余移位寄存器单元与所述移位寄存器单元结构相同；其中，
第1至N/2-1个所述冗余移位寄存器单元的信号输出端分别连接第p-(N/2-2)至p个所述移位寄存器单元的上拉复位信号端；
第N/2至N-2个所述冗余移位寄存器单元的信号输出端分别连接第1至N/2-1个所述冗余移位寄存器单元的上拉复位信号端。
其中，当所述时钟信号的占空比为40％，N为大于或者等于4的偶数时；
第1至(N-2)/2个所述移位寄存器器单元的信号输入端响应于帧开启信号；
第M个所述移位寄存器单元的信号输出端连接第M+(N-2)/2个所述移位寄存器单元的信号输入端；
第L个所述移位寄存器单元的上拉复位信号端连接第L+N/2个所述移位 寄存器单元的信号输出端；M取1至p-(N-2)/2；L取1至p-N/2。
其中，所述显示面板还包括N个冗余移位寄存器，N个冗余移位寄存器分别连接N条时钟信号线；每个所述冗余移位寄存器包括1个冗余移位寄存器单元；所述冗余移位寄存器单元与所述移位寄存器单元结构相同；其中，
第1至N/2个所述冗余移位寄存器单元的信号输出端分别连接第p-N/2+1至p个所述移位寄存器单元的上拉复位信号端；
第N/2+1至N个所述冗余移位寄存器单元的信号输出端分别连接第1至N/2个所述冗余移位寄存器单元的上拉复位信号端。
其中，当所述时钟信号的占空比为50％，N为大于或者等于4的偶数时；
第1至N/2个所述移位寄存器单元的信号输入端响应于帧开启信号；
第M个所述移位寄存器单元的信号输出端连接第M+N/2个所述移位寄存器单元的信号输入端；
第L个所述移位寄存器单元的上拉复位信号端连接第L+(N/2+1)个所述移位寄存器单元的信号输出端；M取1至p-N/2；L取1至p-(N/2+1)。
其中，所述显示面板还包括N+2个冗余移位寄存器，N+2个所述冗余移位寄存器中的第1至N个分别连接N条所述时钟信号线，第N+1和N+2个分别连接第1和2条时钟信号线；每个所述冗余移位寄存器包括1个冗余移位寄存器单元；所述冗余移位寄存器单元与所述移位寄存器单元结构相同；其中，
第1至N/2+1个所述冗余移位寄存器单元的信号输出端分别连接第p-N/2至p个所述移位寄存器单元的上拉复位信号端；
第N/2+2至N+2个所述冗余移位寄存器单元的信号输出端分别连接第1至N/2+1个所述冗余移位寄存器单元的上拉复位信号端。
其中，每组中的q行所述像素单元相邻设置。
第二方面，本公开实施例提供一种显示装置，其包括上述的显示面板。
附图说明
图1为一种移位寄存器单元的电路图；
图2为一种栅极驱动电路的级联示意图；
图3为另一种移位寄存器单元的电路图；
图4为本公开实施例的显示面板的结构示意图；
图5为本公开实施例的一种移位寄存器与时钟信号线的连接示意图；
图6为本公开实施例的另一种移位寄存器与时钟信号线的连接示意图；
图7为本公开实施例的时钟信号线为6，时钟信号的占空比为30％时，一种移位寄存器的级联示意图；
图8为本公开实施例的时钟信号线为8，时钟信号的占空比为30％时，一种移位寄存器的级联示意图；
图9为本公开实施例的时钟信号线为10，时钟信号的占空比为30％时，一种移位寄存器的级联示意图；
图10为本公开实施例的时钟信号线为4，时钟信号的占空比为40％时，一种移位寄存器的级联示意图；
图11为本公开实施例的时钟信号线为6，时钟信号的占空比为40％时，一种移位寄存器的级联示意图；
图12为本公开实施例的时钟信号线为8，时钟信号的占空比为40％时，一种移位寄存器的级联示意图；
图13为本公开实施例的时钟信号线为10，时钟信号的占空比为40％时，一种移位寄存器的级联示意图；
图14为本公开实施例的时钟信号线为4，时钟信号的占空比为50％时，一种移位寄存器的级联示意图；
图15为本公开实施例的时钟信号线为6，时钟信号的占空比为50％时，一种移位寄存器的级联示意图；
图16为本公开实施例的时钟信号线为8，时钟信号的占空比为50％时，一种移位寄存器的级联示意图；
图17为本公开实施例的时钟信号线为10，时钟信号的占空比为50％时，一种移位寄存器的级联示意图；
图18为本公开实施例的再一种移位寄存器与时钟信号线的连接示意图；
图19为本公开实施例的时钟信号线为6，时钟信号的占空比为30％时，另一种移位寄存器的级联示意图；
图20为本公开实施例的时钟信号线为8，时钟信号的占空比为30％时，另一种移位寄存器的级联示意图；
图21为本公开实施例的时钟信号线为10，时钟信号的占空比为30％时，另一种移位寄存器的级联示意图；
图22为本公开实施例的时钟信号线为4，时钟信号的占空比为40％时，另一种移位寄存器的级联示意图；
图23为本公开实施例的时钟信号线为6，时钟信号的占空比为40％时，另一种移位寄存器的级联示意图；
图24为本公开实施例的时钟信号线为8，时钟信号的占空比为40％时，另一种移位寄存器的级联示意图；
图25为本公开实施例的时钟信号线为10，时钟信号的占空比为40％时，另一种移位寄存器的级联示意图；
图26为本公开实施例的时钟信号线为4，时钟信号的占空比为50％时，另一种移位寄存器的级联示意图；
图27为本公开实施例的时钟信号线为6，时钟信号的占空比为50％时，另一种移位寄存器的级联示意图；
图28为本公开实施例的时钟信号线为8，时钟信号的占空比为50％时，另一种移位寄存器的级联示意图；
图29为本公开实施例的时钟信号线为10，时钟信号的占空比为50％时，另一种移位寄存器的级联示意图。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在此需要说明的是，本发明实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本发明实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，以下实施例中是以N型晶体管进行说明的，当采用N型晶体管时，第一极为N型晶体管的源极，第二极为N型晶体管的漏极，栅极输入高电平时，源漏极导通，P型相反。可以想到的是采用P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下轻易想到的，因此也是在本发明实施例的保护范围内的。
其中，由于在本发明实施例中以所采用晶体管为N型晶体管，故在本发明实施例中的工作电平信号则是指高电平信号，非工作电平信号为低电平信 号；相应的工作电平端为高电平信号端，非工作电平端为低电平信号端。
通常显示面板包括多条栅线和多条数据线，栅线和数据线交叉设置限定出多个像素区，每个像素区均设置有像素单元。其中，以各栅线的延伸方向为行方向，各数据线的延伸方向为列方向为例对显示面板的结构进行说明。在驱动显示面板进行显示时，可以根据待显示画面，逐行给栅线写入栅扫描信号，同时给各数据线写入数据电压信号，以使显示面板中的像素单元逐行被点亮。
其中，栅扫描信号由栅极驱动电路提供，数据电压信号由源极驱动电路提供；在相关技术中可以将栅极驱动电路集成在栅极驱动芯片中，将源极驱动电路集成在源极驱动芯片中；而目前为了较少芯片数量，以及实现窄边框或者无边框，提供了一种将栅极驱动电路集成在阵列基板上(Gate On Array；GOA)的技术；其中，栅极驱动电路包括集成在阵列基板上、多个级联的移位寄存器单元，每个移位寄存器单元与栅线一一对应连接，用于为与之连接的栅线提供栅扫描信号。
为了更清楚移位寄存器单元如何实现栅扫描信号的输出，以下结合移位寄存器单元的具体示例进行说明。
在一个示例中，如图1所示的移位寄存器单元的电路图；该移位寄存器单元包括输入子电路1、输出子电路2、上拉复位子电路3，输出复位子电路4；其中，输入子电路1响应于信号输入端INPUT所输入的输入信号，并通过输入信号给上拉节点PU进行充电；输出子电路2响应于上拉节点PU的电位，并将时钟信号端所输入的时钟信号通过信号输出端OUTPUT输出；上拉复位子电路3响应于上拉复位信号端RESET_PU输出的上拉复位信号，并通过低电平信号将上拉节点PU进行复位；输出复位模块响应于输出复位信号，通过低电平信号将信号输出端OUTPUT进行复位。
具体的，如图1所示，输出子电路2包括第一晶体管M1；上拉复位子电路3包括第二晶体管M2；输出子电路2包括第三晶体管M3和存储电容C；输出复位子电路4包括第四晶体管M4；其中，M1的栅极和源极连接信号输 入端INPUT，M1的漏极连接上拉节点PUPU；M2的栅极连接上拉复位信号端RESET_PU，M2的源极连接上拉节点PU，M2的漏极连接低电平信号端；M3的栅极连接上拉节点PU，M3的源极连接时钟信号端，M3的漏极连接信号输出端OUTPUT；C的第一端连接上拉节点PU，C的第二端连接信号输出端OUTPUT；M4的栅极连接输出复位信号端RESET_OUTPUT，M4的源极连接信号输出端OUTPUT，M4的漏极连接低电平信号端。
在输入阶段，信号输入端INPUT写入高电平信号，M1打开，通过高电平信号拉高PU点，并对C进行充电。
在输出阶段，由于在输入阶段PU点被拉高，M3打开，将时钟信号端输入的高电平信号通过信号输出端OUTPUT输出至与移位寄存器单元连接的栅线。
在复位阶段，输出复位信号端RESET_OUTPUT输入高电平信号，M4打开，通过低电平信号端输入的低电平信号拉低信号输出端OUTPUT的输出；上拉复位信号端RESET_PU输入高电平信号，M2打开通过低电平信号端输入的低电平信号拉低上拉节点PU的电位，至此完成上拉节点PU和信号输出端OUTPUT的复位。
在此需要说明的是，移位寄存器单元中可以不设置输出复位子电路4，通过在复位阶段在对上拉节点PU进行复位后，上拉节点PU为低电平，此时M3关断，信号输出端OUTPUT不再输出，以完成对信号输出端OUTPUT的复位。
另外，对于采用上述移位寄存器单元的栅极驱动电路而言，如图2所示，以第1至4个移位寄存器单元(GOA1-GOA4)的级联关系为例；其中，本级移位寄存器单元的信号输出端OUTPUT连接上一级移位寄存器单元的上拉复位信号端RESET_PU，以及下一级移位寄存器单元的信号输入端INPUT。
在另一个示例中，如图3所示，为了优化移位寄存器单元，还提供一款 不仅包括上述输入子电路1、输出子电路2、上拉复位子电路3，而且还包括第一下拉控制子电路、第二下拉控制子电路、第一下拉子电路、第二下拉子电路、第一降噪子电路、第二降噪子电路、级联子电路、放电子电路、第一辅助子电路和第二辅助子电路。其中，放电子电路响应于帧前开启信号端STV0输入的帧前开启信号，并通过低平信号端所输入的低电平对上拉节点PU进行放电；第一下拉控制子电路和第二下拉控制子电路的结构和功能相同，二者只是分时工作；同理，第一下拉子电路和第二下拉子电路的结构和功能相同；第一辅助子电路和第二辅助子电路结构和功能相同；第一降噪子电路和第二降噪子电路的结构和功能相同。对于输入子电路1、输出子电路2、上拉复位子电路3与上述结构和功能相同，故在此不再重复赘述。第一辅助子电路和第二辅助子电路均响应于信号输入端INPUT所输入的输入信号，并分别通过低电平信号拉低第一下拉节点PD1和第二下拉节点PD2；第一下拉控制子电路响应于第一电源电压信号端所输入的第一电源电压，以控制第一下拉节点PD1的电位；第二下拉控制子电路响应于第二电源电压信号端所输入的第二电源电压，以控制第二下拉节点PD2的电位；第一下拉子电路响应于上拉节点PU，并通过低电平信号端输入的电平信号下拉第一下拉节点PD1和第一下拉控制节点PD_CN1；第二下拉子电路响应于上拉节点PU，并通过低电平信号端输入的电平信号下拉第二下拉节点PD2和第二下拉控制节点PD_CN2；第一降噪子电路响应于第一下拉节点PD1的电位，通过低电平信号端输入的电平信号对上拉节点PU、级联信号输出端OUT_C、信号输出端OUTPUT所输出的信号进行降噪。级联子电路响应于上拉节点PU的电位，将时钟信号端所输入的时钟信号通过级联信号输出端OUT_C。
在此需要说明的是，级联信号输出端OUT_C和信号输出端OUTPUT所输出的信号相同，只不过在该移位寄存单元中设置两个输出端，一个为与栅线连接的信号输出端OUTPUT，另一个为用于级联的级联信号输出端OUT_C。之所以，单独设置级联子电路是为了降低信号输出端OUTPUT的负载，以避免影响信号输出端OUTPUT所输出的栅扫描信号。
另外，对于采用上述移位寄存器单元的栅极驱动电路而言，如图2所示，本级移位寄存器单元的级联信号输出端OUT_C连接上一级移位寄存器的上拉复位信号端RESET_PU，以及下一级移位寄存器单元的信号输入端INPUT。当然，应当理解的是，上述移位寄存器单元中也可以不设置级联子电路，此时本级移位寄存器单元的信号输出端OUTPUT连接上一级移位寄存器的上拉复位信号端RESET_PU，以及下一级移位寄存器单元的信号输入端INPUT。
具体的，如图3所示，第一下拉控制子电路和第二下拉控制子电路均包括第五晶体管和第九晶体管；其中，第一下拉控制子电路中和第二控制子电路中的第五晶体管分别用M5和M5'表示，第九晶体管分别用M9和M9'表示。第一下拉子电路和第二下拉子电路均包括第六晶体管和第八晶体管；其中，第一下拉子电路和第二下拉子电路中的第六晶体管分别用M6和M6'表示，第八晶体管分别用M8和M8'表示。第一降噪子电路和第二降噪子电路均包括第十晶体管、第十一晶体管和第十二晶体管；其中，第一降噪子电路和第二降噪子电路中的第十晶体管分别用M10和M10'表示，第十一晶体管分别用M11和M11'表示，第十二晶体管分别用M12和M12'表示。放电子电路包括第七晶体管M7；级联子电路包括第十三晶体管M13。第一辅助子电路和第二辅助子电路均包括第是六晶体管，分别用M16和M16'表示。
继续参照图3，M1的栅极和源极连接信号输入端INPUT，M1的漏极连接上拉节点PUPU；M2的栅极连接上拉复位信号端RESET_PU，M2的源极连接上拉节点PU，M2的漏极连接低电平信号端；M3的栅极连接上拉节点PU，M3的源极连接时钟信号端，M3的漏极连接信号输出端OUTPUT；C的第一端连接上拉节点PU，C的第二端连接信号输出端OUTPUT；M5的栅极和源极均连接第一电源电压端，M5的漏极连接第一下拉控制节点PD_CN1；M9的栅极连接第一下拉控制节点PD_CN1，M9的源极连接第一电源电压端，M9的漏极连接第一下拉节点PD1；M5'的栅极和源极均连接第二电源电压端，M5'的漏极连接第二下拉控制节点PD_CN2；M9'的栅极连接 第二下拉控制节点PD_CN2，M9'的源极连接第二电源电压端，M9'的漏极连接第一下拉节点PD1；M6的栅极连接上拉节点PU，M6的源极连接第一下拉节点PD1，M6的漏极连接低电平信号端；M8的栅极连接上拉节点PU，M8的源极连接第一下拉控制节点PD_CN1，M8的漏极连接低电平信号端；M6'的栅极连接上拉节点PU，M6'的源极连接第二下拉节点PD2，M6'的漏极连接低电平信号端；M8'的栅极连接上拉节点PU，M8'的源极连接第二下拉控制节点PD_CN2，M8'的漏极连接低电平信号端；M10的栅极连接第一下拉节点PD1，M10的源极连接上拉节点PU，M10的漏极连接低电平信号端；M11的栅极连接第一下拉节点PD1，M11的源极连接信号输出端OUTPUT，M11的漏极连接低电平信号端；M12的栅极连接第一下拉节点PD1，M12的源极连接级联信号输出端OUT_C，M12的漏极连接低电平信号端；M10'的栅极连接第二下拉节点PD2，M10'的源极连接上拉节点PU，M10'的漏极连接低电平信号端；M11'的栅极连接第二下拉节点PD2，M11'的源极连接信号输出端OUTPUT，M11'的漏极连接低电平信号端；M12'的栅极连接第二下拉节点PD2，M12'的源极连接级联信号输出端OUT_C，M12'的漏极连接低电平信号端；M7的栅极连接帧前开启信号端，M7的源极连接上拉节点PU，M7的漏极连接低电平信号端；M13的栅极连接上拉节点PU，M13的源极连接时钟信号端，M13的漏极连接级联信号端。M16的栅极连接信号输入端INPUT，M16的源极连接第一下拉节点PD1，M16的漏极连接低电平信号端。M16'的栅极连接信号输入端INPUT，M16'的源极连接第二下拉节点PD2，M16'的漏极连接低电平信号端。
其中，M5和M9组成第一下拉控制子电路和M5'和M9'组成第一下拉控制子电路分时工作(也即轮流工作)；相应的，由于由M10、M11、M12组成的第一降噪子电路和由M10'、M11'、M12'组成的第二降噪子电路分别由第一下拉控制子电路和第二下拉控制子电路控制，故第一降噪子电路和第二降噪子电路也是分时工作。而第一下拉控制子电路和第二下拉控制子电路的工作原理相同，第一降噪子电路和第二降噪子电路的工作原理相同；故以下仅 以第一下拉控制子电路和第一降噪子电路工作时，对移位寄存器单元的工作原理进行说明。
在放电阶段，在帧前也即显示之前，先给帧前开启信号端输入高电平信号，通过低电平信号端所输入的低电平信号，对上拉节点PU进行放电，防止上拉节点PU残留电荷造成显示异常。
在输入阶段，信号输入端INPUT输入高电平信号，M1打开，通过高电平信号拉高上拉节点PU，并对C进行充电，与此同时，M16和M16'均被打开，将第一下拉节点PD1和第二下拉节点PD2拉低，以避免影响上拉节点PU的电位。
在输出阶段，由于在输入阶段上拉节点PU被拉高，M3和M13打开，将时钟信号端输入的高电平信号通过信号输出端OUTPUT输出至与之连接的栅线，与此同时，级联信号输出端OUT_C与信号输出端OUTPUT所输出的信号相同，也即输出高电平信号给上一级移位寄存器单元的上拉复位信号端RESET_PU，以及下一级移位寄存器单元的信号输入端INPUT。
在复位阶段，上拉复位信号端RESET_PU输入高电平信号，M2打开通过低电平信号端输入的低电平信号拉低上拉节点PU的电位，以对上拉节点PU进行复位，由于上拉节点PU被拉低，M3和M13被关断，信号输出端OUTPUT和级联信号输出端OUT_C均不再输出高电平信号。与此同时，第一下拉控制节点PD_CN1和下拉节点均为高电平信号，M10、M11、M12打开，分别对上拉节点PU、信号输出端OUTPUT、级联信号输出端OUT_C的输出进行降噪，直至下一帧扫描开始上拉节点PU电位被拉高。
如图3所示，可以看出的是，为了降低信号输出端OUTPUT的负载，信号输出端OUTPUT所输出的信号仅用于控制栅线的选通与关断，而级联信号输出端OUT_C仅用于本级移位寄存器单元与之上一级、下一级移位寄存器单元的级联。但信号输出端OUTPUT和级联信号输出端OUT_C所输出的信号是同步的，在实际应用中也可以省略级联子电路的设置，通过信号输出端OUTPUT将本级移位寄存器单元与之上一级、下一级移位寄存器单元的 级联。
发明人发现，在相关技术中，栅极驱动电路中的一个移位寄存器单元仅为一条栅线提供栅扫描信号，但随着显示面板尺寸的不断提升，从65inch、75inch到98inch、110inch，分辨率也不断提升，从FHD，UHD到8K产品，刷新率从60HZ提升到120HZ。这就使得产品的设计难度不断增加，尤其是产品中像素的充电率无法得到保证，进而影响显示画质。以110inch、8K、120HZ产品为例，每行像素的充电时间只有1.85us，产品充电时间和充电率无法达到设计要求。而且，产品尺寸过大，显示远端信号的延时也非常大，发生串行的风险很高。
对于上述问题，在本公开实施例中提供以下技术方案。
第一方面，如图4所示，本公开实施例提供一种显示面板，其包括p组像素单元，p组像素单元中的每组包括q行像素单元，p、q均为大于或者等于2的整数；其中，位于同一组的像素单元由同一移位寄存器同时提供栅扫描信号；位于同一组、且处于同一列的像素单元由不同的数据线提供数据电压信号。
在此需要说明的是，如图4所示，显示面板中包括P组像素单元，对应的则包括P个移位寄存器，2P条栅线；若存在h列像素单元，则相应的包括2h条数据线。
在本公开实施例中，由于一组像素单元由同一移位寄存器提供栅扫描信号，并使得位于同一组、且处于同一列的像素单元由不同的数据线提供数据电压信号；这样一来，在控制显示面板显示时，可以使得多行像素单元同时显示，从而可以有效的提高刷新频率，进而避免显示面板也别说大尺寸显示面板出现充电时间和/或充电率不足的问题。
在此需要说明的是，由于多行像素单元同时被扫描，但是根据显示内容，被同时扫描的且位于同一列的像素单元所需的数据电压信号不同，因此则需要通过增加数据线的数量，以满足各个像素单元对数据电压信号的需求。例 如每组像素单元包括两行像素单元，此时每一列像素单元至少需要两条数据线提供数据电压信号。当然，为了避免所增加的数据线过多而影响布线以及显示面板的透过率，每个移位寄存器不宜为过多行像素单元提供栅扫描信号。
在一些实施例中，q＝2，也即每组像素单元包括两行像素单元，每一个移位寄存器为一组像素单元中的两行像素单元同时提供栅扫描信号；且位于不同组像素单元由不同的移位寄存器提供栅扫描信号。位于同一组、且处于同一列的两个像素单元由两条数据线提供数据电压信号。当然，由于每一组像素单元是按照扫描顺序(从上至下或者从下至上的顺序)进行扫描的，因此，当每一组包括两行像素单元时，每一列像素单元可以由两条数据线提供数据电压。例如：每一组中的两行像素单元相邻设置，此时，可以是位于同一组中每一列的第一个像素单元连接一条数据线，每一列中的第二个像素单元连接另一条数据线。当然，该种连接连接方式并不构成对本实施例保护范围的限制，只要是为同一组、且处于同一列的两个像素单元所连接的数据线不同即可。另外，每一组中的两行像素单元也可以非相邻设置，例如：位于第一行和第三行的像素单元为一组。
为了更清楚本公开实施例中的显示面板结构，以每两行像素单元为一组，每列像素单元由两条数据线提供数据数据电压为例进行说明。
在一些实施例中，显示面板不仅包括上述结构还包括N条时钟信号线，N为大于或者4的偶数，像素单元的组数p大于或者等于2N；按照扫描顺序，每相邻设置的N个所述移位寄存器与N条所述时钟信号线一一对应连接，且第i个所述移位寄存器与第i+N个所述移位寄存器连接同一所述时钟信号线；i取1至p-N。具体的，时钟信号线用于为移位寄存器的时钟信号端提供时钟信号。以下结合两种不同的移位寄存器结构对本公开实施例的显示面板进行说明。
在一个示例中，每个移位寄存器包括与每组中像素单元行数相同的移位寄存器单元。也即每组包括两行像素单元，每个移位寄存器则包括两个移位 寄存器单元，且由于两个移位寄存器单元所输出的栅扫描信号相同，故二者可以采用相同的结构。每个移位寄存器单元则可以采用前述的图1或图3中的任意一种。其中，每个移位寄存器中的两个移位寄存器单元连接同一时钟信号线。以下以110inch的显示面板，其采用图3所示21T1C的移位寄存器单元和10条时钟信号线为例，对每个移位寄存器中的移位寄存器单元与时钟信号的连接方式进行说明。
第一种连接方式，10条时钟信号线分别用clk1、clk2......clk10表示。图5中由上至下每10个移位寄存器分别连接clk1、clk2......clk10。以第1个移位寄存器goa1与clk1连接为例。第1个移位寄存器goa1包括两个移位寄存器单元分别记作GOA1和GOA1'，其中，GOA1的时钟信号端和GOA1'的时钟信号端分别通过一条信号连接线与clk1连接。也就是说，信号连接线与移位寄存器单元是一一对应的关系，这样一来，每个移位寄存器的两个移位寄存器单元的时钟信号线的电流平均分配，可以有效的避免信号连接线时钟信号线连接的转接孔处出现大电流导致转接孔烧毁。
第二种连接方式，如图6所示，同样以第一种连接方式的时钟信号线数量为例，此时第1个移位寄存器goa1包括两个移位寄存器单元分别记作GOA1和GOA1'，其中，GOA1的时钟信号端和GOA1'的时钟信号端分别通过同一条信号连接线与clk1连接。也就是说，信号连接线与移位寄存器是一一对应的关系。该种连接方式相较第一种连接方式，信号连接线数量的数量减半，且避免出现大量信号连接线跨接时钟信号线而产生大量的寄生电容，可以有效的提高显示面板的充电率。
当每个移位寄存器包括q个移位寄存器单元，时钟信号线的条数N大于或者等于4的偶数，时钟信号的占空比分别为30％、40％、50％时，对各个移位寄存器单元单元之间的级联关系进行说明。在此需要说明的是，在下述描述中，当移位寄存器包括级联信号输出端OUT_C时，本级以及为寄存器的信号输出端OUTPUT则通过级联信号输出端OUT_C与其它级移位寄存器单元级联。
在一个示例中，当时钟信号线的条数N为大于或者6的偶数，时钟信号的占空比为30％时；第1至(N-4)/2个移位寄存器中的各移位寄存器单元的信号输入端INPUT响应于帧开启信号；第M个移位寄存器中的第j个移位寄存器单元的信号输出端OUTPUT连接第M+(N-4)/2个移位寄存器中的第j个移位寄存器单元的信号输入端INPUT；第L个移位寄存器中的第j个移位寄存器单元的上拉复位信号端RESET_PU连接第L+(N/2-1)个移位寄存器中的第j个移位寄存器单元的信号输出端OUTPUT；M取1至p-(N-4)/2；L取1至p-(N/2-1)；j取1至q。
另外，由于第p个移位寄存器(最后一级移位寄存器)的信号输出端OUTPUT连接第p-(N/2-1)个移位寄存器单元的上拉复位信号端RESET_PU；故从第p-(N/2-2)至p个移位寄存器的各个移位寄存器单元的上拉节点PU没有移位寄存器为之提供复位信号。按照上述推导，第p个移位寄存器的第j个移位寄存器单元的上拉节点PU复位信号端，则需要第p+(N/2-1)个移位寄存器的第j个移位寄存器单元的信号输出端OUTPUT；同时还要保证第p+(N/2-1)个移位寄存器的第j个移位寄存器单元能够正常工作，故需要增加N-2个移位寄存器。为此，在一些实施例中，在显示面板中还设置有N-2个冗余移位寄存器，N-2个冗余移位寄存器分别连接N-2条时钟信号线，每个冗余移位寄存器包括q个冗余移位寄存器单元(与移位寄存器中的移位寄存器单元相同)，其中，第1至N/2-1个冗余移位寄存器中的第j个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-(N/2-2)至p个移位寄存器中的第j个移位寄存器单元的上拉复位信号端RESET_PU；第N/2至N-2个冗余移位寄存器中的第j个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至N/2-1个所述冗余移位寄存器中的第j个冗余移位寄存器单元的上拉复位信号端RESET_PU；j取1至q。
由此可以看出的是，通过第1至N/2-1个冗余移位寄存器所输出的信号，对第p-(N/2-2)至p个移位寄存器进行复位；同时，通过第N/2至N-2个冗余移位寄存器输出的信号对第1至N/2-1个冗余移位寄存器进行复位，以 保证第1至N/2-1个冗余移位寄存器正常工作。
以下举例对当时钟信号线的条数N为大于或者6的偶数，时钟信号的占空比为30％时，各个移位寄存器的级联关系进行说明。
例如：如图7所示，时钟信号线的条数N等于6，6条时钟信号线分别为clk1、clk2......clk6，每组包括两行像素单元，此时j取1、2，也即p个移位寄存器中的每个包括两个移位寄存器单元。此时，每相邻的6个移位寄存器分别连接clk1、clk2......clk6，且每个移位寄存器中的两个移位寄存器单元连接同一条时钟信号线；当然，该种显示面板还包括4个冗余移位寄存器，每个冗余移位寄存器同样包括两个移位寄存器单元；4个冗余移位寄存器中的第1至4个分别连接clk1、clk2......clk4，每个冗余移位寄存器的两个移位寄存器单元连接同一条时钟信号线。其中，第1个移位寄存器中的两个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1个移位寄存器的两个移位寄存器单元响应于帧开启信号。第M个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT连接第M+1个移位寄存器中的第1个移位寄存器单元的信号输入端INPUT；第M个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第M+1个移位寄存器中的第2个移位寄存器单元的信号输入端INPUT；M取1至p-1。第L个移位寄存器中的第1个移位寄存器单元的上拉复位信号连接第L+2个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT；第L个移位寄存器中的第2个移位寄存器单元的上拉复位信号连接第L+2个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT；L取1至p-2。
另外，第p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT连接第1个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第p个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第1个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+1个冗余移位寄存器中的第1个冗余移位寄 存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+1个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；K取1至3。第1和2个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-1和p个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU；第1和2个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-1至p个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU；第3和4个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1和2个冗余移位寄存器中的第1个冗余移位寄存器单元的上拉复位信号端RESET_PU；第3和4个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1和2个冗余移位寄存器中的第2个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图8所示，时钟信号线的条数N等于8，8条时钟信号线分别为clk1、clk2......clk8，每组包括两行像素单元，此时j取1、2，也即p个移位寄存器中的每个包括两个移位寄存器单元。此时每相邻的8个移位寄存器分别连接clk1、clk2......clk8，且每个移位寄存器中的两个移位寄存器单元连接同一条时钟信号线；当然，该种显示面板还包括6个冗余移位寄存器，每个冗余移位寄存器同样包括两个移位寄存器单元；6个冗余移位寄存器分别连接clk1、clk2......clk6，每个冗余移位寄存器的两个移位寄存器单元连接同一条时钟信号线。其中，第1和2个移位寄存器中的两个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1和2个移位寄存器的两个移位寄存器单元响应于帧开启信号。第M个移位寄存器中的第1个所述移位寄存器单元的信号输出端OUTPUT连接第M+2个移位寄存器中的第1个移位寄存器单元的信号输入端INPUT；第M个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第M+2个移位寄存器中的第2个移位寄存器单元的信号输入端INPUT；M取1至p-2。第L个移位寄存器中的 第1个移位寄存器单元的上拉复位信号端RESET_PU连接第L+3个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT；第L个移位寄存器中的第2个移位寄存器单元的上拉复位信号连接第L+3个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT；L取1至p-3。
另外，第p-1和p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT分别连接第1和2个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第p-1和p个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第1和2个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+2个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+2个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；K取1至4。第1至3个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-2至p个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU；第1-3个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-2至p个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU；第4至6个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器中的第1个冗余移位寄存器单元的上拉复位信号端RESET_PU；第4至6个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器中的第2个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图9所示，时钟信号线的条数N等于10，10条时钟信号线分别为clk1、clk2......clk10，每组包括两行像素单元，此时j取1、2，也即p个移位寄存器中的每个包括两个移位寄存器单元。此时每相邻的10个移位寄存器分别连接clk1、clk2......clk10，且每个移位寄存器中的两个移位寄存器 单元连接同一条时钟信号线；当然，该种显示面板还包括8个冗余移位寄存器，每个冗余移位寄存器同样包括两个移位寄存器单元；第1至8个冗余移位寄存器分别连接clk1、clk2......clk8，每个冗余移位寄存器的两个移位寄存器单元连接同一条时钟信号线。其中，第1至3个移位寄存器中的两个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1至3个移位寄存器的两个移位寄存器单元响应于帧开启信号。第M个移位寄存器中的第1个所述移位寄存器单元的信号输出端OUTPUT连接第M+3个移位寄存器中的第1个移位寄存器单元的信号输入端INPUT；第M个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第M+3个移位寄存器中的第2个移位寄存器单元的信号输入端INPUT；M取1至p-3。第L个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU连接第L+4个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT；第L个移位寄存器中的第2个移位寄存器单元的上拉复位信号连接第L+4个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT；L取1至p-4。
另外，第p-2至p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第p-2至p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT连接第1至3个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第K+3个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第K+3个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；K取1至5。第1至4个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-3至p个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU；第1至4个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-3至p个移位寄存 器中的第2个移位寄存器单元的上拉复位信号端RESET_PU；第5至8个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至4个冗余移位寄存器中的第1个冗余移位寄存器单元的上拉复位信号端RESET_PU；第5至8个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至4个冗余移位寄存器中的第2个冗余移位寄存器单元的上拉复位信号端RESET_PU。
在另一个示例中，当时钟信号线的条数N为大于或者4的偶数，时钟信号的占空比为40％时；第1至(N-2)/2个移位寄存器中的各移位寄存器单元的信号输入端INPUT响应于帧开启信号；第M个移位寄存器中的第j个移位寄存器单元的信号输出端OUTPUT连接第M+(N-2)/2个移位寄存器中的第j个移位寄存器单元的信号输入端INPUT；第L个移位寄存器中的第j个移位寄存器单元的上拉复位信号端RESET_PU连接第L+N/2个移位寄存器中的第j个移位寄存器单元的信号输出端OUTPUT；M取1至p-(N-2)/2；L取1至p-N/2；j取1至q。
另外，由于第p个移位寄存器(最后一级移位寄存器)的信号输出端OUTPUT连接第p-N/2个移位寄存器单元的上拉复位信号端RESET_PU；故从第p-N/2+1至P个移位寄存器的各个移位寄存器单元的上拉节点PU没有移位寄存器为之提供复位信号。按照上述推导，第p个移位寄存器的第j个移位寄存器单元的上拉节点PU复位信号端，则需要第p+N/2个移位寄存器的第j个移位寄存器单元的信号输出端OUTPUT；同时还要保证第p+N/2个移位寄存器的第j个移位寄存器单元能够正常工作，故需要增加N个移位寄存器。为此，在一些实施例中，在显示面板中还设置有N个冗余移位寄存器，N个移位寄存器分别连接N条时钟信号线，每个冗余移位寄存器包括q个冗余移位寄存器单元(与移位寄存器中的移位寄存器单元相同)。其中，第1至N/2个冗余移位寄存器中的第j个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-N/2+1至p个移位寄存器中的第j个移位寄存器单元 的上拉复位信号端RESET_PU；第N/2+1至N个冗余移位寄存器中的第j个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至N/2个所述冗余移位寄存器中的第j个冗余移位寄存器单元的上拉复位信号端RESET_PU；j取1至q。
由此可以看出的是，通过第1至N/2个冗余移位寄存器所输出的信号，对第p-N/2+1至p个移位寄存器进行复位；同时，通过第N/2+1至N个冗余移位寄存器输出的信号对第1至N/2个冗余移位寄存器进行复位，以保证第1至N/2个冗余移位寄存器正常工作。
以下举例对当时钟信号线的条数N为大于或者4的偶数，时钟信号的占空比为40％时，各个移位寄存器的级联关系进行说明。
例如：如图10所示，时钟信号线的条数N等于4，4条时钟信号线分别为clk1、clk2......clk4，每组包括两行像素单元，此时j取1、2，也即P个移位寄存器中的每个包括两个移位寄存器单元。此时，每相邻的4个移位寄存器分别连接clk1、clk2......clk4，且每个移位寄存器中的两个移位寄存器单元连接同一条时钟信号线；当然，该种显示面板还包括4个冗余移位寄存器，每个冗余移位寄存器同样包括两个移位寄存器单元；4个冗余移位寄存器中的第1至4个分别连接clk1、clk2......clk4，每个冗余移位寄存器的两个移位寄存器单元连接同一条时钟信号线。其中，第1个移位寄存器中的两个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1个移位寄存器的两个移位寄存器单元响应于帧开启信号。第M个移位寄存器中的第1个所述移位寄存器单元的信号输出端OUTPUT连接第M+1个移位寄存器中的第1个移位寄存器单元的信号输入端INPUT；第M个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第M+1个移位寄存器中的第2个移位寄存器单元的信号输入端INPUT；M取1至p-1。第L个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU连接第L+2个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT；第L个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU连接第L+2 个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT；L取1至p-2。
另外，第p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT连接第1个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第p个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第1个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+1个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+1个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；K取1至3。第1和2个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-1和p个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU；第1和2个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-1至p个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU；第3和4个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1和2个冗余移位寄存器中的第1个冗余移位寄存器单元的上拉复位信号端RESET_PU；第3和4个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1和2个冗余移位寄存器中的第2个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图11所示，时钟信号线的条数N等于6，6条时钟信号线分别为clk1、clk2......clk6，每组包括两行像素单元，此时j取1、2，也即P个移位寄存器中的每个包括两个移位寄存器单元。此时，每相邻的6个移位寄存器分别连接clk1、clk2......clk6，且每个移位寄存器中的两个移位寄存器单元连接同一条时钟信号线；当然，该种显示面板还包括6个冗余移位寄存器，每个冗余移位寄存器同样包括两个移位寄存器单元；6个冗余移位寄存器中 的第1至6个分别连接clk1、clk2......clk6，每个冗余移位寄存器的两个移位寄存器单元连接同一条时钟信号线。其中，第1和2个移位寄存器中的两个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1和2个移位寄存器的两个移位寄存器单元响应于帧开启信号。第M个移位寄存器中的第1个所述移位寄存器单元的信号输出端OUTPUT连接第M+2个移位寄存器中的第1个移位寄存器单元的信号输入端INPUT；第M个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第M+2个移位寄存器中的第2个移位寄存器单元的信号输入端INPUT；M取1至p-2。第L个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU连接第L+3个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT；第L个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU连接第L+3个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT；L取1至p-3。
另外，第p-1和p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT分别连接第1和2个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第p-1和p个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT分别连接第1和2个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+2个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+2个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；K取1、2。第1至3个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-2至p个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU；第1至3个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-2至p个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU；第4 至6个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器中的第1个冗余移位寄存器单元的上拉复位信号端RESET_PU；第4至6个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器中的第2个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图12所示，时钟信号线的条数N等于8，8条时钟信号线分别为clk1、clk2......clk8，每组包括两行像素单元，此时j取1、2，也即p个移位寄存器中的每个包括两个移位寄存器单元。此时每相邻的8个移位寄存器分别连接clk1、clk2......clk8，且每个移位寄存器中的两个移位寄存器单元连接同一条时钟信号线；当然，该种显示面板还包括8个冗余移位寄存器，每个冗余移位寄存器同样包括两个移位寄存器单元；8个冗余移位寄存器分别连接clk1、clk2......clk8，每个冗余移位寄存器的两个移位寄存器单元连接同一条时钟信号线。其中，第1至3个移位寄存器中的两个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1至3个移位寄存器的两个移位寄存器单元响应于帧开启信号。第M个移位寄存器中的第1个所述移位寄存器单元的信号输出端OUTPUT连接第M+3个移位寄存器中的第1个移位寄存器单元的信号输入端INPUT；第M个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第M+3个移位寄存器中的第2个移位寄存器单元的信号输入端INPUT；M取1至p-3。第L个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU连接第L+4个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT；第L个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU连接第L+4个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT；L取1至p-4。
另外，第p-2至p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第p-2至p个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第1至3个冗余移位寄存器中的第2个冗余 移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第K+3个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第K+3个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；K取1至5。第1至4个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-3至p个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU；第5至8个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至4个冗余移位寄存器中的第1个冗余移位寄存器单元的上拉复位信号端RESET_PU；第1至4个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-3至p个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU；第5至8个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至4个冗余移位寄存器中的第2个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图13所示，时钟信号线的条数N等于10，10条时钟信号线分别为clk1、clk2......clk10，每组包括两行像素单元，此时j取1、2，也即p个移位寄存器中的每个包括两个移位寄存器单元。此时每相邻的10个移位寄存器分别连接clk1、clk2......clk10，且每个移位寄存器中的两个移位寄存器单元连接同一条时钟信号线；当然，该种显示面板还包括10个冗余移位寄存器，每个冗余移位寄存器同样包括两个移位寄存器单元；第1至10个冗余移位寄存器分别连接clk1、clk2......clk10，每个冗余移位寄存器的两个移位寄存器单元连接同一条时钟信号线。其中，第1至4个移位寄存器中的两个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1至4个移位寄存器的两个移位寄存器单元响应于帧开启信号。第M个移位寄存器中的第1个所述移位寄存器单元的信号输出端OUTPUT连接第M+4个移位寄存器中的第1个移位寄存器单元的信号输入端INPUT；第M个移位寄存 器中的第2个移位寄存器单元的信号输出端OUTPUT连接第M+4个移位寄存器中的第2个移位寄存器单元的信号输入端INPUT；M取1至p-4。第L个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU连接第L+5个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT；第L个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU连接第L+5个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT；L取1至p-5。
另外，第p-3至p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT分别连接第1至4个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第p-3至p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT连接第1至4个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+4个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+4个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；K取1至6。第1至5个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-4至p个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU；第1至5个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-4至p个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU；第6-10个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至5个冗余移位寄存器中的第1个冗余移位寄存器单元的上拉复位信号端RESET_PU；第6至10个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至5个冗余移位寄存器中的第2个冗余移位寄存器单元的上拉复位信号端RESET_PU。
在另一个示例中，当时钟信号线的条数N为大于或者4的偶数，时钟信号的占空比为50％时；第1至N/2个移位寄存器中的各移位寄存器单元的信号输入端INPUT响应于帧开启信号；第M个移位寄存器中的第j个移位寄存器单元的信号输出端OUTPUT连接第M+N/2个移位寄存器中的第j个移位寄存器单元的信号输入端INPUT；第L个移位寄存器中的第j个移位寄存器单元的上拉复位信号端RESET_PU连接第L+(N/2+1)个移位寄存器中的第j个移位寄存器单元的信号输出端OUTPUT；M取1至p-N/2；L取1至p-(N/2+1)；j取1至q。
另外，由于第p个移位寄存器(最后一级移位寄存器)的信号输出端OUTPUT连接第p-(N/2+1)个移位寄存器单元的上拉复位信号端RESET_PU；故从第p-N/2至P个移位寄存器的各个移位寄存器单元的上拉节点PU没有移位寄存器为之提供复位信号。按照上述推导，第p个移位寄存器的第j个移位寄存器单元的上拉节点PU复位信号端，则需要第p+N/2+1个移位寄存器的第j个移位寄存器单元的信号输出端OUTPUT；同时还要保证第p+N/2+1个移位寄存器的第j个移位寄存器单元能够正常工作，故需要增加N+2个移位寄存器。为此，在一些实施例中，在显示面板中还设置有N+2个冗余移位寄存器，N+2个冗余移位寄存器分别连接中的第1至N个分别连接N条时钟信号线，N+1和N+2分别连接第1和2条时钟信号线，每个冗余移位寄存器包括q个移位寄存器单元(与移位寄存器中的移位寄存器单元相同)。其中，第1至N/2+1个冗余移位寄存器中的第j个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-N/2至p个移位寄存器中的第j个移位寄存器单元的上拉复位信号端RESET_PU；第N/2+2至N+2个冗余移位寄存器中的第j个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至N/2+1个所述冗余移位寄存器中的第j个冗余移位寄存器单元的上拉复位信号端RESET_PU；j取1至q。
由此可以看出的是，通过第1至N/2+1个冗余移位寄存器所输出的信号，对第p-N/2至p个移位寄存器进行复位；同时，通过第N/2+2至N+2个冗余 移位寄存器输出的信号对第1至N/2+1个冗余移位寄存器进行复位，以保证第1至N/2+1个冗余移位寄存器正常工作。
以下举例对当时钟信号线的条数N为大于或者4的偶数，时钟信号的占空比为50％时，各个移位寄存器的级联关系进行说明。
例如：如图14所示，时钟信号线的条数N等于4，4条时钟信号线分别为clk1、clk2......clk4，每组包括两行像素单元，此时j取1、2，也即P个移位寄存器中的每个包括两个移位寄存器单元。此时，每相邻的4个移位寄存器分别连接clk1、clk2......clk4，且每个移位寄存器中的两个移位寄存器单元连接同一条时钟信号线；当然，该种显示面板还包括6个冗余移位寄存器，每个冗余移位寄存器同样包括两个移位寄存器单元；6个冗余移位寄存器中的第1至4个分别连接clk1、clk2......clk4，第5和6分别连接clk1、clk2；每个冗余移位寄存器的两个移位寄存器单元连接同一条时钟信号线。其中，第1和2个移位寄存器中的两个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1和2个移位寄存器的两个移位寄存器单元响应于帧开启信号。第M个移位寄存器中的第1个所述移位寄存器单元的信号输出端OUTPUT连接第M+2个移位寄存器中的第1个移位寄存器单元的信号输入端INPUT；第M个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第M+2个移位寄存器中的第2个移位寄存器单元的信号输入端INPUT；M取1至p-2。第L个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU连接第L+3个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT；第L个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU连接第L+3个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT；L取1至p-3。
另外，第p-1和p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT连接第1和2个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第p-1和p个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第1和2个冗余移位寄存器中的第2个冗余移位 寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+2个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+2个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；K取1至4。第1至3个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-2至p个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU；第1至3个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-2至p个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU；第4至6个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器中的第1个冗余移位寄存器单元的上拉复位信号端RESET_PU；第4至6个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器中的第2个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图15所示，时钟信号线的条数N等于6，6条时钟信号线分别为clk1、clk2......clk6，每组包括两行像素单元，此时j取1、2，也即P个移位寄存器中的每个包括两个移位寄存器单元。此时，每相邻的6个移位寄存器分别连接clk1、clk2......clk6，且每个移位寄存器中的两个移位寄存器单元连接同一条时钟信号线；当然，该种显示面板还包括8个冗余移位寄存器，每个冗余移位寄存器同样包括两个移位寄存器单元；8个冗余移位寄存器中的第1至6个分别连接clk1、clk2......clk6，第7和8个分别连接clk1、clk2；每个冗余移位寄存器的两个移位寄存器单元连接同一条时钟信号线。其中，第1和2个移位寄存器中的两个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1和2个移位寄存器的两个移位寄存器单元响应于帧开启信号。第M个移位寄存器中的第1个所述移位寄存器单元的信号输出端OUTPUT连接第M+3个移位寄存器中的第1个移位寄存器单元的信号输 入端INPUT；第M个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第M+3个移位寄存器中的第2个移位寄存器单元的信号输入端INPUT；M取1至p-3。第L个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU连接第L+4个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT；第L个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU连接第L+4个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT；L取1至p-4。
另外，第p-2至p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第p-2至p个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第K+3个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第K+3个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；K取1至3。第1至4个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-3至p个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU；第1至4个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-3至p个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU；第5至8个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至4个冗余移位寄存器中的第1个冗余移位寄存器单元的上拉复位信号端RESET_PU；第5至8个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至4个冗余移位寄存器中的第2个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图16所示，时钟信号线的条数N等于8，8条时钟信号线分别 为clk1、clk2......clk8，每组包括两行像素单元，此时j取1、2，也即p个移位寄存器中的每个包括两个移位寄存器单元。此时每相邻的8个移位寄存器分别连接clk1、clk2......clk8，且每个移位寄存器中的两个移位寄存器单元连接同一条时钟信号线；当然，该种显示面板还包括10个冗余移位寄存器，每个冗余移位寄存器同样包括两个移位寄存器单元；8个冗余移位寄存器中的第1至8个分别连接clk1、clk2......clk8，第9和10个分别连接clk1、clk2；每个冗余移位寄存器的两个移位寄存器单元连接同一条时钟信号线。其中，第1至4个移位寄存器中的两个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1至4个移位寄存器的两个移位寄存器单元响应于帧开启信号。第M个移位寄存器中的第1个所述移位寄存器单元的信号输出端OUTPUT连接第M+4个移位寄存器中的第1个移位寄存器单元的信号输入端INPUT；第M个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第M+4个移位寄存器中的第2个移位寄存器单元的信号输入端INPUT；M取1至p-4。第L个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU连接第L+5个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT；第L个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU连接第L+5个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT；L取1至p-5。
另外，第p-3至p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT分别连接第1至4个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第p-3至p个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第1至4个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+4个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+4个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；K取 1至6。第1至5个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-4至p个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU；第1至5个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-4至p个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU；第6至10个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至5个冗余移位寄存器中的第1个冗余移位寄存器单元的上拉复位信号端RESET_PU；第6至10个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至5个冗余移位寄存器中的第2个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图17所示，时钟信号线的条数N等于10，10条时钟信号线分别为clk1、clk2......clk10，每组包括两行像素单元，此时j取1、2，也即p个移位寄存器中的每个包括两个移位寄存器单元。此时每相邻的10个移位寄存器分别连接clk1、clk2......clk10，且每个移位寄存器中的两个移位寄存器单元连接同一条时钟信号线；当然，该种显示面板还包括12个冗余移位寄存器，每个冗余移位寄存器同样包括两个移位寄存器单元；12个冗余移位寄存器第1至10个分别连接clk1、clk2......clk10，第11至12个分别连接clk1、clk2；每个冗余移位寄存器的两个移位寄存器单元连接同一条时钟信号线。其中，第1至5个移位寄存器中的两个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1至5个移位寄存器的两个移位寄存器单元响应于帧开启信号。第M个移位寄存器中的第1个所述移位寄存器单元的信号输出端OUTPUT连接第M+5个移位寄存器中的第1个移位寄存器单元的信号输入端INPUT；第M个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT连接第M+5个移位寄存器中的第2个移位寄存器单元的信号输入端INPUT；M取1至p-5。第L个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU连接第L+6个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT；第L个移位寄存器中的第2个移位寄存 器单元的上拉复位信号端RESET_PU连接第L+6个移位寄存器中的第2个移位寄存器单元的信号输出端OUTPUT；L取1至p-6。
另外，第p-4至p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT分别连接第1至5个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第p-4至p个移位寄存器中的第1个移位寄存器单元的信号输出端OUTPUT连接第1至5个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+5个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+5个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输入端INPUT；K取1至7。第1至6个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-5至p个移位寄存器中的第1个移位寄存器单元的上拉复位信号端RESET_PU；第1-6个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-5至p个移位寄存器中的第2个移位寄存器单元的上拉复位信号端RESET_PU；第7至12个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至6个冗余移位寄存器中的第1个冗余移位寄存器单元的上拉复位信号端RESET_PU；第7至12个冗余移位寄存器中的第2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至6个冗余移位寄存器中的第2个冗余移位寄存器单元的上拉复位信号端RESET_PU。
当每个移位寄存器包括1个移位寄存器单元和q个子信号输出端OUTPUT时，时钟信号线的条数N大于或者等于4的偶数，时钟信号的占空比分别为30％、40％、50％时，对各个移位寄存器单元单元之间的级联关系进行说明。图18中仅以q为2，即每个移位寄存器包括1个移位寄存器单元和2个信号输出端OUTPUT为例。在以下描述中所涉及的某一个移位寄存器单元则是指其所属移位寄存器的移位寄存器单元。
在一个示例中，当时钟信号线的条数N为大于或者6的偶数，时钟信号的占空比为30％时；第1至(N-4)/2个移位寄存器单元的信号输入端INPUT响应于帧开启信号；第M个移位寄存器单元的信号输出端OUTPUT连接第M+(N-4)/2个移位寄存器单元的信号输入端INPUT；第L个移位寄存器单元的上拉复位信号端RESET_PU连接第L+(N/2-1)个移位寄存器单元的信号输出端OUTPUT；M取1至p-(N-4)/2；L取1至p-(N/2-1)；j取1至q。
另外，由于第p个移位寄存器单元(最后一级移位寄存器单元)的信号输出端OUTPUT连接第p-(N/2-1)个移位寄存器单元的上拉复位信号端RESET_PU；故从第p-(N/2-2)至P个移位寄存器单元的各个移位寄存器单元的上拉节点PU没有移位寄存器为之提供复位信号。按照上述推导，第p个移位寄存器单元的上拉节点PU复位信号端，则需要第p+(N/2-1)个移位寄存器单元的信号输出端OUTPUT；同时还要保证第p+(N/2-1)个移位寄存器单元能够正常工作，故需要增加N-2个移位寄存器也即增加N-2个冗余移位寄存器单元。为此，在一些实施例中，在显示面板中还设置有N-2个冗余移位寄存器，N-2个移位寄存器分别连接N-2条时钟信号线，每个冗余移位寄存器包括1个移位寄存器单元(与移位寄存器中的移位寄存器单元相同，为了与上述移位寄存器单元相区分，将冗余移位寄存器称之为冗余移位寄存器单元)，其中，第1至N/2-1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-N/2至p个移位寄存器单元的上拉复位信号端RESET_PU；第N/2至N-2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至N/2-1个所述冗余移位寄存器单元的上拉复位信号端RESET_PU；j取1至q。
由此可以看出的是，通过第1至N/2-1个冗余移位寄存器单元所输出的信号，对第p-(N/2-2)至p个移位寄存器单元进行复位；同时，通过第N/2至N-2个冗余移位寄存器单元输出的信号对第1至N/2-1个冗余移位寄存器单元进行复位，以保证第1至N/2-1个冗余移位寄存器单元正常工作。
以下举例对当时钟信号线的条数N为大于或者6的偶数，时钟信号的占 空比为30％时，各个移位寄存器的级联关系进行说明。
例如：如图19所示，时钟信号线的条数N等于6，6条时钟信号线分别为clk1、clk2......clk6，每组包括两行像素单元，此时j取1、2，也即每个移位寄存器中均包括1个移位寄存器单元。此时，每相邻的6个移位寄存器单元分别连接clk1、clk2......clk6；当然，该种显示面板还包括4个冗余移位寄存器，每个冗余移位寄存器同样均包括1移位寄存器单元，称之为冗余移位寄存器单元；4个冗余移位寄存器单元分别连接clk1、clk2......clk4。其中，第1个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1个移位寄存器单元响应于帧开启信号。第M个移位寄存单元的信号输出端OUTPUT连接第M+1个移位寄存器单元的信号输入端INPUT；M取1至p-1。第L个移位寄存器单元的上拉复位信号连接第L+2个移位寄存器单元的信号输出端OUTPUT；L取1至p-2。
另外，第p个移位寄存器单元的信号输出端OUTPUT连接第1个冗余移位寄存单元的信号输入端INPUT；第K个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+1个冗余移位寄存器单元的信号输入端INPUT；K取1至3。第1和2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-1和p个移位寄存器单元的上拉复位信号端RESET_PU；第3和4个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1和2个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图20所示，时钟信号线的条数N等于8，8条时钟信号线分别为clk1、clk2......clk8，每组包括两行像素单元，此时j取1、2，也即p个移位寄存器中的每个包括1个移位寄存器单元和2个子信号输出端OUTPUT。此时每相邻的8个移位寄存器单元分别连接clk1、clk2......clk8；当然，该种显示面板还包括6个冗余移位寄存器，每个冗余移位寄存器均包括1个冗余移位寄存器单元；6个冗余移位寄存器单元分别连接clk1、clk2......clk6。其中，第1和2个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1和2个移位寄存器单元响应于帧开启信号。第M个移位寄存器单元 的信号输出端OUTPUT连接第M+2个移位寄存器单元的信号输入端INPUT；M取1至p-2。第L个移位寄存器单元的上拉复位信号端RESET_PU连接第L+3个移位寄存器单元的信号输出端OUTPUT；第L个移位寄存器单元的上拉复位信号连接第L+3个移位寄存器单元的信号输出端OUTPUT；L取1至p-3。
另外，第p-1和p个移位寄存器单元的信号输出端OUTPUT分别连接第1和2个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+2个冗余移位寄存器单元的信号输入端INPUT；K取1至4。第1至3个冗余移位寄存单元的信号输出端OUTPUT分别连接第p-2至p个移位寄存器单元的上拉复位信号；第4至6个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图21所示，时钟信号线的条数N等于10，10条时钟信号线分别为clk1、clk2......clk10，每组包括两行像素单元，此时j取1、2，也即p个移位寄存器中的每个包括1个移位寄存器单元和2个子信号输出端OUTPUT。此时每相邻的10个移位寄存器单元分别连接clk1、clk2......clk10；当然，该种显示面板还包括8个冗余移位寄存器，每个冗余移位寄存器均包括1个冗余移位寄存器单元；第1至8个冗余移位寄存器单元分别连接clk1、clk2......clk8。其中，第1至3个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1至3个移位寄存器单元响应于帧开启信号。第M个移位寄存器单元的信号输出端OUTPUT连接第M+3个移位寄存器单元的信号输入端INPUT；M取1至p-3。第L个移位寄存器单元的上拉复位信号端RESET_PU连接第L+4个移位寄存器单元的信号输出端OUTPUT；L取1至p-4。
另外，第p-2至p个移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器单元的信号输出端OUTPUT分别连接第K+3个冗余移位寄存器单元的信号 输入端INPUT；K取1至5。第1至4个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-3至p个移位寄存器单元的上拉复位信号端RESET_PU；第5至8个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至4个冗余移位寄存器单元的上拉复位信号端RESET_PU。
在另一个示例中，当时钟信号线的条数N为大于或者4的偶数，时钟信号的占空比为40％时；第1至(N-2)/2个移位寄存器中的移位寄存器单元的信号输入端INPUT响应于帧开启信号；第M个移位寄存器单元的信号输出端OUTPUT连接第M+(N-2)/2个移位寄存器单元的信号输入端INPUT；第L个移位寄存器单元的上拉复位信号端RESET_PU连接第L+N/2个移位寄存器单元的信号输出端OUTPUT；M取1至p-(N-2)/2；L取1至p-N/2。
另外，由于第p个移位寄存器单元(最后一级移位寄存器单元)的信号输出端OUTPUT连接第p-N/2个移位寄存器单元的上拉复位信号端RESET_PU；故从第p-N/2+1至P个移位寄存器单元的上拉节点PU没有移位寄存器单元为之提供复位信号。按照上述推导，第p个移位寄存器单元的上拉节点PU复位信号端，则需要第p+N/2个移位寄存器单元的信号输出端OUTPUT；同时还要保证第p+N/2个移位寄存器单元能够正常工作，故需要增加N个移位寄存器。为此，在一些实施例中，在显示面板中还设置有N个冗余移位寄存器，N个冗余移位寄存器分别连接N条时钟信号线，每个冗余移位寄存器包括1个冗余移位寄存器单元(与移位寄存器中的移位寄存器单元相同)。其中，第1至N/2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-N/2+1至p个移位寄存器单元的上拉复位信号端RESET_PU；第N/2+1至N个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至N/2个冗余移位寄存单元的上拉复位信号端RESET_PU。
由此可以看出的是，通过第1至N/2个冗余移位寄存器所输出的信号，对第p-N/2+1至p个移位寄存器进行复位；同时，通过第N/2+1至N个冗余移位寄存器输出的信号对第1至N/2个冗余移位寄存器进行复位，以保证第 1至N/2个冗余移位寄存器正常工作。
以下举例对当时钟信号线的条数N为大于或者4的偶数，时钟信号的占空比为40％时，各个移位寄存器的级联关系进行说明。
例如：如图22所示，时钟信号线的条数N等于4，4条时钟信号线分别为clk1、clk2......clk4，每组包括两行像素单元，此时j取1、2，也即每个移位寄存器均包括1个移位寄存器单元和2个子信号输出端OUTPUT。此时，每相邻的4个移位寄存器分别连接clk1、clk2......clk4，且每个移位寄存器中的两个移位寄存器单元连接同一条时钟信号线；当然，该种显示面板还包括4个冗余移位寄存器，每个冗余移位寄存器均包括1个冗余移位寄存器单元；4个冗余移位寄存器单元分别连接clk1、clk2......clk4。其中，第1个移位寄存器中的两个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1个移位寄存器单元响应于帧开启信号。第M个移位寄存器单元的信号输出端OUTPUT连接第M+1个移位寄存器单元的信号输入端INPUT；M取1至p-1。第L个移位寄存单元的上拉复位信号端RESET_PU连接第L+2个移位寄存器单元的信号输出端OUTPUT；L取1至p-2。
另外，第p个移位寄存器单元的信号输出端OUTPUT连接第1个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+1个冗余移位寄存器单元的信号输入端INPUT；K取1至3。第1和2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-1和p个移位寄存器单元的上拉复位信号端RESET_PU；第3和4个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1和2个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图23所示，时钟信号线的条数N等于6，6条时钟信号线分别为clk1、clk2......clk6，每组包括两行像素单元，此时j取1、2，也即每个移位寄存器均包括1个移位寄存器单元和2个子信号输出端OUTPUT。此时，每相邻的6个移位寄存器单元分别连接clk1、clk2......clk6；当然，该种显示面板还包括6个冗余移位寄存器，每个冗余移位寄存器均包括1个冗余移位 寄存器单元；6个冗余移位寄存器单元分别连接clk1、clk2......clk6。其中，第1和2个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1和2个移位寄存器单元响应于帧开启信号。第M个移位寄存器单元的信号输出端OUTPUT连接第M+2个移位寄存器单元的信号输入端INPUT；M取1至p-2。第L个移位寄存器单元的上拉复位信号端RESET_PU连接第L+3个移位寄存器单元的信号输出端OUTPUT；L取1至p-3。
另外，第p-1和p个移位寄存器单元的信号输出端OUTPUT分别连接第1和2个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+2个冗余移位寄存器单元的信号输入端INPUT；K取1、2。第1至3个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-2至p个移位寄存器单元的上拉复位信号端RESET_PU；第4至6个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图24所示，时钟信号线的条数N等于8，8条时钟信号线分别为clk1、clk2......clk8，每组包括两行像素单元，此时j取1、2，也即每个移位寄存器包括1个移位寄存器单元和2个子信号输出端OUTPUT。此时每相邻的8个移位寄存器单元分别连接clk1、clk2......clk8；当然，该种显示面板还包括8个冗余移位寄存器，每个冗余移位寄存器均包括1个冗余移位寄存器单元；8个冗余冗余移位寄存器单元分别连接clk1、clk2......clk8，每个冗余移位寄存器单元的两个移位寄存器单元连接同一条时钟信号线。其中，第1至3个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1至3个移位寄存器单元响应于帧开启信号。第M个移位寄存器单元的信号输出端OUTPUT连接第M+3个移位寄存器单元的信号输入端INPUT；M取1至p-3。第L个移位寄存器单元的上拉复位信号端RESET_PU连接第L+4个移位寄存器单元的信号输出端OUTPUT；L取1至p-4。
另外，第p-2至p个移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器 单元的信号输出端OUTPUT分别连接第K+3个冗余移位寄存器单元的信号输入端INPUT；K取1至5。第1至4个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-3至p个移位寄存器单元的上拉复位信号端RESET_PU；第5至8个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至4个冗余移位寄存器单元的上拉复位信号端RESET_PU；
例如：如图25所示，时钟信号线的条数N等于10，10条时钟信号线分别为clk1、clk2......clk10，每组包括两行像素单元，此时j取1、2，也即每个移位寄存器均包括1个移位寄存器单元和2个子信号输出端OUTPUT。此时每相邻的10个移位寄存器单元分别连接clk1、clk2......clk10；当然，该种显示面板还包括10个冗余移位寄存器，每个冗余移位寄存器包括1个移位寄存器单元；第1至10个冗余移位寄存器单元分别连接clk1、clk2......clk10。其中，第1至4个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1至4个移位寄存器单元响应于帧开启信号。第M个移位寄存器单元的信号输出端OUTPUT连接第M+4个移位寄存器单元的信号输入端INPUT；M取1至p-4。第L个移位寄存器单元的上拉复位信号端RESET_PU连接第L+5个移位寄存器单元的信号输出端OUTPUT；L取1至p-5。
另外，第p-3至p个移位寄存器单元的信号输出端OUTPUT分别连接第1至4个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+4个冗余移位寄存器单元的信号输入端INPUT；K取1至6。第1至5个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-4至p个移位寄存器单元的上拉复位信号端RESET_PU；第6-10个冗余移位寄存器器单元的信号输出端OUTPUT分别连接第1至5个冗余移位寄存器单元的上拉复位信号端RESET_PU。
在另一个示例中，当时钟信号线的条数N为大于或者4的偶数，时钟信号的占空比为50％时；第1至N/2个移位寄存器中的移位寄存器单元的信号输入端INPUT响应于帧开启信号；第M个移位寄存器单元的信号输出端 OUTPUT连接第M+N/2个移位寄存器单元的信号输入端INPUT；第L个移位寄存器单元的上拉复位信号端RESET_PU连接第L+(N/2+1)个移位寄存器单元的信号输出端OUTPUT；M取1至p-N/2；L取1至p-(N/2+1)。
另外，由于第p个移位寄存器单元(最后一级移位寄存器单元)的信号输出端OUTPUT连接第p-(N/2+1)个移位寄存器单元的上拉复位信号端RESET_PU；故从第p-N/2至P个移位寄存器单元的上拉节点PU没有移位寄存器单元为之提供复位信号。按照上述推导，第p个移位寄存器单元的上拉节点PU复位信号端，则需要第p+N/2+1个移位寄存器单元的信号输出端OUTPUT；同时还要保证第p+N/2+1个移位寄存器单元能够正常工作，故需要增加N+2个移位寄存器单元。为此，在一些实施例中，在显示面板中还设置有N+2个冗余移位寄存器，每个冗余移位寄存器均包括1个冗余移位寄存器单元(与移位寄存器中的移位寄存器单元相同)，N+2个冗余移位寄存器单元中的第1至N个分别连接N条时钟信号线，第N+1和N+2个分别连接第1和2条时钟信号线。其中，第1至N/2+1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-N/2至p个移位寄存器单元的上拉复位信号端RESET_PU；第N/2+2至N+2个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至N/2+1个所述冗余移位寄存器单元的上拉复位信号端RESET_PU。
由此可以看出的是，通过第1至N/2+1个冗余移位寄存器所输出的信号，对第p-N/2至p个移位寄存器进行复位；同时，通过第N/2+2至N+2个冗余移位寄存器输出的信号对第1至N/2+1个冗余移位寄存器进行复位，以保证第1至N/2+1个冗余移位寄存器正常工作。
以下举例对当时钟信号线的条数N为大于或者4的偶数，时钟信号的占空比为50％时，各个移位寄存器的级联关系进行说明。
例如：如图26所示，时钟信号线的条数N等于4，4条时钟信号线分别为clk1、clk2......clk4，每组包括两行像素单元，此时j取1、2，也即每个移位寄存器均包括1个移位寄存器单元。此时，每相邻的4个移位寄存器单元 分别连接clk1、clk2......clk4；当然，该种显示面板还包括6个冗余移位寄存器，每个冗余移位寄存器均包括1个冗余移位寄存器单元；6个冗余移位寄存器单元中的第1至4个分别连接clk1、clk2......clk4，第5和6个分别连接clk1、clk2。其中，第1和2个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1和2个移位寄存器单元响应于帧开启信号。第M个移位寄存器单元的信号输出端OUTPUT连接第M+2个移位寄存器单元的信号输入端INPUT；M取1至p-2。第L个移位寄存器单元的上拉复位信号端RESET_PU连接第L+3个移位寄存器单元的信号输出端OUTPUT；L取1至p-3。
另外，第p-1和p个移位寄存器单元的信号输出端OUTPUT连接第1和2个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+2个冗余移位寄存器单元的信号输入端INPUT；K取1至4。第1至3个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-2至p个移位寄存器单元的上拉复位信号端RESET_PU；第4至6个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图27所示，时钟信号线的条数N等于6，6条时钟信号线分别为clk1、clk2......clk6，每组包括两行像素单元，此时j取1、2，也即每个移位寄存器中均包括1个移位寄存器单元和2个子信号输出端OUTPUT。此时，每相邻的6个移位寄存器单元分别连接clk1、clk2......clk6；当然，该种显示面板还包括8个冗余移位寄存器，每个冗余移位寄存器均包括1个冗余移位寄存器单元；8个冗余移位寄存器中的第1至6个分别连接clk1、clk2......clk6，第7和8个分别连接clk1、clk2。其中，第1和2个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1和2个移位寄存单元响应于帧开启信号。第M个移位寄存器单元的信号输出端OUTPUT连接第M+3个移位寄存器单元的信号输入端INPUT；M取1至p-3。第L个移位寄存器单元的上拉复位信号端RESET_PU连接第L+4个移位寄存器单元的信号输出 端OUTPUT；L取1至p-4。
另外，第p-2至p个移位寄存器单元的信号输出端OUTPUT分别连接第1至3个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输出端OUTPUT分别连接第K+3个冗余移位寄存器中的第1个冗余移位寄存器单元的信号输入端INPUT；K取1至3。第1至4个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-3至p个移位寄存器单元的上拉复位信号端RESET_PU；第5至8个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至4个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图28所示，时钟信号线的条数N等于8，8条时钟信号线分别为clk1、clk2......clk8，每组包括两行像素单元，此时j取1、2，也即每个移位寄存器均包括1个移位寄存器单元和2个子信号输出端OUTPUT。此时每相邻的8个移位寄存器单元分别连接clk1、clk2......clk8；当然，该种显示面板还包括10个冗余移位寄存器，每个冗余移位寄存器均包括1个冗余移位寄存器单元；10个冗余移位寄存器单元中的第1至8个分别连接clk1、clk2......clk8，第9和10个分别连接clk1、clk2。其中，第1至4个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1至4个移位寄存器单元响应于帧开启信号。第M个移位寄存器单元的信号输出端OUTPUT连接第M+4个移位寄存器单元的信号输入端INPUT；M取1至p-4。第L个移位寄存器单元的上拉复位信号端RESET_PU连接第L+5个移位寄存器单元的信号输出端OUTPUT；L取1至p-5。
另外，第p-3至p个移位寄存器单元的信号输出端OUTPUT分别连接第1至4个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+4个冗余移位寄存器单元的信号输入端INPUT；K取1至6。第1至5个冗余移位寄存器单元的信号输出端OUTPUT分别连接第p-4至p个移位寄存器单元的上拉复位信号端RESET_PU；第6至10个冗余移位寄存器单元的信号输出端OUTPUT分别 连接第1至5个冗余移位寄存器单元的上拉复位信号端RESET_PU。
例如：如图29所示，时钟信号线的条数N等于10，10条时钟信号线分别为clk1、clk2......clk10，每组包括两行像素单元，此时j取1、2，也即每个移位寄存器均包括1个移位寄存器单元和2个子信号输出端OUTPUT。此时每相邻的10个移位寄存器单元分别连接clk1、clk2......clk10；当然，该种显示面板还包括12个冗余移位寄存器，每个冗余移位寄存器均包括1个冗余移位寄存器单元；12个冗余移位寄存器单元第1至10个分别连接clk1、clk2......clk10，第11至12个分别连接clk1、clk2。其中，第1至5个移位寄存器单元的信号输入端INPUT均连接帧开启信号线，也即第1至5个移位寄存器单元响应于帧开启信号。第M个移位寄存器单元的信号输出端OUTPUT连接第M+5个移位寄存器单元的信号输入端INPUT；M取1至p-5。第L个移位寄存器单元的上拉复位信号端RESET_PU连接第L+6个移位寄存器单元的信号输出端OUTPUT；L取1至p-6。
另外，第p-4至p个移位寄存器单元的信号输出端OUTPUT分别连接第1至5个冗余移位寄存器单元的信号输入端INPUT；第K个冗余移位寄存器单元的信号输出端OUTPUT分别连接K+5个冗余移位寄存器单元的信号输入端INPUT；K取1至7。第1至6个冗余移位寄存单元的信号输出端OUTPUT分别连接第p-5至p个移位寄存器单元的上拉复位信号端RESET_PU；第7至12个冗余移位寄存器单元的信号输出端OUTPUT分别连接第1至6个冗余移位寄存器单元的上拉复位信号端RESET_PU。
第二方面，本公开实施例提供一种显示装置，其包括上述的任意一种显示面板。
该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
当然，本实施例的显示装置中还可以包括其他常规结构，如电源单元、 显示驱动单元等。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (22)

  1. 一种显示面板，其包括p组像素单元，所述p组像素单元中的每组包括q行所述像素单元，p、q均为大于或者等于2的整数；其中，位于同一组的所述像素单元由同一移位寄存器同时提供栅扫描信号；位于同一组、且处于同一列的所述像素单元由不同的数据线提供数据电压信号。
  2. 根据权利要求1所述的显示面板，其中，还包括N条时钟信号线，N为大于或者4的偶数，p大于或者等于2N；每个所述移位寄存器连接一条所述时钟信号线，且不同的所述时钟信号线连接所连接的所述移位寄存器不同。
  3. 根据权利要求2所述的显示面板，其中，位于同一行的所述像素单元连接同一栅线；每个所述移位寄存器包括q个移位寄存器单元，所述移位寄存器单元与所述栅线一一对应连接。
  4. 根据权利要求3所述的显示面板，其中，每一个所述移位寄存器单元通过一条信号连接线与所述时钟信号线连接，且不同的所述移位寄存器单元连接不同的所述信号连接线。
  5. 根据权利要求3所述的显示面板，其中，每个所述移位寄存器所包括的多个所述移位寄存器单元通过同一信号连接线与所述时钟信号线连接，且不同的所述移位寄存器所包括的多个所述移位寄存器单元连接不同的信号连接线。
  6. 根据权利要求3所述的显示面板，其中，所述移位寄存器单元均至少包括输入子电路、输出子电路、上拉复位子电路；其中，所述输入子电路响应于信号输入端所输入的输入信号，并将所述输入信号输入至上拉节点；所述输出子电路响应于所述上拉节点的电位，并将所述时钟信号线所输入的时钟信号通过信号输出端输出；所述上拉复位子电路响应于所述上拉复位信号端所输入的上拉复位信号，并通过非工作电平信号对所述上拉节点的电位进行复位；
    每相邻设置的N个所述移位寄存器与N条所述时钟信号线一一对应连接，且第i个所述移位寄存器与第i+N个所述移位寄存器连接同一所述时钟信号线；i取1至p-N。
  7. 根据权利要求6所述的显示面板，其中，当所述时钟信号的占空比为30％，N为大于或者等于6的偶数时；
    第1至(N-4)/2个所述移位寄存器中的各所述移位寄存器单元的信号输入端响应于帧开启信号；
    第M个所述移位寄存器中的第j个所述移位寄存器单元的信号输出端连接第M+(N-4)/2个所述移位寄存器中的所述第j个所述移位寄存器单元的信号输入端；
    第L个所述移位寄存器中的第j个所述移位寄存器单元的上拉复位信号端连接第L+(N/2-1)个所述移位寄存器中的第j个所述移位寄存器单元的信号输出端；M取1至p-(N-4)/2；L取1至p-(N/2-1)；j取1至q。
  8. 根据权利要求7所述显示面板，其中，还包括N-2个冗余移位寄存器，N-2个所述冗余移位寄存器分别连接N-2条时钟信号线，每个所述冗余移位寄存器包括q个冗余移位寄存器单元；所述冗余移位寄存器单元与所述移位寄存器单元结构相同；其中，
    第1至N/2-1个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的信号输出端分别连接第p-(N/2-2)至p个所述移位寄存器中的第j个所述移位寄存器单元的上拉复位信号端；
    第N/2至N-2个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的信号输出端分别连接第1至N/2-1个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的上拉复位信号端。
  9. 根据权利要求6所述的显示面板，其中，当所述时钟信号的占空比为40％，N为大于或者等于4的偶数时；
    第1至(N-2)/2个所述移位寄存器中的各所述移位寄存器单元的信号输入端响应于帧开启信号；
    第M个所述移位寄存器中的第j个所述移位寄存器单元的信号输出端连接第M+(N-2)/2个所述移位寄存器中的第j个所述移位寄存器单元的信号输入端；
    第L个所述移位寄存器中的第j个所述移位寄存器单元的上拉复位信号端连接第L+N/2个所述移位寄存器中的第j个所述移位寄存器单元的信号输出端；M取1至p-(N-2)/2；L取1至p-N/2；j取1至q。
  10. 根据权利要求9所述的显示面板，其中，还包括N个冗余移位寄存器，N个移位寄存器分别连接N条时钟信号线；每个所述冗余移位寄存器包括q个冗余移位寄存器单元；所述冗余移位寄存器单元与所述移位寄存器单元结构相同；其中，
    第1至N/2个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的信号输出端分别连接第p-N/2+1至p个所述移位寄存器中的第j个所述移位寄存器单元的上拉复位信号端；第N/2+1至N个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的信号输出端分别连接第1至N/2个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的上拉复位信号端。
  11. 根据权利要求6所述的显示面板，其中，当所述时钟信号的占空比为50％，N为大于或者等于4的偶数时；
    第1至N/2个所述移位寄存器中的各所述移位寄存器单元的信号输入端响应于帧开启信号；
    第M个所述移位寄存器中的第j个所述移位寄存器单元的信号输出端连接第M+N/2个所述移位寄存器中的第j个所述移位寄存器单元的信号输入端；
    第L个所述移位寄存器中的第j个所述移位寄存器单元的上拉复位信号端连接第L+(N/2+1)个所述移位寄存器中的第j个所述移位寄存器单元的信号输出端；M取1至p-N/2；L取1至p-(N/2+1)；j取1至q。
  12. 根据权利要求11所述的显示面板，其中，还包括N+2个冗余移位寄存器，N+2个冗余移位寄存器中的第1至N个分别连接N条所述时钟信 号线，第N+1和N+2个分别连接第1和2条时钟信号线；每个所述冗余移位寄存器包括q个冗余移位寄存器单元；所述冗余移位寄存器单元与所述移位寄存器单元结构相同；其中，
    第1至N/2+1个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的信号输出端分别连接第p-N/2至p个所述移位寄存器中的第j个所述移位寄存器单元的上拉复位信号端；
    第N/2+2至N+2个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的信号输出端分别连接第1至N/2+1个所述冗余移位寄存器中的第j个所述冗余移位寄存器单元的上拉复位信号端。
  13. 根据权利要求2所述的显示面板，其中，位于同一行的所述像素单元连接同一栅线；每个所述移位寄存器包括一个移位寄存器单元以及与所述移位寄存器单元的信号输出端连接的q个子信号输出端，所述子信号输出端与所述栅线一一对应连接。
  14. 根据权利要求13所述的显示面板，其中，所述移位寄存器单元均至少包括输入子电路、输出子电路、上拉复位子电路；其中，所述输入子电路响应于信号输入端所输入的输入信号，并将所述输入信号输入至上拉节点；所述输出子电路响应于所述上拉节点的电位，并将所述时钟信号线所输入的时钟信号输入至信号输出端，以使所述信号输出端通过q个所述子信号输出端输出；所述上拉复位子电路响应于所述上拉复位信号端所输入的上拉复位信号，并通过非工作电平信号对所述上拉节点的电位进行复位；
    每相邻设置的N个所述移位寄存器单元与N条所述时钟信号线一一对应连接，且第i个所述移位寄存器单元与第i+N个所述移位寄存器单元连接同一所述时钟信号线；i取1至p-N。
  15. 根据权利要求14所述的显示面板，其中，当所述时钟信号的占空比为30％，N为大于或者等于6的偶数时；
    第1至(N-4)/2个所述移位寄存器单元的信号输入端响应于帧开启信号；
    第M个所述移位寄存器单元的信号输出端连接第M+(N-4)/2个所述移位寄存器单元的信号输入端；
    第L个所述移位寄存器单元的上拉复位信号端连接第L+(N/2-1)个所述移位寄存器单元的信号输出端；M取1至p-(N-4)/2；L取1至p-(N/2-1)。
  16. 根据权利要求15所述显示面板，其中，还包括N-2个冗余移位寄存器，N-2个所述冗余移位寄存器分别连接N-2条时钟信号线，每个所述冗余移位寄存器包括1个冗余移位寄存器单元；所述冗余移位寄存器单元与所述移位寄存器单元结构相同；其中，
    第1至N/2-1个所述冗余移位寄存器单元的信号输出端分别连接第p-(N/2-2)至p个所述移位寄存器单元的上拉复位信号端；
    第N/2至N-2个所述冗余移位寄存器单元的信号输出端分别连接第1至N/2-1个所述冗余移位寄存器单元的上拉复位信号端。
  17. 根据权利要求14所述的显示面板，其中，当所述时钟信号的占空比为40％，N为大于或者等于4的偶数时；
    第1至(N-2)/2个所述移位寄存器器单元的信号输入端响应于帧开启信号；
    第M个所述移位寄存器单元的信号输出端连接第M+(N-2)/2个所述移位寄存器单元的信号输入端；
    第L个所述移位寄存器单元的上拉复位信号端连接第L+N/2个所述移位寄存器单元的信号输出端；M取1至p-(N-2)/2；L取1至p-N/2。
  18. 根据权利要求17所述的显示面板，其中，还包括N个冗余移位寄存器，N个冗余移位寄存器分别连接N条时钟信号线；每个所述冗余移位寄存器包括1个冗余移位寄存器单元；所述冗余移位寄存器单元与所述移位寄存器单元结构相同；其中，
    第1至N/2个所述冗余移位寄存器单元的信号输出端分别连接第p-N/2+1至p个所述移位寄存器单元的上拉复位信号端；
    第N/2+1至N个所述冗余移位寄存器单元的信号输出端分别连接第1 至N/2个所述冗余移位寄存器单元的上拉复位信号端。
  19. 根据权利要求14所述的显示面板，其中，当所述时钟信号的占空比为50％，N为大于或者等于4的偶数时；
    第1至N/2个所述移位寄存器单元的信号输入端响应于帧开启信号；
    第M个所述移位寄存器单元的信号输出端连接第M+N/2个所述移位寄存器单元的信号输入端；
    第L个所述移位寄存器单元的上拉复位信号端连接第L+(N/2+1)个所述移位寄存器单元的信号输出端；M取1至p-N/2；L取1至p-(N/2+1)。
  20. 根据权利要求19所述的显示面板，其中，还包括N+2个冗余移位寄存器，N+2个所述冗余移位寄存器中的第1至N个分别连接N条所述时钟信号线，第N+1和N+2个分别连接第1和2条时钟信号线；每个所述冗余移位寄存器包括1个冗余移位寄存器单元；所述冗余移位寄存器单元与所述移位寄存器单元结构相同；其中，
    第1至N/2+1个所述冗余移位寄存器单元的信号输出端分别连接第p-N/2至p个所述移位寄存器单元的上拉复位信号端；
    第N/2+2至N+2个所述冗余移位寄存器单元的信号输出端分别连接第1至N/2+1个所述冗余移位寄存器单元的上拉复位信号端。
  21. 根据权利要求1-20中任一项所述的显示面板，其中，每组中的q行所述像素单元相邻设置。
  22. 一种显示装置，其包括权利要求1-21中任一项所述的显示面板。
PCT/CN2021/099278 2020-07-31 2021-06-10 显示面板及显示装置 WO2022022095A1 (zh)

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