WO2020215906A1 - 阵列基板、其驱动方法及显示装置 - Google Patents

阵列基板、其驱动方法及显示装置 Download PDF

Info

Publication number
WO2020215906A1
WO2020215906A1 PCT/CN2020/078422 CN2020078422W WO2020215906A1 WO 2020215906 A1 WO2020215906 A1 WO 2020215906A1 CN 2020078422 W CN2020078422 W CN 2020078422W WO 2020215906 A1 WO2020215906 A1 WO 2020215906A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrically connected
control
gate
shift register
transistor
Prior art date
Application number
PCT/CN2020/078422
Other languages
English (en)
French (fr)
Inventor
赵晶
赵爽
孙继刚
苏旭
王磊
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Publication of WO2020215906A1 publication Critical patent/WO2020215906A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a driving method thereof, and a display device.
  • the demand for high-resolution display panels increases.
  • the power consumption can be reduced by means of partial display. For example, it is possible to reduce power consumption by displaying a black screen on the part of the display panel that does not need to be displayed, that is, charging the pixels with less power.
  • this partial display method still has redundant power consumption.
  • embodiments of the present disclosure provide an array substrate, a driving method thereof, and a display device to reduce power consumption of the display panel.
  • An embodiment of the present disclosure provides an array substrate, including: a plurality of gate lines, each of which drives a row of pixel units; a plurality of cascaded shift register units, configured to provide gates to the gate lines of the corresponding row A drive signal; and a control circuit, electrically connected between at least part of the shift register unit and the gate line of the corresponding row, the control circuit includes a plurality of control units, each control unit is configured to receive a control signal, And under the control of the control signal, the transmission path between the shift register unit and the gate line of the corresponding row is turned on or off.
  • the gate line includes a first gate line and a second gate line, wherein only the control unit is electrically connected between the first gate line and the corresponding shift register unit.
  • it further includes: a control line electrically connected to all control units electrically connected between the first gate line and the corresponding shift register unit; or, multiple control lines, The control units connected between the first gate line and the corresponding shift register unit are electrically connected in a one-to-one correspondence.
  • a control unit is electrically connected between each shift register unit and the gate line of the corresponding row.
  • it further includes a plurality of control lines, which are electrically connected to each of the control units in a one-to-one correspondence.
  • the gate line includes a first gate line and a second gate line
  • the array substrate further includes a plurality of control lines
  • the plurality of control lines includes a first control line and a second gate line.
  • Control line wherein the first control line is electrically connected to all control units electrically connected between the first gate line and the corresponding shift register unit, and the second control line is electrically connected to the All control units between the second gate line and the corresponding shift register unit are electrically connected.
  • the gate lines are divided into a plurality of gate line groups, and the array substrate further includes a plurality of control lines, wherein each of the control lines is electrically connected to each of the control lines.
  • control unit includes: a first switch transistor, the gate of the first switch transistor is electrically connected to receive the control signal, and the first electrode is connected to the gate drive signal of the shift register unit The output terminal of the is electrically connected, and the second pole is electrically connected to the gate line of the corresponding row.
  • each shift register unit of the plurality of shift register units includes: a second transistor, and the gate of the second switch transistor is electrically connected to the first electrode, and is electrically connected to receive activation Signal or the gate drive signal output by the shift register unit of the previous stage, the second pole is electrically connected to the gate of the third transistor; the third transistor, the first pole of the third transistor is electrically connected to receive the clock signal, the second The first electrode is electrically connected to the first electrode of the first transistor; the fourth transistor, the gate of the fourth transistor is electrically connected to receive the gate drive signal output by the shift register unit of the next stage, and the first electrode is electrically connected to the The second electrode of the second transistor is electrically connected to the power supply voltage; and the fifth transistor, the gate of the fifth transistor is electrically connected to the gate of the fourth transistor, and the first electrode is electrically connected to the third transistor The second pole is electrically connected to the power supply voltage.
  • an embodiment of the present disclosure further provides a display device, including the array substrate provided in the foregoing embodiment.
  • an embodiment of the present disclosure further provides a driving method of an array substrate, including:
  • a control signal of a first level is provided in the first period, and a control signal of a second level is provided in the second period.
  • FIG. 1 shows an example structure of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 shows an exemplary structure of an array substrate provided by an embodiment of the present disclosure
  • FIG. 3 shows an example structure of an array substrate provided by an embodiment of the present disclosure
  • FIG. 4 shows an exemplary structure of an array substrate provided by an embodiment of the present disclosure
  • FIG. 5 shows a schematic structural diagram of a display device provided by an embodiment of the present disclosure
  • FIG. 6 shows a flowchart of a driving method of an array substrate provided by an embodiment of the present disclosure
  • FIG. 7 shows an example timing diagram of the array substrate shown in FIG. 4;
  • FIG. 8 shows an example timing diagram of the array substrate shown in FIG. 4.
  • FIG. 9 shows an example timing chart of the array substrate shown in FIG. 4.
  • the term “electrically connected” may mean that two components are directly electrically connected, or may mean that two components are electrically connected via one or more other components. In addition, these two components can be electrically connected or coupled in a wired or wireless manner.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors, and may also be metal oxide semiconductor field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors.
  • the switching transistor may be an N-type transistor or a P-type transistor. Since the source and drain of the thin film transistor used here are symmetrical, the source and drain can be interchanged.
  • the gate of the transistor is called a control electrode, one of the source and drain is called a first electrode, and the other of the source and drain is called a second electrode.
  • first level and second level are only used to distinguish the two levels from being different in amplitude.
  • the "first level” may be a level that turns off the related transistor
  • the “second level” may be a level that turns on the related transistor.
  • the transistor is exemplified as an N-type thin film transistor
  • the "first level” is exemplified as a low level
  • the “second level” is exemplified as a high level.
  • the array substrate, its driving method, the display panel and the display device provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • the embodiments of the present disclosure are described for an array substrate in which pixel units are driven by a GOA (Gate Driver on Array) drive circuit. It is understandable that the provided example structure can be applied to other Driven array substrate.
  • GOA Gate Driver on Array
  • the array substrate provided by the embodiment of the present disclosure includes a display area and a non-display area surrounding the display area.
  • the display area includes multiple gate lines (G1, G2...Gn) and data lines (S1, S2, S3...) arranged perpendicular to the gate lines (G1, G2...Gn), and gate lines (G1, G2... ...Gn) and data lines (S1, S2, S3...) define a plurality of pixel units 200, the pixel units 200 are arranged in a matrix, and each gate line can drive a row of pixel units 200.
  • each pixel unit 200 may include a switching transistor T0, a storage capacitor Cst, and a liquid crystal capacitor Clc, but this is only an example.
  • the embodiment of the present disclosure does not limit the specific structure of the pixel unit 200, and other forms of pixel units may be used.
  • the non-display area includes a plurality of cascaded shift register units (GOA1, GOA2...GOAn).
  • Each shift register unit (GOA1, GOA2...GOAn) is configured to provide a gate drive signal to the gate line of the corresponding row.
  • the array substrate provided by the embodiment of the present disclosure further includes a control circuit 10, and the control circuit 10 is electrically connected between at least part of the shift register units and the gate lines of the corresponding row.
  • Each control circuit 10 includes a plurality of control units 100.
  • Each control unit 100 is configured to receive the control signal Con, and under the control of the control signal Con, turn on or cut off the transmission path between the shift register unit and the gate line of the corresponding row.
  • the control unit 100 is electrically connected only between a part of the shift register units (GOA1, GOA2...GOAn) and the corresponding gate lines (G1, G2...Gn). As shown in FIG. 1, in the first row of pixel units, one end of the control unit 100 is electrically connected to the output terminal G1' of the gate drive signal of the shift register unit GOA1, and the other end of the control unit 100 is electrically connected to the gate line G1. In the second row of pixel units, one end of the control unit 100 is electrically connected to the output end of the gate drive signal of the shift register unit GOA2 as G2', and the other end of the control unit 100 is electrically connected to the gate line G2.
  • No control unit 100 is arranged between the shift register units of the pixel units from the third row to the 20th row and the corresponding gate lines.
  • one end of the control unit 100 is electrically connected to the output terminal G21' of the gate drive signal of the shift register unit GOA21, and the other end of the control unit 100 is electrically connected to the gate line G21. And so on, up to the nth row of pixel units.
  • control unit 100 is electrically connected between all the shift register units (GOA1, GOA2...GOAn) and the corresponding gate lines (G1, G2...Gn), as shown in FIG. 2.
  • the control circuit 10 is provided between at least part of the shift register unit and the gate line of the corresponding row, so that when full-screen display is performed, all the shift register units can be connected to each other through a control signal.
  • the transmission path between the gate lines of the corresponding row realizes the progressive scanning of the gate lines; when performing partial display, the transmission path between the part of the shift register unit and the gate line of the corresponding row is cut off by the control signal, and only the transmission path is turned on. Setting the transmission path between part of the shift register unit of the control circuit 10 and the gate line of the corresponding row, so that when performing partial display, only the gate line corresponding to the partial display area is scanned, and the remaining row gate lines are not scanned. That is, only the pixel cells corresponding to the partial display area are charged and discharged, and the pixel cells corresponding to the remaining row gate lines are not charged and discharged, so as to reduce the power consumption caused by the charge and discharge of the pixel cells.
  • the power consumption of the shift register unit during operation is much smaller than the power consumption caused by pixel charging and discharging, so the solution of the embodiment of the present disclosure can reduce the power consumption of the array substrate .
  • the control unit 100 of the array substrate includes a first switch transistor T1, and the control unit 100 electrically connected between the first-stage shift register unit GOA1 and the gate line G1 is taken as an example to illustrate the first switch Connection relationship of transistor T1.
  • the gate of the first switching transistor T1 is electrically connected to receive the control signal Con
  • the first pole of T1 is electrically connected to the output terminal G1' of the gate signal driving signal of the shift register unit GOA1
  • the second pole of T1 is connected to the corresponding row
  • the gate line G1 is electrically connected.
  • each shift register unit (GOA1, GOA2...GOAn) of the array substrate includes a second switch transistor T2, a third switch transistor T3, a fourth switch transistor T4, and a fifth switch transistor T5.
  • GOA1 take the first-stage shift register unit GOA1 as an example to illustrate the connection relationship of each switch transistor.
  • the gate of the second switching transistor T2 is electrically connected to the first electrode, and is electrically connected to receive an input signal.
  • Start signal STV for other stages of shift register units (GOA2, GOA3...GOAn), this signal is the gate drive signal output by the previous stage of shift register units.
  • the second electrode of T2 and the gate of the third transistor are electrically connected to the first node Q1.
  • the first pole of the third switch transistor T3 is electrically connected to receive the clock signal CK, and the second pole of T3 is electrically connected to the first pole of the first transistor T1, that is, is connected to the gate drive signal output terminal G1' of the shift register unit .
  • the gate of the fourth switching transistor T4 and the gate of the fifth switching transistor T5 are both electrically connected to receive the gate drive signal output by the shift register unit GOA2 of the subsequent stage after the shift register unit GOA1 of the current stage, that is, the electrical connection To the output terminal G2' of the gate drive signal of the shift register unit GOA2 of the next stage.
  • the first pole of the fourth switch transistor T4 is electrically connected to the second pole of the second switch transistor T2, that is, the second poles of the first node Q1 and T4 are electrically connected to the power supply voltage VSS.
  • the first pole of the fifth switch transistor T5 is electrically connected to the second pole of the third transistor T3 to serve as the output terminal G1' of the gate drive signal of the shift register unit GOA1 of the present stage, and the second pole of T5 is electrically connected to the power supply voltage VSS .
  • the working process of the shift register unit includes that the second switching transistor T2 of the first stage shift register unit GOA1 is turned on under the control of the start signal STV applied to its gate, and the second stage The second switch transistor T2 of the shift register unit GOA2 is turned on under the control of the gate drive signal output by the first stage shift register unit GOA1 applied to its gate, and the second switch of the third stage shift register unit GOA2 The transistor T2 is turned on under the control of the gate drive signal output by the second stage shift register unit GOA2 applied to its gate, and so on, the gate drive signal of the n-1th stage shift register unit GOAn-1 is conductive The second switching transistor T2 of the n-th stage shift register unit GOAn is connected.
  • the output terminal G n'of the gate drive signal of the n-th stage shift register unit GOAn is electrically connected to the gate of the fourth switch transistor T4 and the fifth switch transistor T5 of the n-1th stage shift register unit GOAn-1
  • the potential of the first node Q1 of the -1 stage shift register unit GOAn-1 and the potential of the gate drive signal output terminal Gn-1' are reset.
  • the output terminal G 2'of the gate drive signal of the second-stage shift register unit GOA2 is electrically connected to the gate of the fourth switch transistor T4 and the gate of the fifth switch transistor T5 of the first-stage shift register unit GOA1. It resets the potential of the first node Q1 of the shift register unit GOA1 of the first stage and the potential of the gate drive signal output terminal G1'.
  • circuit structure of the shift register unit shown in FIGS. 3 and 4 is only an example, and the circuit structure of the shift register unit of the embodiment of the present disclosure is not limited to this, and any shift register unit can be used.
  • the gate lines included in the array substrate include a first gate line and a second gate line, wherein only the control unit is electrically connected between the first gate line and the corresponding shift register unit.
  • the cascaded shift register unit GOA3 to the shift register unit GOA20 and the gate lines (G3...G20) of the corresponding row.
  • the switching transistor T1, the shift register unit GOA1, the shift register unit GOA2, the shift register unit GOA21 to the shift register unit GOAn and the gate lines (G1, G2, G21...Gn) of the corresponding row are electrically connected with the first Switch transistor T1.
  • the gate lines (G1, G2, G21...Gn) are used as the first gate line, and the gate lines (G3...G20) are used as the second gate line.
  • the first gate lines (G1, G2, G21...Gn) and the output terminals (G1', G2', G21' of the gate drive signals of the corresponding shift register units (GOA1, GOA2, GOA21...GOAn) ...Gn') is electrically connected to the first switching transistor T1.
  • control line for providing control signals.
  • the control signal applied to the gate of the first switching transistor T1 corresponds to indicating different control lines.
  • a control line can be included in the non-display area of the array substrate, and the control line is electrically connected to the first gate line (G1, G2, G21...Gn) and the corresponding shift register unit (GOA1 , GOA2, GOA21...GOAn) and all control units between the output terminals (G1', G2', G21'...Gn') of the gate drive signal are electrically connected.
  • the same control signal Con applied to the gate of the first transistor T1 indicates that these control signals come from the same control line.
  • a low-level control signal Con can be applied to turn off the first switching transistor T1, thereby turning off the shift register unit (GOA1, The transmission path between GOA2, GOA21...GOAn) and the corresponding row of gate lines (G1, G2, G21...Gn). Therefore, the gate drive signal output by the shift register unit (GOA1, GOA2, GOA21...GOAn) cannot be input to the first gate line (G1, G2, G21...Gn) of the corresponding row, so the first gate line ( G1, G2, G21...Gn) to scan.
  • the first switch Transistor T1 Since there is no electrical connection between the output terminal (G3'...G20') of the gate drive signal from the shift register unit GOA3 to the shift register unit GOA20 and the gate line (G3...G20) of the corresponding row, the first switch Transistor T1, so the signal output from the gate drive signal output terminals (G3'...G20') of the shift register unit GOA3 to the shift register unit GOA20 can be normally input to the corresponding third row of gate lines G3 to 20 On the row gate line G20, the third row of the gate line G3 to the 20th row of the gate line G20 can be scanned.
  • a plurality of control lines may be included in the non-display area of the array substrate, and the plurality of control lines are electrically connected to the first gate lines (G1, G2, G21...Gn) and the corresponding shift register.
  • the control units of the output terminals (G1', G2', G21'...Gn') of the gate drive signals of the units (GOA1, GOA2, GOA21...GOAn) are electrically connected in a one-to-one correspondence.
  • control signal applied to the gate of the first transistor T1 of the pixel unit in the first row is Con1
  • control signal applied to the gate of the first transistor T1 of the pixel unit in the second row is Con2
  • control signal applied to the gate of the first transistor T1 of the pixel unit in the 21st row is Con21
  • the control signal applied to the gate of the first transistor T1 of the pixel unit in the nth row is Conn. Indicates that these control signals come from multiple different control lines.
  • FIG. 1 and FIG. 3 of the embodiment of the present disclosure only illustrate that the gate lines of the third row to the 20th row are scanned, and the gate lines of the remaining rows are not scanned.
  • the gate lines corresponding to the display area may be scanned according to the display needs.
  • the gate lines may not be scanned from the first row of gate lines to the specified row of gate lines, and from the next row to the last row of gate lines of the specified row.
  • Line scanning can also be performed from the first row of gate lines to the designated row of gate lines, and from the next row of the designated row of gate lines to the last row of gate lines without scanning. According to the embodiments of the present disclosure, it is possible to realize sub-regional display and reduce the power consumption of the display panel.
  • control unit 100 For the output terminals (G1', G2'...Gn') of the gate drive signal in each stage of the shift register unit (GOA1, GOA2...GOAn) and the corresponding row of gate lines (G1, G2...Gn)
  • the embodiments in which the control unit 100 is electrically connected to each other can also be used for flexible regional display by arranging different numbers of control lines.
  • a control line may be included in the non-display area of the array substrate, and the control line is electrically connected to the gate lines (G1, G2...Gn) and the corresponding shift register unit (GOA1). , GOA2...GOAn) and all control units between the output terminals (G1', G2'...Gn') of the gate drive signal are electrically connected.
  • the same control signal Con applied to the gate of the first transistor T1 indicates that these control signals come from the same control line.
  • the gate lines may be divided into first gate lines (G1, G2, G21...Gn) and second gate lines (G3...G20).
  • a plurality of control lines may be included in the non-display area of the array substrate, and the plurality of control lines include one first control line and one second control line.
  • the first control line is electrically connected to the first gate line (G1, G2, G21...Gn) and the output terminal (G1') of the gate drive signal of the corresponding shift register unit (GOA1, GOA2, GOA21...GOAn) , G2', G21'...Gn') all control units are electrically connected.
  • the second control line is electrically connected between the second gate line (G3...G20) and the output terminal (G3'...G20') of the gate drive signal of the corresponding shift register unit (GOA3...GOA20) All control units are electrically connected.
  • the same control signal Con1 applied to the gate of a part of the first transistor T1 indicates that these control signals come from the same first control line to apply the same control to the gate of another part of the first transistor T1
  • the signal Con2 indicates that these control signals come from the same first control line.
  • the gate lines in the display area may also be divided into multiple gate line groups, and multiple control lines may be included in the non-display area of the array substrate, wherein each of the multiple control lines is connected to the electrical The control unit between each gate line connected in each gate line group and the corresponding shift register unit is electrically connected.
  • a plurality of control lines may be included in the non-display area of the array substrate, and the plurality of control lines are electrically connected to the gate lines (G1, G2, G3...Gn) and the corresponding shift register units (GOA1, All the control units between the output terminals (G1', G2', G3'...Gn') of the gate drive signals of GOA2, GOA3...GOAn) are electrically connected in a one-to-one correspondence.
  • the embodiment not only can the number of control lines be reduced, it is beneficial to the narrow frame structure, and the manufacturing cost and manufacturing process of the control lines can be reduced, and the sub-region display can be realized more flexibly.
  • the process of sub-regional display of the array substrate according to each embodiment can be obtained with reference to the foregoing embodiment, and will not be repeated here.
  • a control circuit is arranged between at least part of the shift register unit and the gate line of the corresponding row to realize flexible sub-regional display.
  • the solution provided by the embodiment of the present disclosure does not affect the normal operation of the cascaded shift register. Since the power consumption of the shift register is much less than the power consumption generated by the pixel charging and discharging, the solution of the embodiment of the present disclosure can reduce The power consumption of the array substrate.
  • the array substrate provided by the embodiment of the present disclosure may be an array substrate of a liquid crystal display panel, or an array substrate of an organic light emitting display panel.
  • FIG. 5 shows a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the display device 500 may include a display panel 501.
  • the display panel 501 may be composed of any array substrate described in the foregoing embodiments.
  • the display device 500 according to the embodiment of the present disclosure may be any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc.
  • FIG. 6 shows a flowchart of a driving method of an array substrate provided by an embodiment of the present disclosure. As shown in FIG. 6, the driving method 600 includes:
  • step S601 in the first operating mode, the transmission paths between all the shift register units and all the gate lines are turned on.
  • the first working mode is a full-screen display mode.
  • step S602 in the second operating mode, only the transmission paths between part of the shift register units and the gate lines of the corresponding row are turned on.
  • the second working mode is a sub-regional display mode.
  • a first level control signal such as a low level control signal
  • a second level control signal can be provided in the second period to turn on the transmission path between the shift register unit and the gate line of the corresponding row.
  • FIG. 4 is the input and output timing diagram corresponding to Figure 4, applying a high level to the gate of the second transistor T2 of the first stage shift register unit GOA1
  • the signal STV and the control signal Con start to input a high-level signal until it scans to the last row of gate line Gn.
  • the signal of the control signal Con is always a high-level signal.
  • the specific working process of the cascaded shift register units at all levels is:
  • the second switching transistor T2 is turned on, and the first node Q1 starts to charge, thereby turning on the third switching transistor T3.
  • the output terminal G1' of the gate drive signal outputs a high level signal
  • the first switching transistor T1 is turned on under the control of the high level control signal Con, and the output terminal of the gate drive signal
  • the high level signal output by G1' controls the charging of the liquid crystal capacitor Clc of the pixel unit in the first row.
  • the second-stage shift register unit GOA2 the high-level gate drive signal output by the first-stage shift register unit GOA1 turns on the second switching transistor T2, and the first node Q1 starts charging, thereby turning on the third switching transistor T3.
  • the gate drive signal output terminal G2' When the clock signal CK is at a high level, the gate drive signal output terminal G2' outputs a high level signal, the first switching transistor T1 is turned on under the control of the high level control signal terminal Con, and the gate drive signal is output
  • the high-level signal output from the terminal G2' controls the charging of the liquid crystal capacitors of the second row of pixel units.
  • the high-level signal output from the output terminal G2' of the gate drive signal controls the fourth switching transistor T4 and the fifth switching transistor T5 of the first-stage shift register unit GOA1 to turn on, and the first-stage shift register unit GOA1
  • the output terminal G1' of the gate drive signal of the first-stage shift register unit GOA1 of a node Q1 is pulled low, and the liquid crystal capacitor of the first row of pixel units is charged.
  • Embodiment 1 No scanning is performed from the first row to the n-2th row of the gate lines, and the scanning starts from the n-1th row of the gate lines to the end of the nth row of gate lines, as shown in FIG. 4 and FIG. 8, FIG.
  • the high-level start signal STV is applied to the gate of the second transistor T2 of the first-stage shift register unit GOA1, and the control signal Con starts as a low-level signal .
  • the first switching transistors T1 corresponding to the gate lines (G1...Gn-2) from the first row to the n-2th row are all turned off under the control of the low level signal of the control signal Con, until the scan reaches the n-2th
  • the control signal Con is always a low-level signal.
  • the control signal Con is a high-level signal.
  • the specific working process of the cascaded shift register units at various levels can be similar to the working process in full-screen display, except that the first switching transistor T1 corresponding to the gate line from the first row to the n-2th row is in the off state.
  • the signals output from the gate drive signal output terminals of the first-stage shift register unit GOA1 to the n-2th stage shift register unit GOAn-2 cannot be transmitted to the gate lines from the first row to the n-2th row, so the first The gate lines of the row to the n-2th row are not scanned, and the first switching transistor T1 corresponding to the gate line of the n-1th row to the nth row is in a conducting state, and the shift register unit GOA n-1 of the n-1th stage
  • the signal output from the output terminal of the gate drive signal to the n-th stage shift register unit GOAn can be transmitted to the gate line from the n-1th row to the nth row through the first switching transistor T1, so the n-1th row to the nth row
  • Embodiment 2 Scanning the gate lines from the first to n-2th rows, and not scanning the gate lines from the n-1th row to the nth row, as shown in Fig. 4 and Fig. 9, and Fig. 9 is Fig. 4
  • a high-level start signal STV is applied to the gate of the second transistor T2 of the first-stage shift register unit GOA1, and the control signal terminal Con starts as a high-level signal.
  • the first switching transistors T1 corresponding to the gate lines (G1...Gn-2) from row 1 to row n-2 are all turned on under the control of the low level signal of the control signal Con, until the gate lines of the n-2th row are scanned
  • the control signal Con is always a high-level signal.
  • the control signal Con is a low-level signal.
  • the specific working process of the cascaded shift register units at all levels can be similar to the working process in full-screen display, except that the first switching transistor T1 corresponding to the gate line of the first row to the n-2th row is in the conductive state.
  • the signals output from the output terminals of the gate drive signals of the first stage shift register unit GOA1 to the n-2th stage shift register unit GOAn-2 are transmitted to the first row to the n-2th row gate through the first switching transistor T1 Therefore, the gate lines from the first row to the n-2th row are scanned, and the first switching transistor T1 corresponding to the gate line from the n-1th row to the nth row is in the off state, and the n-1th stage shift register
  • the signals output from the output terminals of the gate drive signals of the unit GOA n-1 to the nth stage shift register unit GOAn cannot be transmitted to the gate lines from the n-1th row to the nth row.
  • the row grid lines are scanned to realize sub-regional display and reduce display power consumption.
  • the input and output timing diagrams provided in FIGS. 5 to 7 are only a few examples listed in the present disclosure. In actual display, the input and output timings can be designed according to display needs to realize sub-regional display.
  • 10 control lines can be set correspondingly, and the control unit corresponding to each gate line in each gate line group is the same as that of the same one.
  • the control line is electrically connected.
  • all control lines input high-level signals to control all transistors to be turned on to achieve full-screen display.
  • the first switch transistors corresponding to the group of gate lines are all turned on under the control of a high-level signal input from a corresponding control line.
  • the first switch transistors corresponding to the remaining groups of gate lines are all turned off under the control of the low-level signal input from the control line, so as to realize sub-regional display.
  • the grid lines in the area to be displayed correspond to two adjacent groups of grid lines, and there are only part of the grid lines in the area to be displayed in the adjacent two groups of grid line groups, it is necessary for these two groups of grid line groups to correspond All the first switch transistors of the first switch transistors are turned on under the control of the high-level signal input from the corresponding control line, and the first switch transistors corresponding to the remaining groups of gate lines are all turned off under the control of the low-level signal input from the control line , To achieve sub-regional display.
  • the control circuit is provided between the output terminal of the gate driving signal of at least part of the shift register unit and the gate line of the corresponding row, so that the control circuit is The included control unit is all turned on under the control of the control signal, thereby turning on the transmission path between the shift register unit and the gate line of the corresponding row to realize the progressive scanning of the gate line; when performing partial display, the control circuit The included control unit is partially turned on or off under the control of the control signal to partially turn on or cut off the transmission path between the shift register unit and the gate line of the corresponding row, so that when performing partial display, only The gate lines corresponding to the partial display area are scanned, while the remaining rows of gate lines are not scanned, that is, only the pixels corresponding to the partial display areas are charged and discharged, and the pixels corresponding to the remaining rows of gate lines are not charged and discharged.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种阵列基板、其驱动方法及显示装置，阵列基板包括多条栅线（G1、G2……Gn），每条栅线（G1、G2……Gn）驱动一行像素单元（200）；级联的多个移位寄存器单元（GOA1、GOA2……GOAn），配置为向对应行的栅线（G1、G2……Gn）提供栅极驱动信号；和控制电路（10），电连接在至少部分移位寄存器单元（GOA1、GOA2……GOAn）与对应行的栅线（G1、G2……Gn）之间，控制电路（10）包括多个控制单元（100），每个控制单元（100）被配置为接收控制信号（Con），并在控制信号（Con）的控制下，导通或切断移位寄存器单元（GOA1、GOA2……GOAn）与对应行的栅线（G1、G2……Gn）之间的传输路径。

Description

阵列基板、其驱动方法及显示装置
本申请要求于2019年4月22日提交的、申请号为201910321515.4的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、其驱动方法及显示装置。
背景技术
随着显示技术的普及与应用，对高分辨率显示面板的需求随之增加。而随着显示面板分辨率的增加，其功耗也会增大。可以通过局部显示的方式来降低功耗。例如，可以通过在显示面板不需要显示的部分显示黑画面，即给像素充入较少的电量来降低功耗。但是由于显示面板的点亮功耗主要体现在像素的充放电上，这种局部显示的方法依然存在功耗的冗余浪费。
发明内容
有鉴于此，本公开实施例提供一种阵列基板、其驱动方法及显示装置，用以降低显示面板的功耗。
本公开实施例提供了一种阵列基板，包括：多条栅线，每条栅线驱动一行像素单元；级联的多个移位寄存器单元，配置为向对应行的所述栅线提供栅极驱动信号；和控制电路，电连接在至少部分所述移位寄存器单元与对应行的所述栅线之间，所述控制电路包括多个控制单元，每个控制单元被配置为接收控制信号，并在所述控制信号的控制下，导通或切断所述移位寄存器单元与对应行的所述栅线之间的传输路径。
在一些实施例中，所述栅线包括第一栅线和第二栅线，其中仅在所述第一栅线与对应的所述移位寄存器单元之间电连接所述控制单元。
在一些实施例中，还包括：一条控制线，与电连接在所述第一栅线与对应的所述移位寄存器单元之间的所有控制单元电连接；或者，多条控制线，与电连接在所述第一栅线与对应的所述移位寄存器单元之间的控制单元一一对应电连接。
在一些实施例中，在每个所述移位寄存器单元与对应行的所述栅线之间电连接一所 述控制单元。
在一些实施例中，还包括多条控制线，与每个所述控制单元一一对应电连接。
在一些实施例中，其中，所述栅线包括第一栅线和第二栅线，所述阵列基板还包括多条控制线，所述多条控制线包括一条第一控制线和一条第二控制线，其中所述第一控制线与电连接在所述第一栅线与对应的所述移位寄存器单元之间的所有控制单元电连接，所述第二控制线与电连接在所述第二栅线与对应的所述移位寄存器单元之间的所有控制单元电连接。
在一些实施例中，所述栅线分为多个栅线组，所述阵列基板还包括多条控制线，其中所述多条控制线中的每条控制线与电连接在每个所述栅线组中的各条栅线与对应的所述移位寄存器单元之间的控制单元。
在一些实施例中，所述控制单元包括：第一开关晶体管，所述第一开关晶体管的栅极电连接为接收所述控制信号，第一极与所述移位寄存器单元的栅极驱动信号的输出端电连接，第二极与对应行的所述栅线电连接。
在一些实施例中，所述多个移位寄存器单元中的每个移位寄存器单元包括：第二晶体管，所述第二开关晶体管的栅极与第一极电连接，并电连接为接收启动信号或前一级移位寄存器单元输出的栅极驱动信号，第二极电连接第三晶体管的栅极；第三晶体管，所述第三晶体管的第一极电连接为接收时钟信号，第二极电连接所述第一晶体管的第一极；第四晶体管，所述第四晶体管的栅极电连接为接收后一级移位寄存器单元输出的栅极驱动信号，第一极电连接所述第二晶体管的第二极，第二极电连接电源电压；和第五晶体管，所述第五晶体管的栅极电连接所述第四晶体管的栅极，第一极电连接所述第三晶体管的第二极，第二极电连接所述电源电压。
根据本公开的另一方面，本公开实施例还提供了一种显示装置，包括上述实施例提供的阵列基板。
根据本公开的另一方面，本公开实施例还提供了一种阵列基板的驱动方法，包括：
在第一工作模式下，导通全部所述移位寄存器单元与全部所述栅线之间的传输路径；
在第二工作模式下，仅导通部分所述移位寄存器单元与对应行的所述栅线之间的传输路径。
在一些实施例中，在所述第二工作模式下，在第一时段提供第一电平的控制信号，在第二时段提供第二电平的控制信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，图中：
图1示出了本公开实施例提供的阵列基板的示例结构；
图2示出了本公开实施例提供的阵列基板的示例结构；
图3示出了本公开实施例提供的阵列基板的示例结构；
图4示出了本公开实施例提供的阵列基板的示例结构；
图5示出了本公开实施例提供的显示装置的结构示意图；
图6示出了本公开实施例提供的阵列基板的驱动方法的流程图；
图7示出了图4所示的阵列基板的示例时序图；
图8示出了图4所示的阵列基板的示例时序图；以及
图9示出了图4所示的阵列基板的示例时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下获得的所有其他实施例都属于本公开保护的范围。应注意，贯穿附图，相同的元素由相同或相近的附图标记来表示。在以下描述中，一些具体实施例仅用于描述目的，而不应该理解为对本公开有任何限制，而只是本公开实施例的示例。在可能导致对本公开的理解造成混淆时，将省略常规结构或构造。应注意，图中各部件的形状和尺寸不反映真实大小和比例，而仅示意本公开实施例的内容。
除非另外定义，本公开实施例使用的技术术语或科学术语应当是本领域技术人员所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似词语并不表示任何顺序、数量或重要性，而只是用于区分不同的组成部分。
此外，在本公开实施例的描述中，术语“电连接”可以是指两个组件直接电连接， 也可以是指两个组件之间经由一个或多个其他组件电连接。此外，这两个组件可以通过有线或无线方式电连接或耦接。
本公开实施例中采用的晶体管均可以为薄膜晶体管或场效应管，也可以是金属氧化物半导体场效应管或其他特性相同的器件。根据在电路中的作用，本公开实施例使用的晶体管主要为开关晶体管。开关晶体管可以时N型晶体管，也可以是P型晶体管。由于这里采用的薄膜晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开实施例中，将晶体管的栅极称为控制极，将源极和漏极中的一个称为第一极，将源极和漏极中的另一个称为第二极。
此外，在本公开实施例的描述中，术语“第一电平”和“第二电平”仅用于区别两个电平的幅度不同。在一些实施例中，“第一电平”可以是使相关晶体管关断的电平，“第二电平”可以是使相关晶体管导通的电平。例如，当晶体管被示例为N型薄膜晶体管时，“第一电平”被示例为低电平，“第二电平”被示例为高电平。
下面结合附图，对本公开实施例提供的阵列基板、其驱动方法、显示面板及显示装置进行详细说明。在下面的示例中，针对以GOA(Gate Driver on Array，阵列基板行驱动)驱动电路对像素单元进行驱动的阵列基板来阐述本公开的实施例，可以理解，所提供的示例结构可以应用于其他驱动方式的阵列基板。
如图1和图2所示，本公开实施例提供的阵列基板包括显示区域和包围显示区域的非显示区域。显示区域包括多条栅线(G1、G2……Gn)和与栅线(G1、G2……Gn)垂直交叉设置的数据线(S1、S2、S3……)，栅线(G1、G2……Gn)和数据线(S1、S2、S3……)限定出多个像素单元200，像素单元200排列成矩阵，每条栅线可以驱动一行像素单元200。如图1和图2所示，每个像素单元200可以包括开关晶体管T0、存储电容Cst和液晶电容Clc，但这仅为示例。本公开实施例对像素单元200的具体结构不做限定，可以采用其他形式的像素单元。非显示区域包括级联的多个移位寄存器单元(GOA1、GOA2……GOAn)。每个移位寄存器单元(GOA1、GOA2……GOAn)配置为向对应行的所述栅线提供栅极驱动信号。
如图1和图2所示，本公开实施例提供的阵列基板还包括控制电路10，控制电路10电连接在至少部分移位寄存器单元与对应行的栅线之间。每个控制电路10包括多个控制单元100。每个控制单元100被配置为接收控制信号Con，并在控制信号Con的控制下，导通或切断移位寄存器单元与对应行的栅线之间的传输路径。
在一些实施例中，仅在一部分移位寄存器单元(GOA1、GOA2……GOAn)与对应的栅线(G1、G2……Gn)之间电连接有控制单元100。如图1所示，在第1行像素单元中，控制单元100的一端电连接移位寄存器单元GOA1的栅极驱动信号的输出端G1’，控制单元100的另一端电连接栅线G1。在第2行像素单元中，控制单元100的一端电连接移位寄存器单元GOA2的栅极驱动信号的输出端为G2’，控制单元100的另一端电连接栅线G2。第3行像素单元至第20行像素单元的移位寄存器单元与对应的栅线之间没有布置控制单元100。在第21行像素单元中，控制单元100的一端电连接移位寄存器单元GOA21的栅极驱动信号的输出端G21’，控制单元100的另一端电连接栅线G21。以此类推，直至第n行像素单元。
在一些实施例中，在全部移位寄存器单元(GOA1、GOA2……GOAn)与对应的栅线(G1、G2……Gn)之间均电连接有控制单元100，如图2所示。
本公开实施例提供的阵列基板，通过在至少部分移位寄存器单元与对应行的栅线之间设置控制电路10，由此可以在进行全屏显示时，通过控制信号导通全部移位寄存器单元与对应行的栅线之间的传输路径，实现栅线的逐行扫描；在进行局部显示时，通过控制信号切断部分移位寄存器单元与对应行的栅线之间的传输路径，仅导通未设置控制电路10的部分移位寄存器单元与对应行的栅线之间的传输路径，从而在进行局部显示时，仅对局部显示区域对应的栅线进行扫描，而其余行栅线不进行扫描，即仅对局部显示区域对应的像素单元进行充放电，而其余行栅线对应的像素单元不进行充放电，以降低由于像素单元的充放电而导致的功耗。
并且，虽然级联的移位寄存器单元仍然正常工作，但由于移位寄存器单元工作时的功耗远小于像素充放电所导致的功耗，因此本公开实施例的方案可以降低阵列基板的功耗。
图3和图4示出了本公开实施例提供的阵列基板的其他示例结构。如图3和图4所示，阵列基板的控制单元100包括第一开关晶体管T1，并以第一级移位寄存器单元GOA1与栅线G1之间电连接的控制单元100为例说明第一开关晶体管T1的连接关系。第一开关晶体管T1的栅极电连接为接收控制信号Con，T1的第一极与移位寄存器单元GOA1的栅极信号驱动信号的输出端G1’电连接，T1的第二极与对应行的栅线G1电连接。
如图3和图4所示，阵列基板的每个移位寄存器单元(GOA1、GOA2……GOAn)包括第二开关晶体管T2、第三开关晶体管T3、第四开关晶体管T4和第五开关晶体管 T5，并以第一级移位寄存器单元GOA1为例说明各个开关晶体管的连接关系。
如图3和图4所示，第二开关晶体管T2的栅极和第一极电连接，并电连接为接收输入信号。启动信号STV；对于其他级移位寄存器单元(GOA2、GOA3……GOAn)，该信号为前一级移位寄存器单元输出的栅极驱动信号。T2的第二极与第三晶体管的栅极电连接于第一节点Q1。
第三开关晶体管T3的第一极电连接为接收时钟信号CK，T3的第二极电连接第一晶体管T1的第一极，即与移位寄存器单元的栅极驱动信号的输出端G1’相连。
第四开关晶体管T4的栅极和第五开关晶体管T5的栅极均电连接为接收位于本级移位寄存器单元GOA1之后的后一级移位寄存器单元GOA2输出的栅极驱动信号，即电连接到后一级移位寄存器单元GOA2的栅极驱动信号的输出端G2’。第四开关晶体管T4的第一极电连接第二开关晶体管T2的第二极，即第一节点Q1，T4的第二极电连接电源电压VSS。第五开关晶体管T5的第一极电连接第三晶体管T3的第二极，以作为本级移位寄存器单元GOA1的栅极驱动信号的输出端G1’，T5的第二极电连接电源电压VSS。
移位寄存器单元(GOA1、GOA2……GOAn)的工作过程包括，第一级移位寄存器单元GOA1的第二开关晶体管T2在施加到其栅极的启动信号STV的控制下导通，第二级移位寄存器单元GOA2的第二开关晶体管T2在施加到其栅极的第一级移位寄存器单元GOA1输出的栅极驱动信号的控制下导通，第三级移位寄存器单元GOA2的第二开关晶体管T2在施加到其栅极的第二级移位寄存器单元GOA2输出的栅极驱动信号的控制下导通，依次类推，第n-1级移位寄存器单元GOAn-1的栅极驱动信号导通第n级移位寄存器单元GOAn的第二开关晶体管T2。并且第n级移位寄存器单元GOAn的栅极驱动信号的输出端G n’电连接至第n-1级移位寄存器单元GOAn-1的第四开关晶体管T4的栅极和第五开关晶体管T5的栅极，以使电源电压VSS的低电平信号输出至第n-1级移位寄存器单元GOAn-1的第一节点Q1和栅极驱动信号的输出端Gn-1’，以对第n-1级移位寄存器单元GOAn-1的第一节点Q1的电位和栅极驱动信号的输出端Gn-1’的电位进行复位。依次类推，第2级移位寄存器单元GOA2的栅极驱动信号的输出端G 2’电连接至第1级移位寄存器单元GOA1的第四开关晶体管T4的栅极和第五开关晶体管T5的栅极，以对第1级移位寄存器单元GOA1的第一节点Q1的电位和栅极驱动信号的输出端G1’的电位进行复位。
需要说明的是，图3和图4所示的移位寄存器单元的电路结构仅为示例，本公开的实施例的移位寄存器单元的电路结构不限于此，可以使用任何能够实现移位寄存器单元正常的输入输出功能的结构。
根据实施例，阵列基板所包括的栅线包括第一栅线和第二栅线，其中仅在第一栅线与对应的移位寄存器单元之间电连接控制单元。如图3所示，在所示的n行像素单元中，在级联的移位寄存器单元GOA3到移位寄存器单元GOA20与对应行的栅线(G3……G20)之间未电连接第一开关晶体管T1，移位寄存器单元GOA1、移位寄存器单元GOA2、移位寄存器单元GOA21到移位寄存器单元GOAn与对应行的栅线(G1、G2、G21……Gn)之间电连接有第一开关晶体管T1。其中，以栅线(G1、G2、G21……Gn)作为第一栅线，以栅线(G3……G20)作为第二栅线。其中仅第一栅线(G1、G2、G21……Gn)与对应的移位寄存器单元(GOA1、GOA2、GOA21……GOAn)的栅极驱动信号的输出端(G1’、G2’、G21’……Gn’)之间电连接第一开关晶体管T1。
并且，在阵列基板的非显示区域中，还可以至少一条用于提供控制信号的控制线。在下面的示例中，以施加到第一开关晶体管T1的栅极的控制信号对应指示不同的控制线。
如图1所示，可以在阵列基板的非显示区域中包括一条控制线，该控制线与电连接在第一栅线(G1、G2、G21……Gn)与对应的移位寄存器单元(GOA1、GOA2、GOA21……GOAn)的栅极驱动信号的输出端(G1’、G2’、G21’……Gn’)之间的所有控制单元电连接。在图1中，以施加到第一晶体管T1的栅极的相同的控制信号Con表示这些控制信号来自一条相同的控制线。
这样当显示区域仅需要扫描第3行栅线G3到第20行栅线G20时，可以施加低电平的控制信号Con，以关断第一开关晶体管T1，从而切断移位寄存器单元(GOA1、GOA2、GOA21……GOAn)与对应行的栅线(G1、G2、G21……Gn)之间的传输路径。因此移位寄存器单元(GOA1、GOA2、GOA21……GOAn)输出的栅极驱动信号不能输入到与其对应行的第一栅线(G1、G2、G21……Gn)，从而不对第一栅线(G1、G2、G21……Gn)进行扫描。由于在从移位寄存器单元GOA3到移位寄存器单元GOA20的栅极驱动信号的输出端(G3’……G20’)与对应行的栅线(G3……G20)之间没有电连接第一开关晶体管T1，因此移位寄存器单元GOA3到移位寄存器单元GOA20的栅极驱动信号的输出端(G3’……G20’)输出的信号可以正常输入到与其对应的第3行栅线G3到第 20行栅线G20上，从而可以对第3行栅线G3到第20行栅线G20进行扫描。
如图3所示，可以在阵列基板的非显示区域中包括多条控制线，该多条控制线与电连接在第一栅线(G1、G2、G21……Gn)与对应的移位寄存器单元(GOA1、GOA2、GOA21……GOAn)的栅极驱动信号的输出端(G1’、G2’、G21’……Gn’)之间的控制单元一一对应电连接。在图3中，施加到第1行像素单元的第一晶体管T1的栅极的控制信号为Con1，施加到第2行像素单元的第一晶体管T1的栅极的控制信号为Con2，以此类推，施加到第21行像素单元的第一晶体管T1的栅极的控制信号为Con21，施加到第n行像素单元的第一晶体管T1的栅极的控制信号为Conn。表示这些控制信号来自多条不同的控制线。
另外，需要说明的是，本公开实施例的图1和图3仅是举例说明第3行到第20行栅线进行扫描，其余行栅线不进行扫描。然而在其他实施例中，可以根据显示需要对待显示区域对应的栅线进行扫描，例如可以从第1行栅线到指定行栅线不进行扫描、从指定行栅线的下一行到最后一行栅线进行扫描，还可以是从第1行栅线到指定行栅线进行扫描、从指定行栅线的下一行到最后一行栅线不进行扫描。根据本公开的实施例，可以实现分区域显示，降低显示面板的功耗。
对于在每一级移位寄存器单元(GOA1、GOA2……GOAn)的栅极驱动信号的输出端(G1’、G2’……Gn’)与对应行的栅线(G1、G2……Gn)之间均电连接有控制单元100的实施例，也可以通过布置不同数量的控制线来进行灵活的分区域显示。
根据实施例，如图2所示，可以在阵列基板的非显示区域中包括一条控制线，该控制线与电连接在栅线(G1、G2……Gn)与对应的移位寄存器单元(GOA1、GOA2……GOAn)的栅极驱动信号的输出端(G1’、G2’……Gn’)之间的所有控制单元电连接。在图2中，以施加到第一晶体管T1的栅极的相同的控制信号Con表示这些控制信号来自一条相同的控制线。
根据实施例，如图4所示，可以将栅线划分为第一栅线(G1、G2、G21……Gn)和第二栅线(G3……G20)。可以在阵列基板的非显示区域中包括多条控制线，该多条控制线包括一条第一控制线和一条第二控制线。第一控制线与电连接在第一栅线(G1、G2、G21……Gn)与对应的移位寄存器单元(GOA1、GOA2、GOA21……GOAn)的栅极驱动信号的输出端(G1’、G2’、G21’……Gn’)之间的所有控制单元电连接。第二控制线与电连接在第二栅线(G3……G20)与对应的移位寄存器单元(GOA3…… GOA20)的栅极驱动信号的输出端(G3’……G20’)与之间的所有控制单元电连接。在图4中，以施加到一部分第一晶体管T1的栅极的相同的控制信号Con1表示这些控制信号来自相同的第一控制线，以施加到另一部分第一晶体管T1的栅极的相同的控制信号Con2表示这些控制信号来自相同的第一控制线。
根据实施例，也可以将显示区域中的栅线划分为多个栅线组，并且可以在阵列基板的非显示区域中包括多条控制线，其中多条控制线中的每条控制线与电连接在每个栅线组中的各条栅线与对应的移位寄存器单元之间的控制单元电连接。
根据实施例，可以在阵列基板的非显示区域中包括多条控制线，该多条控制线与电连接在栅线(G1、G2、G3……Gn)与对应的移位寄存器单元(GOA1、GOA2、GOA3……GOAn)的栅极驱动信号的输出端(G1’、G2’、G3’……Gn’)之间的所有控制单元一一对应电连接。
根据实施例，不仅可以减少控制线的数量，有利于窄边框结构，降低控制线的制作成本及制作工艺，还能够更加灵活地实现分区域显示。根据各实施例的阵列基板的分区域显示的过程可以参考前述实施例获得，此处不再赘述。
本公开实施例提供的阵列基板通过在至少部分移位寄存器单元与对应行的栅线之间设置控制电路来实现灵活的分区域显示。在进行局部显示时，仅对局部显示区域对应的栅线进行扫描，而其余行栅线不进行扫描，即仅对局部显示区域对应的像素进行充放电，而其余行栅线对应的像素不进行充放电，并且本公开实施例提供的方案不影响级联的移位寄存器的正常工作，由于移位寄存器工作的功耗远小于像素充放电产生的功耗，因此本公开实施例的方案可以降低阵列基板的功耗。
具体实施时，本公开实施例提供的阵列基板可以是液晶显示面板的阵列基板，也可以是有机发光显示面板的阵列基板。
图5示出了本公开实施例提供的显示装置的结构示意图。如图5所示，根据本公开实施例的显示装置500可以包括显示面板501。显示面板501可以由前述实施例所述的任何阵列基板构成。根据本公开实施例的显示装置500可以是电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图6示出了本公开实施例提供的阵列基板的驱动方法的流程图。如图6所示，驱动方法600包括：
在步骤S601中，在第一工作模式下，导通全部移位寄存器单元与全部栅线之间的 传输路径。第一工作模式为全屏显示模式。
在步骤S602中，在第二工作模式下，仅导通部分移位寄存器单元与对应行的栅线之间的传输路径。第二工作模式为分区域显示模式。
针对图4所示的阵列基板，在第二工作模式下，可以在第一时段提供第一电平的控制信号，例如低电平的控制信号，以切断移位寄存器单元与对应行的栅线之间的传输路径。可以在第二时段提供第二电平的控制信号，例如高电平的控制信号，以导通移位寄存器单元与对应行的栅线之间的传输路径。
下面结合图4所示的阵列基板中的移位寄存器单元的工作原理对液晶显示面板的全屏显示和分区域显示的显示原理进行详细说明，输入输出时序图如图7至图9所示。
(1)全屏显示：如图4和图7所示，图5为图4对应的输入输出时序图，在第一级移位寄存器单元GOA1的第二晶体管T2的栅极施加高电平的启动信号STV，控制信号Con开始输入高电平信号，直至扫描至最后一行栅线Gn，控制信号Con的信号一直为高电平信号，级联的各级移位寄存器单元的具体工作过程为：
第一级移位寄存器单元GOA1，由于STV为高电平信号，因此第二开关晶体管T2导通，第一节点Q1开始充电，由此导通第三开关晶体管T3。当时钟信号CK为高电平时，栅极驱动信号的输出端G1’输出高电平信号，第一开关晶体管T1在高电平的控制信号Con的控制下导通，栅极驱动信号的输出端G1’输出的高电平信号控制第1行像素单元的液晶电容Clc充电。
第二级移位寄存器单元GOA2，第一级移位寄存器单元GOA1输出的高电平的栅极驱动信号导通第二开关晶体管T2，第一节点Q1开始充电，由此导通第三开关晶体管T3。当时钟信号CK为高电平时，栅极驱动信号的输出端G2’输出高电平信号，第一开关晶体管T1在高电平的控制信号端Con的控制下导通，栅极驱动信号的输出端G2’输出的高电平信号控制第2行像素单元的液晶电容充电。同时栅极驱动信号的输出端G2’输出的高电平信号控制第一级移位寄存器单元GOA1的第四开关晶体管T4和第五开关晶体管T5导通，第一级移位寄存器单元GOA1的第一节点Q1第一级移位寄存器单元GOA1的栅极驱动信号的输出端G1’被拉低，第一行像素单元的液晶电容充电完成。
依此类推，直至最后一行像素单元的液晶电容充电完成。对于不同的阵列基板的结构，只需要将设置有第一晶体管T1的像素单元行中移位寄存器单元与对应行的栅线之 间的传输路径均导通，就可以进行正常的全屏显示。
(2)分区域显示，以两个实施例为例进行介绍：
实施例一：从第1行至第n-2行栅线不进行扫描，从第n-1行栅线开始扫描至第n行栅线扫描结束，如图4和图8所示，图8为图4对应的分区域显示的输入输出时序图，在第一级移位寄存器单元GOA1的第二晶体管T2的栅极施加高电平的启动信号STV，控制信号Con开始时为低电平信号，第1行至第n-2行栅线(G1……Gn-2)对应的第一开关晶体管T1在控制信号Con的低电平信号的控制下均关断，直至扫描至第n-2行栅线Gn-2时，控制信号Con一直为低电平信号，从第n-1行栅线Gn-1开始至最后一行Gn，控制信号Con为高电平信号。级联的各级移位寄存器单元的具体工作过程可以与全屏显示时的工作过程相似，不同之处在于第1行至第n-2行栅线对应的第一开关晶体管T1处于关断状态，第1级移位寄存器单元GOA1至第n-2级移位寄存器单元GOAn-2的栅极驱动信号的输出端输出的信号不能传输至第1行至第n-2行栅线，因此第1行至第n-2行栅线不进行扫描，而第n-1行至第n行栅线对应的第一开关晶体管T1处于导通状态，第n-1级移位寄存器单元GOA n-1至第n级移位寄存器单元GOAn的栅极驱动信号的输出端输出的信号可以通过第一开关晶体管T1传输至第n-1行至第n行栅线，因此第n-1行至第n行栅线进行扫描，从而实现分区域显示，降低显示功耗。
实施例二：对第1至第n-2行栅线进行扫描，对第n-1行栅线至第n行栅线不进行扫描，如图4和图9所示，图9为图4对应的分区域显示的输入输出时序图，在第一级移位寄存器单元GOA1的第二晶体管T2的栅极施加高电平的启动信号STV，控制信号端Con开始时为高电平信号，第1行至第n-2行栅线(G1……Gn-2)对应的第一开关晶体管T1在控制信号Con的低电平信号的控制下均导通，直至扫描至第n-2行栅线Gn-2时，控制信号Con一直为高电平信号，从第n-1行栅线Gn-1开始至最后一行Gn，控制信号Con为低电平信号。级联的各级移位寄存器单元的具体工作过程可以与全屏显示时的工作过程相似，不同之处在于第1行至第n-2行栅线对应的第一开关晶体管T1处于导通状态，第1级移位寄存器单元GOA1至第n-2级移位寄存器单元GOAn-2的栅极驱动信号的输出端输出的信号通过第一开关晶体管T1传输至第1行至第n-2行栅线，因此对第1行至第n-2行栅线进行扫描，而第n-1行至第n行栅线对应的第一开关晶体管T1处于关断状态，第n-1级移位寄存器单元GOA n-1至第n级移位寄存器单元GOAn的栅极驱动信号的输出端输出的信号不能传输至第n-1行至第n行栅线，因此不对第n-1 行至第n行栅线进行扫描，从而实现分区域显示，降低显示功耗。
图5至图7所提供的输入输出时序图仅是本公开列举的其中几个示例，实际显示时，可以根据显示需要设计输入输出时序来实现分区域显示。
例如，当将显示区域中的n行栅线均等分为10个栅线组时，可以对应地设置10条控制线，每个栅线组中的各栅线对应的控制单元均与相同的一条控制线电连接。这样在进行全屏显示时，所有控制线均输入高电平信号，控制所有晶体管导通，实现全屏显示。在进行分区域显示时，假设待显示区域正好与其中一组栅线对应，则该组栅线对应的第一开关晶体管在对应的一条控制线输入的高电平信号的控制下均导通，其余组栅线对应的第一开关晶体管在控制线输入的低电平信号的控制下均关断，实现分区域显示。假设待显示区域中的栅线与相邻的两组栅线组对应，且相邻的两组栅线组中均只有部分待显示区域中的栅线，这样就需要这两组栅线组对应的所有第一开关晶体管在各自对应的控制线输入的高电平信号的控制下均导通，其余组栅线对应的第一开关晶体管在控制线输入的低电平信号的控制下均关断，实现分区域显示。
根据本公开实施例提供的阵列基板的驱动方法，通过在至少部分移位寄存器单元的栅极驱动信号的输出端与对应行的栅线之间设置控制电路，这样在进行全屏显示时，控制电路所包括的控制单元在控制信号的控制下全部导通，从而导通移位寄存器单元与对应行的栅线之间的传输路径，实现栅线的逐行扫描；在进行局部显示时，控制电路所包括的控制单元在控制信号的控制下部分地导通或关断，以部分地导通或切断移位寄存器单元与对应行的栅线之间的传输路径，从而在进行局部显示时，仅对局部显示区域对应的栅线进行扫描，而其余行栅线不进行扫描，即仅对局部显示区域对应的像素进行充放电，而其余行栅线对应的像素不进行充放电。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (12)

  1. 一种阵列基板，包括：
    多条栅线，每条栅线驱动一行像素单元；
    级联的多个移位寄存器单元，配置为向对应行的所述栅线提供栅极驱动信号；和
    控制电路，电连接在至少部分所述移位寄存器单元与对应行的所述栅线之间，所述控制电路包括多个控制单元，每个控制单元被配置为接收控制信号，并在所述控制信号的控制下，导通或切断所述移位寄存器单元与对应行的所述栅线之间的传输路径。
  2. 如权利要求1所述的阵列基板，其中，所述栅线包括第一栅线和第二栅线，其中仅在所述第一栅线与对应的所述移位寄存器单元之间电连接所述控制单元。
  3. 如权利要求2所述的阵列基板，还包括：
    一条控制线，与电连接在所述第一栅线与对应的所述移位寄存器单元之间的所有控制单元电连接；或者
    多条控制线，与电连接在所述第一栅线与对应的所述移位寄存器单元之间的控制单元一一对应电连接。
  4. 如权利要求1所述的阵列基板，其中，在每个所述移位寄存器单元与对应行的所述栅线之间电连接一个所述控制单元。
  5. 如权利要求4所述的阵列基板，还包括多条控制线，与每个所述控制单元一一对应电连接。
  6. 如权利要求4所述的阵列基板，其中，所述栅线包括第一栅线和第二栅线，所述阵列基板还包括多条控制线，所述多条控制线包括一条第一控制线和一条第二控制线，其中所述第一控制线与电连接在所述第一栅线与对应的所述移位寄存器单元之间的所有控制单元电连接，所述第二控制线与电连接在所述第二栅线与对应的所述移位寄存器单元之间的所有控制单元电连接。
  7. 如权利要求4所述的阵列基板，其中，所述栅线分为多个栅线组，所述阵列基板还包括多条控制线，其中所述多条控制线中的每条控制线与电连接在每个所述栅线组中的各条栅线与对应的所述移位寄存器单元之间的控制单元电连接。
  8. 如权利要求1-7中任一项所述的阵列基板，其中，所述控制单元包括：
    第一开关晶体管，所述第一开关晶体管的栅极电连接为接收所述控制信号，第一 极与所述移位寄存器单元的栅极驱动信号的输出端电连接，第二极与对应行的所述栅线电连接。
  9. 如权利要求8所述的阵列基板，其中，所述多个移位寄存器单元中的每个移位寄存器单元包括：
    第二晶体管，所述第二开关晶体管的栅极与第一极电连接，并电连接为接收启动信号或前一级移位寄存器单元输出的栅极驱动信号，第二极电连接第三晶体管的栅极；
    第三晶体管，所述第三晶体管的第一极电连接为接收时钟信号，第二极电连接所述第一晶体管的第一极；
    第四晶体管，所述第四晶体管的栅极电连接为接收后一级移位寄存器单元输出的栅极驱动信号，第一极电连接所述第二晶体管的第二极，第二极电连接电源电压；和
    第五晶体管，所述第五晶体管的栅极电连接所述第四晶体管的栅极，第一极电连接所述第三晶体管的第二极，第二极电连接所述电源电压。
  10. 一种显示装置，包括权利要求1-9中任一项所述的阵列基板。
  11. 一种应用于如权利要求1-9中任一项所述的阵列基板的驱动方法，包括：
    在第一工作模式下，导通全部所述移位寄存器单元与全部所述栅线之间的传输路径；
    在第二工作模式下，仅导通部分所述移位寄存器单元与对应行的所述栅线之间的传输路径。
  12. 如权利要求11所述的驱动方法，其中，在所述第二工作模式下，在第一时段提供第一电平的控制信号，在第二时段提供第二电平的控制信号。
PCT/CN2020/078422 2019-04-22 2020-03-09 阵列基板、其驱动方法及显示装置 WO2020215906A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201910321515.4A CN109859674A (zh) 2019-04-22 2019-04-22 阵列基板、其驱动方法、显示面板及显示装置
CN201910321515.4 2019-04-22

Publications (1)

Publication Number Publication Date
WO2020215906A1 true WO2020215906A1 (zh) 2020-10-29

Family

ID=66889325

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/078422 WO2020215906A1 (zh) 2019-04-22 2020-03-09 阵列基板、其驱动方法及显示装置

Country Status (2)

Country Link
CN (1) CN109859674A (zh)
WO (1) WO2020215906A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023045668A1 (zh) * 2021-09-24 2023-03-30 京东方科技集团股份有限公司 显示面板、栅极驱动电路、移位寄存单元及其驱动方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109859674A (zh) * 2019-04-22 2019-06-07 京东方科技集团股份有限公司 阵列基板、其驱动方法、显示面板及显示装置
CN110491331B (zh) * 2019-09-30 2023-01-24 京东方科技集团股份有限公司 一种显示面板、其驱动方法及显示装置
CN111583847B (zh) * 2020-05-08 2022-02-01 武汉华星光电半导体显示技术有限公司 显示模组及其驱动方法、显示装置
CN113674708B (zh) * 2020-05-14 2023-04-11 京东方科技集团股份有限公司 移位寄存器、栅极驱动电路、显示装置及其驱动方法
CN113539163B (zh) * 2021-07-16 2024-03-19 北京京东方显示技术有限公司 显示基板、显示面板和显示装置
CN113963652B (zh) * 2021-11-12 2023-08-18 武汉天马微电子有限公司 显示面板及其驱动方法
CN114974114A (zh) * 2022-05-26 2022-08-30 合肥京东方卓印科技有限公司 显示驱动电路、方法、显示面板及其制备方法、装置
CN115188343B (zh) * 2022-07-18 2023-10-31 深圳创维－Rgb电子有限公司 显示驱动电路、显示驱动方法、显示面板及显示装置
CN115713913A (zh) * 2022-11-29 2023-02-24 京东方科技集团股份有限公司 像素电路、显示基板、显示装置和显示驱动方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110169793A1 (en) * 2009-09-14 2011-07-14 Au Optronics Corp. Liquid Crystal Display, Flat Display and Gate Driving Method Thereof
CN104658466A (zh) * 2015-01-27 2015-05-27 京东方科技集团股份有限公司 一种goa电路及其驱动方法、显示面板及显示装置
CN104851369A (zh) * 2015-06-12 2015-08-19 京东方科技集团股份有限公司 一种柔性显示面板及其驱动方法、显示装置
CN105702193A (zh) * 2016-04-25 2016-06-22 上海中航光电子有限公司 柔性显示面板及其驱动方法、柔性显示装置
CN109389953A (zh) * 2017-08-08 2019-02-26 京东方科技集团股份有限公司 扫描驱动电路及其驱动方法、显示装置
CN109859674A (zh) * 2019-04-22 2019-06-07 京东方科技集团股份有限公司 阵列基板、其驱动方法、显示面板及显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101263531B1 (ko) * 2006-06-21 2013-05-13 엘지디스플레이 주식회사 액정표시장치
JP2008216349A (ja) * 2007-02-28 2008-09-18 Casio Comput Co Ltd 表示駆動装置及び表示装置
CN103680443B (zh) * 2013-12-06 2016-03-30 合肥京东方光电科技有限公司 一种选通驱动电路、栅极驱动电路及显示装置
JP6262523B2 (ja) * 2013-12-27 2018-01-17 エルジー ディスプレイ カンパニー リミテッド 表示装置用の駆動回路および表示装置
CN106782258B (zh) * 2015-11-19 2020-06-02 小米科技有限责任公司 显示屏、显示装置及显示方法
CN106782278B (zh) * 2017-02-17 2020-03-03 京东方科技集团股份有限公司 移位寄存器、栅线驱动方法、阵列基板和显示装置
CN107808651A (zh) * 2017-11-15 2018-03-16 武汉天马微电子有限公司 一种显示面板及显示装置
CN108766377B (zh) * 2018-05-22 2020-12-18 京东方科技集团股份有限公司 显示面板和显示装置
CN109166516A (zh) * 2018-11-12 2019-01-08 京东方科技集团股份有限公司 驱动单元、显示面板及其驱动方法和显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110169793A1 (en) * 2009-09-14 2011-07-14 Au Optronics Corp. Liquid Crystal Display, Flat Display and Gate Driving Method Thereof
CN104658466A (zh) * 2015-01-27 2015-05-27 京东方科技集团股份有限公司 一种goa电路及其驱动方法、显示面板及显示装置
CN104851369A (zh) * 2015-06-12 2015-08-19 京东方科技集团股份有限公司 一种柔性显示面板及其驱动方法、显示装置
CN105702193A (zh) * 2016-04-25 2016-06-22 上海中航光电子有限公司 柔性显示面板及其驱动方法、柔性显示装置
CN109389953A (zh) * 2017-08-08 2019-02-26 京东方科技集团股份有限公司 扫描驱动电路及其驱动方法、显示装置
CN109859674A (zh) * 2019-04-22 2019-06-07 京东方科技集团股份有限公司 阵列基板、其驱动方法、显示面板及显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023045668A1 (zh) * 2021-09-24 2023-03-30 京东方科技集团股份有限公司 显示面板、栅极驱动电路、移位寄存单元及其驱动方法

Also Published As

Publication number Publication date
CN109859674A (zh) 2019-06-07

Similar Documents

Publication Publication Date Title
WO2020215906A1 (zh) 阵列基板、其驱动方法及显示装置
US7508479B2 (en) Liquid crystal display
US10997891B1 (en) Display panel and display apparatus with demultiplexer, and driving method thereof
US11328639B2 (en) Shift register circuit and drive method thereof, gate drive circuit, and display panel
US10431143B2 (en) Shift register, driving method thereof, gate driving circuit and display device
WO2015188406A1 (zh) 可减少驱动芯片的电子装置
WO2021143824A1 (zh) 显示基板、其检测方法及显示装置
CN108806586B (zh) 显示面板、其驱动方法及显示装置
US11062654B2 (en) Shift register unit, gate driving circuit, display device and driving method
US20170262119A1 (en) Touch control device drive method, touch control device drive circuit and touch control device
CN111223449B (zh) 一种显示面板、其驱动方法及显示装置
US11094389B2 (en) Shift register unit and driving method, gate driving circuit, and display device
WO2019007085A1 (zh) 扫描驱动电路及驱动方法、阵列基板和显示装置
US20070109169A1 (en) Systems and methods for providing driving voltages to a display panel
KR101297241B1 (ko) 액정표시장치의 구동장치
CN109377948B (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
US11423823B2 (en) Shift register and driving method thereof, gate driving circuit and display device capabling reset the output terminal
WO2020192340A1 (zh) 移位寄存器、栅极驱动电路及其驱动方法、显示装置
US11087706B2 (en) Display driving circuit having source auxiliary circuit and gate auxiliary circuit and driving method thereof, display panel and display device
TWI427610B (zh) 可降低功率消耗之液晶顯示器及相關驅動方法
KR20010020935A (ko) 표시 장치 및 상기 표시 장치의 구동 방법
CN109983528B (zh) 移位寄存电路、驱动电路、显示装置及驱动方法
CN110244481B (zh) 一种阵列基板、液晶显示装置和驱动方法
JP7371017B2 (ja) シフトレジスタユニット、ゲート駆動回路及び駆動方法
CN111971736B (zh) 移位寄存器、其驱动方法及装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20796437

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20796437

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 20796437

Country of ref document: EP

Kind code of ref document: A1

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 10.05.2022)