WO2022016618A1 - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

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WO2022016618A1
WO2022016618A1 PCT/CN2020/107079 CN2020107079W WO2022016618A1 WO 2022016618 A1 WO2022016618 A1 WO 2022016618A1 CN 2020107079 W CN2020107079 W CN 2020107079W WO 2022016618 A1 WO2022016618 A1 WO 2022016618A1
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array substrate
carbon film
passivation layer
layer
conductive pad
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French (fr)
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胡小波
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US17/048,819 priority Critical patent/US11869904B2/en
Publication of WO2022016618A1 publication Critical patent/WO2022016618A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H10W72/01951—Changing the shapes of bond pads
    • H10W72/01953—Changing the shapes of bond pads by etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a manufacturing method thereof, and a display device.
  • the miniaturization of light-emitting diodes has developed into one of the hot spots of future display technology, and the current liquid crystal displays (Liquid Crystal Display, LCD) and organic light-emitting diodes (Organic Light Compared with Emitting Diode, OLED) display devices, it has fast response, high color gamut, high resolution (Pixels Per Inch, PPI) and low energy consumption.
  • LCD Liquid Crystal Display
  • OLED Organic Light Compared with Emitting Diode
  • PPI Picture Per Inch
  • the miniaturization of light-emitting diodes has many technical difficulties and complex technologies, especially its key technologies, mass transfer technology, organic light-emitting diodes (Light Emitting Diodes).
  • Emitting Diode (LED) particles has become a technical bottleneck, and the sub-millimeter light-emitting diode (Mini-LED) backplane, as a product of the combination of miniature light-emitting diodes and backplanes, has high contrast ratio, high color rendering performance, etc.
  • its cost is slightly higher than that of the liquid crystal display and only about 60% of the organic light emitting diode display device, which is easier to implement than the micro light emitting diode (Micro-LED) and the organic light emitting diode display device. It has become a hot spot in the layout of major panel manufacturers.
  • FIG. 1 it is a schematic diagram of a conventional sub-millimeter light emitting diode backlight module.
  • the conventional sub-millimeter light-emitting diode backlight module includes an array layer and a patterned black organic photoresist layer 104.
  • the array layer includes a thin film transistor 101, a conductive electrode 102 for binding the sub-millimeter light-emitting diode, and a binding for binding the chip-on-chip film.
  • the fixed pins (not shown) and the passivation layer 103 covering the thin film transistor 101 and exposing the conductive electrodes 102 and the binding pins, and the patterned black organic photoresist layer 104 are disposed corresponding to the thin film transistor 101 . Since the patterning of the passivation layer 103 and the patterning of the black organic photoresist layer respectively require a mask, the number of masks used in the conventional sub-millimeter light emitting diode backlight module is relatively large.
  • the purpose of the present application is to provide an array substrate, a method for manufacturing the same, and a display device, so as to reduce the number of photomasks used for manufacturing the array substrate.
  • the present application provides a manufacturing method of an array substrate, the manufacturing method comprising the following steps:
  • the array substrate comprising a thin film transistor and a conductive pad, the passivation layer covering the thin film transistor and the conductive pad;
  • a patterning process is used to remove the passivation layer and the carbon film corresponding to the conductive pads to obtain the array substrate.
  • removing the passivation layer corresponding to the conductive pad and the carbon film by a patterning process includes the following steps:
  • the plasma is prepared from oxygen or hydrogen.
  • the method further includes:
  • the passivation layer corresponding to the conductive pad is removed by dry etching.
  • forming a whole surface carbon film on the passivation layer includes the following steps:
  • a carbon film on the entire surface is formed on the passivation layer by sputtering deposition.
  • the thickness of the carbon film is greater than 100 nanometers.
  • An array substrate comprising:
  • the array layer comprising thin film transistors and conductive pads
  • a patterned carbon film formed on the passivation layer is patterned.
  • the thickness of the patterned carbon film is greater than 100 nanometers.
  • the array substrate further includes a light-emitting element, and the light-emitting element is bound on the conductive pad.
  • the light-emitting element is selected from at least one of a sub-millimeter light-emitting diode or a micro light-emitting diode.
  • the patterned carbon film is obtained by reacting at least the part of the entire carbon film corresponding to the conductive pad with plasma.
  • the plasma is prepared from oxygen or hydrogen.
  • a display device comprising an array substrate, the array substrate comprising:
  • the array layer comprising thin film transistors and conductive pads
  • a patterned carbon film formed on the passivation layer is patterned.
  • the thickness of the patterned carbon film is greater than 100 nanometers.
  • the array substrate further includes a light-emitting element, and the light-emitting element is bound on the conductive pad.
  • the light-emitting element is selected from at least one of a sub-millimeter light-emitting diode or a micro light-emitting diode.
  • the present application provides an array substrate, a manufacturing method thereof, and a display device.
  • the manufacturing method includes the following steps: forming a passivation layer on the array substrate, the array substrate comprising a thin film transistor and a conductive pad, and the passivation layer covering the thin film transistor and the conductive pad; An entire carbon film is formed on the passivation layer; a patterning process is used to pattern the carbon film and the passivation layer to remove the passivation layer and the carbon film corresponding to the conductive pad to obtain an array substrate.
  • the preparation of the black organic layer and the passivation layer requires a photomask respectively, and the present application can reduce the photomask. number of use.
  • FIG. 1 is a schematic diagram of a conventional sub-millimeter light-emitting diode backlight module
  • FIG. 2 is a schematic flowchart of the manufacturing method of the array substrate of the present application.
  • FIG. 3 is a schematic flowchart of removing the passivation layer and the carbon film corresponding to the conductive pad by a patterning process
  • FIG. 4 is a schematic diagram of the manufacturing process of the array substrate of the present application.
  • FIG. 2 is a schematic flowchart of the manufacturing method of the array substrate of the present application.
  • the manufacturing method includes the following steps:
  • S101 forming a passivation layer on an array substrate, the array substrate includes a thin film transistor and a conductive pad, and the passivation layer covers the thin film transistor and the conductive pad.
  • the preparation material of the passivation layer is selected from at least one of silicon nitride and silicon oxide.
  • the passivation layer is a silicon nitride layer.
  • a carbon film on the entire surface is formed on the passivation layer by sputtering deposition.
  • Sputter deposition is physical deposition.
  • the process parameters of sputter deposition are commonly used parameters, which are not described in detail here.
  • the carbon film deposited by physical sputtering has a simple process, and the carbon film has the characteristics of low internal stress, good thermal stability, good compactness and the like, and can shield the thin film transistor from light.
  • the thickness of the carbon film is greater than 100 nanometers, so as to have a good light shielding effect.
  • the passivation layer 205 and the carbon film 206 are patterned by a yellow light process, so that while the carbon film 206 can shield the thin film transistor from light, the conductive pads 2043 and the binding pins are exposed to emit light.
  • the components are bound to the conductive pads, and the flip-chip film is bound to the binding pins.
  • the light-emitting element may be at least one of a sub-millimeter light-emitting diode (Mini-LED), a micro-light-emitting diode (Micro-LED), or an organic light-emitting diode.
  • the manufacturing method of the array substrate of the present application uses the carbon film as the light-shielding layer, and the patterning of the carbon film and the passivation layer uses the same mask, compared with the traditional technology, the organic black photoresist layer is used as the negative photoresist layer, which requires a separate
  • the photomask is used to realize patterning, and the manufacturing method of the present application realizes the light-shielding protection of the thin film transistor, and at the same time reduces the number of photomasks used.
  • FIG. 3 it is a schematic flowchart of removing the passivation layer and the carbon film corresponding to the conductive pad by one patterning process.
  • Using a patterning process to remove the passivation layer and the carbon film corresponding to the conductive pad includes the following steps:
  • a positive photoresist layer is formed on the surface of the passivation layer by coating.
  • a photomask is used to expose the area of the positive photoresist layer corresponding to the conductive pads and the binding pins, and the exposed photoresist layer is developed by a developer to obtain a patterned photoresist layer.
  • S1033 Use plasma to react with the carbon film uncovered by the patterned photoresist layer to remove the carbon film corresponding to the conductive pad.
  • oxygen or hydrogen as a gas source
  • plasma treatment is performed on oxygen or hydrogen, and the carbon film not covered by the patterned photoresist layer reacts with the plasma to generate vaporized hydrocarbons or carbon-oxygen compounds, so that the The carbon film not covered by the patterned photoresist layer is removed, that is, the carbon film corresponding to the conductive pads and the binding pins is removed.
  • the carbon film covered by the patterned photoresist layer is protected by the patterned photoresist layer.
  • dry etching is used to remove the passivation layer corresponding to the conductive pads and the binding pins, and the remaining patterned photoresist layer is removed to obtain an array substrate with the conductive pads and the binding pins exposed.
  • the present application also provides an array substrate, the array substrate comprising:
  • the substrate is a glass substrate.
  • the array layer includes thin film transistors, conductive pads and binding pins, and the conductive pads and the binding pins are located on the same conductive layer.
  • the preparation material of the conductive pad includes at least one of molybdenum, aluminum, titanium and copper.
  • the bonding pin and the conductive pad are composed of a MoTiNi alloy layer, a copper layer and a MoTiNi alloy layer stacked in sequence, wherein the thickness of the MoTiNi alloy layer is 300 angstroms-600 angstroms, and the thickness of the copper layer is 4000 angstroms-5000 angstroms.
  • the array substrate further includes a light-emitting element, and the light-emitting element is bound on the conductive pad.
  • the light emitting element is selected from at least one of sub-millimeter light emitting diodes or micro light emitting diodes.
  • the patterned carbon film is obtained by reacting at least the part of the entire carbon film corresponding to the conductive pad with plasma, and the plasma is prepared from oxygen or hydrogen. Plasma bombards the carbon film to generate hydrocarbons or carbon oxides.
  • the present application also provides a display device, the display device includes a backlight module, and the backlight module includes the above-mentioned array substrate.
  • a substrate 200 is provided, and a gate electrode 201 is formed in a first region 200a of the substrate 200, and the first region 200a is used for forming a thin film transistor.
  • the preparation material of the gate electrode 201 includes at least one of copper, molybdenum and aluminum.
  • source and drain electrodes ( 2041 , 2042 ) are formed in the first region 200 a of the substrate 200 and conductive pads 2043 are formed in the second region 200 b , as shown in FIG. 4 . (A) shown.
  • the source-drain electrodes (2041, 2042) and the conductive pad 2043 are formed in the same layer.
  • bond pins (not shown) are also formed.
  • the second area 200b is located on one side of the first area 200a.
  • the patterned semiconductor layer, the source and drain electrodes (2041, 2042) and the conductive pad 2043, etc. can be obtained by using the same halftone grayscale mask.
  • an entire semiconductor layer and an entire metal layer are sequentially formed, a photoresist layer is formed on the metal layer, and a halftone gray-scale mask is used to expose the photoresist layer to define the photoresist layer of the photoresist layer.
  • the reserved area, the photoresist semi-reserved area, and the photoresist complete removal area are removed by removing the metal layer and the semiconductor layer in the photoresist complete removal area to form an active layer, conductive pads and bonding pins, and then the photoresist half area is removed.
  • the metal layer in the reserved area is partially removed to obtain source and drain electrodes, and the remaining photoresist layer is removed.
  • the passivation layer 205 may be a silicon nitride layer, a silicon oxide layer, a stack of silicon nitride layers and silicon oxide layers.
  • a carbon film 206 is formed on the passivation layer 205 by physical sputtering deposition, as shown in (C) of FIG. 4 .
  • a positive photoresist layer is coated on the entire surface of the carbon film 206, the positive photoresist layer is exposed by a photomask, and then the exposed positive photoresist layer is developed with a developing solution to obtain a patterned positive photoresist layer.
  • the barrier layer 207 is shown in (D) of FIG. 4 .
  • the carbon film 206 corresponding to the conductive pad 2043 is not protected by a positive photoresist layer.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种阵列基板及其制造方法、显示装置，制造方法包括如下步骤：于阵列基板上形成钝化层（205），阵列基板包括薄膜晶体管以及导电垫（2043），钝化层（205）覆盖薄膜晶体管以及导电垫（2043）（S101）；于钝化层（205）上形成整面的碳膜（206）（S102）；采用一次构图工艺去除导电垫（2043）对应的钝化层（205）以及碳膜（206），得到阵列基板（S103）。

Description

阵列基板及其制造方法、显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示装置。
 背景技术
发光二极管微型化发展成未来显示技术的热点之一，和目前的液晶显示器（Liquid Crystal Display，LCD）以及有机发光二极管（Organic Light Emitting Diode，OLED）显示器件相比，具有反应快、高色域、高分辨率（Pixels Per Inch，PPI）以及低能耗等优势。然而，发光二极管微型化技术难点多且技术复杂，特别是其关键技术巨量转移技术、有机发光二极管（Light Emitting Diode，LED）颗粒微型化成为技术瓶颈，而亚毫米发光二极管（Mini-LED）背板作为微型发光二极管与背板结合的产物，其具有高对比度、高显色性能等可与有机发光二极管显示器件相媲美的特点，其成本稍高于液晶显示器且仅为有机发光二极管显示器件的六成左右，相对微型发光二极管（Micro-LED）、有机发光二极管显示器件更易实施，所以亚毫米发光二极管成为各大面板厂商布局热点。
如图1所示，其为传统亚毫米发光二极管背光模组的示意图。传统亚毫米发光二极管背光模组包括阵列层以及图案化黑色有机光阻层104，阵列层包括薄膜晶体管101、用于绑定亚毫米发光二极管的导电电极102、用于绑定覆晶薄膜的绑定引脚（未示出）以及覆盖薄膜晶体管101且使导电电极102以及绑定引脚显露的钝化层103，图案化黑色有机光阻层104对应薄膜晶体管101设置。由于钝化层103的图案化以及黑色有机光阻层的图案化分别需要一个光罩，使得传统亚毫米发光二极管背光模组的光罩使用数目较多。
因此，有必要提出一种技术方案以减少传统亚毫米发光二极管背光模组制造过程中光罩的使用数目。
 技术问题
本申请的目的在于提供一种阵列基板及其制造方法、显示装置，以减少制造阵列基板所需的光罩使用数目。
 技术解决方案
为实现上述目的，本申请提供一种阵列基板的制造方法，所述制造方法包括如下步骤：
于阵列基板上形成钝化层，所述阵列基板包括薄膜晶体管以及导电垫，所述钝化层覆盖所述薄膜晶体管以及所述导电垫；
于所述钝化层上形成整面的碳膜；
采用一次构图工艺去除所述导电垫对应的所述钝化层以及所述碳膜，得到所述阵列基板。
在上述阵列基板的制造方法中，采用一次构图工艺去除所述导电垫对应的所述钝化层以及所述碳膜包括如下步骤：
于所述碳膜远离所述钝化层的表面形成光阻层；
利用光罩对所述光阻层进行曝光以及显影液显影后，得到图案化光阻层；
利用等离子体与所述图案化光阻层未覆盖的所述碳膜进行反应，以去除所述导电垫对应的碳膜。
在上述阵列基板的制造方法中，所述等离子体由氧气或氢气制备得到。
在上述阵列基板的制造方法中，去除所述导电垫对应的所述碳膜后，所述方法还包括：
利用干法蚀刻去除所述导电垫对应的所述钝化层。
在上述阵列基板的制造方法中，于所述钝化层上形成整面的碳膜包括如下步骤：
以石墨为靶材，利用溅射沉积于所述钝化层上形成整面的碳膜。
在上述阵列基板的制造方法中，所述碳膜的厚度大于100纳米。
一种阵列基板，所述阵列基板包括：
基板；
于所述基板上形成的阵列层，所述阵列层包括薄膜晶体管以及导电垫；
覆盖所述薄膜晶体管且使所述导电垫暴露的钝化层；
形成于所述钝化层上的图案化碳膜。
在上述阵列基板中，所述图案化碳膜的厚度大于100纳米。
在上述阵列基板中，所述阵列基板还包括发光元件，所述发光元件绑定于所述导电垫上。
在上述阵列基板中，所述发光元件选自亚毫米发光二极管或微型发光二极管中的至少一种。
在上述阵列基板中，所述图案化碳膜是由整面碳膜至少对应所述导电垫的部分与等离子反应后得到。
在上述阵列基板中，所述等离子体由氧气或氢气制备得到。
一种显示装置，所述显示装置包括阵列基板，所述阵列基板包括：
基板；
于所述基板上形成的阵列层，所述阵列层包括薄膜晶体管以及导电垫；
覆盖所述薄膜晶体管且使所述导电垫暴露的钝化层；
形成于所述钝化层上的图案化碳膜。
在上述显示装置中，所述图案化碳膜的厚度大于100纳米。
在上述显示装置中，所述阵列基板还包括发光元件，所述发光元件绑定于所述导电垫上。
在上述显示装置中，所述发光元件选自亚毫米发光二极管或微型发光二极管中的至少一种。
 有益效果
本申请提供一种阵列基板及其制造方法、显示装置，制造方法包括如下步骤：于阵列基板上形成钝化层，阵列基板包括薄膜晶体管以及导电垫，钝化层覆盖薄膜晶体管以及导电垫；于钝化层形成上形成整面的碳膜；采用一次构图工艺对碳膜以及钝化层进行图案化以去除导电垫对应的钝化层以及碳膜，得到阵列基板。通过以碳膜作为遮光层，且采用一道构图工艺完成碳膜以及钝化层的图案化，相对于传统技术中黑色有机层以及钝化层的制备分别需要一个光罩，本申请可以减少光罩使用数目。
 附图说明
图1为传统亚毫米发光二极管背光模组的示意图；
图2为本申请阵列基板的制造方法的流程示意图；
图3为采用一次构图工艺去除导电垫对应的钝化层以及碳膜的流程示意图；
图4为本申请阵列基板的制造过程示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图2，其为本申请阵列基板的制造方法的流程示意图。制造方法包括如下步骤：
S101：于阵列基板上形成钝化层，阵列基板包括薄膜晶体管以及导电垫，钝化层覆盖薄膜晶体管以及导电垫。
具体地，首先，提供一个阵列基板，阵列基板包括基板以及阵列层，阵列层设置于基板上。阵列层包括薄膜晶体管、导电垫以及绑定引脚。薄膜晶体管作为驱动元件，以控制绑定于导电垫上的发光元件的工作状态。绑定引脚用于绑定覆晶薄膜，覆晶薄膜包括柔性膜以及设置于柔性膜上的驱动芯片。
其次，采用化学气相沉积形成覆盖阵列层的钝化层，钝化层的制备材料选自氮化硅以及氧化硅中的至少一种。具体地，钝化层为氮化硅层。
S102：于钝化层上形成整面的碳膜。
具体地，以石墨为靶材，利用溅射沉积于钝化层上形成整面的碳膜。溅射沉积为物理沉积。溅射沉积的工艺参数为常用参数，此处不做具体描述。利用物理溅射沉积得到的碳膜，工艺简单，且碳膜具有内应力低、热稳定性好、致密性好等特性，且能对薄膜晶体管起到遮光作用。
在本实施例中，碳膜的厚度大于100纳米，以起到良好的遮光作用。例如150纳米、200纳米、500纳米、1000纳米、1500纳米以及3000纳米等。
S103：采用一次构图工艺去除导电垫对应的钝化层以及碳膜，得到阵列基板。
具体地，采用一次黄光制程对钝化层205以及碳膜206进行图案化，以使碳膜206对薄膜晶体管起到遮光作用的同时，导电垫2043以及绑定引脚等暴露出来，将发光元件绑定于导电垫，且将覆晶薄膜绑定于绑定引脚上。其中，发光元件可以为亚毫米发光二极管（Mini-LED）、微型发光二极管（Micro-LED）或者有机发光二极管中的至少一种。
本申请阵列基板的制造方法以碳膜作为遮光层，且碳膜以及钝化层的图案化采用同一个光罩，相对于传统技术中有机黑色光阻层作为负性光阻层需要一个单独的光罩以实现图案化，本申请的制造方法实现对薄膜晶体管的遮光保护的同时，减少光罩的使用数目。
如图3所示，其为采用一次构图工艺去除导电垫对应的钝化层以及碳膜的流程示意图。采用一次构图工艺去除导电垫对应的钝化层以及碳膜包括如下步骤：
S1031：于碳膜远离钝化层的表面形成光阻层。
具体地，采用涂布的方式于钝化层表面形成正性光阻层。
S1032：利用光罩对光阻层进行曝光以及显影液显影后，得到图案化光阻层。
具体地，利用一个光罩对正性光阻层对应导电垫以及绑定引脚的区域进行曝光，利用显影液对曝光处理的光阻层进行显影，得到图案化光阻层。
S1033：利用等离子体与图案化光阻层未覆盖的碳膜进行反应，以去除导电垫对应的碳膜。
具体地，以氧气或氢气作为气源，对氧气或氢气进行等离子化处理，未被图案化光阻层覆盖的碳膜与等离子体发生反应生成气化的碳氢化合物或碳氧化合物，使得到未被图案化光阻层覆盖的碳膜被去除，即对应导电垫以及绑定引脚的碳膜被去除。图案化光阻层覆盖的碳膜为图案化光阻层保护。
再利用干法蚀刻去除导电垫以及绑定引脚对应的钝化层，去除剩余的图案化光阻层，得到导电垫以及绑定引脚暴露的阵列基板。
本申请还提供一种阵列基板，阵列基板包括：
基板；
于基板上形成的阵列层，阵列层包括薄膜晶体管以及导电垫；
覆盖薄膜晶体管且使导电垫暴露的钝化层；
形成于钝化层上的图案化碳膜。
在本实施例中，基板为玻璃基板。阵列层包括薄膜晶体管、导电垫以及绑定引脚，导电垫以及绑定引脚位于同一导电层。
在本实施例中，导电垫的制备材料包括钼、铝、钛以及铜中的至少一种。例如绑定引脚以及导电垫由依次叠置的MoTiNi合金层、铜层以及MoTiNi合金层组成，其中，MoTiNi合金层的厚度为300埃-600埃，铜层的厚度为4000埃-5000埃。
在本实施例中。钝化层的制备材料选自氮化硅以及氧化硅中的至少一种。钝化层的厚度为800埃-6000埃，例如为1500埃、1000埃或者3000埃等。
在本实施例中，图案化碳膜的厚度大于100纳米，例如为150纳米、200纳米或者350纳米。图案化碳膜至少对应薄膜晶体管设置，且使导电垫暴露。
在本实施例中，阵列基板还包括发光元件，发光元件绑定于导电垫上。发光元件选自亚毫米发光二极管或微型发光二极管中的至少一种。
在本实施例中，图案化碳膜是由整面碳膜至少对应导电垫的部分与等离子体反应后得到，等离子体由氧气或氢气制备得到。将等离子体轰击碳膜生成碳氢化合物或碳氧化合物。
本申请还提供一种显示装置，显示装置包括背光模组，背光模组包括上述阵列基板。
以下结合具体实施例对上述方案进行详述。
 S201：在基板上形成阵列层。
具体地，提供一基板200，于基板200的第一区域200a形成栅极201，第一区域200a用于形成薄膜晶体管。其中，栅极201的制备材料包括铜、钼以及铝中的至少一种。
形成覆盖栅极201以及基板200的栅极绝缘层202，于栅极绝缘层202上形成图案化半导体层，其中，图案化半导体层包括于第一区域200a形成的有源层2031。栅极绝缘层202的制备材料选自氮化硅或者氧化硅中的至少一种。图案化半导体层的制备材料可以为多晶硅、金属氧化物或者非晶硅等。
通过形成整面的金属层后，对金属层进行图案化后，在基板200的第一区域200a形成源漏电极（2041，2042）且在第二区域200b形成导电垫2043，如图4中的（A）所示。其中，源漏电极（2041，2042）以及导电垫2043同层形成。对金属层进行图案化后，还形成绑定引脚（未示出）。第二区域200b位于第一区域200a的一侧。
其中，图案化半导体层、源漏电极（2041，2042）以及导电垫2043等可以采用同一个半色调灰阶掩膜板制得到。例如，依次形成整面的半导体层以及整面的金属层，在金属层上形成光阻层，利用半色调灰阶掩膜板对光阻层进行曝光处理后，定义出光阻层的光阻完全保留区、光阻半保留区以及光阻完全去除区，经过对光阻完全去除区的金属层以及半导体层进行去除，以形成有源层、导电垫以及绑定引脚，再对光阻半保留区的金属层进行局部去除，得到源漏电极，去除剩余的光阻层。
S202：于阵列层上形成钝化层。
具体地，采用化学气相沉积形成覆盖源漏电极（2041，2042）、导电垫2043以及栅极绝缘层202的钝化层205，如图4中的（B）所示。钝化层205可以为氮化硅层、氧化硅层、氮化硅层和氧化硅层的叠层。
S203：于钝化层上形成碳膜。
具体地，采用物理溅射沉积在钝化层205上形成一层碳膜206，如图4中的（C）所示。
S204：利用一次构图工艺对碳膜以及钝化层进行图案化，使碳膜以及钝化层对应导电垫的部分去除，且将亚毫米发光二极管绑定于导电垫上，得到阵列基板。
在碳膜206上涂布整面的正性光阻层，利用光罩对正性光阻层进行曝光，再采用显影液对曝光的正性光阻层进行显影处理，得到图案化正性光阻层207，如图4中的（D）所示。其中，导电垫2043对应的碳膜206没有正性光阻层保护。
用氧气以及氢气制备得到的等离子体轰击基板，未被图案化光阻层保护的碳膜206与等离子体反应生成碳氢化合物以及碳氧化合物，碳膜206对应导电垫2043的部分被去除，如图4中的（E）所示；再采用干法蚀刻去除暴露出来的钝化层205，使得导电垫2043暴露，如图4中的（F）所示。
将亚毫米发光二极管208绑定于导电垫2043上，且将覆晶薄膜（未示出）绑定于绑定引脚（未示出）上，得到阵列基板，如图4中的（G）所示。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (16)

  1. 一种阵列基板的制造方法，其中，所述制造方法包括如下步骤：
    于阵列基板上形成钝化层，所述阵列基板包括薄膜晶体管以及导电垫，所述钝化层覆盖所述薄膜晶体管以及所述导电垫；
    于所述钝化层上形成整面的碳膜；
    采用一次构图工艺去除所述导电垫对应的所述钝化层以及所述碳膜，得到所述阵列基板。
  2. 根据权利要求1所述阵列基板的制造方法，其中，所述采用一次构图工艺去除所述导电垫对应的所述钝化层以及所述碳膜包括如下步骤：
    于所述碳膜远离所述钝化层的表面形成光阻层；
    利用光罩对所述光阻层进行曝光以及显影液显影后，得到图案化光阻层；
    利用等离子体与所述图案化光阻层未覆盖的所述碳膜进行反应，以去除所述导电垫对应的碳膜。
  3. 根据权利要求2所述阵列基板的制造方法，其中，所述等离子体由氧气或氢气制备得到。
  4. 根据权利要求2所述阵列基板的制造方法，其中，所述去除所述导电垫对应的所述碳膜后，所述方法还包括：
    利用干法蚀刻去除所述导电垫对应的所述钝化层。
  5. 根据权利要求1所述阵列基板的制造方法，其中，于所述钝化层上形成整面的碳膜包括如下步骤：
    以石墨为靶材，利用溅射沉积于所述钝化层上形成整面的碳膜。
  6. 根据权利要求1所述阵列基板的制造方法，其中，所述碳膜的厚度大于100纳米。
  7. 一种阵列基板，其中，所述阵列基板包括：
    基板；
    于所述基板上形成的阵列层，所述阵列层包括薄膜晶体管以及导电垫；
    覆盖所述薄膜晶体管且使所述导电垫暴露的钝化层；
    形成于所述钝化层上的图案化碳膜。
  8. 根据权利要求7所述的阵列基板，其中，所述图案化碳膜的厚度大于100纳米。
  9. 根据权利要求7所述的阵列基板，其中，所述阵列基板还包括发光元件，所述发光元件绑定于所述导电垫上。
  10. 根据权利要求9所述的阵列基板，其中，所述发光元件选自亚毫米发光二极管或微型发光二极管中的至少一种。
  11. 根据权利要求7所述的阵列基板，其中，所述图案化碳膜是由整面碳膜至少对应所述导电垫的部分与等离子体反应后得到。
  12. 根据权利要求11所述的阵列基板，其中，所述等离子体由氧气或氢气制备得到。
  13. 一种显示装置，其中，所述显示装置包括阵列基板，所述阵列基板包括：
    基板；
    于所述基板上形成的阵列层，所述阵列层包括薄膜晶体管以及导电垫；
    覆盖所述薄膜晶体管且使所述导电垫暴露的钝化层；
    形成于所述钝化层上的图案化碳膜。
  14. 根据权利要求13所述的显示装置，其中，所述图案化碳膜的厚度大于100纳米。
  15. 根据权利要求13所述的显示装置，其中，所述阵列基板还包括发光元件，所述发光元件绑定于所述导电垫上。
  16. 根据权利要求15所述的显示装置，其中，所述发光元件选自亚毫米发光二极管或微型发光二极管中的至少一种。
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