CN111883486B - 阵列基板及其制造方法、显示装置 - Google Patents

阵列基板及其制造方法、显示装置 Download PDF

Info

Publication number
CN111883486B
CN111883486B CN202010697170.5A CN202010697170A CN111883486B CN 111883486 B CN111883486 B CN 111883486B CN 202010697170 A CN202010697170 A CN 202010697170A CN 111883486 B CN111883486 B CN 111883486B
Authority
CN
China
Prior art keywords
carbon film
passivation layer
layer
array substrate
conductive pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010697170.5A
Other languages
English (en)
Other versions
CN111883486A (zh
Inventor
胡小波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to CN202010697170.5A priority Critical patent/CN111883486B/zh
Priority to PCT/CN2020/107079 priority patent/WO2022016618A1/zh
Priority to US17/048,819 priority patent/US11869904B2/en
Publication of CN111883486A publication Critical patent/CN111883486A/zh
Application granted granted Critical
Publication of CN111883486B publication Critical patent/CN111883486B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03614—Physical or chemical etching by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/03622—Manufacturing methods by patterning a pre-deposited material using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

本申请提供一种阵列基板及其制造方法、显示装置，制造方法包括如下步骤：于阵列基板上形成钝化层，阵列基板包括薄膜晶体管以及导电垫，钝化层覆盖薄膜晶体管以及导电垫；于钝化层形成上形成整面的碳膜；采用一次构图工艺对碳膜以及钝化层进行图案化以去除导电垫对应的钝化层以及碳膜，得到阵列基板。通过以碳膜作为遮光层，且采用一道构图工艺完成碳膜以及钝化层的图案化，以减少光罩使用数目。

Description

阵列基板及其制造方法、显示装置
技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及其制造方法、显示装置。
背景技术
发光二极管微型化发展成未来显示技术的热点之一，和目前的液晶显示器(Liquid Crystal Display，LCD)以及有机发光二极管(Organic Light Emitting，OLED)显示器件相比，具有反应快、高色域、高分辨率(Pixels Per Inch，PPI)以及低能耗等优势。然而，发光二极管微型化技术难点多且技术复杂，特别是其关键技术巨量转移技术、有机发光二极管(Light Emitting Diode，LED)颗粒微型化成为技术瓶颈，而亚毫米发光二极管(Mini-LED)背板作为微型发光二极管与背板结合的产物，其具有高对比度、高显色性能等可与有机发光二极管显示器件相媲美的特点，其成本稍高于液晶显示器且仅为有机发光二极管显示器件的六成左右，相对微型发光二极管(Micro-LED)、有机发光二极管显示器件更易实施，所以亚毫米发光二极管成为各大面板厂商布局热点。
如图1所示，其为传统亚毫米发光二极管背光模组的示意图。传统亚毫米发光二极管背光模组包括阵列层以及图案化黑色有机光阻层104，阵列层包括薄膜晶体管101、用于绑定亚毫米发光二极管的导电电极102、用于绑定覆晶薄膜的绑定引脚(未示出)以及覆盖薄膜晶体管101且使导电电极102以及绑定引脚显露的钝化层103，图案化黑色有机光阻层104对应薄膜晶体管101设置。由于钝化层103的图案化以及黑色有机光阻层的图案化分别需要一个光罩，使得传统亚毫米发光二极管背光模组的光罩使用数目较多。
因此，有必要提出一种技术方案以减少传统亚毫米发光二极管背光模组制造过程中光罩的使用数目。
发明内容
本申请的目的在于提供一种阵列基板及其制造方法、显示装置，以减少制造阵列基板所需的光罩使用数目。
为实现上述目的，本申请提供一种阵列基板的制造方法，所述制造方法包括如下步骤：
于阵列基板上形成钝化层，所述阵列基板包括薄膜晶体管以及导电垫，所述钝化层覆盖所述薄膜晶体管以及所述导电垫；
于所述钝化层上形成整面的碳膜；
采用一次构图工艺去除所述导电垫对应的所述钝化层以及所述碳膜，得到所述阵列基板。
在上述阵列基板的制造方法中，采用一次构图工艺去除所述导电垫对应的所述钝化层以及所述碳膜包括如下步骤：
于所述碳膜远离所述钝化层的表面形成光阻层；
利用光罩对所述光阻层进行曝光以及显影液显影后，得到图案化光阻层；
利用等离子体与所述图案化光阻层未覆盖的所述碳膜进行反应，以去除所述导电垫对应的碳膜。
在上述阵列基板的制造方法中，所述等离子体由氧气或氢气制备得到。
在上述阵列基板的制造方法中，去除所述导电垫对应的所述碳膜后，所述方法还包括：
利用干法蚀刻去除所述导电垫对应的所述钝化层。
在上述阵列基板的制造方法中，于所述钝化层上形成整面的碳膜包括如下步骤：
以石墨为靶材，利用溅射沉积于所述钝化层上形成整面的碳膜。
在上述阵列基板的制造方法中，所述碳膜的厚度大于100纳米。
一种阵列基板，所述阵列基板包括：
基板；
于所述基板上形成的阵列层，所述阵列层包括薄膜晶体管以及导电垫；
覆盖所述薄膜晶体管且使所述导电垫暴露的钝化层；
形成于所述钝化层上的图案化碳膜。
在上述阵列基板中，所述图案化碳膜的厚度大于100纳米。
在上述阵列基板中，所述阵列基板还包括发光元件，所述发光元件绑定于所述导电垫上。
一种显示装置，所述显示装置包括上述阵列基板。
有益效果：本申请提供一种阵列基板及其制造方法、显示装置，制造方法包括如下步骤：于阵列基板上形成钝化层，阵列基板包括薄膜晶体管以及导电垫，钝化层覆盖薄膜晶体管以及导电垫；于钝化层形成上形成整面的碳膜；采用一次构图工艺对碳膜以及钝化层进行图案化以去除导电垫对应的钝化层以及碳膜，得到阵列基板。通过以碳膜作为遮光层，且采用一道构图工艺完成碳膜以及钝化层的图案化，相对于传统技术中黑色有机层以及钝化层的制备分别需要一个光罩，本申请可以减少光罩使用数目。
附图说明
图1为传统亚毫米发光二极管背光模组的示意图；
图2为本申请阵列基板的制造方法的流程示意图；
图3为采用一次构图工艺去除导电垫对应的钝化层以及碳膜的流程示意图；
图4为本申请阵列基板的制造过程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图2，其为本申请阵列基板的制造方法的流程示意图。制造方法包括如下步骤：
S101：于阵列基板上形成钝化层，阵列基板包括薄膜晶体管以及导电垫，钝化层覆盖薄膜晶体管以及导电垫。
具体地，首先，提供一个阵列基板，阵列基板包括基板以及阵列层，阵列层设置于基板上。阵列层包括薄膜晶体管、导电垫以及绑定引脚。薄膜晶体管作为驱动元件，以控制绑定于导电垫上的发光元件的工作状态。绑定引脚用于绑定覆晶薄膜，覆晶薄膜包括柔性膜以及设置于柔性膜上的驱动芯片。
其次，采用化学气相沉积形成覆盖阵列层的钝化层，钝化层的制备材料选自氮化硅以及氧化硅中的至少一种。具体地，钝化层为氮化硅层。
S102：于钝化层上形成整面的碳膜。
具体地，以石墨为靶材，利用溅射沉积于钝化层上形成整面的碳膜。溅射沉积为物理沉积。溅射沉积的工艺参数为常用参数，此处不做具体描述。利用物理溅射沉积得到的碳膜，工艺简单，且碳膜具有内应力低、热稳定性好、致密性好等特性，且能对薄膜晶体管起到遮光作用。
在本实施例中，碳膜的厚度大于100纳米，以起到良好的遮光作用。例如150纳米、200纳米、500纳米、1000纳米、1500纳米以及3000纳米等。
S103：采用一次构图工艺去除导电垫对应的钝化层以及碳膜，得到阵列基板。
具体地，采用一次黄光制程对钝化层205以及碳膜206进行图案化，以使碳膜206对薄膜晶体管起到遮光作用的同时，导电垫2043以及绑定引脚等暴露出来，将发光元件绑定于导电垫，且将覆晶薄膜绑定于绑定引脚上。其中，发光元件可以为亚毫米发光二极管(Mini-LED)、微型发光二极管(Micro-LED)或者有机发光二极管中的至少一种。
本申请阵列基板的制造方法以碳膜作为遮光层，且碳膜以及钝化层的图案化采用同一个光罩，相对于传统技术中有机黑色光阻层作为负性光阻层需要一个单独的光罩以实现图案化，本申请的制造方法实现对薄膜晶体管的遮光保护的同时，减少光罩的使用数目。
如图3所示，其为采用一次构图工艺去除导电垫对应的钝化层以及碳膜的流程示意图。采用一次构图工艺去除导电垫对应的钝化层以及碳膜包括如下步骤：
S1031：于碳膜远离钝化层的表面形成光阻层。
具体地，采用涂布的方式于钝化层表面形成正性光阻层。
S1032：利用光罩对光阻层进行曝光以及显影液显影后，得到图案化光阻层。
具体地，利用一个光罩对正性光阻层对应导电垫以及绑定引脚的区域进行曝光，利用显影液对曝光处理的光阻层进行显影，得到图案化光阻层。
S1033：利用等离子体与图案化光阻层未覆盖的碳膜进行反应，以去除导电垫对应的碳膜。
具体地，以氧气或氢气作为气源，对氧气或氢气进行等离子化处理，未被图案化光阻层覆盖的碳膜与等离子体发生反应生成气化的碳氢化合物或碳氧化合物，使得到未被图案化光阻层覆盖的碳膜被去除，即对应导电垫以及绑定引脚的碳膜被去除。图案化光阻层覆盖的碳膜为图案化光阻层保护。
再利用干法蚀刻去除导电垫以及绑定引脚对应的钝化层，去除剩余的图案化光阻层，得到导电垫以及绑定引脚暴露的阵列基板。
本申请还提供一种阵列基板，阵列基板包括：
基板；
于基板上形成的阵列层，阵列层包括薄膜晶体管以及导电垫；
覆盖薄膜晶体管且使导电垫暴露的钝化层；
形成于钝化层上的图案化碳膜。
在本实施例中，基板为玻璃基板。阵列层包括薄膜晶体管、导电垫以及绑定引脚，导电垫以及绑定引脚位于同一导电层。
在本实施例中，导电垫的制备材料包括钼、铝、钛以及铜中的至少一种。例如绑定引脚以及导电垫由依次叠置的MoTiNi合金层、铜层以及MoTiNi合金层组成，其中，MoTiNi合金层的厚度为300埃-600埃，铜层的厚度为4000埃-5000埃。
在本实施例中。钝化层的制备材料选自氮化硅以及氧化硅中的至少一种。钝化层的厚度为800埃-6000埃，例如为1500埃、1000埃或者3000埃等。
在本实施例中，图案化碳膜的厚度大于100纳米，例如为150纳米、200纳米或者350纳米。图案化碳膜至少对应薄膜晶体管设置且使导电垫暴露。
在本实施例中，阵列基板还包括发光元件，发光元件绑定于导电垫上。发光元件选自亚毫米发光二极管或微型发光二极管中的至少一种。
本申请还提供一种显示装置，显示装置包括背光模组，背光模组包括上述阵列基板。
以下结合具体实施例对上述方案进行详述。
S201：在基板上形成阵列层。
具体地，提供一基板200，于基板200的第一区域200a形成栅极201，第一区域200a用于形成薄膜晶体管。其中，栅极201的制备材料包括铜、钼以及铝中的至少一种。
形成覆盖栅极201以及基板200的栅极绝缘层202，于栅极绝缘层202上形成图案化半导体层，其中，图案化半导体层包括于第一区域200a形成的有源层2031。栅极绝缘层202的制备材料选自氮化硅或者氧化硅中的至少一种。图案化半导体层的制备材料可以为多晶硅、金属氧化物或者非晶硅等。
通过形成整面的金属层后，对金属层进行图案化后，在基板200的第一区域200a形成源漏电极(2041，2042)且在第二区域200b形成导电垫2043，如图4中的(A)所示。其中，源漏电极(2041，2042)以及导电垫2043同层形成。对金属层进行图案化后，还形成绑定引脚(未示出)。第二区域200b位于第一区域200a的一侧。
其中，图案化半导体层、源漏电极(2041，2042)以及导电垫2043等可以采用同一个半色调灰阶掩膜板制得到。例如，依次形成整面的半导体层以及整面的金属层，在金属层上形成光阻层，利用半色调灰阶掩膜板对光阻层进行曝光处理后，定义出光阻层的光阻完全保留区、光阻半保留区以及光阻完全去除区，经过对光阻完全去除区的金属层以及半导体层进行去除，以形成有源层、导电垫以及绑定引脚，再对光阻半保留区的金属层进行局部去除，得到源漏电极，去除剩余的光阻层。
S202：于阵列层上形成钝化层。
具体地，采用化学气相沉积形成覆盖源漏电极(2041，2042)、导电垫2043以及栅极绝缘层202的钝化层205，如图4中的(B)所示。钝化层205可以为氮化硅层、氧化硅层、氮化硅层和氧化硅层的叠层。
S203：于钝化层上形成碳膜。
具体地，采用物理溅射沉积在钝化层205上形成一层碳膜206，如图4中的(C)所示。
S204：利用一次构图工艺对碳膜以及钝化层进行图案化，使碳膜以及钝化层对应导电垫的部分去除，且将亚毫米发光二极管绑定于导电垫上，得到阵列基板。
在碳膜206上涂布整面的正性光阻层，利用光罩对正性光阻层进行曝光，再采用显影液对曝光的正性光阻层进行显影处理，得到图案化正性光阻层207，如图4中的(D)所示。其中，导电垫2043对应的碳膜206没有正性光阻层保护。
用氧气以及氢气制备得到的等离子体轰击基板，未被图案化光阻层保护的碳膜206与等离子体反应生成碳氢化合物以及碳氧化合物，碳膜206对应导电垫2043的部分被去除，如图4中的(E)所示；再采用干法蚀刻去除暴露出来的钝化层205，使得导电垫2043暴露，如图4中的(F)所示。
将亚毫米发光二极管208绑定于导电垫2043上，且将覆晶薄膜(未示出)绑定于绑定引脚(未示出)上，得到阵列基板，如图4中的(G)所示。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (6)

1.一种阵列基板的制造方法，其特征在于，所述制造方法包括如下步骤：
于阵列层上形成钝化层，所述阵列层包括薄膜晶体管以及导电垫，所述钝化层覆盖所述薄膜晶体管以及所述导电垫；
于所述钝化层上形成整面的碳膜；
采用一次构图工艺去除所述导电垫对应的所述钝化层以及所述碳膜，得到所述阵列基板。
2.根据权利要求1所述阵列基板的制造方法，其特征在于，所述采用一次构图工艺去除所述导电垫对应的所述钝化层以及所述碳膜包括如下步骤：
于所述碳膜远离所述钝化层的表面形成光阻层；
利用光罩对所述光阻层进行曝光以及显影液显影后，得到图案化光阻层；
利用等离子体与所述图案化光阻层未覆盖的所述碳膜进行反应，以去除所述导电垫对应的碳膜。
3.根据权利要求2所述阵列基板的制造方法，其特征在于，所述等离子体由氧气或氢气制备得到。
4.根据权利要求2所述阵列基板的制造方法，其特征在于，所述去除所述导电垫对应的所述碳膜后，所述方法还包括：
利用干法蚀刻去除剩余的所述碳膜暴露的所述钝化层，以去除所述导电垫对应的所述钝化层。
5.根据权利要求1所述阵列基板的制造方法，其特征在于，于所述钝化层上形成整面的碳膜包括如下步骤：
以石墨为靶材，利用溅射沉积于所述钝化层上形成整面的碳膜。
6.根据权利要求1所述阵列基板的制造方法，其特征在于，所述碳膜的厚度大于100纳米。
CN202010697170.5A 2020-07-20 2020-07-20 阵列基板及其制造方法、显示装置 Active CN111883486B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202010697170.5A CN111883486B (zh) 2020-07-20 2020-07-20 阵列基板及其制造方法、显示装置
PCT/CN2020/107079 WO2022016618A1 (zh) 2020-07-20 2020-08-05 阵列基板及其制造方法、显示装置
US17/048,819 US11869904B2 (en) 2020-07-20 2020-08-05 Array substrate, method for fabricating same, and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010697170.5A CN111883486B (zh) 2020-07-20 2020-07-20 阵列基板及其制造方法、显示装置

Publications (2)

Publication Number Publication Date
CN111883486A CN111883486A (zh) 2020-11-03
CN111883486B true CN111883486B (zh) 2023-11-28

Family

ID=73154932

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010697170.5A Active CN111883486B (zh) 2020-07-20 2020-07-20 阵列基板及其制造方法、显示装置

Country Status (3)

Country Link
US (1) US11869904B2 (zh)
CN (1) CN111883486B (zh)
WO (1) WO2022016618A1 (zh)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102769030A (zh) * 2011-05-03 2012-11-07 爱思开海力士有限公司 半导体器件及其制造方法
CN105762086A (zh) * 2014-12-16 2016-07-13 中芯国际集成电路制造(上海)有限公司 焊盘结构的制作方法、键合结构的制作方法及键合结构
CN107146770A (zh) * 2017-05-10 2017-09-08 京东方科技集团股份有限公司 一种阵列基板的制备方法、阵列基板和显示装置
CN109698133A (zh) * 2017-10-20 2019-04-30 三星电子株式会社 包括钝化间隔物的半导体器件及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7402770B2 (en) * 2005-06-10 2008-07-22 Lsi Logic Corporation Nano structure electrode design
US8193032B2 (en) * 2010-06-29 2012-06-05 International Business Machines Corporation Ultrathin spacer formation for carbon-based FET
US8796741B2 (en) * 2011-10-04 2014-08-05 Qualcomm Incorporated Semiconductor device and methods of making semiconductor device using graphene
US11088050B2 (en) * 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US10892169B2 (en) * 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US9142505B2 (en) * 2013-06-18 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for back end of line semiconductor device processing
TWI546934B (zh) * 2014-10-20 2016-08-21 Playnitride Inc Led陣列擴張方法及led陣列單元
ES2808826T3 (es) * 2015-06-10 2021-03-02 Fundacio Inst De Ciencies Fotòniques Sensor de imagen, sistema optoelectrónico que comprende dicho sensor de imagen y método de fabricación de dicho sensor de imagen
CN109300919B (zh) * 2018-10-15 2020-09-29 上海天马微电子有限公司 Micro LED显示基板及其制作方法、显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102769030A (zh) * 2011-05-03 2012-11-07 爱思开海力士有限公司 半导体器件及其制造方法
CN105762086A (zh) * 2014-12-16 2016-07-13 中芯国际集成电路制造(上海)有限公司 焊盘结构的制作方法、键合结构的制作方法及键合结构
CN107146770A (zh) * 2017-05-10 2017-09-08 京东方科技集团股份有限公司 一种阵列基板的制备方法、阵列基板和显示装置
CN109698133A (zh) * 2017-10-20 2019-04-30 三星电子株式会社 包括钝化间隔物的半导体器件及其制造方法

Also Published As

Publication number Publication date
WO2022016618A1 (zh) 2022-01-27
US20230163146A1 (en) 2023-05-25
CN111883486A (zh) 2020-11-03
US11869904B2 (en) 2024-01-09

Similar Documents

Publication Publication Date Title
US8842231B2 (en) Array substrate and manufacturing method thereof
US9523895B2 (en) TFT-LCD array substrate and manufacturing method thereof
JP5079392B2 (ja) Ｔｆｔ−ｌｃｄアレイ基板構造及びその製造方法
US7439090B2 (en) Method for manufacturing a lower substrate of a liquid crystal display device
US7790487B2 (en) Method for fabricating photo sensor
CN101656232B (zh) 薄膜晶体管阵列基板制造方法
US8305528B2 (en) Liquid crystal display and manufacturing method thereof
US7948570B2 (en) Thin film transistor array substrate and manufacturing method thereof
US8426259B2 (en) Array substrate and method for manufacturing the same
CN102709234B (zh) 薄膜晶体管阵列基板及其制造方法和电子器件
WO2013189160A1 (zh) 阵列基板及其制作方法、显示装置
KR20130106428A (ko) Ｔｆｔ 어레이 기판의 제조 방법
CN101907807A (zh) 具有氧化物薄膜晶体管的显示器及其制造方法
CN105449127A (zh) 发光二极管显示基板及其制作方法、显示装置
US11930679B2 (en) Array substrate, preparation method therefor, and display device
CN111584511B (zh) 阵列基板及其制造方法、显示装置
CN111584512B (zh) 阵列基板及其制造方法、显示装置
CN111524957B (zh) 显示基板及其制作方法、显示装置
CN111883486B (zh) 阵列基板及其制造方法、显示装置
CN110729250A (zh) 阵列基板的制造方法及阵列基板
CN111584604A (zh) Oled显示基板及其制作方法、显示装置
US7808569B2 (en) Method for manufacturing pixel structure
US11374036B2 (en) Array substrate, manufacturing method thereof, and display device
CN112035007B (zh) 触控显示面板及其制备方法
WO2021007976A1 (zh) 彩膜阵列基板的制备方法及彩膜阵列基板

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant