WO2022012200A1 - 反熔丝存储单元状态检测电路及存储器 - Google Patents

反熔丝存储单元状态检测电路及存储器 Download PDF

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Publication number
WO2022012200A1
WO2022012200A1 PCT/CN2021/097849 CN2021097849W WO2022012200A1 WO 2022012200 A1 WO2022012200 A1 WO 2022012200A1 CN 2021097849 W CN2021097849 W CN 2021097849W WO 2022012200 A1 WO2022012200 A1 WO 2022012200A1
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Prior art keywords
memory cell
fuse memory
node
time point
input terminal
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English (en)
French (fr)
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季汝敏
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/570,476 priority Critical patent/US11854605B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4099—Dummy cell treatment; Reference voltage generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/143—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using laser-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components

Definitions

  • the present disclosure relates to the technical field of integrated circuits, exemplarily, to an anti-fuse memory cell state detection circuit and a memory using the circuit.
  • the storage state of the anti-fuse memory cell is often detected through a simple logic gate circuit.
  • FIG. 1 take the anti-fuse memory cell 11 whose word line is connected to the FsBlin3 signal as an example: if the anti-fuse memory cell is programmed during programming, the anti-fuse memory cell changes from a non-storage state to a storage state , the path resistance is reduced to a small value (tens of thousands of ohms to hundreds of thousands of ohms), then when the anti-fuse memory cell is selected, the path current flows through the equivalent resistance in the storage state, generating a relatively small amount on the node Node1.
  • the low voltage makes the logic gate 12 output signal D_out high; on the contrary, if the anti-fuse memory cell is not programmed during programming, the equivalent resistance of the anti-fuse memory cell in the path will be compared. If it is large (several megaohms to several hundreds of megaohms), then the voltage drop generated by the fixed circuit on this path will exceed the switching point of the logic gate 12, so that the output signal D_out of the logic gate 12 is at a low level.
  • the resistance of the anti-fuse memory cell in the non-storage state usually fluctuates in a wide range, and changes in process, voltage, temperature and other factors will also make the switching point of the logic gate circuit in a wide range. These factors may cause errors in the storage state detection of the anti-fuse memory cells, such as misjudging the programmed anti-fuse memory cells as unprogrammed anti-fuse memory cells, or The recorded anti-fuse memory cell is misjudged as the programmed anti-fuse memory cell, resulting in a decrease in yield.
  • the purpose of the present disclosure is to provide an anti-fuse memory cell state detection circuit and a memory using the same, which are used to at least to a certain extent overcome the storage state detection of anti-fuse memory cells due to the limitations and defects of the related art Inaccurate results.
  • an anti-fuse memory cell state detection circuit comprising: an amplifier, a first input terminal is connected to a first reference voltage, a second input terminal is connected to a first node, and an output terminal is connected to a second node;
  • An anti-fuse memory cell array comprising a plurality of anti-fuse memory cell sub-arrays, the bit lines of the plurality of anti-fuse memory cell sub-arrays are all connected to the first node, the plurality of anti-fuse memory cell sub-arrays
  • the word lines of the array are all connected to the controller, and the anti-fuse memory cell sub-array includes a plurality of anti-fuse memory cells; a first switch element, the first end is connected to the power supply, the second end is connected to the first node, and the control end connected to the second node; a second switch element, the first end is connected to the power supply, the second end is connected to the third node, the control end is connected to the second no
  • the controller is configured to: output a first control signal at a first time point to detect a storage state of the anti-fuse memory unit, and output a second control signal to control the first control signal
  • the three switching elements are turned off; the output signal of the comparator is acquired at a second time point to determine the storage state of the anti-fuse memory unit; wherein the second time point is after the first time point.
  • the second time point is determined according to the following methods: obtaining the maximum resistance after breakdown and the minimum resistance when the anti-fuse memory cell is not broken down; The power supply, the maximum resistance and the minimum resistance determine the first voltage change line and the second voltage change line of the first node; the difference between the first voltage change line and the second voltage change line is determined The time point when the preset threshold is reached is set as the second time point.
  • the second reference voltage is determined according to the following manner: determining a first voltage value and the second voltage change of the first voltage change line at the second time point the second voltage value of the line at the second time point; and setting the average value of the first voltage value and the second voltage value as the second reference voltage.
  • the method further includes: a detection capacitor, a first terminal is connected to the third node, and a second terminal is grounded.
  • it further includes: a flip-flop, the input terminal is connected to the output terminal of the comparator, and the first output terminal and the second output terminal are both connected to the controller.
  • the anti-fuse memory cell includes: a selection switch element, a first end of the selection switch element serves as a bit line of the anti-fuse memory cell; an anti-fuse element , the first end of the anti-fuse element is connected to the second end of the selection switch element; the control end of the selection switch element and the control end of the anti-fuse element are both connected to the controller.
  • the first switching element and the second switching element are both P-type transistors
  • the first input terminal of the amplifier is a non-inverting input terminal
  • the second switching element of the amplifier is a non-inverting input terminal.
  • the input terminal is an inverting input terminal; or, the first switching element and the second switching element are both N-type transistors, the first input terminal of the amplifier is an inverting input terminal, and the second input terminal of the amplifier The terminal is the non-inverting input terminal.
  • the acquiring the output signal of the comparator includes: controlling the comparator to be in an enabled state at the second time point to read the output signal of the comparator .
  • a memory including the anti-fuse memory cell state detection circuit according to any one of the above.
  • the resistance of the anti-fuse memory cell to be tested is converted into a linear current source to charge the third node, and the voltage of the third node is charged at the second time point. Comparing with the second reference voltage to obtain the resistance value of the anti-fuse memory cell to be tested currently in the anti-fuse memory cell array, the voltage inversion point used to detect the storage state of the anti-fuse memory cell can be accurately controlled to avoid related In the technology, the storage state of the anti-fuse memory cell is misjudged due to the resistance shift of the anti-fuse memory cell and the inversion voltage shift of the logic gate.
  • FIG. 1 is a schematic diagram of an anti-fuse memory cell state detection circuit in the prior art.
  • FIG. 2 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in an exemplary embodiment of the present disclosure.
  • FIG. 3 is a flowchart of a detection method of the controller CON applied to the circuit shown in FIG. 2 .
  • FIG. 4 is a schematic diagram of an equivalent circuit of the circuit shown in FIG. 2 .
  • FIG. 5 is a schematic diagram of a manner in which the second time point is determined according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a first voltage change line and a second voltage change line.
  • FIG. 7 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in another embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • FIG. 10 is a flowchart of a detection method corresponding to the circuit shown in FIG. 9 .
  • FIG. 11 is a schematic structural diagram of an anti-fuse memory cell in an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram of a comparator in one embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed.
  • well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • FIG. 2 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in an exemplary embodiment of the present disclosure.
  • the anti-fuse memory cell state detection circuit 200 may include:
  • Amplifier 21 the first input terminal is connected to the first reference voltage Vref, the second input terminal is connected to the first node N1, and the output terminal is connected to the second node N2;
  • the anti-fuse memory cell array 22 includes a plurality of anti-fuse memory cell sub-arrays, the bit lines of the plurality of anti-fuse memory cell sub-arrays are connected to the first node N1, and the word lines of the plurality of anti-fuse memory cell sub-arrays are all connected to the first node N1.
  • the controller CON is connected, and the sub-array of anti-fuse memory cells includes a plurality of anti-fuse memory cells;
  • the first switching element M1 the first terminal is connected to the power supply VDD, the second terminal is connected to the first node N1, and the control terminal is connected to the second node N2;
  • the second switching element M2 the first end is connected to the power supply VDD, the second end is connected to the third node N3, and the control end is connected to the second node N2;
  • the third switching element M3, the first end is connected to the third node N3, the second end is grounded, and the control end is connected to the controller CON;
  • the comparator 23 has a first input terminal connected to the third node N3, and a second input terminal connected to the second reference voltage Vtrip.
  • FIG. 11 shows three anti-fuse memory cell sub-arrays, corresponding to three bit lines, each anti-fuse The filament memory cell sub-array includes a plurality of anti-fuse cells 111, and each anti-fuse cell 111 includes a selection switch element M and an anti-fuse element F.
  • the first switching element M1 and the second switching element M2 are both P-type transistors, the first input terminal of the amplifier 21 is a non-inverting input terminal, and the second input terminal is an inverting input terminal.
  • the first switching element M1 and the second switching element M2 are both N-type transistors, the first input terminal of the amplifier 21 is an inverting input terminal, and the second input terminal is a non-inverting input terminal.
  • the default state of the third switching element M3 is turned on, so as to maintain the voltage of the third node N3 to be zero before the voltage detection is performed by the comparator 23 .
  • the controller CON includes not only a control logic circuit for selecting the switching element M in the anti-fuse memory unit, but also a processing logic circuit for further processing the output result of the comparator 23 .
  • the control logic circuit will make Xadd_00 to Xadd_nn valid one by one, so as to detect the states of the anti-fuse elements F_00 to F_nn one by one, and the processing logic circuit will use the states of F_00 to F_nn to perform operations such as redundant replacement. .
  • FIG. 3 is a flowchart of a detection method of the controller CON applied to the circuit shown in FIG. 2 .
  • the controller CON may be configured to perform a detection method 300, which may include:
  • Step S1 outputting a first control signal at a first time point to detect the storage state of the anti-fuse memory unit, and outputting a second control signal to control the third switching element to be turned off;
  • Step S2 obtain the output signal of the comparator at the second time point to determine the storage state of the anti-fuse storage unit
  • the second time point is after the first time point.
  • FIG. 4 is a schematic diagram of an equivalent circuit of the circuit shown in FIG. 2 .
  • the control method shown in FIG. 3 will be described below with reference to FIGS. 2 to 4 .
  • an amplifier 21 , a first switching element M1 and a second switching element M2 are used to convert the resistance of the anti-fuse memory cell to be tested into a linear current source to charge the third node, so as to pass
  • the detection and comparison of the potential of the third node realizes the detection of the resistance (ie, the storage state) of the anti-fuse memory cell to be tested.
  • the voltage of the third node N3 can be detected by using the parasitic capacitance C1 existing at the third node N3.
  • the resistance of the path where the first node N1 is located changes, and the voltage of the first node N1 drops.
  • the source-drain voltage of the first switching element M1 changes, and the feedback circuit of the amplifier 21 generates a first current, and the first current is negatively correlated with the resistance of the anti-fuse memory unit to be tested.
  • the generation of the first current will change the voltage of the second node N2 where the gate of the first switching element M1 is located.
  • the second switching element M2 When the second switching element M2 is controlled to work in a saturated state, the second current flowing through the second switching element M2 and the third node N3 is negatively correlated with the voltage of the second node N2 where the gate of the second switching element M2 is located. That is, the second current is negatively correlated with the resistance of the anti-fuse memory unit to be tested, the greater the resistance of the anti-fuse memory unit to be tested, the smaller the second current; the higher the current.
  • the second current charges the third node N3 through the parasitic capacitor C1, and finally raises the voltage of the third node N3 from zero to the power supply VDD.
  • the larger the second current is the shorter the charging time of the third node N3 is, and the faster the voltage of the third node N3 changes; the smaller the second current is, the longer the charging time of the third node N3 is, and the voltage of the third node N3 changes. slower.
  • the resistance of the anti-fuse memory cell to be tested can be determined. storage status.
  • the method of acquiring the output signal of the comparator 23 can either be to set the comparator 23 to the enabled state and read the output signal of the comparator 23 at the second time point, or it may be to use the comparator 23 to enable the comparator 23 at the second time point.
  • the enable pin controls the comparator 23 to transition to the enable state at the second time point, reads the output signal of the comparator 23, and outputs a comparison result between the voltage of the third node N3 and the second reference voltage Vtrip.
  • Using a suitable second reference voltage and a comparator for detection at a suitable time point can accurately control the inversion point of the comparator, and prevent storage state detection errors caused by resistance shift or the logic gate's own inversion point shift. Therefore, in the embodiment of the present disclosure, the selection of the second time point and the setting of the voltage value of the second reference voltage Vtrip are important means to achieve accurate detection.
  • FIG. 5 is a schematic diagram of a manner in which a third time point is determined according to an embodiment of the present disclosure.
  • the second time point may be determined in the following manner:
  • Step S51 obtaining the maximum resistance after breakdown and the minimum resistance when not being broken down of the anti-fuse memory cell
  • Step S52 determining a first voltage change line and a second voltage change line of the first node according to the power supply, the maximum resistance and the minimum resistance;
  • Step S53 setting a time point when the difference between the first voltage change line and the second voltage change line reaches a preset threshold value as the second time point.
  • the difference between the second time point T2 and the first time point T1 is related to the difference between the first voltage change line and the second voltage change line.
  • FIG. 6 is a schematic diagram of a first voltage change line and a second voltage change line.
  • R1 can be obtained by detecting the resistance of multiple anti-fuse memory cells when they are not broken down
  • R2 can be obtained by detecting the resistance of multiple anti-fuse memory cells after breakdown.
  • the above R1 and R2 are statistical results.
  • the voltage V1(t) of the third node N3 rises from 0 to VDD with the change of time t from the first time point T1.
  • the first voltage change line is:
  • V1(t) I 1 (t)*t/C1 (1)
  • I 1 (t) is the second current when the via resistance includes R1. It is assumed here that the equivalent capacitance of the third node N3 is approximately equal to C1.
  • the voltage V2(t) of the third node N3 rises from 0 to VDD with the change of time t from the first time point T1.
  • the second voltage change line is:
  • V2(t) I 2 (t)*t/C1 (2)
  • I 2 (t) is the second current when the path resistance includes R2.
  • the second time point can be obtained by determining the time point at which ⁇ V(t) is equal to the preset threshold.
  • the preset threshold may be determined according to the parameters of the comparator 23 , for example, greater than twice the differential input voltage threshold of the comparator 23 .
  • the voltage of the third node N3 can be controlled to be zero in various ways, so as to facilitate accurate detection.
  • the reference voltage Vtrip may also be determined according to the line shown in FIG. 6 .
  • the first voltage value V1(T2) of the first voltage change line V1(t) at the second time point T2 and the second voltage value V2(t) of the second voltage change line V2(t) at the second time point T2 may be determined first. T2); then set the average value of the first voltage value V1 (T2) and the second voltage value V2 (T2) as the reference voltage Vtrip, that is:
  • FIG. 7 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in another embodiment of the present disclosure.
  • the detection circuit 200 may further include:
  • the detection capacitor C2 has a first end connected to the third node N3 and a second end connected to the ground.
  • the function of the detection capacitor C2 is the same as that of the parasitic capacitor C1, both for detecting the voltage of the third node N3.
  • the capacitance value of the detection capacitor C2 is quite different from the capacitance value of the parasitic capacitance C1
  • the equivalent capacitance at the third node N3 can be regarded as the detection capacitance C2.
  • the C1 involved in formulas (1) to (4) Can be replaced with C2.
  • FIG. 8 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • the detection circuit 200 may further include:
  • the flip-flop 24, the input terminal of the flip-flop 24 is connected to the output terminal of the comparator 23, and the first output terminal and the second output terminal of the flip-flop 24 are both connected to the controller CON.
  • the flip-flop 24 can be, for example, a D flip-flop, which is used to latch the output signal of the comparator 23 so as to facilitate reading by the controller CON.
  • Those skilled in the art can set the model of the trigger 24 by themselves, and the present disclosure is not limited thereto.
  • the setting of the detection capacitor C2 or the trigger 24 does not affect the implementation of the control method shown in FIG. 3 , and does not affect the selection logic of the second time point and the second reference capacitor.
  • FIG. 9 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • the third node N3 may be used to connect a plurality of bit lines, and the anti-fuse memory cell array 22 may include:
  • a plurality of anti-fuse memory cell sub-arrays 22m (m is a bit line serial number), each anti-fuse memory cell sub-array 22m corresponds to a bit line BLm, and each anti-fuse memory cell sub-array 22m includes a plurality of anti-fuses storage unit;
  • a plurality of fourth switching elements M4m corresponding to the anti-fuse memory cell sub-array 22m the first end of each fourth switching element M4m is connected to the bit line BLm of the corresponding anti-fuse memory cell sub-array 22m, and each fourth The second end of the switching element M4m is connected to the third node N3, the control end of each fourth switching element M4m is connected to the controller CON, and the default state of the fourth switching element M4m is an off state.
  • each anti-fuse memory cell sub-array 22m may include, for example, 16 anti-fuse memory cells connected on one bit line, that is, a column of anti-fuse memory cells.
  • one bit line corresponds to one first switching element M1 , one second switching element M2 , one amplifier 21 and one comparator 23 .
  • FIG. 10 is a flowchart of a detection method corresponding to the circuit shown in FIG. 9 .
  • controller CON can be configured to perform the following methods:
  • Step S1 outputting a first control signal at a first time point to detect the storage state of the anti-fuse memory unit, and outputting a second control signal to control the third switching element to be turned off;
  • Step S101 outputting a third control signal to the fourth switch element corresponding to the anti-fuse memory unit at a third time point to control the fourth switch element to be turned on;
  • Step S2 obtaining the output signal of the comparator at the second time point to determine the storage state of the anti-fuse storage unit
  • the first time point and the third time point are both before the second time point.
  • the method shown in FIG. 3 may further include step S101, and the order of step S101 and step S1 may be exchanged.
  • the third time point may be before the first time point, or after the first time point, and may also be equal to the first time point, as long as the third time point and the first time point are both Before the second time point, the discharge path can be turned on before starting to detect the voltage of the third node N3 at the second time point.
  • the third control signal is at a low level; when the fourth switch element is an N-type transistor, the third control signal is at a high level.
  • the third control signal can also be other types of signals, which is not particularly limited in the present disclosure.
  • FIG. 11 is a schematic diagram of an anti-fuse memory cell in an embodiment of the present disclosure.
  • the anti-fuse memory unit 111 may include:
  • an anti-fuse element F the first end of the anti-fuse element F is connected to the second end of the selection switch element M;
  • control end of the selection switch element M and the control end of the anti-fuse element F are both connected to the controller.
  • FIG. 12 is a schematic diagram of the comparator 23 in one embodiment of the present disclosure.
  • a differential amplifier may be used to implement the function of the comparator 23, in which a self-biasing circuit is employed.
  • the differential amplifier uses a simple two-stage comparator to accurately control the flip point, with self-biasing circuitry to avoid excessive bias current traces.
  • the anti-fuse memory cell state detection circuit and the anti-fuse memory cell state detection method provided by the embodiments of the present disclosure, by passing the amplifier, the first switching element, the second switching element, and the anti-fuse memory cell to be tested at a first time point
  • the resistor constructs a constant current source, charges the third node N3, detects the voltage of the third node at the second time point, and uses the comparator to compare the voltage of the third node with the second reference voltage, which can precisely control the output of the comparator Flip point.
  • a memory including the anti-fuse memory cell state detection circuit according to any one of the above.
  • the memory may be, for example, a DRAM memory.
  • modules or units of the apparatus for action performance are mentioned in the above detailed description, this division is not mandatory. Indeed, according to embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into multiple modules or units to be embodied.
  • the resistance of the anti-fuse memory cell to be tested is converted into a linear current source to charge the third node, and the voltage of the third node is charged at the second time point. Comparing with the second reference voltage to obtain the resistance value of the anti-fuse memory cell to be tested currently in the anti-fuse memory cell array, the voltage inversion point used to detect the storage state of the anti-fuse memory cell can be accurately controlled to avoid related In the technology, the storage state of the anti-fuse memory cell is misjudged due to the resistance shift of the anti-fuse memory cell and the inversion voltage shift of the logic gate.

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Abstract

一种反熔丝存储单元状态检测电路（200）及存储器，电路包括：放大器（21），第一输入端连接第一参考电压，第二输入端连接第一节点，输出端连接第二节点；反熔丝存储单元阵列（22），包括多个位线均连接第一节点、字线均连接控制器的反熔丝存储单元子阵列，反熔丝存储单元子阵列包括多个反熔丝存储单元（111）；第一开关元件，第一端连接电源，第二端连接第一节点，控制端连接第二节点；第二开关元件，第一端连接电源，第二端连接第三节点，控制端连接第二节点；第三开关元件，第一端连接第三节点，第二端接地，控制端连接控制器；比较器（23），第一输入端连接第三节点，第二输入端连接第二参考电压。该检测电路可以提高反熔丝存储单元存储状态检测的准确度。

Description

反熔丝存储单元状态检测电路及存储器
交叉引用
本公开要求于2020年07月16日提交的申请号为202010687680.4、名称为“反熔丝存储单元状态检测电路及存储器”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，示例性而言，涉及一种反熔丝存储单元状态检测电路及应用该电路的存储器。
背景技术
现有技术往往通过简单的逻辑门电路对反熔丝存储单元的存储状态进行检测。参见图1，以字线连接FsBlin3信号的反熔丝存储单元11为例：如果在编程的时候对该反熔丝存储单元进行烧录，该反熔丝存储单元由未存储状态转变为存储状态，通路电阻降低到较小值(几十千欧姆到几百千欧姆)，则当该反熔丝存储单元被选中时，通路电流流经存储状态下的等效电阻，在节点Node1上产生较低的电压，使逻辑门12输出信号D_out为高电平；反之，如果在编程的时候没有对该反熔丝存储单元进行烧录，该反熔丝存储单元在通路中的等效电阻会比较大(几兆欧姆到几百兆欧姆)，那么固定电路在该通路上产生的压降将超过逻辑门12的翻转点，使得逻辑门12的输出信号D_out为低电平。
在实际生产中，反熔丝存储单元在未存储状态下的电阻通常会在一个较宽的范围内波动，工艺、电压、温度等因素发生变化也会使得逻辑门电路的翻转点在较宽的范围内变化，这些因素都可能会导致对反熔丝存储单元的存储状态检测发生错误，例如将烧录过的反熔丝存储单元误判为未烧录反熔丝存储单元，或者将未烧录反熔丝存储单元误判为已烧录反熔丝存储单元，造成良率下降。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种反熔丝存储单元状态检测电路及应用该电路的存储器，用于至少在一定程度上克服由于相关技术的限制和缺陷而导致的反熔丝存储单元的存储状态检测结果不准确的问题。
根据本公开的第一方面，提供一种反熔丝存储单元状态检测电路，包括：放大器，第一输入端连接第一参考电压，第二输入端连接第一节点，输出端连接第二节点；反熔丝存储单元阵列，包括多个反熔丝存储单元子阵列，所述多个反熔丝存储单元子阵列的位线均 连接所述第一节点，所述多个反熔丝存储单元子阵列的字线均连接控制器，所述反熔丝存储单元子阵列包括多个反熔丝存储单元；第一开关元件，第一端连接电源，第二端连接所述第一节点，控制端连接所述第二节点；第二开关元件，第一端连接所述电源，第二端连接第三节点，控制端连接所述第二节点；第三开关元件，第一端连接所述第三节点，第二端接地，控制端连接所述控制器；比较器，第一输入端连接所述第三节点，第二输入端连接第二参考电压。
在本公开的一种示例性实施例中，所述控制器设置为：在第一时间点输出第一控制信号检测所述反熔丝存储单元的存储状态，输出第二控制信号控制所述第三开关元件关断；在第二时间点获取所述比较器的输出信号以确定所述反熔丝存储单元的存储状态；其中，所述第二时间点在所述第一时间点之后。
在本公开的一种示例性实施例中，所述第二时间点根据以下方式确定：获取所述反熔丝存储单元的击穿后的最大电阻和未被击穿时的最小电阻；根据所述电源、所述最大电阻和所述最小电阻确定所述第一节点的第一电压变化线和第二电压变化线；将所述第一电压变化线与所述第二电压变化线的差值达到预设阈值的时间点设置为所述第二时间点。
在本公开的一种示例性实施例中，所述第二参考电压根据以下方式确定：确定所述第一电压变化线在所述第二时间点的第一电压值和所述第二电压变化线在所述第二时间点的第二电压值；将所述第一电压值和所述第二电压值的平均值设置为所述第二参考电压。
在本公开的一种示例性实施例中，还包括：检测电容，第一端连接所述第三节点，第二端接地。
在本公开的一种示例性实施例中，还包括：触发器，输入端连接所述比较器的输出端，第一输出端和第二输出端均连接所述控制器。
在本公开的一种示例性实施例中，所述反熔丝存储单元包括：选择开关元件，所述选择开关元件的第一端作为所述反熔丝存储单元的位线；反熔丝元件，所述反熔丝元件的第一端连接于所述选择开关元件的第二端；所述选择开关元件的控制端和所述反熔丝元件的控制端均连接于所述控制器。
在本公开的一种示例性实施例中，所述第一开关元件、所述第二开关元件均为P型晶体管，所述放大器的第一输入端为同相输入端，所述放大器的第二输入端为反相输入端；或者，所述第一开关元件、所述第二开关元件均为N型晶体管，所述放大器的第一输入端为反相输入端，所述放大器的第二输入端为同相输入端。
在本公开的一种示例性实施例中，所述获取所述比较器的输出信号包括：在所述第二时间点控制所述比较器为使能状态以读取所述比较器的输出信号。
根据本公开的第二方面，提供一种存储器，包括如上述任意一项所述的反熔丝存储单元状态检测电路。
本公开实施例通过使用放大器、第一开关元件和第二开关元件，将待测反熔丝存储单元的电阻转换成线性电流源对第三节点充电，在第二时间点将第三节点的电压与第二参考 电压比较得出反熔丝存储单元阵列中当前待测反熔丝存储单元的电阻值，可以使得用于检测反熔丝存储单元的存储状态的电压翻转点得到精确控制，避免相关技术中由于反熔丝存储单元的电阻偏移和逻辑门的翻转电压偏移导致的反熔丝存储单元的存储状态误判。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中反熔丝存储单元状态检测电路的示意图。
图2是本公开示例性实施例中反熔丝存储单元状态检测电路的结构示意图。
图3是应用于图2所示电路的控制器CON的检测方法的流程图。
图4是图2所示电路的等效电路示意图。
图5是本公开实施例确定第二时间点的方式的示意图。
图6是第一电压变化线和第二电压变化线的示意图。
图7是本公开另一个实施例中反熔丝存储单元状态检测电路的结构示意图。
图8是本公开再一个实施例中反熔丝存储单元状态检测电路的结构示意图。
图9是本公开再一个实施例中反熔丝存储单元状态检测电路的结构示意图。
图10是图9所示电路对应的检测方法的流程图。
图11是本公开一个实施例中反熔丝存储单元的结构示意图。
图12是本公开一个实施例中比较器的示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬 件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图2是本公开示例性实施例中反熔丝存储单元状态检测电路的结构示意图。
参考图2，反熔丝存储单元状态检测电路200可以包括：
放大器21，第一输入端连接第一参考电压Vref，第二输入端连接第一节点N1，输出端连接第二节点N2；
反熔丝存储单元阵列22，包括多个反熔丝存储单元子阵列，多个反熔丝存储单元子阵列的位线连接第一节点N1，多个反熔丝存储单元子阵列的字线均连接控制器CON，所述反熔丝存储单元子阵列包括多个反熔丝存储单元；
第一开关元件M1，第一端连接电源VDD，第二端连接第一节点N1，控制端连接第二节点N2；
第二开关元件M2，第一端连接电源VDD，第二端连接第三节点N3，控制端连接第二节点N2；
第三开关元件M3，第一端连接第三节点N3，第二端接地，控制端连接控制器CON；
比较器23，第一输入端连接第三节点N3，第二输入端连接第二参考电压Vtrip。
图2所示的反熔丝存储单元阵列22和反熔丝存储单元的结构请参见图11，图11中示意出3个反熔丝存储单元子阵列，对应3条位线，每个反熔丝存储单元子阵列包括多个反熔丝单元111，每个反熔丝单元111包括一个选择开关元件M和一个反熔丝元件F。
在一个实施例中，第一开关元件M1、第二开关元件M2均为P型晶体管，放大器21的第一输入端为同相输入端，第二输入端为反相输入端。在另一个实施例中，第一开关元件M1、第二开关元件M2均为N型晶体管，放大器21的第一输入端为反相输入端，第二输入端为同相输入端。本领域技术人员可以根据第一开关元件M1和第二开关元件M2的设置自行确定放大器的连接方式，本公开不以此为限。
可以理解的是，第三开关元件M3的默认状态为导通，以在通过比较器23进行电压检测之前维持第三节点N3的电压为零。
控制器CON不仅包括对反熔丝存储单元中选择开关元件M的控制逻辑电路，也包括对比较器23输出结果的进一步处理的处理逻辑电路。例如，在图11中，控制逻辑电路会使得Xadd_00到Xadd_nn逐一有效，从而逐一检测反熔丝元件F_00到F_nn的状态，而处理逻辑电路则会利用F_00到F_nn的状态去做冗余替换等操作。
图3是应用于图2所示电路的控制器CON的检测方法的流程图。
参考图3，控制器CON可以设置为执行检测方法300，检测方法300可以包括：
步骤S1，在第一时间点输出第一控制信号检测所述反熔丝存储单元的存储状态，输出第二控制信号控制所述第三开关元件关断；
步骤S2，在第二时间点获取所述比较器的输出信号以确定所述反熔丝存储单元的存 储状态；
其中，第二时间点在第一时间点之后。
图4是图2所示电路的等效电路示意图。下面将结合图2～图4对图3所述控制方法进行说明。
参考图4，在本公开实施例中，使用放大器21、第一开关元件M1和第二开关元件M2，将待测反熔丝存储单元的电阻转换成线性电流源对第三节点充电，以通过对第三节点电位的检测和比较实现对待测反熔丝存储单元的电阻(即存储状态)的检测。
在一个实施例中，可以利用第三节点N3存在的寄生电容C1来检测第三节点N3的电压。
在第一时间点通过第一控制信号选中待测反熔丝存储单元后，第一节点N1所在通路的电阻发生变化，第一节点N1的电压下降。第一开关元件M1的源漏电压发生变化，通过放大器21的反馈电路产生第一电流，该第一电流与待测反熔丝存储单元的电阻负相关。第一电流的产生会改变第一开关元件M1栅极所在的第二节点N2的电压。当控制第二开关元件M2工作在饱和状态时，流经第二开关元件M2和第三节点N3的第二电流与第二开关元件M2的栅极所在的第二节点N2的电压负相关。即，第二电流与待测反熔丝存储单元的电阻负相关，待测反熔丝存储单元的电阻越大，第二电流越小；待测反熔丝存储单元的电阻越小，第二电流越大。
在输出第二控制信号控制第三开关元件M3关断后，第二电流通过寄生电容C1对第三节点N3充电，最终将第三节点N3的电压从零提升到电源VDD。第二电流越大，第三节点N3的充电时间越短，第三节点N3的电压变化速度越快；第二电流越小，第三节点N3的充电时间越长，第三节点N3的电压变化速度越慢。通过以上分析可知，待测反熔丝存储单元的电阻越大，第二电流越小，第三节点N3的电压变化速度越慢；待测反熔丝存储单元的电阻越小，第二电流越大，第三节点N3的电压变化速度越快。
通过在合适的第二时间点使用比较器23将第三节点N3的电压与合适的第二参考电压Vtrip相比较，可以判断待测反熔丝存储单元的电阻，即待测反熔丝存储单元的存储状态。
获取比较器23的输出信号的方法既可以为将比较器23设置为使能状态并在第二时间点读取比较器23的输出信号，也可以为在第二时间点通过比较器23的使能引脚控制比较器23在第二时间点转变为使能状态并读取比较器23的输出信号，输出第三节点N3的电压和第二参考电压Vtrip的比较结果。
在合适的时间点采用合适的第二参考电压和比较器进行检测，可以使比较器的翻转点得到精确控制，防止电阻偏移或者逻辑门自身翻转点偏移导致的存储状态检测错误。因此，本公开实施例中，对第二时间点的选择和对第二参考电压Vtrip的电压值的设置是实现精确检测的重要手段。
图5是本公开实施例确定第三时间点的方式的示意图。
参考图5，在本公开的一种示例性实施例中，第二时间点可以根据以下方式确定：
步骤S51，获取所述反熔丝存储单元的击穿后的最大电阻和未被击穿时的最小电阻；
步骤S52，根据所述电源、所述最大电阻和所述最小电阻确定所述第一节点的第一电压变化线和第二电压变化线；
步骤S53，将所述第一电压变化线与所述第二电压变化线的差值达到预设阈值的时间点设置为所述第二时间点。
在本公开实施例中，第二时间点T2与第一时间点T1的差值与第一电压变化线和第二电压变化线的差值相关。
图6是第一电压变化线和第二电压变化线的示意图。
设反熔丝存储单元在未被击穿时的最小电阻为R1，在击穿后的最大电阻为R2，R1可以通过检测多个反熔丝存储单元在未被击穿时的电阻得出，R2可以通过检测多个反熔丝存储单元在击穿后的电阻得出。上述R1和R2都是统计结果，当反熔丝存储单元在研发和生产过程中，会对R1和R2进行统计分析，以此确定R1和R2的具体值。
参考图6，在通路电阻包括R1时，随时间t的变化第三节点N3的电压V1(t)从第一时间点T1开始由0上升至VDD的第一电压变化线为：
V1(t)＝I 1(t)*t/C1   (1)
其中，I 1(t)是在通路电阻包括R1时的第二电流。这里假设第三节点N3的等效电容约等于C1。
在通路电阻包括R2时，随时间t的变化第三节点N3的电压V2(t)从第一时间点T1开始由0上升至VDD的第二电压变化线为：
V2(t)＝I 2(t)*t/C1   (2)
其中，I 2(t)是在通路电阻包括R2时的第二电流。
由公式(1)和(2)可知，V2(t)较V1(t)的值大，则第一电压变化线和第二电压变化线的差值ΔV(t)为：
ΔV(t)＝V2(t)-V1(t)＝(I 2(t)-I 1(t))*t/C1   (3)
确定ΔV(t)等于预设阈值的时间点，即可得到第二时间点。预设阈值可以根据比较器23的参数确定，例如，大于比较器23的差分输入电压阈值的二倍。预设阈值越大，检测准确度越高；预设阈值越小，检测时间越短。因此，本领域技术人员可以根据实际情况自行调整预设阈值的设置数值，以实现检测准确度和检测时间的共同最优方案。
可以理解的是，在开始检测时，可以通过多种方式控制第三节点N3的电压为零，以利于准确检测。
在本公开的一种示例性实施例中，还可以根据图6所示线确定参考电压Vtrip。可以首先确定第一电压变化线V1(t)在第二时间点T2的第一电压值V1(T2)和第二电压变化线V2(t)在第二时间点T2的第二电压值V2(T2)；然后将第一电压值V1(T2)和第二电压值V2(T2)的平均值设置为参考电压Vtrip，即：
Figure PCTCN2021097849-appb-000001
通过上述方式计算第二时间点并根据第二时间点确定用于控制比较器翻转点的参考电压Vtrip，可以在检测比较器输出信号时获得更加准确的检测结果，有效提高检测精度。
图7是本公开另一个实施例中反熔丝存储单元状态检测电路的结构示意图。
参考图7，为了减小第三节点N3的寄生电容容值偏差造成的放电线随机偏差，可以对第三节点N3添加一个额外的电容C2。即，检测电路200还可以包括：
检测电容C2，检测电容C2的第一端连接第三节点N3，第二端接地。
检测电容C2的作用与寄生电容C1相同，均是为了检测第三节点N3的电压。在检测电容C2的容值与寄生电容C1的容值相差较大时，可以将第三节点N3处的等效电容看作是检测电容C2，此时公式(1)～(4)涉及的C1可以替换为C2。
图8是本公开再一个实施例中反熔丝存储单元状态检测电路的结构示意图。
参考图8，在本公开的其他实施例中，检测电路200还可以包括：
触发器24，触发器24的输入端连接比较器23的输出端，触发器24的第一输出端和第二输出端均连接控制器CON。
触发器24例如可以为D触发器，用于对比较器23的输出信号进行锁存，以方便控制器CON读取。本领域技术人员可以自行设置触发器24的型号，本公开不以此为限。
可以理解的是，检测电容C2或触发器24的设置不影响图3所示控制方法的实施，不影响第二时间点和第二参考电容的选取逻辑。
图9是本公开再一个实施例中反熔丝存储单元状态检测电路的结构示意图。
参考图9，在一个实施例中，第三节点N3可以用于连接多个位线，反熔丝存储单元阵列22可以包括：
多个反熔丝存储单元子阵列22m(m为位线序号)，每个反熔丝存储单元子阵列22m对应一条位线BLm，每个反熔丝存储单元子阵列22m包括多个反熔丝存储单元；
与反熔丝存储单元子阵列22m对应的多个第四开关元件M4m，每个第四开关元件M4m的第一端连接对应的反熔丝存储单元子阵列22m的位线BLm，每个第四开关元件M4m的第二端连接第三节点N3，每个第四开关元件M4m的控制端连接控制器CON，第四开关元件M4m的默认状态为关断状态。
其中，每个反熔丝存储单元子阵列22m例如可以包括连接在一条位线上的16个反熔丝存储单元，即一列反熔丝存储单元。在一些实施例中，一条位线对应一个第一开关元件M1、一个第二开关元件M2、一个放大器21和一个比较器23。
通过在第一节点连接多个反熔丝存储单元子阵列22m，可以实现对多个反熔丝存储单元子阵列22m中的反熔丝存储单元的存储状态的检测，示例性方式如图10所示。
图10是图9示电路对应的检测方法的流程图。
参考图10，在图9所示电路中，控制器CON可以设置为执行以下方法：
步骤S1，在第一时间点输出第一控制信号检测所述反熔丝存储单元的存储状态，输出第二控制信号控制所述第三开关元件关断；
步骤S101，在第三时间点对该反熔丝存储单元对应的第四开关元件输出第三控制信号以控制该第四开关元件导通；
步骤S2，在第二时间点获取比较器的输出信号以确定该反熔丝存储单元的存储状态；
其中，第一时间点和第三时间点均在第二时间点之前。
即图3所示的方法还可以包括步骤S101，步骤S101与步骤S1的顺序可以调换。
在图10所示实施例中，第三时间点可以在第一时间点之前，也可以在第一时间点之后，还可以与第一时间点相等，只要第三时间点和第一时间点均在第二时间点之前即可，以在第二时间点开始检测第三节点N3的电压前开启放电通路。
当第四开关元件为P型晶体管时，第三控制信号为低电平；当第四开关元件为N型晶体管时，第三控制信号为高电平。当第四开关元件为其他类型的元件时，第三控制信号也可以为其他类型的信号，本公开对此不作特殊限制。
图11本公开实施例中反熔丝存储单元的示意图。
参考图11，反熔丝存储单元111可以包括：
选择开关元件M，选择开关元件M的第一端作为反熔丝存储单元111的位线；
反熔丝元件F，反熔丝元件F的第一端连接于选择开关元件M的第二端；
其中，选择开关元件M的控制端和反熔丝元件F的控制端均连接于控制器。
图12是本公开一个实施例中比较器23的示意图。
参考图12，在一个实施例中，可以使用差分放大器实现比较器23的功能，在比较器23中采用自偏置电路。差分放大器采用简单的两级比较器，可以准确控制翻转点，通过自偏置电路以避免过多的偏置电流走线。
本公开实施例提供的反熔丝存储单元状态检测电路和反熔丝存储单元状态检测方法，通过在第一时间点通过放大器、第一开关元件、第二开关元件、待测反熔丝存储单元的电阻构建恒流源，对第三节点N3充电，在第二时间点检测第三节点的电压，使用比较器将第三节点的电压与第二参考电压进行比较，可以精确控制比较器的输出翻转点。通过计算反熔丝存储单元未被击穿时的最小电阻R1和击穿后的最大电阻R2，并确定第三节点电压在R1和R2下的电压变化线的差值最大的时间点，可以确定状态检测最准确的第二时间点，通过使用第二时间点对应的两条电压变化线的值的平均值作为参考电压，可以使比较器的输出更为准确，避免相关技术中由于反熔丝存储单元的电阻偏移和逻辑门的翻转电压偏移导致的反熔丝存储单元的存储状态误判。
根据本公开的一个方面，提供一种存储器，包括如上述任意一项所述的反熔丝存储单元状态检测电路。该存储器例如可以是DRAM存储器。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模 块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。
工业实用性
本公开实施例通过使用放大器、第一开关元件和第二开关元件，将待测反熔丝存储单元的电阻转换成线性电流源对第三节点充电，在第二时间点将第三节点的电压与第二参考电压比较得出反熔丝存储单元阵列中当前待测反熔丝存储单元的电阻值，可以使得用于检测反熔丝存储单元的存储状态的电压翻转点得到精确控制，避免相关技术中由于反熔丝存储单元的电阻偏移和逻辑门的翻转电压偏移导致的反熔丝存储单元的存储状态误判。

Claims (10)

  1. 一种反熔丝存储单元状态检测电路，包括：
    放大器，第一输入端连接第一参考电压，第二输入端连接第一节点，输出端连接第二节点；
    反熔丝存储单元阵列，包括多个反熔丝存储单元子阵列，所述多个反熔丝存储单元子阵列的位线均连接所述第一节点，所述多个反熔丝存储单元子阵列的字线均连接控制器，所述反熔丝存储单元子阵列包括多个反熔丝存储单元；
    第一开关元件，第一端连接电源，第二端连接所述第一节点，控制端连接所述第二节点；
    第二开关元件，第一端连接所述电源，第二端连接第三节点，控制端连接所述第二节点；
    第三开关元件，第一端连接所述第三节点，第二端接地，控制端连接所述控制器；
    比较器，第一输入端连接所述第三节点，第二输入端连接第二参考电压。
  2. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，所述控制器设置为：
    在第一时间点输出第一控制信号检测所述反熔丝存储单元的存储状态，输出第二控制信号控制所述第三开关元件关断；
    在第二时间点获取所述比较器的输出信号以确定所述反熔丝存储单元的存储状态；
    其中，所述第二时间点在所述第一时间点之后。
  3. 如权利要求2所述的反熔丝存储单元状态检测电路，其中，所述第二时间点根据以下方式确定：
    获取所述反熔丝存储单元的击穿后的最大电阻和未被击穿时的最小电阻；
    根据所述电源、所述最大电阻和所述最小电阻确定所述第一节点的第一电压变化线和第二电压变化线；
    将所述第一电压变化线与所述第二电压变化线的差值达到预设阈值的时间点设置为所述第二时间点。
  4. 如权利要求3所述的反熔丝存储单元状态检测电路，其中，所述第二参考电压根据以下方式确定：
    确定所述第一电压变化线在所述第二时间点的第一电压值和所述第二电压变化线在所述第二时间点的第二电压值；
    将所述第一电压值和所述第二电压值的平均值设置为所述第二参考电压。
  5. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，还包括：
    检测电容，第一端连接所述第三节点，第二端接地。
  6. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，还包括：
    触发器，输入端连接所述比较器的输出端，第一输出端和第二输出端均连接所述控制 器。
  7. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，所述反熔丝存储单元包括：
    选择开关元件，所述选择开关元件的第一端作为所述反熔丝存储单元的位线；
    反熔丝元件，所述反熔丝元件的第一端连接于所述选择开关元件的第二端；
    所述选择开关元件的控制端和所述反熔丝元件的控制端均连接于所述控制器。
  8. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，所述第一开关元件、所述第二开关元件均为P型晶体管，所述放大器的第一输入端为同相输入端，所述放大器的第二输入端为反相输入端；或者，所述第一开关元件、所述第二开关元件均为N型晶体管，所述放大器的第一输入端为反相输入端，所述放大器的第二输入端为同相输入端。
  9. 如权利要求2所述的反熔丝存储单元状态检测电路，其中，所述获取所述比较器的输出信号包括：
    在所述第二时间点控制所述比较器为使能状态以读取所述比较器的输出信号。
  10. 一种存储器，包括如权利要求1～9任一项所述的反熔丝存储单元状态检测电路。
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