WO2022012048A1 - 一种信号测试点检测方法、系统及相关组件 - Google Patents
一种信号测试点检测方法、系统及相关组件 Download PDFInfo
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- WO2022012048A1 WO2022012048A1 PCT/CN2021/077383 CN2021077383W WO2022012048A1 WO 2022012048 A1 WO2022012048 A1 WO 2022012048A1 CN 2021077383 W CN2021077383 W CN 2021077383W WO 2022012048 A1 WO2022012048 A1 WO 2022012048A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2813—Checking the presence, location, orientation or value, e.g. resistance, of components or conductors
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2803—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP] by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor
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- the present application relates to the field of signal detection, and in particular, to a signal test point detection method, system and related components.
- signal testing is an indispensable part.
- the signal test cannot be performed.
- the traces and the chip are designed on the same layer on the PCB (Printed Circuit Board), it is not possible to change the layer vias. If there is no test point added to the trace, the oscilloscope will not be able to test.
- the purpose of the present application is to provide a signal test point detection method, system, electronic device and computer-readable storage medium, which can reduce the impact on the signal integrity performance, and complete the signal test point detection by a detection tool, compared with manual detection. , which can reduce a lot of man-hours and improve the detection efficiency and reliability.
- the application provides a method for detecting a signal test point, which is applied to a detection tool, including:
- the test information of the signal line is acquired, and a test point is added on the signal line according to the test information and the line length specification of the test point from the receiving end chip.
- the test information includes one or more of ID information, connection level information, layer-change via information, measurement point information, and connected chip pin information.
- the signal test point detection method further includes:
- the marking information of the signal line is generated according to the testing information and/or the wire length specification, and the marking information is stored in a database.
- the process of generating the marking information of the signal line according to the test information and/or the trace length specification specifically includes:
- the first mark is generated
- the trace length from the via to the receiver chip is greater than the trace length specification, and the trace length from the measuring point to the receiver chip is greater than the trace A length specification to generate the first token.
- the signal test point detection method further includes:
- the signal test point detection method further includes:
- the process of adding a measuring point on the signal line according to the test information and the trace length specification of the measuring point from the receiving end chip specifically includes:
- test point is added to the test point addition area according to the test information and the trace length specification of the test point from the receiver chip, and the test information of the signal line is updated.
- the signal test point detection method further includes:
- the present application also provides a signal test point detection system, which is applied to a detection tool, including:
- a determination module configured to receive a signal line selection instruction and SI information, and determine a signal line and a receiver chip in the PCB file according to the signal line selection instruction and the SI information;
- the adding module is used for acquiring the test information of the signal line, and adding a test point on the signal line according to the test information and the line length specification between the test point and the receiving end chip.
- an electronic device including:
- the processor is configured to implement the steps of the signal test point detection method according to any one of the above when executing the computer program.
- the present application also provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, any one of the above-mentioned methods is implemented.
- the steps of the signal test point detection method are described in detail below.
- the present application provides a method for detecting signal test points.
- a PCB file is obtained through a detection tool, so as to determine the information of all signal lines on the PCB, so as to ensure the comprehensiveness of the detection of signal line test points without omission, and then the detection
- the tool determines the target signal line and the receiving end chip according to the signal line selection command and SI information, and selects the position of the measuring point on the signal line according to the line length specification of the measuring point from the receiving end chip to reduce the impact on the signal integrity performance.
- the signal test point detection is completed by the detection tool, which can reduce a lot of man-hours and improve the detection efficiency and reliability compared with manual detection.
- the present application also provides a signal test point detection system, an electronic device and a computer-readable storage medium, which have the same beneficial effects as the above signal test point detection method.
- 1 is a flow chart of steps of a method for detecting a signal test point provided by the application
- FIG. 2 is a schematic diagram of a detection tool display interface provided by the application
- FIG. 3 is a schematic structural diagram of a signal test point detection system provided by the present application.
- the core of the present application is to provide a signal test point detection method, system, electronic device and computer-readable storage medium, which can reduce the impact on the signal integrity performance, and complete the signal test point detection by a detection tool, compared with manual detection. , which can reduce a lot of man-hours and improve the detection efficiency and reliability.
- FIG. 1 is a flow chart of the steps of a method for detecting a signal test point provided by the application, applied to a detection tool, and the method for detecting a signal test point includes:
- S102 Receive the signal line selection instruction and SI (Signal Integrity, signal integrity) information, and determine the signal line and the receiver chip in the PCB file according to the signal line selection instruction and the SI information;
- SI Signal Integrity, signal integrity
- a PCB file can be obtained, so as to obtain all information of the PCB, such as signal line information, PCB level information, via hole information, and the like.
- the user may input a signal line selection instruction, and the signal line selection instruction may include a keyword corresponding to the signal line, so that the detection tool can filter out the signal line selected by the user according to the keyword for subsequent detection.
- the signal line selection command can also include the complete signal line name.
- the detection tool selects the signal line according to the complete signal line name. After selecting the signal line, the detection tool outputs the information of the chip connected to the signal line.
- a signal line can be connected to one or more chips.
- the current receiver chip can be determined according to the SI information.
- the user After determining the signal line and the receiver chip, the user inputs the trace length specification from the measuring point to the receiver chip, so that the detection tool can perform subsequent detection operations after receiving the trace length specification.
- S103 Acquire the test information of the signal line, and add a test point on the signal line according to the test information and the line length specification of the distance between the test point and the receiving end chip.
- test information of the signal line is obtained.
- the test information includes but is not limited to its ID information, layer information, layer-changing via information (connection layer, coordinates, etc.), measurement point information (layer, coordinates, etc.) etc.), connected chip pins, etc.
- the signal test point detection method further includes:
- the marking information of the signal line is generated according to the test information and/or the trace length specification, and the marking information is stored in the database.
- the process of generating the marking information of the signal line according to the test information and/or the trace length specification specifically includes:
- the first mark is generated
- the trace length from the via hole to the receiver chip is greater than the trace length specification, and the trace length from the measuring point to the receiver chip is greater than the trace length specification, the first mark is generated.
- the layer-change via information can refer to the number of layer-change vias. If the number of layer-change vias is 0, it means that the trace and the chip are on the same layer. Check whether there are test points. If not, mark "via 0, testpoint” 0, Fail", record to the database, if there is a measuring point, query the measuring point level, get the trace length from the measuring point to the receiving chip, and compare it with the trace length specification, if it is greater than the trace length specification, mark it as "via 0,testpoint 1,Fail", recorded in the database, if it is less than or equal to the trace length specification, marked as "via 0,testpoint 1,Pass”, recorded in the database.
- the trace length from the via to the receiver chip If the number of vias is not 0, query the trace length from the via to the receiver chip, and compare it with the trace length specification. If it is less than or equal to the trace length specification, mark it as "via 1, Pass” and record it in the database middle. If it is greater than the trace length specification, continue to check the test point information. If there is, query the trace length from the test point to the receiving chip, and compare it with the trace length specification. If it is greater than the trace length specification, mark it as "via 1, test 1,fail", recorded in the database. If it is less than or equal to the trace length specification, mark it as "via 1, test 1, Pass” and record it in the database. The mark with fail among the above marks is the first mark.
- the information of all signal lines marked as fail can be displayed on the display interface, which is convenient for users to view and add test points later.
- the information displayed on the display interface can include but not limited to signal Line name Net Name, layer Layer, test point Testpoint, via information Via, trace length Length, mark Result, as shown in Figure 2.
- the user can select the signal line that currently needs to add a measuring point according to all the signal lines that are fail indicated on the above-mentioned display interface, and generate a corresponding selection command.
- the detection tool can control the height of the signal line.
- the error message of adding error pops up, the user can delete it and add it again, if it is less than or equal to the line length specification, pop up the correct message to add, continue to click the next signal line to perform the same operation until the selected signal line All measuring points are added.
- the user can also output a review instruction, so that the detection tool will re-check the selected signal line after receiving the review instruction.
- the information corresponding to the signal line will be displayed on the display interface, and the user can continue to improve the design. If all meet the design requirements, a prompt message corresponding to all the design requirements will pop up.
- the measurement point information and inspection result information of the selected signal line can be stored in a file, which is convenient for subsequent reference and facilitates the SI tester to locate the test point.
- the PCB file is first obtained by the detection tool, so as to determine the information of all signal lines on the PCB, to ensure the comprehensiveness of the detection of the signal line test points, and no omission phenomenon occurs, and then the detection tool selects the instruction according to the signal line Determine the target signal line and the receiving end chip with the SI information, and select the position of the measuring point on the signal line according to the line length specification of the measuring point from the receiving end chip to reduce the impact on the signal integrity performance, and the signal is completed by the inspection tool.
- Test point detection compared with manual detection, can reduce a lot of man-hours, improve detection efficiency and reliability, and facilitate SI engineer wiring inspection, layout engineer wiring design, and SI test engineer back-to-board testing, so as to ensure signal SI quality and thus ensure The system is reliable and stable, with a wide range of applications and a high degree of promotion.
- FIG. 3 is a schematic structural diagram of a signal test point detection system provided by the application, applied to a detection tool, and the signal test point detection system includes:
- the determining module 2 is used to receive the signal line selection instruction and SI information, and determine the signal line and the receiving end chip in the PCB file according to the signal line selection instruction and the SI information;
- Adding module 3 is used to obtain the test information of the signal line, and add the test point on the signal line according to the test information and the trace length specification of the test point from the receiving end chip.
- the PCB file is first obtained by the detection tool, so as to determine the information of all signal lines on the PCB, to ensure the comprehensiveness of the detection of the signal line test points, and no omission phenomenon occurs, and then the detection tool selects the instruction according to the signal line Determine the target signal line and the receiving end chip with the SI information, and select the position of the measuring point on the signal line according to the line length specification of the measuring point from the receiving end chip to reduce the impact on the signal integrity performance, and the signal is completed by the inspection tool.
- Test point detection compared with manual detection, can reduce a lot of man-hours, improve detection efficiency and reliability, and facilitate SI engineer wiring inspection, layout engineer wiring design, and SI test engineer back-to-board testing, so as to ensure signal SI quality and thus ensure The system is reliable and stable, with a wide range of applications and a high degree of promotion.
- the test information includes one or more of ID information, connection level information, layer-change via information, measurement point information, and connected chip pin information.
- the signal test point detection system further includes:
- the marking module is used to generate the marking information of the signal line according to the test information and/or the specification of the trace length, and store the marking information in the database.
- the process of generating the marking information of the signal line according to the test information and/or the trace length specification specifically includes:
- the first mark is generated
- the trace length from the via hole to the receiver chip is greater than the trace length specification, and the trace length from the measuring point to the receiver chip is greater than the trace length specification, the first mark is generated.
- the signal test point detection system further includes:
- the display module is used to display the signal lines corresponding to all the first marks.
- the signal test point detection system further includes:
- the processing module is used to determine the measuring point addition area on the signal line according to the position of the receiver chip;
- adding module 3 is specifically used for:
- the measuring point is added to the measuring point adding area, and the test information of the signal line is updated.
- the signal test point detection system further includes:
- the result generating module is used for generating information corresponding to the detection result of the signal line.
- an electronic device comprising:
- the processor is configured to implement the steps of the signal test point detection method described in any one of the above embodiments when executing the computer program.
- the electronic device provided by the present application has the same beneficial effects as the above-mentioned signal test point detection method.
- the present application also provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the method for detecting a signal test point as described in any one of the above embodiments is implemented A step of.
- the computer-readable storage medium provided by the present application has the same beneficial effects as the above-mentioned signal test point detection method.
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Abstract
一种信号测试点检测方法、系统、电子设备及计算机可读存储介质，应用于检测工具，该信号测试点检测方法包括：获取PCB文件(S101)；接收信号线选择指令及SI信息，根据信号线选择指令及SI信息在PCB文件中确定信号线及接收端芯片(S102)；获取信号线的测试信息，根据测试信息及测点距离接收端芯片的走线长度规范在信号线上添加测点(S103)。该方法能够减少对信号完整性性能的影响，且由检测工具完成信号测试点检测，相较于人工检测，可以减少大量工时，提高了检测效率及可靠性。
Description
本申请要求于2020年07月14日提交中国专利局、申请号为202010674399.7、发明名称为“一种信号测试点检测方法、系统及相关组件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本申请涉及信号检测领域，特别涉及一种信号测试点检测方法、系统及相关组件。
在服务器、存储器等研发中，为保证硬件系统正常运行，信号测试是必不可少的一环。但是某些情况信号测试无法进行，比如某些需要示波器进行点测的信号，PCB(Printed Circuit Board，印制电路板)上如果走线和芯片设计在了同一层，没有打换层过孔也没有在走线上添加测试点的，那么示波器就无法点测。基于此，需要人工汇总需要示波器进行点测的信号，并在信号线上确定测点，根据SI的要求进行PCB设计，但是考虑到由于添加测点会降低信号完整性性能，且添加测点的位置可能需要多次尝试以满足实际工程需要，人工设计及检查繁琐且会有遗漏出现，降低测试效率及可靠性。
因此，如何提供一种解决上述技术问题的方案是本领域技术人员目前需要解决的问题。
发明内容
本申请的目的是提供一种信号测试点检测方法、系统、电子设备及计算机可读存储介质，能够减少对信号完整性性能的影响，且由检测工具完成信号测试点检测，相较于人工检测，可以减少大量工时，提高了检测效率及可靠性。
为解决上述技术问题，本申请提供了一种信号测试点检测方法，应用 于检测工具，包括：
获取PCB文件；
接收信号线选择指令及SI信息，根据所述信号线选择指令及所述SI信息在所述PCB文件中确定信号线及接收端芯片；
获取所述信号线的测试信息，根据所述测试信息及测点距离所述接收端芯片的走线长度规范在所述信号线上添加测点。
优选的，所述测试信息包括ID信息、连接层面信息、换层过孔信息、测点信息、连接的芯片管脚信息中的一种或多种。
优选的，该信号测试点检测方法还包括：
根据所述测试信息和/或所述走线长度规范生成所述信号线的标记信息，并将所述标记信息存储到数据库。
优选的，所述根据所述测试信息和/或所述走线长度规范生成所述信号线的标记信息的过程具体包括：
当所述换层过孔信息为0，且无测点，生成第一标记；
当所述换层过孔信息为0，且测点到所述接收端芯片的走线长度大于所述走线长度规范，生成所述第一标记；
当所述换层过孔信息不为0、过孔距离所述接收端芯片的走线长度大于所述走线长度规范、且测点到所述接收端芯片的走线长度大于所述走线长度规范，生成所述第一标记。
优选的，该信号测试点检测方法还包括：
显示所有所述第一标记对应的信号线。
优选的，该信号测试点检测方法还包括：
根据所述接收端芯片的位置确定所述信号线上的测点添加区；
相应的，所述根据所述测试信息及测点距离所述接收端芯片的走线长度规范在所述信号线上添加测点的过程具体包括：
根据所述测试信息及测点距离所述接收端芯片的走线长度规范在所述测点添加区上添加测点，并更新所述信号线的测试信息。
优选的，该信号测试点检测方法还包括：
生成与所述信号线的检测结果对应的信息。
为解决上述技术问题，本申请还提供了一种信号测试点检测系统，应用于检测工具，包括：
获取模块，用于获取PCB文件；
确定模块，用于接收信号线选择指令及SI信息，根据所述信号线选择指令及所述SI信息在所述PCB文件中确定信号线及接收端芯片；
添加模块，用于获取所述信号线的测试信息，根据所述测试信息及测点距离所述接收端芯片的走线长度规范在所述信号线上添加测点。
为解决上述技术问题，本申请还提供了一种电子设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行所述计算机程序时实现如上文任意一项所述的信号测试点检测方法的步骤。
为解决上述技术问题，本申请还提供了一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如上文任意一项所述的信号测试点检测方法的步骤。
本申请提供了一种信号测试点检测方法，首先通过检测工具获取PCB文件，从而确定PCB上所有信号线的信息，保证对信号线测试点检测的全面性，不会出现遗漏现象，然后该检测工具根据信号线选择指令和SI信息确定目标信号线及接收端芯片，在该信号线上按照测点距离接收端芯片的走线长度规范选择测点的位置，减少对信号完整性性能的影响，且由检测工具完成信号测试点检测，相较于人工检测，可以减少大量工时，提高了检测效率及可靠性。本申请还提供了一种信号测试点检测系统、电子设备及计算机可读存储介质，具有和上述信号测试点检测方法相同的有益效果。
为了更清楚地说明本申请实施例，下面将对实施例中所需要使用的附图做简单的介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请所提供的一种信号测试点检测方法的步骤流程图；
图2为本申请所提供的一种检测工具显示界面的示意图；
图3为本申请所提供的一种信号测试点检测系统的结构示意图。
本申请的核心是提供一种信号测试点检测方法、系统、电子设备及计算机可读存储介质，能够减少对信号完整性性能的影响，且由检测工具完成信号测试点检测，相较于人工检测，可以减少大量工时，提高了检测效率及可靠性。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参照图1，图1为本申请所提供的一种信号测试点检测方法的步骤流程图，应用于检测工具，该信号测试点检测方法包括：
S101：获取PCB文件；
S102：接收信号线选择指令及SI(Signal Integrity，信号完整性)信息，根据信号线选择指令及SI信息在PCB文件中确定信号线及接收端芯片；
具体的，当本申请的检测工具运行时，可以获取PCB文件，从而获取该PCB的所有信息，如信号线信息、PCB层面信息、过孔信息等。用户可以输入信号线选择指令，信号线选择指令可以包括信号线对应的关键字，以便检测工具根据关键字过滤出用户选择的信号线，进行后续的检测。当然，信号线选择指令也可以包括完整的信号线名称，检测工具根据完整的信号线名称选择信号线，选择完信号线后，检测工具输出该信号线连接的芯片信息，可以理解的是，每一信号线可以连接一个或多个芯片，在设置测点时，需要分别设置，因此可根据SI信息确定当前的接收端芯片。在确定信号线和接收端芯片后，用户输入测点距离接收端芯片的走线长度规范，以便检测工具在接收到该走线长度规范后进行后续的检测操作。
S103：获取信号线的测试信息，根据测试信息及测点距离接收端芯片的走线长度规范在信号线上添加测点。
具体的，在确定信号线后，获取该信号线的测试信息，测试信息包括但不限于其ID信息，层面信息、换层过孔信息(连接层面、坐标等)、测点信息(层面、坐标等)、连接的芯片管脚等信息。
作为一种优选的实施例，该信号测试点检测方法还包括：
根据测试信息和/或走线长度规范生成信号线的标记信息，并将标记信息存储到数据库。
作为一种优选的实施例，根据测试信息和/或走线长度规范生成信号线的标记信息的过程具体包括：
当换层过孔信息为0，且无测点，生成第一标记；
当换层过孔信息为0，且测点到接收端芯片的走线长度大于走线长度规范，生成第一标记；
当换层过孔信息不为0、过孔距离接收端芯片的走线长度大于走线长度规范、且测点到接收端芯片的走线长度大于走线长度规范，生成第一标记。
具体的，换层过孔信息具体可以指换层过孔数量，如果换层过孔数量为0，说明走线和芯片在同一层，检查是否有测点，如果没有，标记“via 0,testpoint 0，Fail”，记录到数据库，如果有测点，查询测点层面，获取测点到接收芯片的走线长度，并与走线长度规范进行比较，如果大于走线长度规范，标记为“via 0,testpoint 1,Fail”，记录到数据库中，如果小于或等于走线长度规范，标记为“via 0,testpoint 1,Pass”，记录到数据库中。如果过孔数量不为0，查询过孔距离接收端芯片的走线长度，并与走线长度规范进行比较，如果小于或等于走线长度规范，标记为“via 1,Pass”，记录到数据库中。如果大于走线长度规范，继续检查测点信息，如果有，查询测点到接收芯片的走线长度，并与走线长度规范进行比较，如果大于走线长度规范，标记为“via 1,test 1,fail”，记录到数据库中。如果小于或等于走线长度规范，标记为“via 1,test 1,Pass”，记录到数据库中。上述标记中带有fail的标记即为第一标记。
经过上述检测后，作为一种优选的实施例，可以将标记为fail的所有信号线的信息显示在显示界面，便于用户查看及后续添加测试点，显示界面上显示的信息可以包括但不限于信号线名称Net Name、层面Layer、测点Testpoint，过孔信息Via，走线长度Length，标记Result，参照图2所示。
进一步的，用户可以根据上述显示界面上提示的所有为fail的信号线选择当前需要添加测点的信号线，生成对应的选择指令，检测工具在接收到该选择指令后，可以控制该信号线高亮，并定位到接收端附近，即确定该信号线上的测点添加区，在该测点添加区上添加测点，并计算此测点到接收芯片引脚的走线长度，如果大于走线长度规范，弹出添加错误的提示信息，用户可删掉重新添加，如果小于或等于走线长度规范，弹出添加正确的提示信息，继续点击下一个信号线进行同样操作，直至所选择的信号线全部完成测点添加。
作为一种优选的实施例，为保证测点添加的可靠性，用户还可以输出复核指令，以便检测工具在接收到该复核指令后，对所选择的信号线重新检查一遍，如有不符合的会将该信号线对应的信息显示在显示界面中，用户可继续完善设计，如全部符合设计要求，则会弹出与全部符合设计要求对应的提示信息。
作为一种优选的实施例，可以将所选择的信号线的测点信息、检查结果信息存储到文档中，便于后续查阅，方便SI测试人员对测试点的定位。
可见，本实施例中首先通过检测工具获取PCB文件，从而确定PCB上所有信号线的信息，保证对信号线测试点检测的全面性，不会出现遗漏现象，然后该检测工具根据信号线选择指令和SI信息确定目标信号线及接收端芯片，在该信号线上按照测点距离接收端芯片的走线长度规范选择测点的位置，减少对信号完整性性能的影响，且由检测工具完成信号测试点检测，相较于人工检测，可以减少大量工时，提高了检测效率及可靠性，同时便于SI工程师布线检视、layout工程师布线设计、SI测试工程师回板测试，从而保证信号SI质量，进而保证系统的可靠及稳定，使用范围广，推广度高。
请参照图3，图3为本申请所提供的一种信号测试点检测系统的结构示意图，应用于检测工具，该信号测试点检测系统包括：
获取模块1，用于获取PCB文件；
确定模块2，用于接收信号线选择指令及SI信息，根据信号线选择指令及SI信息在PCB文件中确定信号线及接收端芯片；
添加模块3，用于获取信号线的测试信息，根据测试信息及测点距离接收端芯片的走线长度规范在信号线上添加测点。
可见，本实施例中首先通过检测工具获取PCB文件，从而确定PCB上所有信号线的信息，保证对信号线测试点检测的全面性，不会出现遗漏现象，然后该检测工具根据信号线选择指令和SI信息确定目标信号线及接收端芯片，在该信号线上按照测点距离接收端芯片的走线长度规范选择测点的位置，减少对信号完整性性能的影响，且由检测工具完成信号测试点检测，相较于人工检测，可以减少大量工时，提高了检测效率及可靠性，同时便于SI工程师布线检视、layout工程师布线设计、SI测试工程师回板测试，从而保证信号SI质量，进而保证系统的可靠及稳定，使用范围广，推广度高。
作为一种优选的实施例，测试信息包括ID信息、连接层面信息、换层过孔信息、测点信息、连接的芯片管脚信息中的一种或多种。
作为一种优选的实施例，该信号测试点检测系统还包括：
标记模块，用于根据测试信息和/或走线长度规范生成信号线的标记信息，并将标记信息存储到数据库。
作为一种优选的实施例，根据测试信息和/或走线长度规范生成信号线的标记信息的过程具体包括：
当换层过孔信息为0，且无测点，生成第一标记；
当换层过孔信息为0，且测点到接收端芯片的走线长度大于走线长度规范，生成第一标记；
当换层过孔信息不为0、过孔距离接收端芯片的走线长度大于走线长度规范、且测点到接收端芯片的走线长度大于走线长度规范，生成第一标记。
作为一种优选的实施例，该信号测试点检测系统还包括：
显示模块，用于显示所有第一标记对应的信号线。
作为一种优选的实施例，该信号测试点检测系统还包括：
处理模块，用于根据接收端芯片的位置确定信号线上的测点添加区；
相应的，添加模块3具体用于：
根据测试信息及测点距离接收端芯片的走线长度规范在测点添加区上添加测点，并更新信号线的测试信息。
作为一种优选的实施例，该信号测试点检测系统还包括：
结果生成模块，用于生成与信号线的检测结果对应的信息。
另一方面，本申请还提供了一种电子设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行计算机程序时实现如上文任意一个实施例所描述的信号测试点检测方法的步骤。
对于本申请所提供的一种电子设备的介绍请参照上述实施例，本申请在此不再赘述。
本申请所提供的一种电子设备具有和上述信号测试点检测方法相同的有益效果。
另一方面，本申请还提供了一种计算机可读存储介质，计算机可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现如上文任意一个实施例所描述的信号测试点检测方法的步骤。
对于本申请所提供的一种计算机可读存储介质的介绍请参照上述实施例，本申请在此不再赘述。
本申请所提供的一种计算机可读存储介质具有和上述信号测试点检测方法相同的有益效果。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要 求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的状况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其他实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。
Claims (10)
- 一种信号测试点检测方法，其特征在于，应用于检测工具，包括：获取PCB文件；接收信号线选择指令及SI信息，根据所述信号线选择指令及所述SI信息在所述PCB文件中确定信号线及接收端芯片；获取所述信号线的测试信息，根据所述测试信息及测点距离所述接收端芯片的走线长度规范在所述信号线上添加测点。
- 根据权利要求1所述的信号测试点检测方法，其特征在于，所述测试信息包括ID信息、连接层面信息、换层过孔信息、测点信息、连接的芯片管脚信息中的一种或多种。
- 根据权利要求2所述的信号测试点检测方法，其特征在于，该信号测试点检测方法还包括：根据所述测试信息和/或所述走线长度规范生成所述信号线的标记信息，并将所述标记信息存储到数据库。
- 根据权利要求3所述的信号测试点检测方法，其特征在于，所述根据所述测试信息和/或所述走线长度规范生成所述信号线的标记信息的过程具体包括：当所述换层过孔信息为0，且无测点，生成第一标记；当所述换层过孔信息为0，且测点到所述接收端芯片的走线长度大于所述走线长度规范，生成所述第一标记；当所述换层过孔信息不为0、过孔距离所述接收端芯片的走线长度大于所述走线长度规范、且测点到所述接收端芯片的走线长度大于所述走线长度规范，生成所述第一标记。
- 根据权利要求4所述的信号测试点检测方法，其特征在于，该信号测试点检测方法还包括：显示所有所述第一标记对应的信号线。
- 根据权利要求1所述的信号测试点检测方法，其特征在于，该信号测试点检测方法还包括：根据所述接收端芯片的位置确定所述信号线上的测点添加区；相应的，所述根据所述测试信息及测点距离所述接收端芯片的走线长度规范在所述信号线上添加测点的过程具体包括：根据所述测试信息及测点距离所述接收端芯片的走线长度规范在所述测点添加区上添加测点，并更新所述信号线的测试信息。
- 根据权利要求1-6任意一项所述的信号测试点检测方法，其特征在于，该信号测试点检测方法还包括：生成与所述信号线的检测结果对应的信息。
- 一种信号测试点检测系统，其特征在于，应用于检测工具，包括：获取模块，用于获取PCB文件；确定模块，用于接收信号线选择指令及SI信息，根据所述信号线选择指令及所述SI信息在所述PCB文件中确定信号线及接收端芯片；添加模块，用于获取所述信号线的测试信息，根据所述测试信息及测点距离所述接收端芯片的走线长度规范在所述信号线上添加测点。
- 一种电子设备，其特征在于，包括：存储器，用于存储计算机程序；处理器，用于执行所述计算机程序时实现如权利要求1-7任意一项所述的信号测试点检测方法的步骤。
- 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1-7任意一项所述的信号测试点检测方法的步骤。
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| CN101201861A (zh) * | 2006-12-14 | 2008-06-18 | 英业达股份有限公司 | 自动检查测试点的方法与电脑可读取存储媒介 |
| CN101430722A (zh) * | 2007-11-09 | 2009-05-13 | 英业达股份有限公司 | 测试点布设检测方法 |
| CN101470167A (zh) * | 2007-12-28 | 2009-07-01 | 英业达股份有限公司 | 测试点的配置方法 |
| CN101620565A (zh) * | 2008-07-04 | 2010-01-06 | 福建升腾资讯有限公司 | 终端系统的功能自动化测试方法 |
| US20120124544A1 (en) * | 2010-11-17 | 2012-05-17 | Inventec Corporation | Method for setting test point |
| US20160109517A1 (en) * | 2014-10-16 | 2016-04-21 | Mentor Graphics Corporation | Test Point Insertion For Low Test Pattern Counts |
| JP2018132877A (ja) * | 2017-02-14 | 2018-08-23 | Ｎｅｃプラットフォームズ株式会社 | プリント基板の測定点設定システム、測定点設定方法及び測定点設定プログラム |
| CN111880076A (zh) * | 2020-07-14 | 2020-11-03 | 苏州浪潮智能科技有限公司 | 一种信号测试点检测方法、系统及相关组件 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115291075A (zh) * | 2022-06-24 | 2022-11-04 | 杭州未名信科科技有限公司 | 一种高速信号质量的测试方法和测试装置 |
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| CN111880076A (zh) | 2020-11-03 |
| CN111880076B (zh) | 2022-11-18 |
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