WO2022011769A1 - 像素驱动电路及其驱动方法、显示面板 - Google Patents

像素驱动电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2022011769A1
WO2022011769A1 PCT/CN2020/109554 CN2020109554W WO2022011769A1 WO 2022011769 A1 WO2022011769 A1 WO 2022011769A1 CN 2020109554 W CN2020109554 W CN 2020109554W WO 2022011769 A1 WO2022011769 A1 WO 2022011769A1
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WIPO (PCT)
Prior art keywords
transistor
compensation
gate
light
driving circuit
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Application number
PCT/CN2020/109554
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English (en)
French (fr)
Inventor
张淑媛
赵晟焕
戴超
Original Assignee
武汉华星光电半导体显示技术有限公司
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/262,312 priority Critical patent/US11436977B2/en
Publication of WO2022011769A1 publication Critical patent/WO2022011769A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • the present application relates to the field of display technology, and in particular, to a pixel driving circuit and a driving method thereof, and a display panel.
  • the backplane made of low-temperature polysilicon technology can make the display panel achieve a higher pixel density, due to the large leakage current of silicon-based transistors, when the display panel uses a low refresh frequency, the display effect of the display panel is poor. Display quality.
  • Embodiments of the present application provide a pixel driving circuit, a driving method thereof, and a display panel, which can maintain a stable gate voltage of a driving transistor, reduce the influence of the source or drain of the driving transistor on the gate of the driving transistor, and improve the The display effect of the display panel.
  • An embodiment of the present application provides a pixel driving circuit, including: a light-emitting device, a driving transistor, and a compensation module; the compensation module at least includes: an initialization transistor and a compensation transistor;
  • the initialization transistor is used for responding to the first scan signal and transmitting a potential variable signal to the gate of the driving transistor to initialize the gate voltage of the driving transistor;
  • the compensation transistor is used for responding to the compensation control signal and transmitting the data signal with the compensation threshold voltage to the gate of the driving transistor;
  • the type of the initialization transistor is different from that of the compensation transistor; the potential variable signal dynamically compensates the gate voltage of the driving transistor in the light-emitting phase.
  • the initialization transistor is one of a silicon transistor or an oxide transistor
  • the compensation transistor is the other of a silicon transistor or an oxide transistor.
  • the initialization transistor is a silicon transistor and the compensation transistor is an oxide transistor.
  • the initialization transistor is a P-type transistor; the compensation transistor is an N-type transistor.
  • the potential variable signal is a constant low level signal when the initialization transistor responds to the first scan signal and the compensation transistor responds to the compensation control signal, and is continuous during the light-emitting phase rising signal.
  • the pixel driving circuit further includes a data writing module for responding to the second scan signal and transmitting the data signal to the source or drain of the driving transistor.
  • the pixel driving circuit further includes a storage module for maintaining the gate voltage of the driving transistor.
  • the pixel driving circuit further includes a light-emitting control module, and the light-emitting control module is configured to control the light-emitting device to emit light in response to a light-emitting control signal.
  • the pixel driving circuit further includes a reset module for responding to the second scan signal and transmitting the reset signal to the anode of the light emitting device.
  • the reset signal is a constant signal.
  • the light emitting device includes one of an organic light emitting diode, a sub-millimeter light emitting diode, and a micro light emitting diode.
  • the present application also provides a driving method for a pixel driving circuit, which is used for driving the pixel driving circuit.
  • the driving method includes:
  • the initialization transistor of the compensation module responds to the first scan signal, and the potential variable signal is transmitted to the gate of the driving transistor to initialize the gate voltage of the driving transistor;
  • the compensation transistor of the compensation module responds to the compensation control signal, and transmits the data signal with the compensation threshold voltage to the gate of the driving transistor to compensate the threshold voltage of the driving transistor;
  • the driving transistor drives the light-emitting device to emit light, and the potential variable signal dynamically compensates the gate voltage of the driving transistor.
  • the potential variable signal is a constant signal in the initialization stage and the compensation stage, and the potential variable signal is continuous with the gate voltage of the driving transistor before compensation in the light-emitting stage rising or falling continuously.
  • the present application also provides a display panel, comprising: a plurality of pixels and a pixel driving circuit for controlling the pixels to emit light;
  • the pixel driving circuit includes: a light-emitting device forming the pixel, configured to provide driving for the light-emitting device a current driving transistor, a potential variable signal line for providing a potential variable signal, an initialization transistor, and a compensation transistor; the initialization transistor and the compensation transistor have semiconductor layers of different materials;
  • the gate of the compensation transistor is connected to the compensation control signal line, one of the source or the drain of the compensation transistor is connected to the gate of the driving transistor, and the other of the source or the drain is connected to the drive transistor. one of the source or drain of the drive transistor is connected;
  • the gate of the initialization transistor is connected to the first scan signal line, one of the source or drain of the initialization transistor is connected to the potential variable signal line, and the other of the source or drain is connected to the The gate connection of the drive transistor.
  • the carrier mobilities of the semiconductor layers of the initialization transistor and the compensation transistor are different; the carrier mobility of the semiconductor layer of the initialization transistor is greater than that of the compensation transistor. or, the carrier mobility of the semiconductor layer of the initialization transistor is smaller than the carrier mobility of the semiconductor layer of the compensation transistor.
  • the pixel driving circuit further includes:
  • the gate of the data writing transistor is connected to the second scan signal line, one of the source or the drain of the data writing transistor is connected to the data signal line, and the source or the drain is connected to the data signal line.
  • the other one is connected to one of the source or drain of the drive transistor;
  • the upper plate of the storage capacitor is connected to the first voltage terminal
  • the lower plate and the source or drain of the initialization transistor are connected to one of the gates of the driving transistor and the source of the compensation transistor
  • One of the electrode or the drain is connected to the gate of the drive transistor and the gate of the drive transistor is connected.
  • the pixel driving circuit further includes:
  • a first switch transistor the gate of the first switch transistor is connected to the light-emitting control signal line, one of the source or the drain of the first switch transistor is connected to the first voltage terminal, and the source or the drain is connected to the first voltage terminal. The other one is connected to one of the source or drain of the drive transistor;
  • a second switching transistor the gate of the second switching transistor is connected to the light-emitting control signal line, and one of the source or drain of the second switching transistor is connected to the source or drain of the driving transistor One of the source or drain is connected to the anode of the light emitting device.
  • the pixel driving circuit further includes:
  • the gate of the reset transistor is connected to the second scan signal line, one of the source or drain of the reset transistor is connected to the reset signal line, and the other of the source or drain is connected to the second scan signal line
  • the anode of the light-emitting device is connected, and the reset transistor and the initialization transistor have a semiconductor layer of the same material.
  • the display panel further includes a conductive layer located between the pixel driving circuit and the light emitting device, in a top view, the conductive layer and the orthographic projection of the compensation transistor overlap, and the The conductive layer covers the compensation transistor.
  • the preparation material of the conductive layer includes at least one of gold, silver, copper, lithium, sodium, potassium, magnesium, aluminum, and zinc.
  • the pixel driving circuit includes: a light-emitting device, a driving transistor, and a compensation module; the compensation module at least includes: an initialization transistor and a a compensation transistor; the initialization transistor is used for responding to the first scan signal and transmitting a potential variable signal to the gate of the driving transistor to initialize the gate voltage of the driving transistor; the compensation transistor is used for responding to the compensation control signal and transmits a data signal with a compensated threshold voltage to the gate of the drive transistor; wherein the initialization transistor is of a different type from the compensation transistor; the potential variable signal dynamically compensates the drive transistor in the light-emitting phase
  • the gate voltage is used to maintain the stability of the gate voltage of the driving transistor in the light-emitting stage, and reduce the influence of the source or drain of the driving transistor on the gate of the driving transistor, which can improve the display effect of the display panel.
  • FIG. 1 is a schematic diagram of a pixel driving circuit provided by an embodiment of the present application
  • 2A-2B are schematic structural diagrams of pixel driving circuits provided by embodiments of the present application.
  • 3A is a working timing diagram of the pixel driving circuit provided in FIG. 2A;
  • 3B is a working timing diagram of the pixel driving circuit provided in FIG. 2B;
  • 3C is a working timing diagram of a potential variable signal and a gate voltage of a driving transistor provided by an embodiment of the present application;
  • 4A to 4C are schematic structural diagrams of a display panel according to an embodiment of the present application.
  • 5A to 5B are schematic structural diagrams of pixel driving circuits according to embodiments of the present application.
  • FIG. 1 is a schematic diagram of a pixel driving circuit provided by an embodiment of the present application, as shown in FIGS. 2A to 2B , which are schematic structural diagrams of a pixel driving circuit provided by an embodiment of the present application;
  • FIG. 3A which is the working timing diagram of the pixel driving circuit provided in FIG. 2A ;
  • FIG. 3B which is the working timing diagram of the pixel driving circuit provided in FIG. 2B ;
  • FIG. 3C which is the potential variable signal provided by the embodiment of the application
  • the operating timing diagram of the gate voltage of the drive transistor is a schematic diagram of a pixel driving circuit provided by an embodiment of the present application.
  • FIGS. 2A to 2B are schematic structural diagrams of a pixel driving circuit provided by an embodiment of the present application
  • FIG. 3A which is the working timing diagram of the pixel driving circuit provided in FIG. 2A
  • FIG. 3B which is the working timing diagram of the pixel driving circuit provided in FIG. 2B
  • FIG. 3C which is the potential variable
  • An embodiment of the present application provides a pixel driving circuit, including: a light-emitting device D1, a driving transistor T1, and a compensation module 100; the compensation module 100 at least includes: an initialization transistor T2 and a compensation transistor T3;
  • the initialization transistor T2 is used for responding to the first scan signal Scan1 and transmitting the variable potential signal VI1 to the gate of the driving transistor T1 to initialize the gate voltage Vg of the driving transistor T1;
  • the compensation transistor T3 is used for responding to the compensation control signal Scan3 and transmitting the data signal Vdata with the compensation threshold voltage to the gate of the driving transistor T1;
  • the initialization transistor T2 and the compensation transistor T3 are of different types; the potential variable signal VI1 dynamically compensates the gate voltage Vg of the driving transistor T1 in the light-emitting stage t3, so as to maintain the The gate voltage Vg of the driving transistor T1 is stable, and the influence of the source or drain of the driving transistor T1 on the gate of the driving transistor T1 is reduced.
  • the initialization transistor T2 is one of a silicon transistor or an oxide transistor
  • the compensation transistor T3 is the other of a silicon transistor or an oxide transistor.
  • the compensation transistor T3 can be used to reduce the source or drain (point B) of the driving transistor T1.
  • point B One of the effects on the gate (Q point) voltage Vg of the drive transistor T1.
  • the compensation transistor T3 will have a certain leakage current.
  • the leakage current characteristics of the initialization transistor T2 and the variable potential signal VI1 are used.
  • the initialization transistor T2 is an oxide transistor
  • the compensation transistor T3 is a silicon transistor; but since the leakage current of the silicon transistor is greater than that of the oxide transistor, the initialization transistor T2 is an oxide transistor.
  • the compensation transistor T3 is a silicon transistor, the leakage current of the compensation transistor T3 is larger than that of the initialization transistor T2, which affects the effect of the variable potential signal VI1 on the gate voltage Vg of the driving transistor T1. Compensation effect.
  • the initialization transistor T2 is a silicon transistor
  • the compensation transistor T3 is an oxide transistor
  • the leakage current of the compensation transistor T3 is smaller than the Initialize the characteristics of the leakage current of the transistor T2, reduce the influence of one of the source or drain (point B) of the driving transistor T1 on the voltage Vg of the gate (point Q) of the driving transistor T1, and use the initialization
  • the transistor T2 has the characteristics of large leakage current, and the influence of the leakage current of the compensation transistor T3 on the driving transistor T1 is reduced by the variable potential signal VI1, so that the gate voltage Vg of the driving transistor T1 is maintained It is constant to ensure stable light emission of the light-emitting device D1.
  • the initialization transistor T2 and the compensation transistor T3 can be either P-type transistors or N-type transistors; further, since P-type oxide transistors are restricted by current P-type oxide materials, high-quality P-type transistors can be prepared. Oxide transistors are also restricted. Therefore, on the basis of considering the prior art, when the initialization transistor T2 or the compensation transistor T3 is an oxide transistor, an N-type oxide transistor is selected. However, it is not intended to limit the oxide transistor in this application to be an N-type transistor, and the oxide transistor in this application can also be a P-type transistor.
  • the silicon transistors include monocrystalline silicon transistors, polycrystalline silicon transistors, microcrystalline silicon transistors, amorphous silicon or other transistors containing silicon; the oxide transistors include metals such as zinc, indium, gallium, tin or titanium, and the like. oxide transistors.
  • the polysilicon transistors include low temperature polysilicon transistors; the oxide transistors include oxide transistors containing zinc oxide, zinc tin oxide, zinc indium oxide, indium oxide, titanium oxide, indium gallium zinc oxide, indium zinc tin oxide, etc. .
  • the pixel driving circuit further includes a data writing module 200, the data writing module 200 is used for responding to the second scan signal Scan2 and transmitting the data signal Vdata to the The source or drain of the driving transistor T1.
  • the compensation transistor T3 when the compensation transistor T3 adopts the same type of transistor as the data writing transistor T4, the compensation transistor T3 can directly use the second scan signal Scan2 to replace the compensation control signal Scan3.
  • the data writing module 200 includes a data writing transistor T4, the gate of the data writing transistor T4 is connected to the second scan signal Scan2, the data signal Vdata It is transmitted to the first electrode of the data writing transistor T4, and the second electrode of the data writing transistor T4 is connected to the first electrode of the driving transistor T1.
  • the pixel driving circuit further includes a storage module 300 for maintaining the gate voltage Vg of the driving transistor T1.
  • the storage module 300 includes a storage capacitor C1, one end of the storage capacitor C1 is connected to the first voltage terminal Vdd, and the other end of the storage capacitor C1 is connected to the driving transistor T1
  • the gate of , the second pole of the initialization transistor T2, and the first pole of the compensation transistor T3 are connected.
  • the upper plate of the storage capacitor C1 is connected to the first voltage terminal Vdd
  • the lower plate of the storage capacitor C2 is connected to the gate of the driving transistor T1 and the second electrode of the initialization transistor T2 .
  • the first pole of the compensation transistor T3 is connected.
  • the pixel driving circuit further includes a light-emitting control module 400, and the light-emitting control module 400 is configured to control the light-emitting device D1 to emit light in response to the light-emitting control signal EM.
  • the lighting control module 400 includes a first switching transistor T5 and a second switching transistor T6; the lighting control signal EM is transmitted to the gate of the first switching transistor T5 and the gate of the first switching transistor T5.
  • the gate of the second switch transistor T6 the first pole of the first switch transistor T5 is connected to the first voltage terminal Vdd, and the second pole of the first switch transistor T5 is connected to the first pole of the drive transistor T1.
  • One pole is connected; the first pole of the second switching transistor T6 is connected to the second pole of the driving transistor T1, and the second pole of the second switching transistor T6 is connected to the anode of the light emitting device D1.
  • the pixel driving circuit further includes a reset module 500 for responding to the second scan signal Scan2 and transmitting the reset signal VI2 to the anode of the light emitting device D1.
  • the reset module 500 includes a reset transistor T7; the second scan signal Scan2 is transmitted to the gate of the reset transistor T7, and the reset signal VI2 is transmitted to the reset transistor
  • the first pole of T7 and the second pole of the reset transistor T7 are connected to the anode of the light emitting device D1.
  • the reset signal VI2 is a constant signal; in the light-emitting stage t3, the required potential variable signal VI1 can be provided by the driving chip.
  • the types of the reset transistor T7 and the initialization transistor T2 may be different or the same. Specifically, in the pixel driving circuit shown in FIG. 2A , the reset transistor T7 and the initialization transistor T2 are of different types; further, the reset transistor T7 and the compensation transistor T3 are of the same type. In the pixel driving circuit shown in FIG. 2B , the reset transistor T7 and the initialization transistor T2 are of the same type; further, the reset transistor T7 and the compensation transistor T3 are of different types.
  • the light-emitting device D1 includes one of an organic light-emitting diode, a sub-millimeter light-emitting diode and a micro light-emitting diode.
  • the cathode of the light-emitting device D1 is connected to the second voltage terminal Vss as an example; in addition, the light-emitting device D1 can also use the anode to be connected to the first voltage terminal.
  • the form of Vdd is arranged in the pixel driving circuit, which will not be repeated here.
  • the first electrode of the present application can be one of the drain electrode or the source electrode, and correspondingly, the second electrode is the other one of the source electrode or the drain electrode.
  • the present application further provides a driving method for a pixel driving circuit, which is used for driving the pixel driving circuit.
  • the driving method includes:
  • the initialization transistor T2 of the compensation module 100 responds to the first scan signal Scan1, the potential variable signal VI1 is transmitted to the gate of the driving transistor T1, and the gate voltage of the driving transistor T1 is initialized Vg;
  • the compensation transistor T3 of the compensation module 100 responds to the compensation control signal Scan3, and transmits the data signal Vdata with the compensation threshold voltage to the gate of the driving transistor T1 to compensate the threshold voltage of the driving transistor T1 ;
  • the driving transistor T1 drives the light-emitting device D1 to emit light, and the variable potential signal VI1 dynamically compensates the gate voltage Vg of the driving transistor T1.
  • variable potential signal VI1 is a constant signal in the initialization phase t1 and the compensation phase t2, and the variable potential signal VI1 changes with the gate of the driving transistor T1 before compensation in the light-emitting phase t3
  • the voltage Vg continuously rises or falls continuously.
  • the potential variable signal VI1 is proportional to the gate voltage Vg of the driving transistor T1 before compensation in amplitude; In terms of timing, the variable potential signal VI1 continuously increases with the decrease of the gate voltage Vg of the driving transistor T1 before compensation, or continuously decreases with the increase of the gate voltage Vg of the driving transistor T1 before compensation, In order to keep the gate voltage Vg of the driving transistor T1 stable after compensation.
  • the required potential variable signal VI1 can be provided by the driving chip.
  • the amplitudes of the reset signal VI2 and the variable potential signal VI1 during the initialization phase t1 and the compensation phase t2 may be equal, or may not be equal, which will not be repeated here.
  • the driving transistor T1, the compensation transistor T3, the data writing transistor T4, the first switching transistor T5, the second switching transistor T6 and the reset transistor T7 is a P-type silicon transistor
  • the initialization transistor T2 is an N-type oxide transistor
  • the compensation transistor T3 and the data writing transistor T4 share the second scan signal Scan2 for example; in the Nth frame period (N Frame), including the initialization stage t1, the compensation stage t2 and the light-emitting stage t3;
  • the initialization transistor T2 responds to the first scan signal Scan1, the initialization transistor T2 is turned on, and the potential variable signal VI1 is transmitted to the gate of the driving transistor T1; the storage The lower plate of the capacitor C1 is connected to the variable potential signal VI1, the voltage difference between the upper plate and the lower plate of the storage capacitor C1 becomes larger, the storage capacitor C1 is charged, and the gate of the driving transistor T1 The voltage Vg is reset to the low-level signal Vini by the variable potential signal VI1, and the driving transistor T1 is turned on to realize the initialization of the driving transistor T1.
  • the compensation transistor T3, the data writing transistor T4 and the reset transistor T7 are turned on in response to the second scan signal Scan2, and the data signal Vdata is transmitted to the driving transistor T1
  • the first pole (point A) the compensating transistor T3 is turned on so that the gate of the driving transistor T1 is connected to the second pole, and the data signal Vdata with the function of compensating the threshold voltage Vth is transmitted to the driving transistor T1
  • the existence of the storage capacitor C1 makes the gate voltage Vg of the driving transistor T1 gradually rise from Vini until the driving transistor T1 is fully turned on, and the storage capacitor C1 maintains the gate of the driving transistor T1 pole voltage Vg, so as to compensate the threshold voltage Vth of the driving transistor T1;
  • the conduction of the reset transistor T7 enables the reset signal VI2 to be transmitted to the anode of the light-emitting device D1, so as to realize the compensation of the light-emitting device Initialization of D1.
  • the first switching transistor T5 and the second switching transistor T6 are turned on in response to the light-emitting control signal EM, and the driving transistor T1 forms a driving current to drive the light-emitting device D1 to emit light;
  • the compensation transistor T3 in the off state reduces the influence of the second pole (point B) of the driving transistor T1 on the voltage Vg of the gate (point Q) of the driving transistor T1, using the initializing transistor T2 in the off state.
  • the leakage current characteristic and the potential variable signal VI1 dynamically compensate the influence on the gate voltage Vg of the driving transistor T1 caused by the leakage current of the compensation transistor T3, so that the gate voltage Vg of the driving transistor T1 is Keep stable; that is, Vg is kept at Vdata+Vth to ensure stable light emission of the light-emitting device D1.
  • the driving transistor T1, the initialization transistor T2, the data writing transistor T4, the first switching transistor T5, and the second switching transistor T6 and the reset transistor T7 is a P-type silicon transistor
  • the compensation transistor T3 is an N-type oxide transistor; in the Nth frame period (N Frame), including the initialization stage t1, the compensation stage t2 and the Lighting stage t3;
  • the initialization transistor T2 responds to the first scan signal Scan1, the initialization transistor T2 is turned on, and the potential variable signal VI1 is transmitted to the gate of the driving transistor T1; the storage The capacitor C1 is charged, the gate voltage Vg of the driving transistor T1 is reset to the low-level signal Vini by the variable potential signal VI1, the driving transistor T1 is turned on, and the initialization of the driving transistor T1 is realized.
  • the compensation transistor T3 is turned on in response to the compensation control signal Scan3, the data writing transistor T4 and the reset transistor T7 are turned on in response to the second scan signal Scan2, and the data signal is turned on Vdata is transmitted to the first pole (point A) of the driving transistor T1; the compensation transistor T3 is turned on so that the gate of the driving transistor T1 is connected to the second pole, and has the function of compensating the data signal of the threshold voltage Vth Vdata is transmitted to the gate of the driving transistor T1.
  • the existence of the storage capacitor C1 makes the gate voltage Vg of the driving transistor T1 gradually rise from Vini until the driving transistor T1 is fully turned on.
  • the first switching transistor T5 and the second switching transistor T6 are turned on in response to the light-emitting control signal EM, and the driving transistor T1 forms a driving current to drive the light-emitting device D1 to emit light;
  • the compensation transistor T3 in the off state reduces the influence of the second pole (point B) of the driving transistor T1 on the voltage Vg of the gate (point Q) of the driving transistor T1, using the initializing transistor T2 in the off state.
  • the leakage current characteristic and the potential variable signal VI1 dynamically compensate the influence on the gate voltage Vg of the driving transistor T1 caused by the leakage current of the compensation transistor T3, so that the gate voltage Vg of the driving transistor T1 is Keep stable; that is, Vg is kept at Vdata+Vth to ensure stable light emission of the light-emitting device D1.
  • variable potential signal VI1 is a constant low level signal when the initialization transistor T2 responds to the first scan signal Scan1 and the compensation transistor T3 responds to the compensation control signal Scan3, and is continuous in the light-emitting phase t3 rising signal.
  • the driving transistor T1 the data writing transistor T4 , the first switching transistor T5 , the second switching transistor T6 and the reset transistor are all used.
  • T7 is an example of a P-type transistor for illustration. Those skilled in the art can also replace it with an N-type transistor, and invert some of the corresponding signals to achieve the above functions, which will not be repeated here.
  • FIGS. 4A to 4C are schematic structural diagrams of a display panel provided by an embodiment of the present application
  • FIGS. 5A to 5B are schematic structural diagrams of a pixel driving circuit provided by an embodiment of the present application.
  • the present application further provides a display panel, comprising: a plurality of pixels 600 and a pixel driving circuit for controlling the pixels 600 to emit light;
  • the pixel driving circuit includes: a light emitting device D1 forming the pixels 600, and configured to transmit light to the pixels 600.
  • the light-emitting device D1 provides a drive transistor T1 for driving current, a potential variable signal line VI11 for providing a potential variable signal VI1, an initialization transistor T2, and a compensation transistor T3; the initialization transistor T2 and the compensation transistor T3 have different materials. semiconductor layer;
  • the gate of the compensation transistor T3 is connected to the compensation control signal line S3, one of the source or the drain of the compensation transistor T3 is connected to the gate of the driving transistor T1, and the other of the source or the drain is connected to the gate of the driving transistor T1. one is connected to one of the source or drain of the drive transistor T1;
  • the gate of the initialization transistor T2 is connected to the first scanning signal line S1
  • one of the source or the drain of the initialization transistor T2 is connected to the potential variable signal line VI11
  • the source or the drain is connected to the potential variable signal line VI11.
  • the other is connected to the gate of the driving transistor T1.
  • the carrier mobility of the semiconductor layers 601 and 602 of the initialization transistor T2 and the compensation transistor T3 are different; the carrier mobility of the semiconductor layer 601 of the initialization transistor T2 is greater than the compensation The carrier mobility of the semiconductor layer 602 of the transistor T3; or, the carrier mobility of the semiconductor layer 601 of the initialization transistor T2 is smaller than the carrier mobility of the semiconductor layer 602 of the compensation transistor T3 mobility.
  • the semiconductor layers 601 and 602 of the initialization transistor T2 and the compensation transistor T3 include P-type transistor semiconductors or N-type transistor semiconductors.
  • the semiconductor layer 601 of the initialization transistor T2 includes one of a silicon semiconductor layer or an oxide semiconductor layer
  • the semiconductor layer 602 of the compensation transistor T3 includes one of a silicon semiconductor layer or an oxide semiconductor layer. another.
  • the pixel driving circuit further includes:
  • the data writing transistor T4 the gate of the data writing transistor T4 is connected to the second scanning signal line S2, the source or the drain of the data writing transistor T4 is connected to the data signal line Data, the source the other of the electrode or the drain is connected to one of the source or the drain of the drive transistor T1;
  • Storage capacitor C1 the upper plate of the storage capacitor C1 is connected to the first voltage terminal Vdd, and the lower plate is connected to the source or drain of the initialization transistor T2.
  • One of the gates of the drive transistor T1, all The source or drain of the compensation transistor T3 is connected to one of the gates of the driving transistor T1 and the gate of the driving transistor T1.
  • the pixel driving circuit further includes: a first switch transistor T5, the gate of the first switch transistor T5 is connected to the light-emitting control signal line EM1, and one of the source or the drain of the first switch transistor T5 is connected to the light-emitting control signal line EM1.
  • the first voltage terminal Vdd is connected, and the other one of the source electrode or the drain electrode is connected to one of the source electrode or the drain electrode of the driving transistor T1;
  • a second switching transistor T6 the gate of the second switching transistor T6 is connected to the light-emitting control signal line EM1, and one of the source or the drain of the second switching transistor T6 is connected to the driving transistor T1 One of the source or drain is connected, and the other of the source or drain is connected to the anode of the light emitting device D1.
  • the pixel driving circuit further includes: a reset transistor T7, the gate of the reset transistor T7 is connected to the second scan signal line S2, and one of the source or the drain of the reset transistor T7 is connected to the reset signal line VI12 , the other of the source or drain is connected to the anode of the light emitting device D1.
  • the reset transistor T7 and the initialization transistor T2 may have semiconductor layers of different materials, or may have semiconductor layers of the same material, as shown in FIG. 5A and FIG. 5B .
  • the reset transistor T7 and the initialization transistor T2 have semiconductor layers of different materials; further, the reset transistor T7 and the compensation transistor T3 have semiconductor layers of the same material .
  • the reset transistor T7 and the initialization transistor T2 have semiconductor layers of the same material; further, the reset transistor T7 and the compensation transistor T3 have semiconductor layers of different materials Floor.
  • the compensation transistor T3 may be connected to the compensation control signal line S3 or the second scan signal line S2 to reduce the difficulty of the process.
  • the driving transistor T1, the data writing transistor T4, the first switching transistor T5, the second switching transistor T6 and the reset transistor are all used in the pixel driving circuit shown in FIGS. 5A-5B.
  • T7 is a P-type transistor, and those skilled in the art can also use an N-type transistor, which will not be repeated here.
  • the light-emitting device D1 adopts a common cathode connection method (that is, the cathode of the light-emitting device D1 is connected to the second voltage terminal Vss) as an example, and those skilled in the art also A common anode connection method may be adopted (that is, the anode of the light-emitting device D1 is connected to the first voltage terminal Vdd), which will not be repeated here.
  • the display panel further includes a substrate 700 , the pixel driving circuit is located on the substrate 700 , and the light-emitting device D1 is located at a distance from the pixel driving circuit away from the substrate 700 . side.
  • the substrate 700 includes a flexible substrate and a rigid substrate; the preparation material of the substrate 700 includes glass, quartz, ceramic, plastic or polymer resin, etc.; the polymer resin includes polyethersulfone, polyacrylate, polyarylene, etc. Ester, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyallyl ester, polyimide, polycarbonate, triacetate At least one of cellulose acetate propionate.
  • the display panel also includes:
  • the first semiconductor layer 701 is formed on the substrate 700, and the first semiconductor layer 701 includes a source region 701a, a channel region 701b, and a drain region 701c; the substrate material of the first semiconductor layer 701 may be It is an N-type or P-type silicon semiconductor.
  • the first insulating layer 702 covers the substrate 700 and the first semiconductor layer 701.
  • the materials for preparing the first insulating layer 702 include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, tantalum oxide, At least one of hafnium oxide, zirconium oxide, or titanium oxide.
  • a first gate 703 is formed on a side of the first insulating layer 702 away from the first semiconductor layer 701 and is aligned with the first semiconductor layer 701 .
  • the first gate 703 is connected to the first semiconductor layer 701
  • the source region 701a, the channel region 701b, and the drain region 701c constitute the source, gate and drain of the silicon transistor, and the first gate 703 is made of molybdenum, aluminum, silver, magnesium, At least one of gold, nickel, titanium, tantalum, tungsten (W), and the like. Further, the preparation material of the first gate electrode 703 is molybdenum.
  • a second insulating layer 704 is formed on the side of the first gate electrode 703 away from the substrate 700 , and the materials for preparing the second insulating layer 704 include silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. , at least one of tantalum oxide, hafnium oxide, zirconium oxide or titanium oxide.
  • a second gate layer is formed on the side of the second insulating layer 704 away from the first gate 703 , and the second gate layer includes a second gate arranged in alignment with the first gate 703 electrode 7051 and a third gate electrode 7052 disposed away from the second gate electrode 7051; the second gate electrode 7051 and the first gate electrode 703 constitute the upper electrode of the storage capacitor C1 in the pixel driving circuit plate and lower plate.
  • the preparation material of the second gate layer includes at least one of molybdenum, aluminum, silver, magnesium, gold, nickel, titanium, tantalum, tungsten (W) and the like. Further, the preparation material of the second gate layer is molybdenum.
  • a third insulating layer 706 is formed on the side of the second gate layer away from the substrate 700 , and the materials for preparing the third insulating layer 706 include silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. , at least one of tantalum oxide, hafnium oxide, zirconium oxide or titanium oxide.
  • the second semiconductor layer 707 is located on the side of the third insulating layer 706 away from the substrate 700.
  • the second semiconductor layer 707 includes a source region 707a, a channel region 707b, and a drain region 707c;
  • the material of the second semiconductor layer 707 is an oxide semiconductor, and the oxide semiconductor may include at least one of metal oxides of zinc, indium, gallium, tin or titanium; further, the oxide semiconductor may include zinc oxide , at least one of zinc tin oxide, zinc indium oxide, indium oxide, titanium oxide, indium gallium zinc oxide, indium zinc tin oxide, and the like.
  • the fourth insulating layer 708 is formed on the side of the second semiconductor layer 707 away from the substrate 700, and the materials for preparing the fourth insulating layer 708 include silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. , at least one of tantalum oxide, hafnium oxide, zirconium oxide or titanium oxide.
  • the fourth gate 709 is formed on the side of the fourth insulating layer 708 away from the second semiconductor layer 707 and is aligned with the third gate 7052; the fourth gate 709 is connected to the The source region 707a, the channel region 707b, and the drain region 707c of the second semiconductor layer 707 form the source, gate, and drain of an oxide transistor, wherein the third gate 7052 constitutes an oxide transistor in the bottom gate section.
  • the preparation material of the fourth gate 709 includes at least one of molybdenum, aluminum, silver, magnesium, gold, nickel, titanium, tantalum, tungsten (W) and the like. Further, the preparation material of the fourth gate 709 is molybdenum.
  • a fifth insulating layer 710 is formed on the side of the fourth gate 709 away from the substrate 700 , and the materials for preparing the fifth insulating layer 710 include silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide. , at least one of tantalum oxide, hafnium oxide, zirconium oxide or titanium oxide.
  • the first metal layer 711 is formed on the side of the fifth insulating layer 710 away from the substrate 700, and the first metal layer 711 is connected to the gate electrode of the silicon transistor, the oxide transistor, The source electrode and the drain electrode are connected; the preparation material of the first metal layer 711 includes at least one of gold, silver, copper, lithium, sodium, potassium, magnesium, aluminum, and zinc.
  • the sixth insulating layer 712 is formed on the side of the first metal layer 711 away from the substrate 700 , and the sixth insulating layer 712 can be made of organic materials or inorganic materials and mixtures thereof.
  • the anode 713 is formed on the side of the sixth insulating layer 712 away from the substrate 700.
  • the anode 713 is made of one of indium tin oxide, indium tin oxide, indium tin oxide, or indium tin oxide, indium oxide A combination of tin-zinc and silver, the anode 713 is electrically connected to the first metal layer 711 through vias.
  • the pixel definition layer 716 is formed on the side of the anode 713 away from the substrate 700 , and the shape of the opening of the pixel definition layer 716 is consistent with the pattern of the pixel 600 .
  • the light-emitting layer 715 is in contact with the anode 713 through the opening on the pixel definition layer 716, and the light-emitting layer 715 includes an organic light-emitting material; further, the light-emitting layer 715 further includes a fluorescent material and a quantum dot material , at least one of perovskite materials.
  • the cathode 714 is located on the side of the light-emitting layer 715 and the pixel definition layer 716 away from the anode 713 ; the anode 713 , the cathode 714 and the anode 713 and the cathode 714
  • the light emitting layer 715 forms the light emitting device D1.
  • the encapsulation layer 719 is located on the side of the light-emitting device D1 away from the substrate 700, and the preparation material of the encapsulation layer 719 includes a combination of organic materials and inorganic materials.
  • the first semiconductor layer 701, the first insulating layer 702, the first gate 703, the second insulating layer 704, the second gate layer, the third insulating layer 706, the second semiconductor layer 707, the fourth insulating layer 708, the fourth gate 709, the fifth insulating layer 710 and the first metal layer 711 form the pixel driver circuit.
  • the display panel further includes a conductive layer 720 located between the pixel driving circuit and the light-emitting device D1. From a viewing angle, the orthographic projections of the conductive layer 720 and the oxide transistor overlap, and the conductive layer 720 covers the oxide transistor, as shown in FIG. 4B .
  • the conductive layer 720 overlaps with the orthographic projection of the initialization transistor T2, and the conductive layer 720 covers the initialization transistor T2; similarly, if the The compensation transistor T3 is an oxide transistor, the conductive layer 720 overlaps with the orthographic projection of the compensation transistor T3, and the conductive layer 720 covers the compensation transistor T3.
  • the display panel further includes a seventh insulating layer 717, the seventh insulating layer 717 is located on the side of the conductive layer 720 close to the substrate 700, and the conductive layer 720 is located on the sixth insulating layer Between 712 and the seventh insulating layer 717, the conductive layer 720 is connected to the first metal layer 711 through the opening of the seventh insulating layer 717, and the preparation materials of the conductive layer 720 include gold, silver, copper , at least one of lithium, sodium, potassium, magnesium, aluminum, and zinc; the preparation materials of the seventh insulating layer 717 include organic materials or inorganic materials and mixtures thereof.
  • the display panel further includes a buffer layer 718 , and the preparation material of the buffer layer 718 includes organic materials, inorganic materials and combinations thereof; specifically, the preparation material of the buffer layer 718 includes silicon nitride , silicon oxide, silicon oxynitride, etc.
  • the plurality of pixels 600 are respectively connected to the potential variable signal line VI11 and the reset signal line VI12 .
  • the potential variable signal line VI11 may be located in the left and right border regions of the display panel and extend from the left and right border regions to the display area of the display panel, and the reset signal line VI12 may be located in the lower border of the display panel. area and extend from the lower border area to the display area of the display panel.
  • the reset signal line VI12 can be connected to a driver chip, and the driver chip provides the required potential variable signal VI1, in order to reduce the influence on the left and right frames of the display panel, the potential variable signal
  • the line VI11 may be located in the lower border area of the display panel and extend from the lower border area to the display area of the display panel, and the reset signal line VI12 may be located in the left and right border areas of the display panel and extend from the left and right border areas of the display panel.
  • the frame area extends toward the display area of the display panel.
  • the display panel may further include unshown parts such as color filters, touch electrodes, and the like.
  • the pixel driving circuit, the driving method thereof, and the display panel provided by the embodiments of the present application include: a light-emitting device D1, a driving transistor T1, and a compensation module 100; the compensation module 100 at least includes: an initialization transistor T2 and a compensation transistor T3; the initialization transistor T2 is used to respond to the first scan signal Scan1 and transmit the potential variable signal VI1 to the gate of the driving transistor T1, and initialize the gate voltage Vg of the driving transistor T1; the compensation transistor T3 for responding to the compensation control signal Scan3 and transmitting the data signal Vdata with the compensation threshold voltage to the gate of the driving transistor T1; wherein the initialization transistor T2 is of a different type from the compensation transistor T3; the potential is variable
  • the signal VI1 dynamically compensates the gate voltage Vg of the driving transistor T1 in the light-emitting phase, so as to maintain the gate voltage Vg of the driving transistor T1 stable in the light-emitting phase t3 and lower the source or drain of the driving transistor T1 The

Abstract

一种像素驱动电路及其驱动方法、显示面板，像素驱动电路包括驱动晶体管（T1）及至少包括类型不同的初始化晶体管（T2）和补偿晶体管（T3）的补偿模块（100），补偿晶体管（T3）将具有补偿阈值电压的数据信号（Vdata）传输至驱动晶体管（T1）的栅极；初始化晶体管（T2）将电位可变信号（VI1）传输至驱动晶体管（T1）的栅极，以在发光阶段（t3）动态补偿驱动晶体管（T1）的栅极电压（Vg），改善显示效果。

Description

像素驱动电路及其驱动方法、显示面板 技术领域
本申请涉及显示技术领域，尤其涉及一种像素驱动电路及其驱动方法、显示面板。
 背景技术
采用低温多晶硅技术制成的背板虽然可以使显示面板达到较高的像素密度，但由于硅类晶体管的漏电流较大，在显示面板使用低刷新频率时，显示面板的显示效果较差，影响显示品质。
 技术问题
本申请实施例提供一种像素驱动电路及其驱动方法、显示面板，可以维持驱动晶体管的栅极电压稳定，降低所述驱动晶体管的源极或漏极对所述驱动晶体管栅极的影响，改善显示面板的显示效果。
 技术解决方案
本申请实施例提供一种像素驱动电路，包括：发光器件、驱动晶体管以及补偿模块；所述补偿模块至少包括：初始化晶体管及补偿晶体管；
所述初始化晶体管用于响应第一扫描信号并将电位可变信号传输至所述驱动晶体管的栅极，初始化所述驱动晶体管的栅极电压；
所述补偿晶体管用于响应补偿控制信号并将具有补偿阈值电压的数据信号传输至所述驱动晶体管的栅极；
其中，所述初始化晶体管与所述补偿晶体管的类型不同；所述电位可变信号在发光阶段动态补偿所述驱动晶体管的栅极电压。
在一些实施例中，所述初始化晶体管为硅晶体管或氧化物晶体管的其中之一，所述补偿晶体管为硅晶体管或氧化物晶体管的其中另一。
在一些实施例中，所述初始化晶体管为硅晶体管，所述补偿晶体管为氧化物晶体管。
在一些实施例中，所述初始化晶体管为P型晶体管；所述补偿晶体管为N型晶体管。
在一些实施例中，所述电位可变信号在所述初始化晶体管响应所述第一扫描信号、所述补偿晶体管响应所述补偿控制信号时为恒定低电平信号，在所述发光阶段为连续上升信号。
在一些实施例中，所述像素驱动电路还包括数据写入模块，所述数据写入模块用于响应第二扫描信号并将所述数据信号传输至所述驱动晶体管的源极或漏极。
在一些实施例中，所述像素驱动电路还包括存储模块，所述存储模块用于维持所述驱动晶体管的栅极电压。
在一些实施例中，所述像素驱动电路还包括发光控制模块，所述发光控制模块用于响应发光控制信号控制所述发光器件发光。
在一些实施例中，所述像素驱动电路还包括复位模块，所述复位模块用于响应第二扫描信号并将复位信号传输至所述发光器件的阳极。
在一些实施例中，所述复位信号为恒定信号。
在一些实施例中，所述发光器件包括有机发光二极管、次毫米发光二极管及微型发光二极管的其中一种。
本申请还提供一种像素驱动电路的驱动方法，用于驱动所述的像素驱动电路，在第N帧周期内，所述驱动方法包括：
初始化阶段，所述补偿模块的所述初始化晶体管响应所述第一扫描信号，所述电位可变信号传输至所述驱动晶体管的栅极，初始化所述驱动晶体管的栅极电压；
补偿阶段，所述补偿模块的所述补偿晶体管响应所述补偿控制信号，将具有补偿阈值电压的数据信号传输至所述驱动晶体管的栅极，补偿所述驱动晶体管的阈值电压；
所述发光阶段，所述驱动晶体管驱动所述发光器件发光，所述电位可变信号动态补偿所述驱动晶体管的栅极电压。
在一些实施例中，所述电位可变信号在所述初始化阶段和所述补偿阶段为恒定信号，所述电位可变信号在所述发光阶段随补偿前的所述驱动晶体管的栅极电压连续上升或连续下降。
本申请还提供一种显示面板，包括：多个像素及控制所述像素发光的像素驱动电路；所述像素驱动电路包括：形成所述像素的发光器件，被配置为向所述发光器件提供驱动电流的驱动晶体管，用于提供电位可变信号的电位可变信号线，初始化晶体管，以及，补偿晶体管；所述初始化晶体管和补偿晶体管具有不同材料的半导体层；
所述补偿晶体管的栅极与补偿控制信号线连接，所述补偿晶体管的源极或漏极中的一者与所述驱动晶体管的栅极连接，源极或漏极中的另一者与所述驱动晶体管的源极或漏极中的一者连接；
所述初始化晶体管的栅极与第一扫描信号线连接，所述初始化晶体管的源极或漏极中的一者与电位可变信号线连接，源极或漏极中的另一者与所述驱动晶体管的栅极连接。
在一些实施例中，所述初始化晶体管和所述补偿晶体管的所述半导体层的载流子迁移率不同；所述初始化晶体管的所述半导体层的载流子迁移率大于所述补偿晶体管的所述半导体层的载流子迁移率；或，所述初始化晶体管的所述半导体层的载流子迁移率小于所述补偿晶体管的所述半导体层的载流子迁移率。
在一些实施例中，所述像素驱动电路还包括：
数据写入晶体管，所述数据写入晶体管的栅极与第二扫描信号线连接，所述数据写入晶体管的源极或漏极中的一者与数据信号线连接，源极或漏极中的另一者与所述驱动晶体管的源极或漏极中的一者连接；
存储电容，所述存储电容的上极板与第一电压端连接，下极板与所述初始化晶体管的源极或漏极中连接所述驱动晶体管栅极的一者、所述补偿晶体管的源极或漏极中连接所述驱动晶体管栅极的一者及所述驱动晶体管的栅极连接。
在一些实施例中，所述像素驱动电路还包括：
第一开关晶体管，所述第一开关晶体管的栅极与发光控制信号线连接，所述第一开关晶体管的源极或漏极中的一者与第一电压端连接，源极或漏极中的另一者与所述驱动晶体管的源极或漏极中的一者连接；
第二开关晶体管，所述第二开关晶体管的栅极与所述发光控制信号线连接，所述第二开关晶体管的源极或漏极中的一者与所述驱动晶体管的源极或漏极中的一者连接，源极或漏极中的另一者与所述发光器件的阳极连接。
在一些实施例中，所述像素驱动电路还包括：
复位晶体管，所述复位晶体管的栅极与第二扫描信号线连接，所述复位晶体管的源极或漏极中的一者与复位信号线连接，源极或漏极中的另一者与所述发光器件的阳极连接，所述复位晶体管与所述初始化晶体管具有相同材料的半导体层。
在一些实施例中，所述显示面板还包括位于所述像素驱动电路与所述发光器件之间的导电层，在俯视视角下，所述导电层与所述补偿晶体管的正投影重合，且所述导电层覆盖所述补偿晶体管。
在一些实施例中，所述导电层的制备材料包括金、银、铜、锂、钠、钾、镁、铝、锌中的至少一种。
 有益效果
相较于现有技术，本申请实施例提供的像素驱动电路及其驱动方法、显示面板，所述像素驱动电路包括：发光器件、驱动晶体管以及补偿模块；所述补偿模块至少包括：初始化晶体管及补偿晶体管；所述初始化晶体管用于响应第一扫描信号并将电位可变信号传输至所述驱动晶体管的栅极，初始化所述驱动晶体管的栅极电压；所述补偿晶体管用于响应补偿控制信号并将具有补偿阈值电压的数据信号传输至所述驱动晶体管的栅极；其中，所述初始化晶体管与所述补偿晶体管的类型不同；所述电位可变信号在发光阶段动态补偿所述驱动晶体管的栅极电压，以在所述发光阶段维持所述驱动晶体管的栅极电压稳定，降低所述驱动晶体管的源极或漏极对所述驱动晶体管栅极的影响，可以改善显示面板的显示效果。
 附图说明
图1为本申请的实施例提供的像素驱动电路的原理图；
图2A~图2B为本申请的实施例提供的像素驱动电路的结构示意图；
图3A为图2A提供的像素驱动电路的工作时序图；
图3B为图2B提供的像素驱动电路的工作时序图；
图3C为本申请的实施例提供的电位可变信号及驱动晶体管栅极电压的工作时序图；
图4A~图4C为本申请的实施例提供的显示面板的结构示意图；
图5A~图5B为本申请的实施例提供的像素驱动电路的结构示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
具体的，请参阅图1，其为本申请的实施例提供的像素驱动电路的原理图，如图2A~图2B，其为本申请的实施例提供的像素驱动电路的结构示意图；如图3A，其为图2A提供的像素驱动电路的工作时序图；如图3B，其为图2B提供的像素驱动电路的工作时序图；如图3C，其为本申请的实施例提供的电位可变信号及驱动晶体管栅极电压的工作时序图。
本申请实施例提供一种像素驱动电路，包括：发光器件D1、驱动晶体管T1以及补偿模块100；所述补偿模块100至少包括：初始化晶体管T2及补偿晶体管T3；
所述初始化晶体管T2用于响应第一扫描信号Scan1并将电位可变信号VI1传输至所述驱动晶体管T1的栅极，初始化所述驱动晶体管T1的栅极电压Vg；
所述补偿晶体管T3用于响应补偿控制信号Scan3并将具有补偿阈值电压的数据信号Vdata传输至所述驱动晶体管T1的栅极；
其中，所述初始化晶体管T2与所述补偿晶体管T3的类型不同；所述电位可变信号VI1在发光阶段t3动态补偿所述驱动晶体管T1的栅极电压Vg，以在所述发光阶段t3维持所述驱动晶体管T1的栅极电压Vg稳定，降低所述驱动晶体管T1的源极或漏极对所述驱动晶体管T1栅极的影响。
进一步地，所述初始化晶体管T2为硅晶体管或氧化物晶体管的其中之一，所述补偿晶体管T3为硅晶体管或氧化物晶体管的其中另一。
具体地，请继续参阅图2A~图2B及图3A~图3B，在所述发光阶段t3，利用所述补偿晶体管T3可减小所述驱动晶体管T1的源极或漏极（B点）中的一者对所述驱动晶体管T1栅极（Q点）电压Vg的影响。但所述补偿晶体管T3会存在一定的漏电流，为降低所述补偿晶体管T3的漏电流对所述驱动晶体管T1的影响，利用所述初始化晶体管T2的漏电流特性及所述电位可变信号VI1动态补偿因所述补偿晶体管T3的漏电流造成的对所述驱动晶体管T1的栅极电压Vg的影响，以使所述驱动晶体管T1的栅极电压Vg保持恒定，保证所述发光器件D1的稳定发光。更进一步地，可保证所述发光器件D1在任何刷新频率下均可实现稳定发光。
更进一步地，所述初始化晶体管T2为氧化物晶体管，所述补偿晶体管T3为硅晶体管；但由于硅晶体管的漏电流要大于氧化物晶体管的漏电流，因此在所述初始化晶体管T2为氧化物晶体管，所述补偿晶体管T3为硅晶体管时，所述补偿晶体管T3的漏电流要大于所述初始化晶体管T2的漏电流，影响所述电位可变信号VI1对所述驱动晶体管T1的栅极电压Vg的补偿效果。
因此，为提高对所述驱动晶体管T1的栅极电压Vg的补偿效果，所述初始化晶体管T2为硅晶体管，所述补偿晶体管T3为氧化物晶体管，利用所述补偿晶体管T3的漏电流小于所述初始化晶体管T2的漏电流的特性，降低所述驱动晶体管T1的源极或漏极（B点）中的一者对所述驱动晶体管T1栅极（Q点）电压Vg的影响，利用所述初始化晶体管T2具有较大的漏电流的特性，通过所述电位可变信号VI1降低所述补偿晶体管T3的漏电流对所述驱动晶体管T1的影响，以使所述驱动晶体管T1的栅极电压Vg保持恒定，保证所述发光器件D1的稳定发光。
所述初始化晶体管T2及所述补偿晶体管T3可以为P型晶体管，也可为N型晶体管；进一步地，由于P型氧化物晶体管受目前P型氧化物材料的制约，制备出高质量的P型氧化物晶体管也受到制约，因此，在考虑现有技术的基础上，当所述初始化晶体管T2或所述补偿晶体管T3为氧化物晶体管时，选用N型氧化物晶体管。但在此并不用于限制本申请中的所述氧化物晶体管为N型晶体管，在本申请中所述氧化物晶体管也可为P型晶体管。
其中，所述硅晶体管包括单晶硅晶体管、多晶硅晶体管、微晶硅晶体管、非晶硅或其他含硅的晶体管；所述氧化物晶体管包括含锌、铟、镓、锡或钛等金属及其氧化物的氧化物晶体管。进一步地，所述多晶硅晶体管包括低温多晶硅晶体管；所述氧化物晶体管包括含氧化锌、氧化锌锡、氧化锌铟、氧化铟、氧化钛、氧化铟镓锌、氧化铟锌锡等的氧化物晶体管。
请继续参阅图1和图2A~图2B，所述像素驱动电路还包括数据写入模块200，所述数据写入模块200用于响应第二扫描信号Scan2并将所述数据信号Vdata传输至所述驱动晶体管T1的源极或漏极。
其中，所述补偿晶体管T3采用与所述数据写入晶体管T4相同类型的晶体管时，所述补偿晶体管T3可直接利用所述第二扫描信号Scan2代替所述补偿控制信号Scan3。
具体地，请参阅图2A~图2B，所述数据写入模块200包括数据写入晶体管T4，所述数据写入晶体管T4的栅极与所述第二扫描信号Scan2连接，所述数据信号Vdata传输至所述数据写入晶体管T4的第一极，所述数据写入晶体管T4的第二极与所述驱动晶体管T1的第一极连接。
所述像素驱动电路还包括存储模块300，所述存储模块300用于维持所述驱动晶体管T1的栅极电压Vg。
具体地，请参阅图2A~图2B，所述存储模块300包括存储电容C1，所述存储电容C1的一端与第一电压端Vdd连接，所述存储电容C1的另一端与所述驱动晶体管T1的栅极、所述初始化晶体管T2的第二极、所述补偿晶体管T3的第一极连接。具体地，所述存储电容C1的上极板与所述第一电压端Vdd连接，所述存储电容C2的下极板与所述驱动晶体管T1的栅极、所述初始化晶体管T2的第二极、所述补偿晶体管T3的第一极连接。
所述像素驱动电路还包括发光控制模块400，所述发光控制模块400用于响应发光控制信号EM控制所述发光器件D1发光。
具体地，请参阅图2A~图2B，所述发光控制模块400包括第一开关晶体管T5和第二开关晶体管T6；所述发光控制信号EM传输至所述第一开关晶体管T5的栅极与所述第二开关晶体管T6的栅极，所述第一开关晶体管T5的第一极与所述第一电压端Vdd连接，所述第一开关晶体管T5的第二极与所述驱动晶体管T1的第一极连接；所述第二开关晶体管T6的第一极与所述驱动晶体管T1的第二极连接，所述第二开关晶体管T6的第二极与所述发光器件D1的阳极连接。
所述像素驱动电路还包括复位模块500，所述复位模块500用于响应第二扫描信号Scan2并将复位信号VI2传输至所述发光器件D1的阳极。
具体地，请参阅图2A~图2B，所述复位模块500包括复位晶体管T7；所述第二扫描信号Scan2传输至所述复位晶体管T7的栅极，所述复位信号VI2传输至所述复位晶体管T7的第一极，所述复位晶体管T7的第二极与所述发光器件D1的阳极连接。
其中，所述复位信号VI2为恒定信号；在所述发光阶段t3，可通过驱动芯片提供所需的所述电位可变信号VI1。
所述复位晶体管T7与所述初始化晶体管T2的类型可以不同，也可相同。具体地，在图2A所示的像素驱动电路中，所述复位晶体管T7与所述初始化晶体管T2的类型不同；进一步地，所述复位晶体管T7与所述补偿晶体管T3的类型相同。而在图2B所示的像素驱动电路中，所述复位晶体管T7与所述初始化晶体管T2的类型相同；进一步地，所述复位晶体管T7与所述补偿晶体管T3的类型不同。
所述发光器件D1包括有机发光二极管、次毫米发光二极管及微型发光二极管的其中一种。
在图2A~图2B所示的像素驱动电路中，均以所述发光器件D1的阴极接第二电压端Vss为例；此外，所述发光器件D1亦可采用阳极接所述第一电压端Vdd的形式布置于所述像素驱动电路中，在此对其不再进行赘述。
为区分晶体管中除栅极以外的源极与漏极，本申请的第一极可以为漏极或源极的一者，相应地，第二极为源极或漏极中的另一者。
本申请还提供一种像素驱动电路的驱动方法，用于驱动所述像素驱动电路，在第N帧周期（N Frame）内，所述驱动方法包括：
初始化阶段t1，所述补偿模块100的所述初始化晶体管T2响应第一扫描信号Scan1，所述电位可变信号VI1传输至所述驱动晶体管T1的栅极，初始化所述驱动晶体管T1的栅极电压Vg；
补偿阶段t2，所述补偿模块100的所述补偿晶体管T3响应补偿控制信号Scan3，将具有补偿阈值电压的数据信号Vdata传输至所述驱动晶体管T1的栅极，补偿所述驱动晶体管T1的阈值电压；
所述发光阶段t3，所述驱动晶体管T1驱动所述发光器件D1发光，所述电位可变信号VI1动态补偿所述驱动晶体管T1的栅极电压Vg。
其中，所述电位可变信号VI1在所述初始化阶段t1和所述补偿阶段t2为恒定信号，所述电位可变信号VI1在所述发光阶段t3随补偿前的所述驱动晶体管T1的栅极电压Vg连续上升或连续下降。
具体地，在所述发光阶段t3，由于所述驱动晶体管T1的栅极受所述驱动晶体管T1的源极或漏极(B点)的影响，所述驱动晶体管T1的栅极电压Vg会出现连续的变动，因此，为使所述驱动晶体管T1的栅极电压Vg维持稳定，在幅值上所述电位可变信号VI1与补偿前的所述驱动晶体管T1的栅极电压Vg成正比；在时序上，所述电位可变信号VI1随补偿前的所述驱动晶体管T1的栅极电压Vg的下降而连续上升，或随补偿前的所述驱动晶体管T1的栅极电压Vg的上升连续下降，以使所述驱动晶体管T1的栅极电压Vg在补偿后维持稳定。
在所述发光阶段t3，可通过驱动芯片提供所需的所述电位可变信号VI1。所述复位信号VI2可与所述电位可变信号VI1在所述初始化阶段t1和所述补偿阶段t2时的幅值相等，也可不相等，在此对其不再进行赘述。
下面将结合图2A~图2B及图3A~图3B详细描述利用所述驱动方法驱动所述像素驱动电路的工作原理。
请继续参阅图2A与图3A，以所述驱动晶体管T1、所述补偿晶体管T3、所述数据写入晶体管T4、所述第一开关晶体管T5、所述第二开关晶体管T6及所述复位晶体管T7为P型硅晶体管、所述初始化晶体管T2为N型氧化物晶体管；所述补偿晶体管T3与所述数据写入晶体管T4共用所述第二扫描信号Scan2为例；在第N帧周期（N Frame）内，包括所述初始化阶段t1、所述补偿阶段t2及所述发光阶段t3；
在所述初始化阶段t1：所述初始化晶体管T2响应所述第一扫描信号Scan1，所述初始化晶体管T2导通，所述电位可变信号VI1传输至所述驱动晶体管T1的栅极；所述存储电容C1下极板接入所述电位可变信号VI1，所述存储电容C1的上极板与下极板之间电压差变大，所述存储电容C1充电，所述驱动晶体管T1的栅极电压Vg被所述电位可变信号VI1复位至低电平信号Vini，所述驱动晶体管T1导通，实现所述驱动晶体管T1的初始化。
在所述补偿阶段t2：所述补偿晶体管T3、所述数据写入晶体管T4及所述复位晶体管T7响应所述第二扫描信号Scan2导通，所述数据信号Vdata传输至所述驱动晶体管T1的第一极（A点）；所述补偿晶体管T3导通使得所述驱动晶体管T1的栅极与第二极连接，具有补偿阈值电压Vth作用的所述数据信号Vdata被传输至所述驱动晶体管T1的栅极，所述存储电容C1的存在使得所述驱动晶体管T1的栅极电压Vg由Vini逐渐抬升直至使所述驱动晶体管T1充分导通，所述存储电容C1维持所述驱动晶体管T1的栅极电压Vg，从而实现对所述驱动晶体管T1的阈值电压Vth的补偿；所述复位晶体管T7的导通使得所述复位信号VI2被传输至所述发光器件D1的阳极，实现对所述发光器件D1的初始化。
在所述发光阶段t3：所述第一开关晶体管T5和所述第二开关晶体管T6响应所述发光控制信号EM导通，所述驱动晶体管T1形成驱动电流驱动所述发光器件D1发光；利用处于截止状态的所述补偿晶体管T3降低所述驱动晶体管T1的第二极（B点）对所述驱动晶体管T1栅极（Q点）电压Vg的影响，利用处于截止状态的所述初始化晶体管T2的漏电流特性及所述电位可变信号VI1动态补偿因所述补偿晶体管T3的漏电流造成的对所述驱动晶体管T1的栅极电压Vg的影响，以使所述驱动晶体管T1的栅极电压Vg保持稳定；即Vg保持在Vdata+Vth，保证所述发光器件D1的稳定发光。
与之相似地，请继续参阅图2B与图3B，以所述驱动晶体管T1、所述初始化晶体管T2、所述数据写入晶体管T4、所述第一开关晶体管T5、所述第二开关晶体管T6及所述复位晶体管T7为P型硅晶体管、所述补偿晶体管T3为N型氧化物晶体管；在第N帧周期（N Frame）内，包括所述初始化阶段t1、所述补偿阶段t2及所述发光阶段t3；
在所述初始化阶段t1：所述初始化晶体管T2响应所述第一扫描信号Scan1，所述初始化晶体管T2导通，所述电位可变信号VI1传输至所述驱动晶体管T1的栅极；所述存储电容C1充电，所述驱动晶体管T1的栅极电压Vg被所述电位可变信号VI1复位至低电平信号Vini，所述驱动晶体管T1导通，实现所述驱动晶体管T1的初始化。
在所述补偿阶段t2：所述补偿晶体管T3响应所述补偿控制信号Scan3导通，所述数据写入晶体管T4及所述复位晶体管T7响应所述第二扫描信号Scan2导通，所述数据信号Vdata传输至所述驱动晶体管T1的第一极（A点）；所述补偿晶体管T3导通使得所述驱动晶体管T1的栅极与第二极连接，具有补偿阈值电压Vth作用的所述数据信号Vdata被传输至所述驱动晶体管T1的栅极，所述存储电容C1的存在使得所述驱动晶体管T1的栅极电压Vg由Vini逐渐抬升直至使所述驱动晶体管T1充分导通，所述存储电容C1维持所述驱动晶体管T1的栅极电压Vg，从而实现对所述驱动晶体管T1的阈值电压Vth的补偿；所述复位晶体管T7的导通使得所述复位信号VI2被传输至所述发光器件D1的阳极，实现对所述发光器件D1的初始化。
在所述发光阶段t3：所述第一开关晶体管T5和所述第二开关晶体管T6响应所述发光控制信号EM导通，所述驱动晶体管T1形成驱动电流驱动所述发光器件D1发光；利用处于截止状态的所述补偿晶体管T3降低所述驱动晶体管T1的第二极（B点）对所述驱动晶体管T1栅极（Q点）电压Vg的影响，利用处于截止状态的所述初始化晶体管T2的漏电流特性及所述电位可变信号VI1动态补偿因所述补偿晶体管T3的漏电流造成的对所述驱动晶体管T1的栅极电压Vg的影响，以使所述驱动晶体管T1的栅极电压Vg保持稳定；即Vg保持在Vdata+Vth，保证所述发光器件D1的稳定发光。
请继续参阅图2A~图2B和图3A~图3B，在所述发光阶段t3，由于所述第一开关晶体管T5导通，所述第一电压端Vdd将信号Vdd1传输至所述驱动晶体管T1的第一极，所述驱动晶体管T1的栅极电压Vg与第一极（A点）电压之差Vgs等于Vg-Vdd1；因此，由Vg=Vdata+Vth、Vgs=Vg-Vdd1和驱动电流I=(C oxμ mW/L)*(Vgs-Vth) 2/2(其中，C ox、μ m、W、L分别为晶体管的单位面积沟道电容、沟道迁移率、沟道宽和沟道长)可得；所述驱动电流I=(C oxμ mW/L)*(Vg-Vdd1-Vg+Vdata) 2/2=(C oxμ mW/L)*(Vdata-Vdd1) 2/2；以此所述驱动电流I不受所述阈值电压Vth的变化的影响，保证所述发光器件D1发光的稳定性。
所述电位可变信号VI1在所述初始化晶体管T2响应所述第一扫描信号Scan1、所述补偿晶体管T3响应所述补偿控制信号Scan3时为恒定低电平信号，在所述发光阶段t3为连续上升信号。
在图2A~图2B所述的像素驱动电路中，均以所述驱动晶体管T1、所述数据写入晶体管T4、所述第一开关晶体管T5、所述第二开关晶体管T6及所述复位晶体管T7为P型晶体管为例进行说明，本领域的相关技术人员也可将其替换为N型晶体管，并将相应的部分信号进行反相实现上述功能，在此对其不再进行赘述。
请参阅图4A~图4C，其为本申请的实施例提供的显示面板的结构示意图；如图5A~图5B，其为本申请的实施例提供的像素驱动电路的结构示意图。
本申请还提供一种显示面板，包括：多个像素600及控制所述像素600发光的像素驱动电路；所述像素驱动电路包括：形成所述像素600的发光器件D1，被配置为向所述发光器件D1提供驱动电流的驱动晶体管T1，用于提供电位可变信号VI1的电位可变信号线VI11，初始化晶体管T2，以及，补偿晶体管T3；所述初始化晶体管T2和补偿晶体管T3具有不同材料的半导体层；
所述补偿晶体管T3的栅极与补偿控制信号线S3连接，所述补偿晶体管T3的源极或漏极中的一者与所述驱动晶体管T1的栅极连接，源极或漏极中的另一者与所述驱动晶体管T1的源极或漏极中的一者连接；
所述初始化晶体管T2的栅极与第一扫描信号线S1连接，所述初始化晶体管T2的源极或漏极中的一者与所述电位可变信号线VI11连接，源极或漏极中的另一者与所述驱动晶体管T1的栅极连接。
其中，所述初始化晶体管T2和所述补偿晶体管T3的所述半导体层601和602的载流子迁移率不同；所述初始化晶体管T2的所述半导体层601的载流子迁移率大于所述补偿晶体管T3的所述半导体层602的载流子迁移率；或，所述初始化晶体管T2的所述半导体层601的载流子迁移率小于所述补偿晶体管T3的所述半导体层602的载流子迁移率。
进一步地，所述初始化晶体管T2和所述补偿晶体管T3的所述半导体层601和602包括P型晶体管半导体或N型晶体管半导体。
进一步地，所述初始化晶体管T2的所述半导体层601包括硅半导体层或氧化物半导体层的其中之一，所述补偿晶体管T3的所述半导体层602包括硅半导体层或氧化物半导体层的其中另一。
请继续参阅图5A~图5B，在一些实施例中，所述像素驱动电路还包括：
数据写入晶体管T4，所述数据写入晶体管T4的栅极与第二扫描信号线S2连接，所述数据写入晶体管T4的源极或漏极中的一者与数据信号线Data连接，源极或漏极中的另一者与所述驱动晶体管T1的源极或漏极中的一者连接；
存储电容C1，所述存储电容C1的上极板与第一电压端Vdd连接，下极板与所述初始化晶体管T2的源极或漏极中连接所述驱动晶体管T1栅极的一者、所述补偿晶体管T3的源极或漏极中连接所述驱动晶体管T1栅极的一者及所述驱动晶体管T1的栅极连接。
所述像素驱动电路还包括：第一开关晶体管T5，所述第一开关晶体管T5的栅极与发光控制信号线EM1连接，所述第一开关晶体管T5的源极或漏极中的一者与第一电压端Vdd连接，源极或漏极中的另一者与所述驱动晶体管T1的源极或漏极中的一者连接；
第二开关晶体管T6，所述第二开关晶体管T6的栅极与所述发光控制信号线EM1连接，所述第二开关晶体管T6的源极或漏极中的一者与所述驱动晶体管T1的源极或漏极中的一者连接，源极或漏极中的另一者与所述发光器件D1的阳极连接。
所述像素驱动电路还包括：复位晶体管T7，所述复位晶体管T7的栅极与第二扫描信号线S2连接，所述复位晶体管T7的源极或漏极中的一者与复位信号线VI12连接，源极或漏极中的另一者与所述发光器件D1的阳极连接。
进一步地，所述复位晶体管T7与所述初始化晶体管T2可以具有不同材料的半导体层，也可具有相同材料的半导体层，如图5A和图5B所示。在如图5A所示的像素驱动电路中，所述复位晶体管T7与所述初始化晶体管T2具有不同材料的半导体层；进一步地，所述复位晶体管T7与所述补偿晶体管T3具有相同材料的半导体层。而在如图5B所示的像素驱动电路中，所述复位晶体管T7与所述初始化晶体管T2具有相同材料的半导体层；进一步地，所述复位晶体管T7与所述补偿晶体管T3具有不同材料的半导体层。
其中，在如图5A所示的所示像素驱动电路中，所述补偿晶体管T3可与所述补偿控制信号线S3连接，也可与所述第二扫描信号线S2连接，以降低制程难度。
在如图5A~图5B所示的像素驱动电路中均以所述驱动晶体管T1、所述数据写入晶体管T4、所述第一开关晶体管T5、所述第二开关晶体管T6及所述复位晶体管T7为P型晶体管为例，本领域的相关技术人员也可用N型晶体管实现，在此对其不再进行赘述。
在所述显示面板的所述像素驱动电路中，均以所述发光器件D1采用共阴极接法（即所述发光器件D1的阴极接第二电压端Vss）为例，本领域相关技术人员亦可采用共阳极接法（即所述发光器件D1的阳极接所述第一电压端Vdd），在此对其不再进行赘述。
请继续参阅图4A~图4C，所述显示面板还包括衬底700，所述像素驱动电路位于所述衬底700上，所述发光器件D1位于所述像素驱动电路远离所述衬底700的一侧。
所述衬底700包括柔性衬底与刚性衬底；所述衬底700的制备材料包括玻璃、石英、陶瓷、塑料或聚合物树脂等；聚合物树脂包括聚醚砜、聚丙烯酸酯、聚芳酯、聚醚酰亚胺、聚萘二甲酸乙二醇酯、聚对苯二甲酸乙二醇酯、聚苯硫醚、聚烯丙基酯、聚酰亚胺、聚碳酸酯、三乙酸纤维素、醋酸丙酸纤维素中的至少一种。
所述显示面板还包括：
第一半导体层701，形成于所述衬底700上，所述第一半导体层701包括源极区701a，沟道区701b，漏极区701c；所述第一半导体层701的衬底材料可以为N型或者P型硅半导体。
第一绝缘层702，覆盖所述衬底700及所述第一半导体层701，所述第一绝缘层702的制备材料包括氮化硅、氧化硅、氧氮化硅、氧化铝、氧化钽、氧化铪、氧化锆或氧化钛中的至少一种。
第一栅极703，形成于所述第一绝缘层702远离所述第一半导体层701的一侧，且与所述第一半导体层701对位设置，所述第一栅极703与所述源极区701a、所述沟道区701b、所述漏极区701c构成硅晶体管的源极、栅极与漏极，所述第一栅极703的制备材料包括钼、铝、银、镁、金、镍、钛、钽、钨(W)等中的至少一种。进一步的，所述第一栅极703的制备材料为钼。
第二绝缘层704，形成于所述第一栅极703远离所述衬底700的一侧，所述第二绝缘层704的制备材料包括氮化硅、氧化硅、氧氮化硅、氧化铝、氧化钽、氧化铪、氧化锆或氧化钛中的至少一种。
第二栅极层，形成于所述第二绝缘层704远离所述第一栅极703的一侧，所述第二栅极层包括与所述第一栅极703对位设置的第二栅极7051以及远离所述第二栅极7051设置的第三栅极7052；所述第二栅极7051与所述第一栅极703构成所述像素驱动电路中的所述存储电容C1的上极板与下极板。所述第二栅极层的制备材料包括钼、铝、银、镁、金、镍、钛、钽、钨(W)等中的至少一种。进一步的，所述第二栅极层的制备材料为钼。
第三绝缘层706，形成于所述第二栅极层远离所述衬底700的一侧，所述第三绝缘层706的制备材料包括氮化硅、氧化硅、氧氮化硅、氧化铝、氧化钽、氧化铪、氧化锆或氧化钛中的至少一种。
第二半导体层707，位于所述第三绝缘层706远离所述衬底700的一侧，所述第二半导体层707包括源极区707a，沟道区707b，漏极区707c；所述第二半导体层707的材料为氧化物半导体，所述氧化物半导体可包括锌、铟、镓、锡或钛的金属的氧化物中的至少一种；进一步地，所述氧化物半导体可包括氧化锌、氧化锌锡、氧化锌铟、氧化铟、氧化钛、氧化铟镓锌、氧化铟锌锡等中的至少一种。
第四绝缘层708，形成于所述第二半导体层707远离所述衬底700的一侧，所述第四绝缘层708的制备材料包括氮化硅、氧化硅、氧氮化硅、氧化铝、氧化钽、氧化铪、氧化锆或氧化钛中的至少一种。
第四栅极709，形成于所述第四绝缘层708远离所述第二半导体层707的一侧，且与所述第三栅极7052对位设置；所述第四栅极709与所述第二半导体层707的所述源极区707a、所述沟道区707b、所述漏极区707c形成氧化物晶体管的源极、栅极、漏极，其中第三栅极7052构成氧化物晶体管中的底栅部分。所述第四栅极709的制备材料包括钼、铝、银、镁、金、镍、钛、钽、钨(W)等中的至少一种。进一步的，所述第四栅极709的制备材料为钼。
第五绝缘层710，形成于所述第四栅极709远离所述衬底700的一侧，所述第五绝缘层710的制备材料包括氮化硅、氧化硅、氧氮化硅、氧化铝、氧化钽、氧化铪、氧化锆或氧化钛中的至少一种。
第一金属层711，形成于所述第五绝缘层710远离所述衬底700的一侧，所述第一金属层711通过过孔与所述硅晶体管、所述氧化物晶体管的栅极、源极、漏极连接；所述第一金属层711的制备材料包括金、银、铜、锂、钠、钾、镁、铝、锌中的至少一种。
第六绝缘层712，形成于所述第一金属层711远离所述衬底700的一侧，所述第六绝缘层712可以为采用有机材料或者无机材料及其混合物。
阳极713，形成于所述第六绝缘层712远离所述衬底700的一侧，所述阳极713的制备材料包括氧化铟锡、氧化铟锡锌中的一种，或氧化铟锡、氧化铟锡锌与银的组合，所述阳极713通过过孔与所述第一金属层711电性连接。
像素定义层716，形成于所述阳极713远离所述衬底700的一侧，所述像素定义层716的开孔形状与所述像素600的图案一致。
发光层715，通过所述像素定义层716上的所述开孔与所述阳极713接触，所述发光层715包括有机发光材料；进一步地，所述发光层715还包括荧光材料、量子点材料、钙钛矿材料中的至少一种。
阴极714，位于所述发光层715及所述像素定义层716远离所述阳极713的一侧；所述阳极713，所述阴极714及位于所述阳极713和所述阴极714之间的所述发光层715形成所述发光器件D1。
封装层719，位于所述发光器件D1远离所述衬底700的一侧，所述封装层719的制备材料包括有机材料与无机材料的组合。
在垂直于所述衬底700的方向上，所述第一半导体层701、所述第一绝缘层702、所述第一栅极703、所述第二绝缘层704、所述第二栅极层、所述第三绝缘层706、所述第二半导体层707、所述第四绝缘层708、所述第四栅极709、所述第五绝缘层710及第一金属层711形成所述像素驱动电路。
为避免所述封装层719中的氢元素与氧元素对所述氧化物晶体管造成影响，所述显示面板还包括位于所述像素驱动电路与所述发光器件D1之间的导电层720，在俯视视角下，所述导电层720与所述氧化物晶体管的正投影重合，且所述导电层720覆盖所述氧化物晶体管，如图4B所示。进一步地，若所述初始化晶体管T2为氧化物晶体管，所述导电层720与所述初始化晶体管T2的正投影重合，且所述导电层720覆盖所述初始化晶体管T2；与之相似地，若所述补偿晶体管T3为氧化物晶体管，所述导电层720与所述补偿晶体管T3的正投影重合，且所述导电层720覆盖所述补偿晶体管T3。
具体地，所述显示面板还包括第七绝缘层717，所述第七绝缘层717位于所述导电层720靠近所述衬底700的一侧，所述导电层720位于所述第六绝缘层712与所述第七绝缘层717之间，所述导电层720通过所述第七绝缘层717的开孔与第一金属层711连接，所述导电层720的制备材料包括金、银、铜、锂、钠、钾、镁、铝、锌中的至少一种；所述第七绝缘层717的制备材料包括有机材料或者无机材料及其混合物。
请继续参与图4A~图4B，所述显示面板还包括缓冲层718，所述缓冲层718的制备材料包括有机材料与无机材料及其组合；具体地，缓冲层718的制备材料包括氮化硅、氧化硅、氮氧化硅等。
请继续参阅图4C，所述在俯视视角下，多个所述像素600分别与所述电位可变信号线VI11和所述复位信号线VI12连接。
所述电位可变信号线VI11可位于所述显示面板的左右边框区域并从所述左右边框区域向所述显示面板的显示区延伸，所述复位信号线VI12可位于所述显示面板的下边框区域并从所述下边框区域向所述显示面板的显示区延伸。
由于所述复位信号线VI12可与驱动芯片连接，利用所述驱动芯片提供所需的所述电位可变信号VI1，所以为降低对所述显示面板的左右边框的影响，所述电位可变信号线VI11可位于所述显示面板的下边框区域并从所述下边框区域向所述显示面板的显示区延伸，所述复位信号线VI12可位于所述显示面板的左右边框区域并从所述左右边框区域向所述显示面板的显示区延伸。
进一步地，所述显示面板还可包括彩色滤光片、触控电极等未示出部分。
本申请实施例提供的像素驱动电路及其驱动方法、显示面板，所述像素驱动电路包括：发光器件D1、驱动晶体管T1以及补偿模块100；所述补偿模块100至少包括：初始化晶体管T2及补偿晶体管T3；所述初始化晶体管T2用于响应第一扫描信号Scan1并将电位可变信号VI1传输至所述驱动晶体管T1的栅极，初始化所述驱动晶体管T1的栅极电压Vg；所述补偿晶体管T3用于响应补偿控制信号Scan3并将具有补偿阈值电压的数据信号Vdata传输至所述驱动晶体管T1的栅极；其中，所述初始化晶体管T2与所述补偿晶体管T3的类型不同；所述电位可变信号VI1在发光阶段动态补偿所述驱动晶体管T1的栅极电压Vg，以在所述发光阶段t3维持所述驱动晶体管T1的栅极电压Vg稳定，降低所述驱动晶体管T1的源极或漏极对所述驱动晶体管T1栅极的影响，可以改善显示面板的显示效果。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的像素驱动电路及其驱动方法、显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种像素驱动电路，其中，包括：发光器件、驱动晶体管以及补偿模块；所述补偿模块至少包括：初始化晶体管及补偿晶体管；
    所述初始化晶体管用于响应第一扫描信号并将电位可变信号传输至所述驱动晶体管的栅极，初始化所述驱动晶体管的栅极电压；
    所述补偿晶体管用于响应补偿控制信号并将具有补偿阈值电压的数据信号传输至所述驱动晶体管的栅极；
    其中，所述初始化晶体管与所述补偿晶体管的类型不同；所述电位可变信号在发光阶段动态补偿所述驱动晶体管的栅极电压。
  2. 根据权利要求1所述的像素驱动电路，其中，所述初始化晶体管为硅晶体管或氧化物晶体管的其中之一，所述补偿晶体管为硅晶体管或氧化物晶体管的其中另一。
  3. 根据权利要求2所述的像素驱动电路，其中，所述初始化晶体管为硅晶体管，所述补偿晶体管为氧化物晶体管。
  4. 根据权利要求3所述的像素驱动电路，其中，所述初始化晶体管为P型晶体管；所述补偿晶体管为N型晶体管。
  5. 根据权利要求4所述的像素驱动电路，其中，所述电位可变信号在所述初始化晶体管响应所述第一扫描信号、所述补偿晶体管响应所述补偿控制信号时为恒定低电平信号，在所述发光阶段为连续上升信号。
  6. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括数据写入模块，所述数据写入模块用于响应第二扫描信号并将所述数据信号传输至所述驱动晶体管的源极或漏极。
  7. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括存储模块，所述存储模块用于维持所述驱动晶体管的栅极电压。
  8. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括发光控制模块，所述发光控制模块用于响应发光控制信号控制所述发光器件发光。
  9. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括复位模块，所述复位模块用于响应第二扫描信号并将复位信号传输至所述发光器件的阳极。
  10. 根据权利要求9所述的像素驱动电路，其中，所述复位信号为恒定信号。
  11. 根据权利要求1所述的像素驱动电路，其中，所述发光器件包括有机发光二极管、次毫米发光二极管及微型发光二极管的其中一种。
  12. 一种像素驱动电路的驱动方法，其中，用于驱动如权利要求1所述的像素驱动电路，在第N帧周期内，所述驱动方法包括：
    初始化阶段，所述补偿模块的所述初始化晶体管响应所述第一扫描信号，所述电位可变信号传输至所述驱动晶体管的栅极，初始化所述驱动晶体管的栅极电压；
    补偿阶段，所述补偿模块的所述补偿晶体管响应所述补偿控制信号，将具有补偿阈值电压的数据信号传输至所述驱动晶体管的栅极，补偿所述驱动晶体管的阈值电压；
    所述发光阶段，所述驱动晶体管驱动所述发光器件发光，所述电位可变信号动态补偿所述驱动晶体管的栅极电压。
  13. 根据权利要求12所述的驱动方法，其中，所述电位可变信号在所述初始化阶段和所述补偿阶段为恒定信号，所述电位可变信号在所述发光阶段随补偿前的所述驱动晶体管的栅极电压连续上升或连续下降。
  14. 一种显示面板，其中，包括：多个像素及控制所述像素发光的像素驱动电路；所述像素驱动电路包括：形成所述像素的发光器件，被配置为向所述发光器件提供驱动电流的驱动晶体管，用于提供电位可变信号的电位可变信号线，初始化晶体管，以及，补偿晶体管；所述初始化晶体管和补偿晶体管具有不同材料的半导体层；
    所述补偿晶体管的栅极与补偿控制信号线连接，所述补偿晶体管的源极或漏极中的一者与所述驱动晶体管的栅极连接，源极或漏极中的另一者与所述驱动晶体管的源极或漏极中的一者连接；
    所述初始化晶体管的栅极与第一扫描信号线连接，所述初始化晶体管的源极或漏极中的一者与电位可变信号线连接，源极或漏极中的另一者与所述驱动晶体管的栅极连接。
  15. 根据权利要求14所述的显示面板，其中，所述初始化晶体管和所述补偿晶体管的所述半导体层的载流子迁移率不同；所述初始化晶体管的所述半导体层的载流子迁移率大于所述补偿晶体管的所述半导体层的载流子迁移率；或，所述初始化晶体管的所述半导体层的载流子迁移率小于所述补偿晶体管的所述半导体层的载流子迁移率。
  16. 根据权利要求14所述的显示面板，其中，所述像素驱动电路还包括：
    数据写入晶体管，所述数据写入晶体管的栅极与第二扫描信号线连接，所述数据写入晶体管的源极或漏极中的一者与数据信号线连接，源极或漏极中的另一者与所述驱动晶体管的源极或漏极中的一者连接；
    存储电容，所述存储电容的上极板与第一电压端连接，下极板与所述初始化晶体管的源极或漏极中连接所述驱动晶体管栅极的一者、所述补偿晶体管的源极或漏极中连接所述驱动晶体管栅极的一者及所述驱动晶体管的栅极连接。
  17. 根据权利要求14所述的显示面板，其中，所述像素驱动电路还包括：
    第一开关晶体管，所述第一开关晶体管的栅极与发光控制信号线连接，所述第一开关晶体管的源极或漏极中的一者与第一电压端连接，源极或漏极中的另一者与所述驱动晶体管的源极或漏极中的一者连接；
    第二开关晶体管，所述第二开关晶体管的栅极与所述发光控制信号线连接，所述第二开关晶体管的源极或漏极中的一者与所述驱动晶体管的源极或漏极中的一者连接，源极或漏极中的另一者与所述发光器件的阳极连接。
  18. 根据权利要求14所述的显示面板，其中，所述像素驱动电路还包括：
    复位晶体管，所述复位晶体管的栅极与第二扫描信号线连接，所述复位晶体管的源极或漏极中的一者与复位信号线连接，源极或漏极中的另一者与所述发光器件的阳极连接，所述复位晶体管与所述初始化晶体管具有相同材料的半导体层。
  19. 根据权利要求14所述的显示面板，其中，所述显示面板还包括位于所述像素驱动电路与所述发光器件之间的导电层，在俯视视角下，所述导电层与所述补偿晶体管的正投影重合，且所述导电层覆盖所述补偿晶体管。
  20. 根据权利要求19所述的显示面板，其中，所述导电层的制备材料包括金、银、铜、锂、钠、钾、镁、铝、锌中的至少一种。
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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112233621B (zh) * 2020-10-10 2022-10-18 Oppo广东移动通信有限公司 一种像素驱动电路、显示面板及电子设备
CN117496874A (zh) * 2020-10-15 2024-02-02 厦门天马微电子有限公司 显示面板及其驱动方法以及显示装置
CN112150964B (zh) * 2020-10-23 2024-04-09 厦门天马微电子有限公司 显示面板及其驱动方法以及显示装置
US11763730B2 (en) 2020-11-11 2023-09-19 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel driving circuit having an initialization and compensation and display panel
CN112397029B (zh) * 2020-11-17 2022-04-08 武汉华星光电半导体显示技术有限公司 像素驱动电路及ltpo显示面板
CN112509517B (zh) 2020-11-26 2022-07-12 合肥维信诺科技有限公司 像素电路的驱动方法、显示面板
CN112530368B (zh) * 2020-12-08 2022-09-30 京东方科技集团股份有限公司 像素电路、显示面板及显示装置
CN112365843B (zh) * 2020-12-09 2022-02-08 武汉天马微电子有限公司 像素驱动电路及其驱动方法、显示面板及装置
CN112397565B (zh) * 2020-12-09 2022-08-05 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN112435628B (zh) * 2020-12-17 2021-12-28 武汉天马微电子有限公司 显示面板及其显示控制方法、占空比调整方法及显示装置
CN113192458B (zh) 2021-01-12 2022-04-15 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示面板
CN113066434B (zh) * 2021-03-24 2023-07-18 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、显示面板
CN113140179B (zh) * 2021-04-12 2022-08-05 武汉华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法、显示面板
CN115529840A (zh) * 2021-04-26 2022-12-27 京东方科技集团股份有限公司 像素电路、像素驱动方法和显示装置
US20230028312A1 (en) * 2021-04-26 2023-01-26 Chengdu Boe Optoelectronics Technology Co., Ltd. Pixel circuit, pixel driving method and display device
CN113160740A (zh) * 2021-04-28 2021-07-23 厦门天马微电子有限公司 显示面板和显示装置
TWI773294B (zh) * 2021-04-30 2022-08-01 友達光電股份有限公司 驅動電路及其驅動方法
CN113299230B (zh) * 2021-05-27 2023-01-10 昆山国显光电有限公司 像素驱动电路、像素驱动电路的驱动方法和显示面板
CN113450715B (zh) * 2021-06-25 2022-10-28 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN113724651B (zh) * 2021-09-06 2023-12-05 武汉华星光电半导体显示技术有限公司 一种阵列基板及显示面板
CN114078430A (zh) * 2021-12-09 2022-02-22 武汉华星光电半导体显示技术有限公司 像素电路及显示面板
CN114299859B (zh) * 2021-12-30 2023-05-30 湖北长江新型显示产业创新中心有限公司 一种阵列基板及其驱动方法、显示面板和显示装置
CN114446238A (zh) * 2022-01-26 2022-05-06 合肥维信诺科技有限公司 像素驱动电路、驱动方法及显示装置
CN114550653B (zh) * 2022-02-17 2024-04-09 京东方科技集团股份有限公司 像素驱动电路以及显示装置
CN114974130A (zh) * 2022-05-24 2022-08-30 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板及显示装置
WO2023226013A1 (zh) * 2022-05-27 2023-11-30 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN114913802A (zh) * 2022-05-31 2022-08-16 Tcl华星光电技术有限公司 像素驱动电路和显示面板
CN114999368A (zh) * 2022-05-31 2022-09-02 Tcl华星光电技术有限公司 像素驱动电路和显示面板

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105006218A (zh) * 2015-05-15 2015-10-28 友达光电股份有限公司 像素电路及其驱动方法
CN107799068A (zh) * 2016-08-31 2018-03-13 乐金显示有限公司 有机发光显示器
US20180144683A1 (en) * 2016-11-23 2018-05-24 Samsung Display Co., Ltd. Organic light emitting diode display device and method of driving the same
CN110277060A (zh) * 2019-05-21 2019-09-24 合肥维信诺科技有限公司 一种像素电路和显示装置
CN110322842A (zh) * 2019-05-21 2019-10-11 合肥维信诺科技有限公司 一种像素驱动电路及显示装置
CN110648629A (zh) * 2019-10-31 2020-01-03 厦门天马微电子有限公司 显示面板及其制作方法、显示装置
CN111276099A (zh) * 2020-03-24 2020-06-12 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板以及显示面板

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100560780B1 (ko) * 2003-07-07 2006-03-13 삼성에스디아이 주식회사 유기전계 발광표시장치의 화소회로 및 그의 구동방법
KR100873078B1 (ko) * 2007-04-10 2008-12-09 삼성모바일디스플레이주식회사 화소 및 이를 이용한 유기전계발광 표시장치 및 그의구동방법
JP2009276744A (ja) * 2008-02-13 2009-11-26 Toshiba Mobile Display Co Ltd Ｅｌ表示装置
US9818765B2 (en) * 2013-08-26 2017-11-14 Apple Inc. Displays with silicon and semiconducting oxide thin-film transistors
KR102288351B1 (ko) * 2014-10-29 2021-08-11 삼성디스플레이 주식회사 표시장치 및 그 구동방법
KR102307500B1 (ko) * 2015-03-20 2021-10-01 삼성디스플레이 주식회사 표시 장치의 화소회로 및 이를 포함하는 표시 장치
CN205541822U (zh) * 2016-04-06 2016-08-31 京东方科技集团股份有限公司 像素电路、阵列基板、显示面板和显示装置
US10157572B2 (en) * 2016-11-01 2018-12-18 Innolux Corporation Pixel driver circuitry for a display device
CN106448554A (zh) * 2016-11-30 2017-02-22 武汉华星光电技术有限公司 Oled驱动电路及oled显示面板
CN106601191B (zh) * 2016-12-02 2019-01-15 武汉华星光电技术有限公司 Oled驱动电路及oled显示面板
KR102564603B1 (ko) * 2016-12-20 2023-08-08 엘지디스플레이 주식회사 유기발광표시장치 및 그의 구동방법
CN107610652B (zh) * 2017-09-28 2019-11-19 京东方科技集团股份有限公司 像素电路、其驱动方法、显示面板及显示装置
CN108598087B (zh) * 2018-04-26 2021-01-15 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板、电子装置
US10490128B1 (en) * 2018-06-05 2019-11-26 Apple Inc. Electronic devices having low refresh rate display pixels with reduced sensitivity to oxide transistor threshold voltage
CN109523953A (zh) * 2018-12-21 2019-03-26 深圳市华星光电半导体显示技术有限公司 有源矩阵有机发光二极管像素驱动电路
CN111276497B (zh) * 2020-02-18 2023-08-15 京东方科技集团股份有限公司 驱动背板和显示面板
CN212365460U (zh) * 2020-07-17 2021-01-15 武汉华星光电半导体显示技术有限公司 像素驱动电路及显示面板

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105006218A (zh) * 2015-05-15 2015-10-28 友达光电股份有限公司 像素电路及其驱动方法
CN107799068A (zh) * 2016-08-31 2018-03-13 乐金显示有限公司 有机发光显示器
US20180144683A1 (en) * 2016-11-23 2018-05-24 Samsung Display Co., Ltd. Organic light emitting diode display device and method of driving the same
CN110277060A (zh) * 2019-05-21 2019-09-24 合肥维信诺科技有限公司 一种像素电路和显示装置
CN110322842A (zh) * 2019-05-21 2019-10-11 合肥维信诺科技有限公司 一种像素驱动电路及显示装置
CN110648629A (zh) * 2019-10-31 2020-01-03 厦门天马微电子有限公司 显示面板及其制作方法、显示装置
CN111276099A (zh) * 2020-03-24 2020-06-12 京东方科技集团股份有限公司 像素驱动电路及其驱动方法、阵列基板以及显示面板

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