WO2022007315A1 - 一种改善emi的深沟槽mos器件及其制造方法 - Google Patents

一种改善emi的深沟槽mos器件及其制造方法 Download PDF

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WO2022007315A1
WO2022007315A1 PCT/CN2020/132013 CN2020132013W WO2022007315A1 WO 2022007315 A1 WO2022007315 A1 WO 2022007315A1 CN 2020132013 W CN2020132013 W CN 2020132013W WO 2022007315 A1 WO2022007315 A1 WO 2022007315A1
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layer
trench
conductivity type
epitaxial layer
upper side
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French (fr)
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薛璐
何军
胡兴正
刘海波
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南京华瑞微集成电路有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the technical field of semiconductors, in particular to a deep trench MOS device for improving EMI and a manufacturing method thereof.
  • the cross-sectional view of an ordinary DeepTrench superjunction MOS power transistor is due to the characteristics of its process method, resulting in a vertically smooth P-pillar topography; in power adapter type applications with high EMI requirements, the smooth topography of P-pillar will cause In the process of MOS switching, Coss charges and discharges quickly, oscillates greatly, has a lot of noise, and has poor EMI performance. Therefore, improvements are necessary.
  • the purpose of the present invention is to provide a deep trench MOS device with improved EMI and a manufacturing method thereof in view of the deficiencies in the prior art.
  • the present invention provides a method for manufacturing a deep trench MOS device for improving EMI, comprising the following steps:
  • Step 1 Provide a substrate of the first conductivity type, fabricate several intermediate epitaxial layers on the substrate, and implant a heavily doped layer of the first conductivity type on the upper side of each intermediate epitaxial layer, and in the middle of the uppermost layer
  • the surface epitaxial layer is made on the upper side of the epitaxial layer
  • Step 2 a masking layer is formed on the surface epitaxial layer, a JEFT injection opening is formed on the masking layer in the active region, and a JEFT implantation operation is performed on the surface epitaxial layer through the JEFT injection opening, so that a JEFT implantation operation is performed on the surface epitaxial layer.
  • a JEFT implantation region forming a JEFT implantation region;
  • Step 3 make a trench opening on the masking layer, and make a trench on the surface epitaxial layer and the middle epitaxial layer through the trench opening, and the bottom of the trench is arranged in the middle epitaxial layer of the lowest layer, and is directed to all the layers. Filling the trenches with impurities of the second conductivity type;
  • Step 4 performing an annealing operation to anneal the heavily doped layer to form a pillar of the first conductivity type whose end is deep into the trench;
  • Step 5 grow an oxide layer on the surface epitaxial layer, the JEFT implantation area and the upper side of the trench, and remove the oxide layer in the active area, leaving only the oxide layer in the terminal area;
  • Step 6 A gate oxide layer is long on the upper side of the surface epitaxial layer in the oxide layer and the active region, polycrystalline is deposited on the upper side of the gate oxide layer in the active region, and polycrystalline is doped and etched. Etch away the polycrystalline and gate oxide layers on the upper side of the trench and between the active area and the terminal area;
  • Step 7 performing impurity implantation and well push operations on the surface epitaxial layers and polycrystals on both sides of the polycrystal in the active region to form a heavily doped region of the first conductivity type, and at the same time heavily doped the polycrystal;
  • Step 8 depositing a dielectric layer on the surface epitaxial layer, the trench, the heavily doped region of the first conductivity type and the upper side of the polycrystal, and etching the dielectric layer to form a connection hole;
  • a metal layer is formed by sputtering on the upper side of the dielectric layer and in the connection hole, and the metal layer is etched to form a gate region and a source region.
  • the implanted element of the heavily doped layer of the first conductivity type is phosphorus, the implanted energy is 60-80 KeV, and the implanted dose is 1E12-3E12.
  • the intermediate epitaxial layer includes 6 to 8 layers.
  • a junction region of the second conductivity type is implanted into the surface epitaxial layer around the trench, and the outer side of the upper end of the trench is connected to the junction region of the second conductivity type.
  • each intermediate epitaxial layer is 1-3 ⁇ cm, and the thickness thereof is 5-7 ⁇ m.
  • the present invention also provides a deep trench MOS device for improving EMI, comprising a substrate of a first conductivity type, and a plurality of intermediate epitaxial layers and surface epitaxial layers are sequentially provided on the upper side of the substrate, so A trench is formed in the middle epitaxial layer and the surface epitaxial layer, the bottom of the trench is arranged in the bottom middle epitaxial layer, the trench is filled with impurities of the second conductivity type, and the two sides of the trench are Several first conductivity type pillars are formed on the upper side of each intermediate epitaxial layer, the ends of the first conductivity type pillars are deep into the trench, and the surface epitaxial layers on both sides of the trench are provided with JEFT
  • an oxide layer is grown on the upper side of the surface epitaxial layer of the terminal region, a gate oxide layer is grown on the upper side of the surface epitaxial layer in the oxide layer and the active region, and the gate oxide layer in the active region is Polycrystalline is deposited on the
  • the intermediate epitaxial layer includes 6 to 8 layers.
  • a junction region of the second conductivity type is implanted into the surface epitaxial layer around the trench, and the outer side of the upper end of the trench is connected to the junction region of the second conductivity type.
  • each intermediate epitaxial layer is 1-3 ⁇ cm, and the thickness thereof is 5-7 ⁇ m.
  • a passivation layer is deposited on the upper side of the metal layer and the dielectric layer, and the passivation layer is etched to form an opening area of the gate electrode and the source electrode; the lower side of the substrate is sequentially evaporated with Ti, Ni and Ag layers.
  • the present invention arranges several first-conductivity-type pillars on both sides of the trench, and the ends of the first-conductivity-type pillars penetrate deep into the second-conductivity-type pillars in the trench, thereby changing the inner diameter of the trench.
  • the shape of the second conductive type of the pillar makes the charging and discharging of Coss slow during the switching process, reducing the switching oscillation, reducing the switching noise, and improving the EMI performance; and because the overall EPI thickness and mask are not increased. layer, the cost will not increase.
  • FIG. 1 is a schematic structural diagram of a substrate, an intermediate epitaxial layer and a surface epitaxial layer according to an embodiment of the present invention
  • FIG. 2 is a schematic view of the structure after performing a JEFT operation on the surface epitaxial layer
  • FIG. 3 is a schematic view of the structure after etching trenches and backfilling
  • Fig. 5 is the structural schematic diagram after the oxide layer is arranged in the terminal area
  • FIG. 6 is a schematic view of the structure after the long gate oxide layer is deposited and polycrystalline
  • FIG. 7 is a schematic structural diagram of a dielectric layer deposited and etched to form connecting holes
  • FIG. 8 is a schematic view of the structure after the metal layer is formed by sputtering.
  • an embodiment of the present invention provides a method for manufacturing a deep trench MOS device with improved EMI, including the following steps:
  • a substrate 1 of a first conductivity type is provided, several intermediate epitaxial layers 2 are fabricated on the substrate 1, and a heavily doped layer 3 of the first conductivity type is formed on the upper side of each intermediate epitaxial layer 2 by implantation.
  • a surface epitaxial layer 4 is formed on the upper side of the uppermost intermediate epitaxial layer 2 .
  • the substrate 1 is heavily doped with the first conductivity type, and the resistivity of the substrate 1 is usually 0.001-0.005 ⁇ cm. Different device withstand voltages can be obtained by choosing different epitaxial resistivity and thickness. Both the middle epitaxial layer 2 and the surface epitaxial layer 4 are lightly doped with the first conductivity type.
  • a layer of epitaxy with a thickness of 5-7 ⁇ m is first grown on the upper side of the substrate 1 , and an impurity injection of the first conductivity type is performed once, and the heavily doped layer 3 of the first conductivity type is injected with elements.
  • the implanted energy is 60-80KeV
  • the implanted dose is 1E12-3E12.
  • the operations of growth epitaxy and impurity injection are repeated, generally 5 to 7 times, so that 6 to 8 layers of the heavily doped layer 3 of the first conductivity type can be fabricated.
  • the resistivity of the surface epitaxial layer 4 is 1-3 ⁇ cm, and the thickness is preferably 5 ⁇ m.
  • the total thickness of the middle epitaxial layer 2 and the surface epitaxial layer 4 is preferably 45-60 ⁇ m, and the withstand voltage of the device can reach 500V-800V.
  • a masking layer 5 is grown on the surface epitaxial layer 4
  • a JEFT implantation opening 6 is formed on the masking layer 5 in the active region
  • a JEFT implantation operation is performed on the surface epitaxial layer 4 through the JEFT implantation opening 6, so that the surface epitaxial layer 4 is subjected to a JEFT implantation operation.
  • a JEFT implanted region 7 is formed on layer 4 .
  • the JEFT injection opening 6 is formed by sequentially applying glue, exposing and etching on the masking layer 5 . In order not to affect the subsequent process, the glue applied in this step needs to be removed after the JEFT injection operation is completed.
  • JEFT implanted energy 60KeV-80KeV
  • implanted dose 1E12-3E12
  • implanted element phosphorus element.
  • a trench opening 8 is formed on the masking layer 5, and a trench 9 is formed on the surface epitaxial layer 4 and the middle epitaxial layer 2 through the trench opening 8, and the bottom of the trench 9 is arranged on the bottom middle epitaxial layer 2 Inside, the trench 9 is filled with impurities of the second conductivity type.
  • the trench opening 8 and the trench 9 are also formed by gluing, exposing and etching. In order not to affect the subsequent process, after filling the trench 9 with impurities, the glue applied in this step should be removed.
  • Step 4 performing an annealing operation to anneal the heavily doped layer 3 to form a pillar 10 of the first conductivity type whose end portion is deep into the trench 9 .
  • Annealing temperature 1100°C
  • annealing time 30-180 minutes.
  • step 5 the oxide layer 11 is grown on the surface epitaxial layer 4, the JEFT implantation region 7 and the upper side of the trench 9, and the oxide layer 11 in the active region is removed, and only the oxide layer 11 in the terminal region is retained.
  • the thickness of the grown oxide layer 11 is preferably 8000-12000 angstroms.
  • Step 6 In the oxide layer 11 and the upper side of the surface epitaxial layer 4 in the active region, the gate oxide layer 12 is long, and polycrystalline 13 is deposited on the upper side of the gate oxide layer 12 in the active region, and polycrystalline doping is performed , and etch away the termination region, the upper side of the trench 9 and the polycrystalline 13 and gate oxide layer 12 between the active region and the termination region.
  • the thickness of the gate oxide layer 12 is preferably 700-1200 angstroms
  • the thickness of the polycrystalline 13 is preferably 6000-8000 angstroms.
  • the doping of the polycrystalline 13 in this step is done through a diffusion furnace.
  • step 7 the surface epitaxial layer 4 on both sides of the polycrystalline 13 and the polycrystalline 13 in the active region perform impurity implantation and well push operations to form a heavily doped region 14 of the first conductivity type, and at the same time re-doping the polycrystalline 13 miscellaneous.
  • Step 8 depositing a dielectric layer 15 on the surface epitaxial layer 4 , the trench 9 , the heavily doped region 14 of the first conductivity type and the upper side of the polycrystalline 13 , and etching the dielectric layer 15 to form a connection hole 16 .
  • the dielectric layer 15 is preferably BPSG (borophosphosilicate glass), and the thickness of the dielectric layer 15 is preferably 10,000 angstroms.
  • a metal layer 17 is formed by sputtering on the upper side of the dielectric layer 15 and in the connection hole 16, and the metal layer 17 is etched to form a gate region and a source region.
  • the metal layer 17 is preferably an aluminum layer, and its thickness is preferably 4 ⁇ m.
  • a junction region 18 of the second conductivity type may also be implanted into the surface epitaxial layer 4 around the trench 9, and the outer side of the upper end of the trench 9 is connected to the junction region 18 of the second conductivity type .
  • a passivation layer is deposited on the upper side of the metal layer 17, and the passivation layer is etched to form opening regions of the gate electrode and the source electrode.
  • Step 11 thinning is performed from the bottom side of the substrate 1 , the remaining thickness of the device is 200 ⁇ m-300 ⁇ m, and Ti, Ni and Ag (titanium, nickel and silver) are sequentially evaporated on the bottom side of the substrate 1 .
  • the present invention also provides a deep trench MOS device for improving EMI, comprising a substrate 1 of a first conductivity type, wherein the substrate 1 is The first conductivity type is heavily doped, and the resistivity of the substrate 1 is usually 0.001-0.005 ⁇ cm. Different device withstand voltages can be obtained by choosing different epitaxial resistivity and thickness.
  • intermediate epitaxial layers 2 and surface epitaxial layers 4 are sequentially provided on the upper side of the substrate 1 , and both the intermediate epitaxial layers 2 and the surface epitaxial layers 4 are lightly doped with the first conductivity type.
  • a layer of epitaxy with a thickness of 5-7 ⁇ m is first grown on the upper side of the substrate 1, and then a first conductivity type impurity injection is performed once to form a first conductivity type heavily doped layer 3.
  • the implanted element of the heavily doped layer 3 of the first conductivity type is preferably phosphorus, the implanted energy is 60-80 KeV, and the implanted dose is 1E12-3E12.
  • the resistivity of the surface epitaxial layer 4 is 1-3 ⁇ cm, and the thickness is preferably 5 ⁇ m.
  • the total thickness of the middle epitaxial layer 2 and the surface epitaxial layer 4 is preferably 45-60 ⁇ m, and the withstand voltage of the device can reach 500V-800V.
  • a trench 9 is formed in the intermediate epitaxial layer 2 and the surface epitaxial layer 4, the bottom of the trench 9 is arranged in the bottommost intermediate epitaxial layer 2, the trench 9 is filled with impurities of the second conductivity type, and the trench 9 is filled with impurities of the second conductivity type.
  • a plurality of first conductive type pillars 10 are formed on the upper side of each intermediate epitaxial layer 2 on both sides, and the first conductive type pillars 10 are formed by annealing the heavily doped layer 3 of the first conductive type. The temperature of the annealing is : 1100°C, annealing time: 30-180 minutes.
  • the end of the pillar 10 of the first conductivity type penetrates deep into the interior of the trench 9, and the surface epitaxial layer 4 on both sides of the trench 9 is provided with a JEFT implantation region 7, and the JEFT implantation region 7 is formed by the JEFT implantation operation.
  • An oxide layer 11 is grown on the upper side of the surface epitaxial layer 4 in the termination region, and the thickness of the oxide layer 11 is preferably 8000-12000 angstroms.
  • a gate oxide layer 12 is formed on the upper side of the oxide layer 11 and the surface epitaxial layer 4 in the active region, and the thickness of the gate oxide layer 12 is preferably 700-1200 angstroms.
  • a polycrystalline 13 is deposited on the upper side of the gate oxide layer 12 in the active region, and the thickness of the polycrystalline 13 is preferably 6000-8000 angstroms.
  • the terminal area, the upper side of the trench 9 and the gate oxide layer 12 and the polycrystalline 13 between the active area and the terminal area, and the surface epitaxial layer 4 on both sides of the polycrystalline 13 is formed with the first conductivity type.
  • the heavily doped region 14 is heavily doped to the polycrystalline 13 at the same time.
  • the surface epitaxial layer 4 not covered by the gate oxide layer 12 and the upper ends of the trench 9 are formed with heavily doped regions 14 of the first conductivity type.
  • the implantation dose of the heavily doped regions 14 of the first conductivity type is : 5E15-1E16, implant energy: 60KeV-120KeV, implant element: arsenic, push well temperature: 950 °C, push well time: 30 minutes.
  • a dielectric layer 15 is deposited on the surface epitaxial layer 4 , the trench 9 , the heavily doped region 14 of the first conductivity type and the upper side of the polycrystalline 13 .
  • the dielectric layer 15 is preferably BPSG (borophosphosilicate glass), and the thickness of the dielectric layer 15 Preferably it is 10000 angstroms.
  • a connection hole 16 is formed on the dielectric layer 15 by etching, a metal layer 17 is formed on the upper side of the dielectric layer 15 and in the connection hole 16 by sputtering, and the metal layer 17 is etched to form the gate region and the source region of the MOS device.
  • the metal layer 17 is preferably an aluminum layer, and its thickness is preferably 4 ⁇ m.
  • a junction region 18 of the second conductivity type may be implanted into the surface epitaxial layer 4 around the trench 9 , and the outer side of the upper end of the trench 9 is connected to the junction region 18 of the second conductivity type.
  • Junction region 18 Implanted amount: 4E13-6E13, implanted energy: 100KeV-140KeV, implanted element: boron.
  • a passivation layer can also be deposited on the upper side of the metal layer 17 and the dielectric layer 15, and an opening area with a gate electrode and a source electrode can be formed by etching on the passivation layer, or Ti can be sequentially evaporated on the lower side of the substrate 1. , Ni and Ag layers, thinned from the bottom side of the substrate 1 before evaporating the Ti, Ni and Ag layers, and the remaining thickness of the device is 200 ⁇ m-300 ⁇ m.

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Abstract

一种改善EMI的深沟槽MOS器件及其制造方法。该器件包括衬底（1）、若干层中间外延层（2）和表面外延层（4），中间外延层（2）和表面外延层（4）内形成有沟槽（9），沟槽（9）的底部设置在最底层的中间外延层（2）内，沟槽（9）内填充有第二导电类型的杂质，沟槽（9）的两侧的每层中间外延层（2）上侧形成若干个第一导电类型的pillar（10），第一导电类型的pillar（10）的端部深入至沟槽（9）的内部。通过在沟槽（9）的两侧设置若干个第一导电类型的pillar（10），从而改变沟槽（9）内的第二导电类型的pillar（10）的形状，使得开关过程中，Coss的充放电会变缓，减小了开关震荡，降低了开关噪声，EMI性能得到提升；且由于未增加整体的EPI厚度及光罩层，成本也不会增加。

Description

一种改善EMI的深沟槽MOS器件及其制造方法 技术领域
本发明涉及半导体技术领域，具体涉及一种改善EMI的深沟槽MOS器件及其制造方法。
背景技术
普通DeepTrench超结MOS功率管的剖面图由于其工艺方法的特征，导致P-pillar形貌是垂直平滑的；在对EMI有高要求的电源适配器类型应用中，P-pillar平滑的形貌会导致MOS开关过程中，Coss充放电快，震荡大，噪声多，EMI性能不佳。因此，有必要进行改进。
发明内容
本发明的目的是针对现有技术存在的不足，提供一种改善EMI的深沟槽MOS器件及其制造方法。
为实现上述目的，在第一方面，本发明提供了一种改善EMI的深沟槽MOS器件的制造方法，包括以下步骤：
步骤1，提供第一导电类型的衬底，在所述衬底上制作若干层中间外延层，每层中间外延层的上侧注入形成有第一导电类型的重掺杂层，在最上层中间外延层上侧制作表面外延层；
步骤2，在所述表面外延层上长掩蔽层，在有源区内的掩蔽层上制作JEFT注入开口，并通过所述JEFT注入开口对表面外延层进行JEFT注入操作，以在表面外延层上形成JEFT注入区；
步骤3，在所述掩蔽层上制作沟槽开口，并通过所述沟槽开口在表面外延层和中间外延层上制作沟槽，沟槽的底部设置在最底层的中间外延层内，向所述沟槽内填充第二导电类型的杂质；
步骤4，执行退火操作，以将所述重掺杂层退火形成端部深入至沟槽内部的第一导电类型的pillar；
步骤5，在表面外延层、JEFT注入区和沟槽的上侧长氧化层，并将有源区内的氧化层去除，仅保留终端区的氧化层；
步骤6，在所述氧化层和有源区内的表面外延层的上侧长栅氧化层，在有 源区内的栅氧化层的上侧沉积多晶，并进行多晶掺杂，并刻蚀掉沟槽上侧以及有源区与终端区之间的多晶及栅氧化层；
步骤7，在有源区内多晶两侧的表面外延层及多晶执行杂质注入和推阱操作，以形成第一导电类型的重掺杂区，同时对多晶重掺杂；
步骤8，在所述表面外延层、沟槽、第一导电类型的重掺杂区和多晶的上侧沉积介质层，在所述介质层上刻蚀形成连接孔；
步骤9，在所述介质层的上侧及连接孔内溅射形成金属层，并将所述金属层刻蚀形成栅区和源区。
进一步的，所述第一导电类型的重掺杂层的注入元素为磷，注入的能量60-80KeV，注入的剂量1E12-3E12。
进一步的，所述中间外延层包括6至8层。
进一步的，在步骤4中的退火操作前，还在沟槽四周的表面外延层内注入形成有第二导电类型的结区，所述沟槽的上端外侧与第二导电类型的结区连接。
进一步的，每层中间外延层的电阻率为1-3Ω.cm，且其厚度为5-7μm。
在第二方面，本发明还提供了一种改善EMI的深沟槽MOS器件，包括第一导电类型的衬底，所述衬底上侧依次设有若干层中间外延层和表面外延层，所述中间外延层和表面外延层内形成有沟槽，所述沟槽的底部设置在最底层的中间外延层内，所述沟槽内填充有第二导电类型的杂质，所述沟槽两侧的每层中间外延层上侧形成若干个第一导电类型的pillar，所述第一导电类型的pillar的端部深入至沟槽的内部，所述沟槽两侧的表面外延层上设有JEFT注入区，在终端区的表面外延层的上侧长有氧化层，在所述氧化层和有源区内的表面外延层的上侧长有栅氧化层，在有源区内的栅氧化层的上侧沉积有多晶，并刻蚀掉终端区、沟槽上侧以及有源区与终端区之间的栅氧化层和多晶，在所述多晶两侧的表面外延层内形成有第一导电类型的重掺杂区，同时对所述多晶进行重掺杂，在所述表面外延层、沟槽、第一导电类型的重掺杂区和多晶的上侧沉积有介质层，在所述介质层上刻蚀形成有连接孔，在所述介质层的上侧及连接孔内溅射形成有金属层，所述金属层刻蚀形成有栅区和源区。
进一步的，所述中间外延层包括6至8层。
进一步的，在退火操作前，还在沟槽四周的表面外延层内注入形成有第二导电类型的结区，所述沟槽的上端外侧与第二导电类型的结区连接。
进一步的，每层中间外延层的电阻率为1-3Ω.cm，且其厚度为5-7μm。
进一步的，所述金属层和介质层的上侧沉积有钝化层，所述钝化层上刻蚀形成有栅极和源极的开口区；所述衬底的下侧依次蒸发有Ti、Ni和Ag层。
有益效果：本发明通过在沟槽的两侧设置若干个第一导电类型的pillar，第一导电类型的pillar的端部深入至沟槽内的第二导电类型的pillar内，从而改变沟槽内的第二导电类型的pillar的形状，使得开关过程中，Coss的充放电会变缓，减小了开关震荡，降低了开关噪声，EMI性能得到提升；且由于未增加整体的EPI厚度及光罩层，成本也不会增加。
附图说明
图1是本发明实施例的衬底、中间外延层和表面外延层的结构示意图；
图2是在表面外延层上执行JEFT操作后的结构示意图；
图3是刻蚀沟槽并回填后的结构示意图；
图4是执行退火操作后的结构示意图；
图5是在终端区设置氧化层后的结构示意图；
图6是长栅氧化层并沉积多晶后的结构示意图；
图7是沉淀介质层并刻蚀形成连接孔后的结构示意图；
图8是溅射形成金属层后的结构示意图。
具体实施方式
下面结合附图和具体实施例，进一步阐明本发明，本实施例在以本发明技术方案为前提下进行实施，应理解这些实施例仅用于说明本发明而不用于限制本发明的范围。
如图1至8所示，本发明实施例提供了一种改善EMI的深沟槽MOS器件的制造方法，包括以下步骤：
步骤1，提供第一导电类型的衬底1，在衬底1上制作若干层中间外延层2，每层中间外延层2的上侧注入形成有第一导电类型的重掺杂层3，在最上层中间外延层2上侧制作表面外延层4。其中，衬底1为第一导电类型重掺杂，衬 底1的电阻率通常为0.001-0.005Ω.cm。选择不同的外延电阻率和厚度，可得到不同的器件耐压。中间外延层2和表面外延层4均为第一导电类型轻掺杂。在制作中间外延层2时，先在衬底1的上侧生长一层厚度为5-7μm外延，进行一次第一导电类型的杂质普注，第一导电类型的重掺杂层3的注入元素优选为磷，注入的能量60-80KeV，注入的剂量1E12-3E12。然后重复生长外延和杂质普注操作，一般重复5至7次，即可制作出6至8层第一导电类型的重掺杂层3。表面外延层4的电阻率为1-3Ω.cm，厚度优选为5μm。中间外延层2与表面外延层4的总厚度优选为45-60μm，器件耐压可以达到500V-800V。
步骤2，在表面外延层4上长掩蔽层5，在有源区内的掩蔽层5上制作JEFT注入开口6，并通过JEFT注入开口6对表面外延层4进行JEFT注入操作，以在表面外延层4上形成JEFT注入区7。具体的，JEFT注入开口6是通过在掩蔽层5上依次涂胶、曝光和刻蚀形成。为了不影响后续工艺，在完成JEFT注入操作后，需要将此步骤涂的胶去除。JEFT注入的能量：60KeV-80KeV,注入剂量：1E12-3E12,注入元素：磷元素。
步骤3，在掩蔽层5上制作沟槽开口8，并通过沟槽开口8在表面外延层4和中间外延层2上制作沟槽9，沟槽9的底部设置在最底层的中间外延层2内，向沟槽9内填充第二导电类型的杂质。沟槽开口8和沟槽9也是经过涂胶、曝光和刻蚀形成。为了不影响后续工艺，在向沟槽9内填充好杂质后，应将此步骤中涂的胶去除。
步骤4，执行退火操作，以将重掺杂层3退火形成端部深入至沟槽9内部的第一导电类型的pillar 10。退火的温度：1100℃，退火的时间：30-180分钟。
步骤5，在表面外延层4、JEFT注入区7和沟槽9的上侧长氧化层11，并将有源区内的氧化层11去除，仅保留终端区的氧化层11。生长氧化层11的厚度优选为8000-12000埃。
步骤6，在氧化层11和有源区内的表面外延层4的上侧长栅氧化层12，在有源区内的栅氧化层12的上侧沉积多晶13，并进行多晶掺杂，并刻蚀掉终端区、沟槽9上侧以及有源区与终端区之间的多晶13及栅氧化层12。其中，栅 氧化层12的厚度优选为700-1200埃，多晶13的厚度优选为6000-8000埃。此步骤中的对多晶13掺杂是通过扩散炉进行掺杂。
步骤7，在有源区内多晶13两侧的表面外延层4及多晶13执行杂质注入和推阱操作，以形成第一导电类型的重掺杂区14，同时对多晶13重掺杂。第一导电类型的重掺杂区14的注入剂量：5E15-1E16,注入能量：60KeV-120KeV，注入元素：砷，推阱温度：950℃，推阱时间：30分钟。
步骤8，在表面外延层4、沟槽9、第一导电类型的重掺杂区14和多晶13的上侧沉积介质层15，在介质层15上刻蚀形成连接孔16。介质层15优选为BPSG(硼磷硅玻璃)，介质层15的厚度优选为10000埃。
步骤9，在介质层15的上侧及连接孔16内溅射形成金属层17，并将金属层17刻蚀形成栅区和源区。其中，金属层17优选为铝层，其厚度优选为4μm。
在步骤4中的退火操作前，还可以在沟槽9四周的表面外延层4内注入形成有第二导电类型的结区18，沟槽9的上端外侧与第二导电类型的结区18连接。结区18注入剂量：4E13-6E13,注入能量：100KeV-140KeV，注入元素：硼。
还可以像现有技术一样选择性执行以下步骤：
步骤10，在金属层17的上侧沉积钝化层，并将钝化层刻蚀形成栅极和源极的开口区。
步骤11，从衬底1的底侧进行减薄，器件的剩余厚度为200μm-300μm，在衬底1的底侧依次蒸发Ti、Ni和Ag(钛、镍和银)。
结合图1至8，基于以上实施例，本领域技术人员可以理解，本发明还提供了一种改善EMI的深沟槽MOS器件，包括第一导电类型的衬底1，其中，衬底1为第一导电类型重掺杂，衬底1的电阻率通常为0.001-0.005Ω.cm。选择不同的外延电阻率和厚度，可得到不同的器件耐压。
在衬底1的上侧依次设有若干层中间外延层2和表面外延层4，中间外延层2和表面外延层4均为第一导电类型轻掺杂。在制作中间外延层2时，先在衬底1的上侧生长一层厚度为5-7μm外延，然后进行一次第一导电类型的杂质普注，即可形成第一导电类型的重掺杂层3，第一导电类型的重掺杂层3的注入元素优选为磷，注入的能量60-80KeV，注入的剂量1E12-3E12。然后重复 生长外延和杂质普注操作，一般重复5至7次，即可制作出6至8层第一导电类型的重掺杂层3。表面外延层4的电阻率为1-3Ω.cm，厚度优选为5μm。中间外延层2与表面外延层4的总厚度优选为45-60μm，器件耐压可以达到500V-800V。
在中间外延层2和表面外延层4内形成有沟槽9，沟槽9的底部设置在最底层的中间外延层2内，在沟槽9内填充有第二导电类型的杂质，在沟槽9两侧的每层中间外延层2的上侧形成若干个第一导电类型的pillar 10，第一导电类型的pillar 10由上述第一导电类型的重掺杂层3经退火形成，退火的温度：1100℃，退火的时间：30-180分钟。第一导电类型的pillar 10的端部深入至沟槽9的内部，沟槽9两侧的表面外延层4上设有JEFT注入区7，JEFT注入区7通过JEFT注入操作形成，JEFT操作注入的能量：60KeV-80KeV,注入剂量：1E12-3E12,注入元素：磷元素。
在终端区的表面外延层4的上侧长有氧化层11，氧化层11的厚度优选为8000-12000埃。在氧化层11和有源区内的表面外延层4的上侧长有栅氧化层12，栅氧化层12的厚度优选为700-1200埃。在有源区内的栅氧化层12的上侧沉积有多晶13，多晶13的厚度优选为6000-8000埃。并刻蚀掉终端区、沟槽9上侧以及有源区与终端区之间的栅氧化层12和多晶13，在多晶13两侧的表面外延层4内形成有第一导电类型的重掺杂区14，同时对多晶13进行重掺杂。在有源区内无栅氧化层12覆盖的表面外延层4和沟槽9上侧两端制作有第一导电类型的重掺杂区14，第一导电类型的重掺杂区14的注入剂量：5E15-1E16,注入能量：60KeV-120KeV，注入元素：砷，推阱温度：950℃，推阱时间：30分钟。在表面外延层4、沟槽9、第一导电类型的重掺杂区14和多晶13的上侧沉积介质层15，介质层15优选为BPSG(硼磷硅玻璃)，介质层15的厚度优选为10000埃。在介质层15上刻蚀形成有连接孔16，在介质层15的上侧及连接孔16内溅射形成金属层17，并将金属层17刻蚀形成MOS器件的栅区和源区。金属层17优选为铝层，其厚度优选为4μm。
在退火操作前，还可以在沟槽9四周的表面外延层4内注入形成有第二导电类型的结区18，沟槽9的上端外侧与第二导电类型的结区18连接。结区18 注入量：4E13-6E13,注入能量：100KeV-140KeV，注入元素：硼。
还可以在金属层17和介质层15的上侧沉积有钝化层，在钝化层上刻蚀形成有栅极和源极的开口区，也可以在衬底1的下侧依次蒸发有Ti、Ni和Ag层，在蒸发Ti、Ni和Ag层前，先从衬底1的底侧进行减薄，器件的剩余厚度为200μm-300μm。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，其它未具体描述的部分，属于现有技术或公知常识。在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

  1. 一种改善EMI的深沟槽MOS器件的制造方法，其特征在于，包括以下步骤：
    步骤1，提供第一导电类型的衬底，在所述衬底上制作若干层中间外延层，每层中间外延层的上侧注入形成有第一导电类型的重掺杂层，在最上层中间外延层上侧制作表面外延层；
    步骤2，在所述表面外延层上长掩蔽层，在有源区内的掩蔽层上制作JEFT注入开口，并通过所述JEFT注入开口对表面外延层进行JEFT注入操作，以在表面外延层上形成JEFT注入区；
    步骤3，在所述掩蔽层上制作沟槽开口，并通过所述沟槽开口在表面外延层和中间外延层上制作沟槽，沟槽的底部设置在最底层的中间外延层内，向所述沟槽内填充第二导电类型的杂质；
    步骤4，执行退火操作，以将所述重掺杂层退火形成端部深入至沟槽内部的第一导电类型的pillar；
    步骤5，在表面外延层、JEFT注入区和沟槽的上侧长氧化层，并将有源区内的氧化层去除，仅保留终端区的氧化层；
    步骤6，在所述氧化层和有源区内的表面外延层的上侧长栅氧化层，在栅氧化层的上侧沉积多晶，并进行多晶掺杂，并刻蚀掉终端区、沟槽上侧以及有源区与终端区之间的多晶及栅氧化层；
    步骤7，在有源区内多晶两侧的表面外延层及多晶执行杂质注入和推阱操作，以形成第一导电类型的重掺杂区，同时对多晶重掺杂；
    步骤8，在所述表面外延层、沟槽、第一导电类型的重掺杂区和多晶的上侧沉积介质层，在所述介质层上刻蚀形成连接孔；
    步骤9，在所述介质层的上侧及连接孔内溅射形成金属层，并将所述金属层刻蚀形成栅区和源区。
  2. 根据权利要求1所述的改善EMI的深沟槽MOS器件的制造方法，其特征在于，所述第一导电类型的重掺杂层的注入元素为磷，注入的能量60-80KeV，注入的剂量1E12-3E12。
  3. 根据权利要求1所述的改善EMI的深沟槽MOS器件的制造方法，其特征 在于，所述中间外延层包括6至8层。
  4. 根据权利要求1所述的改善EMI的深沟槽MOS器件的制造方法，其特征在于，在步骤4中的退火操作前，还在沟槽四周的表面外延层内注入形成有第二导电类型的结区，所述沟槽的上端外侧与第二导电类型的结区连接。
  5. 根据权利要求1所述的改善EMI的深沟槽MOS器件的制造方法，其特征在于，每层中间外延层的电阻率为1-3Ω.cm，且其厚度为5-7μm。
  6. 一种改善EMI的深沟槽MOS器件，其特征在于，包括第一导电类型的衬底，所述衬底上侧依次设有若干层中间外延层和表面外延层，所述中间外延层和表面外延层内形成有沟槽，所述沟槽的底部设置在最底层的中间外延层内，所述沟槽内填充有第二导电类型的杂质，所述沟槽两侧的每层中间外延层上侧形成若干个第一导电类型的pillar，所述第一导电类型的pillar的端部深入至沟槽的内部，所述沟槽两侧的表面外延层上设有JEFT注入区，在终端区的表面外延层的上侧长有氧化层，在所述氧化层和有源区内的表面外延层的上侧长有栅氧化层，在有源区内的栅氧化层的上侧沉积有多晶，并刻蚀掉终端区、沟槽上侧以及有源区与终端区之间的栅氧化层和多晶，在所述多晶两侧的表面外延层内形成有第一导电类型的重掺杂区，同时对所述多晶进行重掺杂，在所述表面外延层、沟槽、第一导电类型的重掺杂区和多晶的上侧沉积有介质层，在所述介质层上刻蚀形成有连接孔，在所述介质层的上侧及连接孔内溅射形成有金属层，所述金属层刻蚀形成有栅区和源区。
  7. 根据权利要求6所述的改善EMI的深沟槽MOS器件，其特征在于，所述中间外延层包括6至8层。
  8. 根据权利要求6所述的改善EMI的深沟槽MOS器件，其特征在于，在退火操作前，还在沟槽四周的表面外延层内注入形成有第二导电类型的结区，所述沟槽的上端外侧与第二导电类型的结区连接。
  9. 根据权利要求6所述的改善EMI的深沟槽MOS器件，其特征在于，每层中间外延层的电阻率为1-3Ω.cm，且其厚度为5-7μm。
  10. 根据权利要求6所述的改善EMI的深沟槽MOS器件，其特征在于，所述金属层和介质层的上侧沉积有钝化层，所述钝化层上刻蚀形成有栅极和源极 的开口区；所述衬底的下侧依次蒸发有Ti、Ni和Ag层。
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CN111668292A (zh) * 2020-07-09 2020-09-15 南京华瑞微集成电路有限公司 一种改善emi的深沟槽mos器件及其制造方法
CN112117330B (zh) * 2020-09-21 2024-05-07 南京华瑞微集成电路有限公司 一种改善深槽超结mosfet耐压的器件结构及其工艺方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9136381B1 (en) * 2014-11-18 2015-09-15 Texas Instruments Incorporated Super junction MOSFET with integrated channel diode
CN105720089A (zh) * 2016-02-16 2016-06-29 上海华虹宏力半导体制造有限公司 超级结及其制造方法
CN109713029A (zh) * 2018-12-14 2019-05-03 无锡紫光微电子有限公司 一种改善反向恢复特性的多次外延超结器件制作方法
CN111668292A (zh) * 2020-07-09 2020-09-15 南京华瑞微集成电路有限公司 一种改善emi的深沟槽mos器件及其制造方法
CN212303676U (zh) * 2020-07-09 2021-01-05 南京华瑞微集成电路有限公司 一种改善emi的深沟槽mos器件

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9136381B1 (en) * 2014-11-18 2015-09-15 Texas Instruments Incorporated Super junction MOSFET with integrated channel diode
CN105720089A (zh) * 2016-02-16 2016-06-29 上海华虹宏力半导体制造有限公司 超级结及其制造方法
CN109713029A (zh) * 2018-12-14 2019-05-03 无锡紫光微电子有限公司 一种改善反向恢复特性的多次外延超结器件制作方法
CN111668292A (zh) * 2020-07-09 2020-09-15 南京华瑞微集成电路有限公司 一种改善emi的深沟槽mos器件及其制造方法
CN212303676U (zh) * 2020-07-09 2021-01-05 南京华瑞微集成电路有限公司 一种改善emi的深沟槽mos器件

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