WO2022000173A1 - 线路板及其制作方法 - Google Patents

线路板及其制作方法 Download PDF

Info

Publication number
WO2022000173A1
WO2022000173A1 PCT/CN2020/098882 CN2020098882W WO2022000173A1 WO 2022000173 A1 WO2022000173 A1 WO 2022000173A1 CN 2020098882 W CN2020098882 W CN 2020098882W WO 2022000173 A1 WO2022000173 A1 WO 2022000173A1
Authority
WO
WIPO (PCT)
Prior art keywords
opening
inner layer
layer structure
circuit board
mask
Prior art date
Application number
PCT/CN2020/098882
Other languages
English (en)
French (fr)
Inventor
徐筱婷
周倩楠
胡先钦
何明展
沈芾云
Original Assignee
庆鼎精密电子（淮安）有限公司
鹏鼎控股(深圳)股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 庆鼎精密电子（淮安）有限公司, 鹏鼎控股(深圳)股份有限公司 filed Critical 庆鼎精密电子（淮安）有限公司
Priority to PCT/CN2020/098882 priority Critical patent/WO2022000173A1/zh
Priority to CN202080063205.8A priority patent/CN114365584A/zh
Priority to TW109122164A priority patent/TWI770547B/zh
Publication of WO2022000173A1 publication Critical patent/WO2022000173A1/zh
Priority to US17/709,659 priority patent/US20220225510A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447—Lead-in-hole components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3485—Applying solder paste, slurry or powder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09572—Solder filled plated through-hole in the final product
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/26—Cleaning or polishing of the conductive pattern

Definitions

  • the invention relates to the field of electronic components, in particular to a circuit board and a manufacturing method thereof.
  • the application provides a method for making a circuit board, comprising the following steps:
  • An inner layer structure is provided, the inner layer structure includes a conductive circuit and a cover layer, the cover layer is arranged on the outermost side of the inner layer structure, and the conductive circuit includes a first connection end;
  • a mask is provided on the side of the cover layer away from the conductive circuit, the mask is provided with a plurality of first openings penetrating the mask;
  • the cover layer is etched through the mask to form a second opening, so that the first connection end is exposed by the second opening;
  • An electronic component is provided, and the electronic component is electrically connected to the first connection end.
  • the diameter of the second opening gradually increases from the inside to the outside of the inner layer structure.
  • the number of the second openings is multiple, the multiple second openings are arranged at intervals, and the multiple second openings with different sizes are completed by one laser cutter head in one scanning path.
  • the step of surface-treating the inner layer structure includes:
  • a gold layer is formed on the surface of the first connection end exposed by the second opening.
  • the mask is removed before the surface treatment is performed on the inner layer structure; a conductive paste is arranged in the second opening, so that at least part of the electronic component is arranged in the second opening and is electrically connected to the conductive circuit through the conductive paste.
  • the application also provides a circuit board, comprising:
  • An inner layer structure the inner layer structure includes a conductive circuit, a cover layer and a plurality of second openings, the cover layer is arranged at least part of the outermost part of the inner layer structure, and the conductive circuit includes a first connection end , the first connection end is exposed by the second opening;
  • the gold chemical layer is disposed on the surface of the first connection end located in the second opening;
  • the electronic components are electrically connected with the conductive lines through the gold layer.
  • the diameter of the second opening gradually increases from the inside to the outside of the inner layer structure.
  • the cross-sectional shape of the second opening is a trapezoid, and the edge of the second opening in contact with the first connecting end is the top edge of the trapezoid.
  • the cover layer includes an elastic polymer material, and the material of the cover layer includes liquid crystal polymer, polypropylene, polyethylene terephthalate, polyimide, polytetrafluoroethylene, and polyethylene. at least one of olefins.
  • the circuit board of the present application can solve the problems of limited etching precision in the traditional solder mask process, and it is difficult to achieve small-sized and high-precision punching openings and electrical connection of components, reducing the production process and reducing the material cost.
  • the cover layer can be made of elastic polymer material.
  • the cover layer of the elastic polymer material can absorb part of the pressure when the electronic components are squeezed with the inner layer structure, so as to prevent the electronic components from breaking .
  • a plurality of second openings with different sizes can be completed by one laser cutter head in one scanning path.
  • the laser cutter head will only be stacked inside when scanning to the first opening. That is, using the laser to cooperate with the mask for etching can reduce the replacement of the laser cutter head and the adjustment of the energy parameters, and the etching of multiple second openings can be realized in one scanning process, which improves the production efficiency; and, the etching process Among them, the shape of the second opening can be determined by the shape of the first opening on the mask.
  • the shape and size of the mask can be limited, and it can be applied to punching openings of various shapes and sizes, so that the second opening is The shape need not be limited by the maximum fillet of the laser head.
  • FIG. 1 is a schematic diagram of a prefabricated inner layer structure in a manufacturing process of a circuit board according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of etching the inner layer structure by laser matching a mask in a manufacturing process of a circuit board according to an embodiment of the present invention.
  • FIG. 3 is a schematic plan view of etching with a laser matched with a mask in a manufacturing process of a circuit board according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of removing residues in the second opening in a manufacturing process of a circuit board according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of surface treatment of the first connection end in the manufacturing process of the circuit board according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of forming a gold layer in the second opening in a manufacturing process of a circuit board according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of disposing conductive paste in the second opening in the manufacturing process of the circuit board according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of arranging electronic components in a manufacturing process of a circuit board according to an embodiment of the present invention.
  • FIG. 9 is a schematic cross-sectional view of a wiring board according to an embodiment of the present invention.
  • the first substrate 101 is the first substrate 101
  • a manufacturing method of a circuit board comprising the following steps:
  • Step S1 providing an inner layer structure 10 , the inner layer structure 10 includes a conductive circuit 102 and a cover layer 104 , the cover layer 104 is disposed on the outermost side of the inner layer structure 10 , and the conductive circuit 102 includes a first connection end 105 .
  • a prefabricated circuit board motherboard is provided.
  • the circuit board motherboard is an inner layer structure 10
  • the inner layer structure 10 may include a first substrate 101 , a conductive circuit 102 , and an adhesive layer. 103 and cover layer 104.
  • the conductive circuit 102 is disposed on the surface of the first substrate 101
  • the adhesive layer 103 is disposed on the side of the conductive circuit 102 away from the first substrate 101
  • the cover layer 104 is disposed on the side of the adhesive layer 103 away from the conductive circuit 102
  • the cover layer 104 is bonded to the first substrate 101 and the conductive traces 102 and covers the conductive traces 102 .
  • the inner layer structure 10 may be a double-layer board, the two layers of conductive lines 102 are disposed on the opposite surfaces of the first substrate 101 , and the adhesive layer 103 and the cover layer 104 are both disposed to be opposite to the inner layer structure 10 . both surfaces of the back.
  • the inner layer structure 10 may not include a solder mask layer.
  • the traditional solder mask layer has limited etching accuracy, and it is difficult to achieve small-scale, high-precision etching and component placement;
  • the protective effect of the laminated structure 10 can reduce the manufacturing process, reduce the material cost, and improve the reliability of the product.
  • Step S2 providing a mask 20 on the side of the cover layer 104 away from the conductive line 102 , the mask 20 is provided with a plurality of first openings 21 penetrating the mask 20 ; the cover layer is exposed to the cover layer through the mask 20 by means of laser etching 104 is etched to form a second opening 106 so that the first connection end 105 is exposed by the second opening 106 .
  • the mask 20 covers the surface of the cover layer 104 , and the laser cutter head 22 emits laser light to etch the inner layer structure 10 .
  • the cover layer 104 corresponds to the first opening 21 At least part of it is removed to form the second opening 106 .
  • the mask 20 can be a prefabricated structure, and the prefabricated mask 20 can be reused.
  • the portion of the adhesive layer 103 corresponding to the first opening 21 is removed during the laser etching process so that the first connection end 105 is exposed.
  • the diameter of the second opening 106 gradually increases from the inside of the inner layer structure 10 to the outside, and the second opening 106 with a small inside and a large outside is formed during the etching process.
  • the second opening 106 which is small in the inside and large in the outside, can facilitate the gas to escape during the subsequent stamping process.
  • the number of the first openings 21 and the second openings 106 may be multiple, and the multiple second openings 106 may be arranged at intervals, wherein the distance between two adjacent second openings 106 may be smaller than the distance between them and other second openings 106 . Spacing between openings 106 .
  • a plurality of second openings 106 with different sizes are completed by one laser cutter head 22 in one scanning path.
  • the laser cutter head 22 does not etch the inner layer structure 10 until the first opening 21 is scanned.
  • the adjustment of the energy parameter can realize the etching of the plurality of second openings 106 in one scanning process, thereby improving the manufacturing efficiency. As shown in FIG.
  • the shape of the second opening 106 can be determined by the shape of the first opening 21 on the mask 20 .
  • the shape and size of the mask 20 and the shape and size of the first opening 21 on the mask 20 can be limited. It is applied to punching openings of various shapes and sizes, so that the shape of the second opening 106 does not need to be limited by the maximum rounding of the laser cutter head 22 .
  • Step S3 performing surface treatment on the inner layer structure 10 .
  • Step S31 removing the mask 20 .
  • the removed mask 20 can be reused in the above process.
  • Step S32 As shown in FIG. 4, there may be residues 24 in the second opening 106 after laser etching, and the residues 24 may be glue residue or ablation ash after etching. The residue 24 in the opening 106 is removed so that the surface of the first connection end 105 is sufficiently exposed.
  • Step S33 As shown in FIG. 5 , surface treatment is performed on the surface of the first connection end 105, and the surface treatment can improve the smoothness and flatness of the first connection end 105.
  • Step S34 As shown in FIG. 6 , a gold layer 11 is formed on the surface of the first connection end 105 exposed by the second opening 106 .
  • a gold metallization layer 11 may be formed on the surface of the first connection terminal 105 by a process such as chemical coating or physical coating.
  • the gold metallization layer 11 may be a metallized conductive layer such as a nickel layer or a gold layer.
  • Step S35 As shown in FIG. 7 , the conductive paste 12 is arranged in the second opening 106 to electrically connect the conductive paste 12 and the gold layer 11 , that is, the conductive paste 12 and the first connection terminal 105 are electrically connected through the gold layer 11 . sexual connection.
  • Step S4 providing the electronic element 13 to electrically connect the electronic element 13 to the first connection terminal 105 .
  • the electronic component 13 includes a first surface 131 and a second surface 132 disposed on opposite sides, the first surface 131 is in contact with the inner layer structure 10 , and the second surface 132 is disposed on the electronic component 13 away from the inner layer structure 10 .
  • the electronic component 13 further includes two electrical pins 130.
  • the two electrical pins 130 are disposed in the second opening 106 and are electrically connected to the gold layer 11 through the conductive paste 12.
  • the two electrical pins 130 can be arranged with two adjacent second openings 106 .
  • the present application also provides a circuit board 1 manufactured by the above manufacturing method.
  • the circuit board 1 includes an inner layer structure 10 , a gold layer 11 , a conductive paste 12 and an electronic component 13 .
  • the inner layer structure 10 includes a first substrate 101 , a conductive circuit 102 , an adhesive layer 103 and a cover layer 104 .
  • the conductive circuit 102 is disposed on the surface of the first substrate 101
  • the adhesive layer 103 is disposed on the side of the conductive circuit 102 away from the first substrate 101
  • the cover layer 104 is disposed on the side of the adhesive layer 103 away from the conductive circuit 102
  • the cover layer 104 The adhesive layer 103 is bonded to the first substrate 101 and the conductive traces 102 and covers the conductive traces 102 .
  • the inner layer structure 10 may be a double-layer board, the two layers of conductive lines 102 are disposed on opposite surfaces of the first substrate 101 , and the adhesive layer 103 and the cover layer 104 are both disposed opposite to the inner layer structure 10 . both surfaces of the back.
  • the inner layer structure 10 may not include a solder mask layer.
  • the traditional solder mask layer has limited etching accuracy, and it is difficult to achieve small-scale, high-precision etching and component placement;
  • the protective effect of the laminated structure 10 can reduce the manufacturing process, reduce the material cost, and improve the reliability of the product.
  • the inner layer structure 10 further includes a second opening 106 , the conductive trace 102 includes a first connecting end 105 , and the second opening 106 penetrates at least part of the adhesive layer 103 and the cover layer 104 to expose at least part of the first connecting end 105 .
  • the diameter of the second opening 106 gradually increases from the inside of the inner layer structure 10 to the outside.
  • the cross-sectional shape of the second opening 106 is a trapezoid, and the edge of the second opening 106 in contact with the first connecting end 105 is the top edge of the trapezoid.
  • the gold layer 11 is disposed on the surface of the first connection end 105 located in the second opening 106 .
  • a gold metallization layer 11 may be formed on the surface of the first connection terminal 105 by a process such as chemical coating or physical coating.
  • the gold metallization layer 11 may be a metallized conductive layer such as a nickel layer or a gold layer.
  • a conductive paste 12 is further disposed in the second opening 106 , and the conductive paste 12 fills at least part of the second opening 106 and is electrically connected to the gold layer 11 .
  • the electronic components 13 are electrically connected to the conductive lines 102 through the gold layer 11 .
  • the electronic component 13 includes a first surface 131 and a second surface 132 disposed on opposite sides, the first surface 131 is in contact with the inner layer structure 10 , and the second surface 132 is disposed on the electronic component 13 away from the inner layer.
  • the electronic component 13 further includes two electrical pins 130, the two electrical pins 130 are arranged in the second opening 106 and are electrically connected to the gold layer 11 through the conductive paste 12, and the two electrical pins 130 It can be arranged in two adjacent second openings 106 .
  • the first surface 131 of the electronic component 13 is not in direct contact with the inner layer structure 10 .
  • the cover layer 104 can be made of an elastic polymer material, and the material of the cover layer 104 includes liquid crystal polymer, polypropylene, polyethylene terephthalate, polyimide, polytetrafluoroethylene and polyolefin at least one of them.
  • the cover layer 104 of elastic polymer material can absorb part of the pressure when the electronic component 13 is pressed against the inner layer structure 10 , so as to prevent the electronic component 13 from cracking.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

本申请提供一种线路板的制作方法，包括如下步骤：提供一内层叠构，所述内层叠构包括一导电线路及一覆盖层，所述覆盖层设置于所述内层叠构最外侧，所述导电线路包括第一连接端；在所述覆盖层远离所述导电线路一侧提供一掩膜，所述掩膜开设有多个贯穿所述掩膜的第一开口；使用激光蚀刻的方式，透过所述掩膜对所述覆盖层进行蚀刻形成第二开口，使所述第一连接端由所述第二开口暴露；对所述内层叠构进行表面处理；提供电子元件，使所述电子元件与所述第一连接端电性连接。本申请还提供一种由上述制作方法制作的线路板。

Description

线路板及其制作方法 技术领域
本发明涉及电子元件领域，尤其涉及一种线路板及其制作方法。
背景技术
近年来，电子产品被广泛应用在日常工作和生活中，轻、薄、小的电子产品越来越受到欢迎。线路板作为电子产品的主要部件，其占据了电子产品的较大空间，因此线路板的体积在很大程度上影响了电子产品的体积，大体积的线路板势必难以符合电子产品轻、薄、短、小之趋势。
现有的线路板，若需要减小线路板的体积，一种解决思路是提高线路板上电子元件(如电阻、电容)的排布密度以及使用更小的电子元件，提升排布密度或替换更小的电子元件需要在线路板上开设尺寸更小、密度更大的接脚端口。传统技术采用防焊制程在线路板上制作接脚端口，受菲林涨缩以及曝光设备的影响，很难制作出小尺寸、高精度的接脚端口；另外，通过防焊制程制作的端口的形状呈现外窄内宽(上窄下宽)的正梯形结构，使得在锡膏进行回流焊时端口内的气体不易排出，造成焊接不良以及元件的可靠性降低。
如何解决上述问题，是本领域技术人员需要考虑的。
发明内容
有鉴于此，有必要提供一种解决上述问题的线路板的制作方法，还提供一种上述制作方法制作的线路板。
本申请提供一种线路板的制作方法，包括如下步骤：
提供一内层叠构，所述内层叠构包括一导电线路及一覆盖层，所述覆盖层设置于所述内层叠构最外侧，所述导电线路包括第一连接端；
在所述覆盖层远离所述导电线路一侧提供一掩膜，所述掩膜开设有多个贯穿所述掩膜的第一开口；
使用激光蚀刻的方式，透过所述掩膜对所述覆盖层进行蚀刻形成第二开口，使所述第一连接端由所述第二开口暴露；
对所述内层叠构进行表面处理；以及
提供电子元件，使所述电子元件与所述第一连接端电性连接。
于一实施例中，在垂直于所述内层叠构的方向上，所述第二开口的直径由所述内层叠构内部向外部逐渐增大。
于一实施例中，所述第二开口的数量为多个，多个所述第二开口间隔设置，多个尺寸不完全相同的所述第二开口由一个激光刀头在一次扫描路径中完成。
于一实施例中，对所述内层叠构进行表面处理的步骤包括：
去除所述第二开口内的残留物；
对所述第一连接端的表面进行前处理；以及
在所述第一连接端由所述第二开口暴露的表面形成一化金层。
于一实施例中，对所述内层叠构进行表面处理前移除所述掩膜；在所述第二开口中设置导电膏，使所述电子元件的至少部分设置于所述第二开口中并通过所述导电膏与所述导电线路电性连接。
本申请还提供一种线路板，包括：
内层叠构，所述内层叠构包括一导电线路、一覆盖层及多个第二开口，所述覆盖层设置于所述内层叠构最外侧的至少部分，所述导电线路包括第一连接端，所述第一连接端由所述第二开口暴露；
化金层，所述化金层设置于所述第一连接端位于所述第二开口中的表面；以及
电子元件，电子元件通过所述化金层与所述导电线路电性连接。
于一实施例中，在垂直于所述内层叠构的方向上，所述第二开口的直径 由所述内层叠构内部向外部逐渐增大。
于一实施例中，所述第二开口的截面图形为梯形，所述第二开口与所述第一连接端接触的边为该梯形顶边。于一实施例中，所述覆盖层包含弹性高分子材料，所述覆盖层的材料包括液晶聚合物、聚丙烯、聚对苯二甲酸乙二酯、聚酰亚胺、聚四氟乙烯以及聚烯烃中的至少一种。
相较于现有技术，本申请的线路板可以解决传统的防焊制程蚀刻精度有限，难以实现小尺寸、高精度的打件开口及元件电性连接等问题，减少制作流程，降低物料成本，提升产品可靠性；覆盖层可采用弹性高分子材料，第一表面与覆盖层接触时，弹性高分子材料的覆盖层可以吸收电子元件与内层叠构挤压时的部分压力，避免电子元件产生破裂。本申请的线路板的制作方法，多个尺寸不完全相同的第二开口可由一个激光刀头在一次扫描路径中完成，由于存在掩膜，使得激光刀头在扫描至第一开口时才会对内层叠构进行蚀刻，即，使用激光配合掩膜进行蚀刻可以减少激光刀头的替换及能量参数的调整，在一次扫描过程中即可实现对多个第二开口的蚀刻，提高制作效率；且，蚀刻过程中，第二开口的形状可由掩膜上第一开口的形状决定，在制作掩膜时可以通过限制掩膜的形状以及大小，应用于各种形状以及大小的打件开口，使得第二开口的形状无需受制于激光刀头最大圆角化的限制。
附图说明
图1是本发明一实施方式的线路板的制作流程中预制的内层叠构的示意图。
图2是本发明一实施方式的线路板的制作流程中激光配合掩膜对内层叠构进行蚀刻的示意图。
图3是本发明一实施方式的线路板的制作流程中激光配合掩膜对蚀刻的平面示意图。
图4是本发明一实施方式的线路板的制作流程中去除第二开口内的残留物的示意图。
图5是本发明一实施方式的线路板的制作流程中对第一连接端进行表面处理的示意图。
图6是本发明一实施方式的线路板的制作流程中在第二开口中形成化金层的示意图。
图7是本发明一实施方式的线路板的制作流程中在第二开口内设置导电膏的示意图。
图8是本发明一实施方式的线路板的制作流程中设置电子元件的示意图。
图9是本发明一实施方式的线路板的截面示意图。
主要元件符号说明
线路板                    1
内层叠构                  10
第一基板                  101
导电线路                  102
粘胶层                    103
覆盖层                    104
第一连接端                105
第二开口                  106
化金层                    11
导电膏                    12
电子元件                  13
电接脚                    130
第一表面                  131
第二表面                  132
掩膜                      20
第一开口                  21
激光刀头                  22
残留物                    24
如下具体实施方式将结合上述附图进一步说明本发明。
具体实施方式
以下描述将参考附图以更全面地描述本申请内容。附图中所示为本申请的示例性实施例。然而，本申请可以以许多不同的形式来实施，并且不应该被解释为限于在此阐述的示例性实施例。提供这些示例性实施例是为了使本申请透彻和完整，并且将本申请的范围充分地传达给本领域技术人员。类似的附图标记表示相同或类似的组件。
本文使用的术语仅用于描述特定示例性实施例的目的，而不意图限制本申请。如本文所使用的，除非上下文另外清楚地指出，否则单数形式“一”，“一个”和“该”旨在也包括复数形式。此外，当在本文中使用时，“包括”和/或“包含”或“包括”和/或“包括”或“具有”和/或“具有”，整数，步骤，操作，组件和/或组件，但不排除存在或添加一个或多个其它特征，区域，整数，步骤，操作，组件，组件和/或其群组。
除非另外定义，否则本文使用的所有术语(包括技术和科学术语)具有与本申请所属领域的普通技术人员通常理解的相同的含义。此外，除非文中明确定义，诸如在通用字典中定义的那些术语应该被解释为具有与其在相关技术和本申请内容中的含义一致的含义，并且将不被解释为理想化或过于正式的含义。
以下内容将结合附图对示例性实施例进行描述。须注意的是，参考附图中所描绘的组件不一定按比例显示；而相同或类似的组件将被赋予相同或相似的附图标记表示或类似的技术用语。
下面参照附图，对本申请的具体实施方式作进一步的详细描述。
一种线路板1的制作方法，包括如下步骤：
步骤S1：提供一内层叠构10，内层叠构10包括一导电线路102及一覆盖层104，覆盖层104设置于内层叠构10最外侧，导电线路102包括第一连接端105。
如图1所示，于一实施例中，提供一预制的线路板母板，该线路板母板为内层叠构10，内层叠构10可包括第一基板101、导电线路102、粘胶层103以及覆盖层104。导电线路102设置于第一基板101的表面，粘胶层103设置于导电线路102远离第一基板101一侧，覆盖层104设置于粘胶层103远离导电线路102一侧，覆盖层104通过粘胶层103与第一基板101及导电线路102粘结并覆盖导电线路102。
于一实施例中，内层叠构10可以为一双层板，两层导电线路102设置于第一基板101相背的两表面，粘胶层103及覆盖层104均设置与内层叠构10相背的两表面。
于一实施例中，内层叠构10可不包括防焊层，传统的防焊层蚀刻精度有限，难以实现小尺寸、高精度的蚀刻及元件安放；去除防焊层，使覆盖层104兼具内层叠构10的防护作用，可减少制作流程，降低物料成本，提升产品可靠性。
步骤S2：在覆盖层104远离导电线路102一侧提供一掩膜20，掩膜20开设有多个贯穿掩膜20的第一开口21；使用激光蚀刻的方式，透过掩膜20对覆盖层104进行蚀刻形成第二开口106，使第一连接端105由第二开口106暴露。
如图2所示，于一实施例中，掩膜20覆盖于覆盖层104的表面，通过激光刀头22发射激光并对内层叠构10进行蚀刻，蚀刻过程中，覆盖层104对应第一开口21的至少部分被去除以形成第二开口106。
于一实施例中，掩膜20可以为预制结构，所述预制的掩膜20可重复使用。
于一实施例中，当内层叠构10包括粘胶层103时，激光蚀刻过程中去除 粘胶层103与第一开口21对应的部分使得第一连接端105暴露。
于一实施例中，在垂直于内层叠构10的方向上，第二开口106的直径由内层叠构10内部向外部逐渐增大，在蚀刻过程中形成内小外大的第二开口106，该内小外大的第二开口106可有利于后续打件过程中气体溢出。
于一实施例中，第一开口21及第二开口106的数量可以为多个，多个第二开口106间隔设置，其中，相邻两个第二开口106的间距可小于其与其他第二开口106之间的间距。
于一实施例中，多个尺寸不完全相同的第二开口106由一个激光刀头22在一次扫描路径中完成。在蚀刻过程中，由于存在掩膜20，使得激光刀头22在扫描至第一开口21时才会对内层叠构10进行蚀刻，即，使用激光配合掩膜20进行蚀刻可以减少激光刀头的替换及能量参数的调整，在一次扫描过程中即可实现对多个第二开口106的蚀刻，提高制作效率。如图3所示，使用激光配合掩膜20可以实现一次扫描对多个第二开口106的蚀刻，可避免因过度蚀刻对内层叠构10造成损伤，且可进一步提升蚀刻精度；且，蚀刻过程中，第二开口106的形状可由掩膜20上第一开口21的形状决定，在制作掩膜20时可以通过限制掩膜20的形状以及大小，以及掩膜20上第一开口21的形状及大小，应用于各种形状以及大小的打件开口，使得第二开口106的形状无需受制于激光刀头22最大圆角化的限制。
步骤S3：对内层叠构10进行表面处理。
步骤S31：移除掩膜20。
于一实施例中，移除后的掩膜20可再次用于上述工艺中。
步骤S32：如图4所示，激光蚀刻后的第二开口106中可能存在残留物24，残留物24可以为残胶或者蚀刻后的烧蚀灰烬，使用等离子体或其他除胶工艺对第二开口106中的残留物24进行清除，以使第一连接端105的表面充分暴露。
步骤S33：如图5所示，对第一连接端105的表面进行表面处理，表面 处理可以提高第一连接端105的光洁度及平整度。
步骤S34：如图6所示，在第一连接端105由第二开口106暴露的表面形成一化金层11。于一实施例中，可以通过化学镀膜或物理镀膜等工艺，在第一连接端105表面形成一化金层11，化金层11可以为镍层、金层等金属化导电层。
步骤S35：如图7所示，在第二开口106中设置导电膏12，使导电膏12与化金层11电性连接，即，导电膏12与第一连接端105通过化金层11电性连接。
步骤S4：提供电子元件13，使电子元件13与第一连接端105电性连接。
于一实施例中，如图8所示，使电子元件13的至少部分设置于第二开口106中并通过导电膏12与第一连接端105电性连接。具体的，电子元件13包括设置于相背两侧的第一表面131及第二表面132，第一表面131与内层叠构10接触，第二表面132设置于电子元件13远离内层叠构10一侧，电子元件13还包括两个电接脚130，两个电接脚130设置于第二开口106中并通过导电膏12与化金层11电性连接，两个电接脚130可设置与相邻的两个第二开口106中。挤压设置电接脚130时，设置于下窄上宽的第二开口106中的导电膏12逐渐填充第二开口106，且第二开口106中的气体可及时排除。
如图9所示，本申请还提供由上述制作方法制作的线路板1。
线路板1包括内层叠构10、化金层11、导电膏12及电子元件13。
内层叠构10包括第一基板101、导电线路102、粘胶层103以及覆盖层104。导电线路102设置于第一基板101的表面，粘胶层103设置于导电线路102远离第一基板101一侧，覆盖层104设置于粘胶层103远离导电线路102一侧，覆盖层104通过粘胶层103与第一基板101及导电线路102粘结并覆盖导电线路102。
于一实施例中，内层叠构10可以为一双层板，两层导电线路102设置于第一基板101相背的两表面，粘胶层103及覆盖层104均设置与内层叠构10 相背的两表面。
于一实施例中，内层叠构10可不包括防焊层，传统的防焊层蚀刻精度有限，难以实现小尺寸、高精度的蚀刻及元件安放；去除防焊层，使覆盖层104兼具内层叠构10的防护作用，可减少制作流程，降低物料成本，提升产品可靠性。
内层叠构10还包括第二开口106，导电线路102包括第一连接端105，第二开口106贯穿粘胶层103及覆盖层104的至少部分使第一连接端105的至少部分暴露。
在垂直于内层叠构10的方向上，第二开口106的直径由内层叠构10内部向外部逐渐增大。于一实施例中，第二开口106的截面图形为梯形，第二开口106与第一连接端105接触的边为该梯形的顶边。
化金层11设置于第一连接端105位于第二开口106中的表面。于一实施例中，可以通过化学镀膜或物理镀膜等工艺，在第一连接端105表面形成一化金层11，化金层11可以为镍层、金层等金属化导电层。
于一实施例中，第二开口106中还设置有导电膏12，导电膏12填充第二开口106的至少部分并与化金层11电性连接。
电子元件13通过化金层11与导电线路102电性连接。
于一实施例中，电子元件13包括设置于相背两侧的第一表面131及第二表面132，第一表面131与内层叠构10接触，第二表面132设置于电子元件13远离内层叠构10一侧，电子元件13还包括两个电接脚130，两个电接脚130设置于第二开口106中并通过导电膏12与化金层11电性连接，两个电接脚130可设置与相邻的两个第二开口106中。在其他实施例中，电子元件13的第一表面131并未直接与内层叠构10接触。
于一实施例中，覆盖层104可采用弹性高分子材料，覆盖层104的材料包括液晶聚合物、聚丙烯、聚对苯二甲酸乙二酯、聚酰亚胺、聚四氟乙烯以及聚烯烃中的至少一种。第一表面131与覆盖层104接触时，弹性高分子材料的覆盖层104可以吸收电子元件13与内层叠构10挤压时的部分压力，避免电子元件13产生破裂。
以上所述，仅是本发明的较佳实施方式而已，并非对本发明任何形式上的限制，虽然本发明已是较佳实施方式揭露如上，并非用以限定本发明，任何熟悉本专业的技术人员，在不脱离本发明技术方案范围内，当可利用上述揭示的技术内容做出些许更动或修饰为等同变化的等效实施方式，但凡是未脱离本发明技术方案内容，依据本发明的技术实质对以上实施方式所做的任何简单修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (9)

  1. 一种线路板的制作方法，其特征在于，包括如下步骤：
    提供一内层叠构，所述内层叠构包括一导电线路及一覆盖层，所述覆盖层设置于所述内层叠构最外侧，所述导电线路包括第一连接端；
    在所述覆盖层远离所述导电线路一侧提供一掩膜，所述掩膜开设有多个贯穿所述掩膜的第一开口；
    使用激光蚀刻的方式，透过所述掩膜对所述覆盖层进行蚀刻形成第二开口，使所述第一连接端由所述第二开口暴露；
    对所述内层叠构进行表面处理；以及
    提供电子元件，使所述电子元件与所述第一连接端电性连接。
  2. 如权利要求1所述的线路板的制作方法，其特征在于，在垂直于所述内层叠构的方向上，所述第二开口的直径由所述内层叠构内部向外部逐渐增大。
  3. 如权利要求1所述的线路板的制作方法，其特征在于，所述第二开口的数量为多个，多个所述第二开口间隔设置，多个尺寸不完全相同的所述第二开口由一个激光刀头在一次扫描路径中完成。
  4. 如权利要求1所述的线路板的制作方法，其特征在于，对所述内层叠构进行表面处理的步骤包括：
    去除所述第二开口内的残留物；
    对所述第一连接端的表面进行前处理；以及
    在所述第一连接端由所述第二开口暴露的表面形成一化金层。
  5. 如权利要求1所述的线路板的制作方法，其特征在于，对所述内层叠构进行表面处理前移除所述掩膜；在所述第二开口中设置导电膏，使所述电子元件的至少部分设置于所述第二开口中并通过所述导电膏与所述导电线路电性连接。
  6. 一种线路板，其特征在于，包括：
    内层叠构，所述内层叠构包括一导电线路、一覆盖层及多个第二开口，所述覆盖层设置于所述内层叠构最外侧的至少部分，所述导电线路包括第一连接端，所述第一连接端由所述第二开口暴露；
    化金层，所述化金层设置于所述第一连接端位于所述第二开口中的表面；以及
    电子元件，电子元件通过所述化金层与所述导电线路电性连接。
  7. 如权利要求6所述的线路板，其特征在于，在垂直于所述内层叠构的方向上，所述第二开口的直径由所述内层叠构内部向外部逐渐增大。
  8. 如权利要求7所述的线路板，其特征在于，所述第二开口的截面图形为梯形，所述第二开口与所述第一连接端接触的边为该梯形顶边。
  9. 如权利要求6所述的线路板，其特征在于，所述覆盖层包括弹性高分子材料，所述覆盖层的材料包括液晶聚合物、聚丙烯、聚对苯二甲酸乙二酯、聚酰亚胺、聚四氟乙烯以及聚烯烃中的至少一种。
PCT/CN2020/098882 2020-06-29 2020-06-29 线路板及其制作方法 WO2022000173A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/CN2020/098882 WO2022000173A1 (zh) 2020-06-29 2020-06-29 线路板及其制作方法
CN202080063205.8A CN114365584A (zh) 2020-06-29 2020-06-29 线路板及其制作方法
TW109122164A TWI770547B (zh) 2020-06-29 2020-06-30 線路板及其製作方法
US17/709,659 US20220225510A1 (en) 2020-06-29 2022-03-31 Circuit board and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/098882 WO2022000173A1 (zh) 2020-06-29 2020-06-29 线路板及其制作方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/709,659 Continuation-In-Part US20220225510A1 (en) 2020-06-29 2022-03-31 Circuit board and method for manufacturing the same

Publications (1)

Publication Number Publication Date
WO2022000173A1 true WO2022000173A1 (zh) 2022-01-06

Family

ID=79317831

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/098882 WO2022000173A1 (zh) 2020-06-29 2020-06-29 线路板及其制作方法

Country Status (4)

Country Link
US (1) US20220225510A1 (zh)
CN (1) CN114365584A (zh)
TW (1) TWI770547B (zh)
WO (1) WO2022000173A1 (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997037520A1 (en) * 1996-03-29 1997-10-09 Intel Corporation Method for depositing solder onto pad-on and pad-off via contacts
CN101730382A (zh) * 2008-10-28 2010-06-09 英业达股份有限公司 线路板与电子组件的接合结构
KR20120124554A (ko) * 2011-05-04 2012-11-14 삼성전기주식회사 인쇄회로기판 및 그 제조방법
CN105592620A (zh) * 2014-10-21 2016-05-18 富葵精密组件(深圳)有限公司 电路板及其制法
CN206402512U (zh) * 2016-11-03 2017-08-11 宏启胜精密电子(秦皇岛)有限公司 柔性电路板
CN107666771A (zh) * 2016-07-29 2018-02-06 同扬光电（江苏）有限公司 线路板结构
CN110087392A (zh) * 2018-01-25 2019-08-02 欣兴电子股份有限公司 线路板结构及其制作方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5712192A (en) * 1994-04-26 1998-01-27 International Business Machines Corporation Process for connecting an electrical device to a circuit substrate
US6631558B2 (en) * 1996-06-05 2003-10-14 Laservia Corporation Blind via laser drilling system
JP3670196B2 (ja) * 2000-04-26 2005-07-13 三井金属鉱業株式会社 プリント配線板の製造法
JP3920195B2 (ja) * 2002-11-11 2007-05-30 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP4646618B2 (ja) * 2004-12-20 2011-03-09 イビデン株式会社 光路変換部材、多層プリント配線板および光通信用デバイス
JP2006278929A (ja) * 2005-03-30 2006-10-12 Shinko Electric Ind Co Ltd フレキシブル回路基板の製造方法
TWI394504B (zh) * 2005-05-31 2013-04-21 Hitachi Via Mechanics Ltd 印刷配線板之製造方法與使用該方法製出的銅箔層積板以及處理液
CN100446232C (zh) * 2005-10-27 2008-12-24 全懋精密科技股份有限公司 倒装片基板的表面结构
JP5243735B2 (ja) * 2007-06-18 2013-07-24 ローム株式会社 回路基板及び半導体装置
CN101320719A (zh) * 2008-07-09 2008-12-10 日月光半导体制造股份有限公司 线路载板及其制作方法
TWI399148B (zh) * 2009-09-15 2013-06-11 Unimicron Technology Corp 電路板焊接墊結構及其製法
US10149392B2 (en) * 2015-02-16 2018-12-04 Nippo Mektron, Ltd. Manufacturing method of flexible printed wiring board
TWI637836B (zh) * 2016-04-06 2018-10-11 綠點高新科技股份有限公司 模內射出物品的製法及其製品及電子裝置的殼件
TWI621194B (zh) * 2017-06-28 2018-04-11 中華精測科技股份有限公司 測試介面板組件
CN107949166B (zh) * 2017-11-30 2020-04-14 广州兴森快捷电路科技有限公司 埋置元件电路板的制作方法及埋置元件电路板
CN108803149B (zh) * 2018-07-20 2021-05-25 京东方科技集团股份有限公司 面光源及其制作方法以及液晶显示装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997037520A1 (en) * 1996-03-29 1997-10-09 Intel Corporation Method for depositing solder onto pad-on and pad-off via contacts
CN101730382A (zh) * 2008-10-28 2010-06-09 英业达股份有限公司 线路板与电子组件的接合结构
KR20120124554A (ko) * 2011-05-04 2012-11-14 삼성전기주식회사 인쇄회로기판 및 그 제조방법
CN105592620A (zh) * 2014-10-21 2016-05-18 富葵精密组件(深圳)有限公司 电路板及其制法
CN107666771A (zh) * 2016-07-29 2018-02-06 同扬光电（江苏）有限公司 线路板结构
CN206402512U (zh) * 2016-11-03 2017-08-11 宏启胜精密电子(秦皇岛)有限公司 柔性电路板
CN110087392A (zh) * 2018-01-25 2019-08-02 欣兴电子股份有限公司 线路板结构及其制作方法

Also Published As

Publication number Publication date
US20220225510A1 (en) 2022-07-14
TW202201689A (zh) 2022-01-01
TWI770547B (zh) 2022-07-11
CN114365584A (zh) 2022-04-15

Similar Documents

Publication Publication Date Title
JP4701506B2 (ja) 回路ブロック体の製造方法、配線回路装置の製造方法並びに半導体装置の製造方法
CN101013686B (zh) 互连衬底、半导体器件及其制造方法
JP2011023751A (ja) 電子部品内蔵型多層印刷配線基板及びその製造方法
JP2008258625A (ja) インターポーザおよびその製造方法ならびに電子回路パッケージ
US10477704B2 (en) Multilayer board and electronic device
JP2004095756A (ja) 半導体パッケージおよびその製造方法、並びに電子装置
US20160247696A1 (en) Interposer and method for producing the same
JP2018512694A (ja) 電気接続構造の製造方法
CN101534610A (zh) 埋入式电容元件电路板及其制造方法
TWI736918B (zh) 電路板及其製造方法
TW201343016A (zh) 無基板電子元件
TWI656819B (zh) 柔性電路板製作方法
WO2022000173A1 (zh) 线路板及其制作方法
WO2022000191A1 (zh) 内埋式电路板及其制作方法
JP3907845B2 (ja) 半導体装置
JP2011151103A (ja) 電子部品相互の接続構造及び接続方法
JP6939982B2 (ja) 高周波モジュール
CN108550531B (zh) 封装基板的制造方法
CN106332444A (zh) 电路板及其制作方法
KR20030011433A (ko) 다층 인쇄회로기판의 숨겨진 레이저 비아홀 제조방법
CN110290644A (zh) 一种阶梯式金手指线路板的制作方法
TWI851014B (zh) 功率半導體封裝訊號連接元件與半導體模組
CN115397110B (zh) 一种带台阶槽及埋入式线路的基板制作方法
TWI838798B (zh) 晶片封裝單元及其製造方法及由其所堆疊形成的封裝結構
KR101154352B1 (ko) 임베디드 인쇄회로기판용 부재 및 그 제조 방법 및 임베디드 인쇄회로기판용 부재를 이용한 임베디드 인쇄회로기판 제조 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20943594

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20943594

Country of ref document: EP

Kind code of ref document: A1