WO2021258936A1 - 显示面板、显示装置 - Google Patents

显示面板、显示装置 Download PDF

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Publication number
WO2021258936A1
WO2021258936A1 PCT/CN2021/094896 CN2021094896W WO2021258936A1 WO 2021258936 A1 WO2021258936 A1 WO 2021258936A1 CN 2021094896 W CN2021094896 W CN 2021094896W WO 2021258936 A1 WO2021258936 A1 WO 2021258936A1
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WIPO (PCT)
Prior art keywords
terminal
transistor
node
pixel
shift register
Prior art date
Application number
PCT/CN2021/094896
Other languages
English (en)
French (fr)
Inventor
钱昱翰
刘利宾
韩龙
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21828004.8A priority Critical patent/EP4099314A4/en
Priority to US17/771,102 priority patent/US11875722B2/en
Publication of WO2021258936A1 publication Critical patent/WO2021258936A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel and a display device.
  • the corner positions of the four-curved screen display panel include a stretched area, a normal display area, and a transition area between the stretched area and the normal display area.
  • a gate drive circuit is integrated in the transition zone.
  • the gate drive circuit usually includes a cascaded shift register unit and a signal line group for providing drive signals to the shift register unit.
  • the shift register unit and the signal line group are usually arranged in two phases in the same row. Between adjacent pixel units.
  • the pixel driving circuit needs to be set at an offset pixel opening position. Therefore, the pixel drive circuit needs to be connected to the anode at the pixel opening position by extending the anode wiring.
  • the extended anode wiring has a certain resistance, which will cause the pixel drive circuit to be shifted and the pixel drive circuit that does not shift. Different driving voltages are provided to the anode, which eventually results in uneven display of the display panel.
  • a display panel including a display area, a frame area located at the periphery of the display area, a stretch area located at a corner position of the display panel, and a normal display area of the display area. And located in the transition area between the stretching area and the normal display area, the display panel further includes: a base substrate, a plurality of pixel units, a first gate driving circuit, and a second gate driving circuit. A plurality of pixel units are located on one side of the base substrate and are integrated in the transition area, and the plurality of pixel units are arranged in rows and columns in the transition area; the first gate driving circuit is located on the base substrate facing all directions.
  • the first gate drive circuit includes a first shift register unit and a first signal line group, the first signal line group includes The first shift register unit provides the first signal line segment group of the driving signal; wherein, the base substrate includes a plurality of integrated parts, and the integrated parts are located in the same row.
  • the orthographic projection of two adjacent pixel units on the base substrate In between, the orthographic projection of the first shift register unit on the base substrate and the orthographic projection of the first signal line segment group on the base substrate are respectively located in different integration parts in the same row;
  • second The gate driving circuit is located on the side of the base substrate facing the pixel unit and is integrated in the frame area.
  • the second gate driving circuit includes a plurality of cascaded second shift register units; The number of transistors in the first shift register unit is smaller than the number of transistors in the second shift register unit.
  • the orthographic projection of the first shift register unit on the base substrate and the orthographic projection of the first signal line segment group on the base substrate are respectively located in the same row. Adjacent to the two integrated parts.
  • a plurality of the pixel units form a plurality of pixel islands distributed in rows and columns, and the orthographic projection of the first gate drive circuit on the base substrate is located at the adjacent pixel islands. Between the orthographic projections of the plane where the base substrate is located.
  • each of the pixel islands includes two pixel units distributed along a column direction, and each of the pixel islands includes: B pixel openings located in the first pixel opening row and arranged adjacently And R pixel openings, two G pixel openings located in the second pixel opening row and distributed along the column direction, B pixel openings and R pixel openings located in the third pixel opening row and adjacently arranged; wherein, the second pixel opening row is located Between the first pixel opening row and the third pixel opening row, the pixel openings of the same color are located in the same pixel opening column, and the pixel openings of different colors are located in different pixel opening columns.
  • the first gate driving circuit includes a plurality of cascaded first shift register units, and the first signal line group includes one-to-one with the first gate driving circuit.
  • the first signal line segment groups are respectively used to provide driving signals to the corresponding first shift register units.
  • the transition region includes a curved edge region extending along a curve, and at least a part of the first shift register unit located in the curved edge region is positioned on the base substrate by an orthographic projection Different columns, correspondingly, the orthographic projection of at least a part of the first signal line segment group located in the bend area on the base substrate is located in a different column.
  • the first signal line segment groups located in different columns are connected by connecting line segment groups extending in the row direction, and the orthographic projection of the connecting line segment groups on the base substrate is located in adjacent locations.
  • the pixel island is between the orthographic projections of the plane where the base substrate is located.
  • the first signal line group includes one or more of a clock signal line and a power signal line.
  • the display panel further includes a second signal line group, and the second signal line group is used to provide a driving signal to a plurality of the second shift register units; wherein, the second signal line group
  • the shift register unit and the first shift register unit are cascaded, and the same signal lines in the first signal line group and the second signal line group are connected.
  • the first shift register unit includes: a first input circuit, a second input circuit, a control circuit, a first output circuit, a second output circuit, and the first input circuit is connected to the first input circuit.
  • the clock signal terminal, the first power terminal, and the first node are used to transmit the signal of the first power terminal to the first node in response to the signal of the first clock signal terminal;
  • the second input circuit is connected to the first clock
  • the signal terminal, the signal input terminal, and the second node are used to transmit the signal of the signal input terminal to the second node in response to the signal of the first clock signal terminal;
  • the control circuit is connected to the first node, the second node,
  • the first clock signal terminal is used to transmit the signal of the first clock signal terminal to the first node in response to the signal of the second node;
  • the first output circuit is connected to the first node, the second power terminal, and output Terminal, used to transmit the signal of the second power terminal to the output terminal in response to the signal of the first node;
  • the first input circuit includes a first transistor, a first terminal of the first transistor is connected to the first power terminal, a second terminal is connected to the first node, and a control terminal is connected to the The first clock signal terminal;
  • the second input circuit includes a second transistor, the first terminal of the second transistor is connected to the signal input terminal, the second terminal is connected to the second node, and the control terminal is connected to the first clock signal terminal
  • the control circuit includes a third transistor, the first terminal of the third transistor is connected to the first node, the second terminal is connected to the first clock signal terminal, and the control terminal is connected to the second node;
  • the first output The circuit includes a fourth transistor and a first capacitor.
  • the first terminal of the fourth transistor is connected to the second power terminal, the second terminal is connected to the output terminal, and the control terminal is connected to the first node; the first capacitor is connected to the Between the second power terminal and the first node; the second output circuit includes a fifth transistor and a second capacitor, the first terminal of the fifth transistor is connected to the second clock signal terminal, and the second terminal is connected to the output terminal , The control terminal is connected to the second node; the second capacitor is connected between the second node and the output terminal.
  • the second shift register unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a fifth transistor, a sixth transistor, and a seventh transistor ,
  • the eighth transistor, the second capacitor, the first end of the first transistor is connected to the signal input end, the second end is connected to the first node, the control end is connected to the first clock signal end; the first end of the second transistor is connected to the first Clock signal terminal, the second terminal is connected to the second node, the control terminal is connected to the first node; the first terminal of the third transistor is connected to the first power terminal, the second terminal is connected to the second node, and the control terminal is connected to the first node.
  • a clock signal terminal; the first terminal of the fourth transistor is connected to the second power terminal, the second terminal is connected to the output terminal, and the control terminal is connected to the second node; the first capacitor is connected to the second node and the second power source Between the terminals; the first terminal of the fifth transistor is connected to the second power terminal, the second terminal is connected to the third node, and the control terminal is connected to the second node; the first terminal of the sixth transistor is connected to the third node, The second terminal is connected to the first node, the control terminal is connected to the second clock signal terminal; the first terminal of the seventh transistor is connected to the first node, the second terminal is connected to the fourth node, and the control terminal is connected to the first power terminal The first terminal of the eighth transistor is connected to the output terminal, the second terminal is connected to the second clock signal terminal, and the control terminal is connected to the fourth node; the second capacitor is connected between the fourth node and the output terminal .
  • the first signal line segment group is connected to the first shift register unit through a first connecting line group extending in a row direction;
  • the first signal line segment group includes: A clock signal line segment, a second clock signal line segment, a first power line segment, and a second power line segment;
  • the first connection line group includes: a first clock connection line, a second clock connection line, a first power connection line, and a second power supply Connection line; wherein the first clock signal line is connected to the gates of the first transistor and the second transistor through the first clock connection line, and the second clock signal line segment is connected through the second clock connection line Is connected to a source/drain of the fifth transistor, the first power line segment is connected to a source/drain of the third transistor through the first power connection line, and the second power line segment passes through all
  • the second power connection line is connected to an electrode of the first capacitor.
  • the display panel includes an active layer, a first conductive layer, a second conductive layer, and a third conductive layer which are sequentially stacked on one side of the base substrate;
  • the source layer is used to form the channel region of the transistor in the first shift register unit, and part of the first conductive layer is used to form the gate of the transistor in the first shift register unit and the first capacitor,
  • the first electrode of the second capacitor, part of the second conductive layer is used to form the second electrode of the first capacitor and the second capacitor, and part of the third conductive layer is used to form the first shift register unit Source/drain of the middle transistor;
  • the first power signal line segment is located on one side of the first shift register unit, the first clock signal line segment, the second clock signal line segment, and the second power supply line segment are located on the first
  • a power signal line segment is away from the side of the first shift register unit;
  • the first power connection line is formed by part of the third conductive layer, and the first clock connection line and the second clock connection line are partly formed by the third
  • the first conductive layer is formed; the second power connection line includes a first connection portion and a second connection portion, the first connection portion is connected to the second power line segment through a via hole, and the second connection portion is connected to the The second electrode of the first capacitor is connected, and the first connection portion and the second connection portion are connected through a via located between the second power line segment and the first capacitor, wherein the first connection portion is partially
  • the first conductive layer is formed, and the second conductive portion is formed by part of the third conductive layer.
  • the display panel includes a pixel unit located between a first shift register unit and the first signal line segment group;
  • the orthographic projection of the first clock connection line on the base substrate and the orthographic projection of the second clock connection line on the base substrate are respectively located on opposite sides of the pixel unit.
  • the first transistor, the second transistor, and the third transistor are located on a side of the fourth transistor and the fifth transistor away from a pixel unit, and the output terminal passes through the gate line and the The pixel unit is connected to the adjacent pixel driving circuit.
  • the second capacitor is located on a side of the fourth transistor and the fifth transistor away from the first transistor, the second transistor, and the third transistor.
  • the pixel unit includes a switching transistor, and the second end of the fifth transistor is connected to the gate of the switching transistor in the adjacent pixel unit through a gate line; wherein, the switching transistor The gate and the gate line are formed by part of the first conductive layer.
  • the display panel further includes a stretched area located at the corners of the display panel, and a normal display area located in the display area, and the transition area is located in the stretched area and the normal display area. Between the normal display area.
  • the pixel density in the transition area is less than the pixel density in the normal display area.
  • the stretching zone includes a first stretching zone located in the display zone, and the pixel density in the first stretching zone is less than the pixel density in the normal display zone.
  • the display panel includes an array substrate and an encapsulation layer encapsulated on one side of the array substrate, and the stretching area is provided with a hollow opening penetrating the array substrate and the encapsulation layer .
  • a display device including the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of the structure of a four-curved screen display panel in the related art
  • Figure 2 is a structural diagram of the transition area of the four-curved screen display panel in the related art
  • FIG. 3 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a transition area in an exemplary embodiment of a display panel of the present disclosure
  • Figure 5 is a cross-sectional view of the broken line A-A in Figure 4.
  • FIG. 6 is a partial enlarged view of the dashed box 10 in FIG. 3;
  • FIG. 7 is a schematic structural diagram of a transition area in an exemplary embodiment of a display panel of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a first shift register unit in an exemplary embodiment of a display panel of the present disclosure
  • FIG. 9 is a schematic structural diagram of a second shift register unit in an exemplary embodiment of the display panel of the present disclosure.
  • FIG. 10a is a timing diagram of each node in a driving method of the first shift register unit shown in FIG. 8; FIG.
  • 10b is a timing diagram of each node in a driving method of the second shift register unit shown in FIG. 9;
  • Fig. 11 is a partial enlarged view of the first shift register unit in Figs. 4 and 6;
  • FIG. 12 is a schematic diagram of the structure of the active layer in FIG. 11;
  • FIG. 13 is a schematic diagram of the structure of the first conductive layer in FIG. 11;
  • FIG. 14 is a schematic diagram of the structure of the second conductive layer in FIG. 11;
  • FIG. 15 is a schematic diagram of the structure of the third conductive layer in FIG. 11;
  • FIG. 16 is a design layout of the second gate driving circuit in the display panel of the present disclosure.
  • FIG. 17 is a schematic diagram of the structure of the active layer in FIG. 16;
  • FIG. 18 is a schematic diagram of the structure of the first conductive layer in FIG. 16;
  • FIG. 19 is a schematic diagram of the structure of the second conductive layer in FIG. 16;
  • FIG. 20 is a schematic diagram of the structure of the third conductive layer in FIG. 16.
  • FIG. 1 it is a schematic diagram of the structure of a four-curved screen display panel in the related art.
  • the four-curved screen display panel includes a display area 1 and a frame area 2 located at the periphery of the display area 1.
  • the display panel also includes a stretching area 4 located at a corner of the display panel.
  • the stretching area 4 includes a second area located in the display area 1.
  • a stretching area 41 is located in the second stretching area 42 of the frame area 2.
  • the display panel further includes a normal display area 11 located in the display area 1, and a transition area 3 between the normal display area 11 and the first stretching area 41. .
  • the pixel density on the transition area 3 is less than the pixel density of the normal display area 11.
  • the transition area 3 may be integrated with a gate drive circuit, and the gate drive circuit may be used to provide a gate drive signal to the pixel drive circuit or Enable signal.
  • the transition area 3 may be integrated with a plurality of pixel units distributed in rows and columns and a gate driving circuit.
  • the gate driving circuit may include a shift register unit 61 and a signal line group 62, where the shift register unit 61 may include multiple transistors and multiple capacitor structures.
  • the shift register unit 61 and the signal line group 62 may be arranged between two adjacent pixel units in the same row. As shown in FIG.
  • the pixel driving circuit 5 on the side of the shift register unit 61 and the signal line group 62 needs to be offset from the pixel opening 71.
  • the pixel driving circuit 5 needs to be connected to the anode at the position of the pixel opening 71 by extending the anode wiring.
  • the pixel driving circuit in other pixel units does not need to be arranged offset from the pixel opening, and the pixel driving circuit is located directly below the pixel opening.
  • the drive signal output from the shifted pixel drive circuit to the anode has a certain voltage drop, which will cause the shifted pixel drive circuit and the unshifted pixel drive circuit.
  • Different driving voltages are output to the anode, which eventually leads to uneven display of the display panel.
  • FIG. 3 is a schematic structural diagram of an exemplary embodiment of the display panel of the present disclosure
  • FIG. 4 is a display panel of the present disclosure.
  • FIG. 5 is a cross-sectional view of the dashed line AA in FIG. 4.
  • the display panel includes a transition area 3 located in the display area 1.
  • the display panel also includes a base substrate 8, a plurality of pixel units 7, and a first gate driving circuit.
  • a plurality of pixel units 7 are located on one side of the base substrate and integrated in the transition area 3, and the plurality of pixel units 7 are distributed in rows and columns of the transition area, wherein the dotted line AA may extend along the row direction X;
  • the first gate driving circuit is located on the side of the base substrate facing the pixel unit 7 and is integrated in the transition area 3.
  • the first gate driving circuit may include a first shift register unit 61 and a first shift register unit 61.
  • a signal line group, the first signal line group may include a first signal line segment group 62 for providing driving signals to the first shift register unit; wherein, the base substrate 8 may include a plurality of integrated parts 81.
  • the integrated part 81 may be located between the orthographic projection of two adjacent pixel units 7 on the base substrate in the same row, and the orthographic projection of the first shift register unit 61 on the base substrate and the The orthographic projections of the first signal line segment group 62 on the base substrate are respectively located in different integration parts in the same row.
  • the display panel provided by the present disclosure is arranged in the same row by the orthographic projection of the first shift register unit 61 on the base substrate and the orthographic projection of the first signal line segment group 62 on the base substrate.
  • the integration part 81 is different, thereby avoiding display unevenness due to the shift of the pixel driving circuit in the transition area.
  • the display panel may further include a stretched area 4 located at a corner position of the display panel, and a normal display area 11 located in the display area, and the transition area 3 It may be located between the stretching area 4 and the normal display area 11.
  • the pixel density in the transition area 3 may be less than the pixel density in the normal display area, so as to reserve a space for arranging the first gate driving circuit.
  • the display panel may include an array substrate and an encapsulation layer encapsulated on one side of the array substrate, and the stretching area 4 is provided with a hollow opening penetrating the array substrate and the encapsulation layer.
  • the hollow opening can enhance the bending ability of the stretching zone 4, so that the four sides of the display panel can be bent in the direction of the back plate.
  • the stretched area 4 may include a first stretched area 41 and a second stretched area 42 located in the display area 1, and the pixel density in the first stretched area 41 may be less than the pixel density in the normal display area , To reserve space for setting the hollow opening.
  • the second stretching area 42 may be located in the frame area of the display panel.
  • the orthographic projection of the first shift register unit 61 on the base substrate 8 and the first signal line segment group 62 on the front of the base substrate 8 may be respectively located in two adjacent integration parts 81 in the same row. This arrangement can reduce the length of the signal connection line between the first signal line segment group 62 and the first shift register unit 61. It should be understood that, in other exemplary embodiments, the orthographic projection of the first shift register unit 61 on the base substrate 8 and the first signal line segment group 62 on the front of the base substrate 8 The projections may also be located in the same row and not adjacent to two integrated parts 81.
  • the transition area 3 may include a first extension area 31, a second extension area 32, and a third extension area 33 connected between the first extension area 31 and the second extension area 32.
  • the first extension area 31 may extend in a straight line along the column direction Y
  • the third extension area 33 may extend along a curve
  • the second extension area 32 may extend in a straight line along the column direction Y.
  • part of the first shift register unit located in the third extension area 33 may be located in different pixel columns in the orthographic projection of the base substrate.
  • the cascade direction of the first shift register unit in the first gate driving circuit is the same as the extension direction of the third extension region 33. It should be understood that in the first extension area 31 and the second extension area 32, the first shift register units may be linearly cascaded along the column direction, that is, in the first extension area 31 and the second extension area 32, the first shift register unit The shift register units are located in the same pixel column.
  • the first gate driving circuit may include a plurality of cascaded first shift register units 61. As shown in FIG. 7, this exemplary embodiment only illustrates four cascaded first shifts.
  • the register unit 61 wherein the two first shift register units 61 connected in cascade can be cascaded through the connecting line 9.
  • the first signal line group may include a plurality of first signal line segment groups 62 arranged in a one-to-one correspondence with the first gate driving circuit, and the first signal line segment group 62 is used to transfer the corresponding first shift register Unit 61 provides drive signals.
  • the signal lines of the same type in the plurality of first signal line segment groups 62 are connected.
  • the first signal line segment group 62 may include a first clock signal line segment CK, a second clock signal line segment CB, a first power supply line segment VGL, and a second power supply line segment VGH.
  • Each group of the first signal line segment group 62 The first clock signal line segment CK in each group is connected to each other; the second clock signal line segment CB in each group of first signal line segment group 62 is connected to each other; the first power line segment VGL in each group of first signal line segment group 62 is connected to each other;
  • the second power supply line segments VGH in the first signal line segment group 62 are connected to each other.
  • the orthographic projections of the first shift register unit in the second pixel row and the first shift register unit in the third pixel row on the base substrate are located in different pixel columns, so that the first shift register unit can be bent along Direction cascade.
  • the first signal line group may also include other numbers and types of signal lines.
  • the first signal line group may include clock signal lines and power signal lines. One or more of.
  • a plurality of the pixel units 7 may form a plurality of pixel islands 07 distributed in rows and columns, and the orthographic projection of the first gate driving circuit on the base substrate may be located The adjacent pixel islands are between the orthographic projections of the plane where the base substrate is located. Orthographic projections of at least part of the first signal line segment group located in the curved edge area on the base substrate are located in different columns. For example, as shown in FIG. 7, the first signal line segment group in the third pixel row and the first signal line segment group located in the second pixel row are located in different columns. As shown in FIG.
  • the line segment group may be connected by a connecting line segment group 08 extending in the row direction, and the orthographic projection of the connecting line segment group 08 on the base substrate may be located between the orthographic projections of the adjacent pixel islands on the plane where the base substrate is located. between.
  • each of the pixel islands 07 may include two pixel units 7 distributed along the column direction, and each of the pixel islands includes: B pixel openings 71 located in the first pixel opening row and arranged adjacently. And R pixel openings 72, two G pixel openings 73 located in the second pixel opening row and distributed along the column direction, B pixel openings 71 and R pixel openings 72 located in the third pixel opening row and adjacently arranged; wherein, the second The pixel opening row is located between the first pixel opening row and the third pixel opening row, and the pixel openings of the same color are located in the same pixel opening column, and the pixel openings of different colors are located in different pixel opening columns.
  • the display panel may further include a frame area 2 located at the periphery of the display area, and the display panel may further include a second gate driving circuit 12 located on the substrate.
  • the substrate faces one side of the pixel unit and is integrated in the frame area 2.
  • the second gate driving circuit 12 may include a plurality of cascaded second shift register units, and a The second shift register unit provides the second signal line group of the driving signal.
  • the first gate driving circuit can be used to provide driving signals to all pixel units that are in the same line with the pixel units in the transition area.
  • the second gate driving circuit can be used to provide driving signals to the remaining pixel units.
  • the second shift register unit may be cascaded with the first shift register unit, and the first signal line group may be connected to the same kind of signal lines in the second signal line group. That is, the first shift register unit and the second shift register unit can be connected to the same signal line group, which can provide the same clock signal and power signal to the first shift register unit and the second shift register unit at the same time , The first shift register unit and the second shift register unit can be driven step by step under the same clock signal and power signal.
  • the number of transistors in the first shift register unit may be less than the number of transistors in the second shift register unit. This arrangement can make the orthographic projection of the first shift register unit located in the transition area on the base substrate have a smaller area, so as to facilitate the layout of the display panel. It should be understood that in other exemplary embodiments, the number of transistors in the first shift register unit may also be equal to or greater than the number of transistors in the second shift register unit.
  • the following exemplary embodiment provides a specific structure of the first shift register unit and the second shift register unit.
  • FIG. 8 it is a schematic structural diagram of the first shift register unit in an exemplary embodiment of the display panel of the present disclosure.
  • the first shift register unit includes: a first input circuit 1, a second input circuit 2, a control circuit 3, a first output circuit 4, and a second output circuit 5.
  • the first input circuit 1 is connected to a first clock signal terminal CK 1.
  • the first power terminal VGL and the first node N1 are used to transmit the signal of the first power terminal VGL to the first node N1 in response to the signal of the first clock signal terminal CK;
  • the second input circuit 2 is connected The first clock signal terminal CK, the signal input terminal Input, and the second node N2 are used to transmit the signal of the signal input terminal Input to the second node N2 in response to the signal of the first clock signal terminal CK;
  • the control circuit 3 is connected to the first node N1, the second node N2, and the first clock signal terminal CK, and is used to transmit the signal of the first clock signal terminal CK to the first node N2 in response to the signal of the second node N2.
  • a node N1; the first output circuit 4 is connected to the first node N1, the second power supply terminal VGH, and the output terminal OUT, and is used to transmit the signal of the second power supply terminal VGH to the signal of the first node N1
  • the output terminal OUT; the second output circuit 5 is connected to the second node N2, the second clock signal terminal CB, and the output terminal OUT, for responding to the signal of the second node N2 to turn the second clock signal terminal CB The signal is transmitted to the output terminal OUT.
  • the first input circuit 1 may include a first transistor T1, a first terminal of the first transistor T1 is connected to the first power supply terminal VGL, and a second terminal is connected to the first node N1 to control Terminal is connected to the first clock signal terminal CK;
  • the second input circuit 2 may include a second transistor T2, the first terminal of the second transistor T2 is connected to the signal input terminal Input, and the second terminal is connected to the second node N2,
  • the control terminal is connected to the first clock signal terminal CK;
  • the control circuit includes a third transistor T3, the first terminal of the third transistor T3 is connected to the first node N1, and the second terminal is connected to the first clock signal terminal CK ,
  • the control terminal is connected to the second node N2;
  • the first output circuit 4 may include a fourth transistor T4 and a first capacitor C1, the first terminal of the fourth transistor T4 is connected to the second power terminal VGH, and the second terminal
  • the output terminal OUT is connected, the control terminal is connected to the first node N1;
  • the first terminal of the fifth transistor T5 is connected to the second clock signal terminal CB, the second terminal is connected to the output terminal OUT, and the control terminal is connected to the second node N2; the second capacitor C2 can Connected between the second node N2 and the output terminal OUT.
  • the first to fifth transistors may be P-type transistors.
  • the second shift register unit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, The eighth transistor T8 and the second capacitor C2.
  • the first terminal of the first transistor T1 is connected to the signal input terminal Input, the second terminal is connected to the first node N1, and the control terminal is connected to the first clock signal terminal CK; Terminal is connected to the first clock signal terminal CK, the second terminal is connected to the second node N2, the control terminal is connected to the first node N1; the first terminal of the third transistor T3 is connected to the first power terminal VGL, and the second terminal is connected to the For the second node N2, the control terminal is connected to the first clock signal terminal CK; the first terminal of the fourth transistor T4 is connected to the second power terminal VGH, the second terminal is connected to the output terminal OUT, and the control terminal is connected to the second node N2
  • the first capacitor C1 is connected between the second node N2 and the second power terminal VGH; the first terminal of the fifth transistor T5 is connected to the second power terminal VGH, and the second terminal is connected to the third node N3, The control terminal is connected to the second node N2; the first terminal of the sixth transistor T6 is
  • the terminal is connected to the second clock signal terminal CB, the control terminal is connected to the fourth node N4; the second capacitor C2 is connected between the fourth node N4 and the output terminal OUT.
  • the first to eighth transistors may be P-type transistors.
  • FIG. 10a it is a timing diagram of each node in a driving method of the first shift register unit shown in FIG. 8.
  • the first to fifth transistors may be P-type transistors.
  • the first power supply terminal VGL continuously outputs a low level
  • the second power supply terminal VGH continuously outputs a high level.
  • the driving method of the first shift register unit shown in FIG. 8 includes two stages: the first stage and the second stage.
  • the first clock signal terminal CK outputs a low-level signal
  • the second clock signal terminal CB outputs a high-level signal
  • the signal input terminal Input outputs a low-level signal
  • the first to fifth switching transistors are all turned on
  • the output terminal OUT outputs a high-level signal
  • the first clock signal terminal CK outputs a high-level signal
  • the second clock signal terminal CB outputs a low-level signal
  • the signal input terminal Input outputs a high-level signal.
  • the fifth transistor T5 is turned on, the second transistor, the first transistor, and the fourth transistor are all turned off, and the output terminal outputs a low level.
  • FIG. 10b it is a timing diagram of each node in a driving method of the second shift register unit shown in FIG. 9.
  • the first to eighth transistors may be P-type transistors.
  • the first power supply terminal VGL continuously outputs a low level
  • the second power supply terminal VGH continuously outputs a high level.
  • the driving method of the second shift register unit shown in FIG. 9 includes two stages: the first stage and the second stage.
  • the first clock signal terminal CK outputs a low-level signal
  • the second clock signal terminal CB outputs a high-level signal
  • the signal input terminal Input outputs a low-level signal
  • the first transistor, the second transistor, and the fourth The transistor is turned on, and the output terminal outputs a high level.
  • the first clock signal terminal CK outputs a high-level signal
  • the second clock signal terminal CB outputs a low-level signal
  • the signal input terminal Input outputs a high-level signal
  • the first transistor, the third transistor, and the fourth The transistor is turned off
  • the eighth transistor is turned on, and the output terminal outputs a low level.
  • first shift register unit and the second shift register unit in this exemplary embodiment can be driven by themselves under the same driving signal, that is, the first shift register unit and the second shift register unit can be driven by themselves under the same driving signal.
  • the shift register unit can be connected to the same signal line group.
  • first shift register unit and the second shift register unit may also have other structures to choose from, which all fall within the protection scope of the present disclosure.
  • the first shift register unit adopts a 5T2C structure
  • the second shift register unit adopts an 8T2C structure.
  • the number of transistors in the first shift register unit may be smaller than the number of transistors in the second shift register unit. This arrangement can make the orthographic projection of the first shift register unit located in the transition area on the base substrate have a smaller area, thereby facilitating the layout of the display panel.
  • the first shift register unit may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, a second capacitor C2.
  • the connection structure of the transistor and the capacitor in the first shift register unit is the same as the circuit structure in FIG. 8.
  • the first shift register unit may be formed by sequentially stacking an active layer, a first conductive layer, a second conductive layer, and a third conductive layer which are arranged on a base substrate.
  • FIG. 12 is a schematic diagram of the structure of the active layer in FIG. 11.
  • the active layer includes a first active part 121, a second active part 122, a third active part 123, a fourth active part 124, and a fifth active part 125, wherein the first active part 121 is used for The channel region of the first transistor T1 is formed, the second active portion 122 is used to form the channel region of the second transistor T2, the third active portion 123 is used to form the channel region of the third transistor T3, and the fourth active portion 123 is used to form the channel region of the third transistor T3.
  • the portion 124 is used to form the channel region of the fourth transistor T4, and the fifth active portion 125 is used to form the channel region of the fifth transistor T5.
  • FIG. 13 is a schematic diagram of the structure of the first conductive layer in FIG. 11.
  • the first conductive portion includes conductive portion 131, conductive portion 132, conductive portion 133, conductive portion 134, conductive portion 135, conductive portion 136, conductive portion 137, conductive portion 138, conductive portion 139, and conductive portion 140.
  • the conductive portion 131 is used to form the gate of the first transistor T1
  • the conductive portion 132 is used to form the gate of the second transistor T2
  • the conductive portion 133 is used to form the gate of the third transistor T3
  • the conductive portion 134 is used to form the gate of the third transistor T3.
  • the conductive portion 135 is used to form the gate of the fifth transistor T5
  • the conductive portion 136 is used to form the first electrode of the second capacitor
  • the conductive portion 137 is used to form the first electrode of the first capacitor.
  • the conductive portion 138 and the conductive portion 132 are connected to form a first clock signal terminal.
  • the conductive portion 138 may be connected to the first clock signal line segment CK.
  • the conductive portion 139 is used to form a second clock signal terminal.
  • the conductive portion 139 may be connected to the second clock signal line segment CB.
  • the conductive portion 140 is connected to the conductive portion 137 to form a second power source terminal.
  • the conductive portion 140 may be connected to the second power line segment VGH.
  • FIG. 14 it is a schematic diagram of the structure of the second conductive layer in FIG. 11.
  • the second conductive layer includes a conductive portion 141 and a conductive portion 142.
  • the conductive portion 141 is used to form the second electrode of the first capacitor, and the conductive portion 142 is used to form the second electrode of the second capacitor.
  • the third conductive layer may include conductive portions 151, conductive portions 152, conductive portions 153, conductive portions 154, conductive portions 155, conductive portions 156, conductive portions 157, and conductive portions 158.
  • the conductive portion 151 is connected to one side of the second active portion 122 through a via hole, and is used to form a signal input terminal Input, so that the signal input terminal is connected to the first terminal of the second transistor.
  • the conductive portion 152 is respectively connected to the other side of the second active portion 122 and the conductive portion 133 through via holes, so that the second end of the second transistor is connected to the gate of the third transistor.
  • the conductive portion 153 may be connected to one side of the first active portion 121 through a via hole to form a first power terminal, so that the first terminal of the first transistor is connected to the first power terminal, where, in FIG. 4,
  • the conductive part 153 may be connected to the first power line segment VGL.
  • the conductive portion 154 is respectively connected to the other side of the first active portion 121, one side of the third active portion 123, and the conductive portion 137 through via holes, so that the second end of the first transistor and the first end of the third transistor The terminal and an electrode of the first capacitor are connected to each other.
  • the conductive portion 155 is respectively connected to the same side of the three fifth active portions 125 and the conductive portion 139 through via holes, so that the first terminal of the fifth transistor is connected to the second clock signal terminal CB.
  • the conductive portion 158 is connected to the conductive portion 156 to form an output terminal.
  • the conductive portion 156 is respectively connected to the other side of the three fifth active portions 125 through via holes, so that the second end of the fifth transistor is connected to the output end.
  • the conductive portion 157 is respectively connected to the conductive portion 141 on the side of the fourth active portion 124 through via holes, so that the first terminal of the fourth transistor is connected to the second power supply terminal VGH.
  • the display panel may include a pixel unit located between the first shift register unit and the first signal line segment group (for example, the pixel unit located in the middle in FIG. 4 Pixel unit); the orthographic projection of the first clock connection line on the base substrate and the orthographic projection of the second clock connection line on the base substrate are respectively located in the pixel unit (for example, in the middle in FIG. 4 ⁇ pixel unit) on opposite sides.
  • a pixel unit located between the first shift register unit and the first signal line segment group for example, the pixel unit located in the middle in FIG. 4 Pixel unit
  • the orthographic projection of the first clock connection line on the base substrate and the orthographic projection of the second clock connection line on the base substrate are respectively located in the pixel unit (for example, in the middle in FIG. 4 ⁇ pixel unit) on opposite sides.
  • This setting can prevent the first clock connection line 92 and the second clock connection line 93 from being adjacent It is set so as to avoid mutual interference between the signals on the first clock connection line 92 and the second clock connection line 93.
  • the first power connection line 91 may be located on the side of the first clock connection line 92 away from the pixel unit, and the second power connection line may be located on the side of the second clock connection line 93 away from the pixel unit.
  • the arrangement can prevent the first clock connection line from being arranged adjacent to the second clock connection line of the previous pixel row, and at the same time can prevent the second clock connection line from being arranged adjacent to the first clock connection line of the next pixel row.
  • the first transistor T1, the second transistor T2, and the third transistor T3 may be located in the fourth transistor T4 and the fifth transistor T5 away from a pixel unit (for example, , Figure 4, the rightmost pixel unit) side.
  • This setting can make the output end (ie, the output end) of the fourth transistor T4 and the fifth transistor T5 adjacent to the pixel unit (the rightmost pixel unit in FIG. 4), that is, the output end can be adjacent to the rightmost pixel unit in FIG.
  • the side pixel unit is adjacent, and the output terminal can be connected to the adjacent pixel driving circuit in the pixel unit through a shorter gate line.
  • the second capacitor C2 may be located on a side of the fourth transistor and the fifth transistor away from the first transistor, the second transistor, and the third transistor. That is, the second capacitor C2 may be located between the fourth transistor, the fifth transistor and the rightmost pixel unit in FIG. 4.
  • This arrangement can isolate part of the transistors in the first shift register unit from the transistors in the rightmost pixel unit in FIG. 4 through the second capacitor C2, thereby avoiding the patterning of each functional structure layer of the transistors in the display panel is too dense. In turn, the process difficulty in the patterning process of the display panel is reduced.
  • the second signal line group may include a first clock signal line CK and a second gate driving circuit.
  • the second shift register unit includes first to eighth transistors T1-T8 and a first capacitor C1 and a second capacitor C2.
  • the connection structure of the transistor and the capacitor in the second shift register unit may be the same as the circuit structure in FIG. 9.
  • the second gate driving circuit may also be formed by sequentially stacking the above-mentioned active layer, the first conductive layer, the second conductive layer, and the third conductive layer which are arranged on the base substrate.
  • the active layer may include a first active portion 171, a second active portion 172, a third active portion 173, and a fourth active portion 174.
  • the first active portion 171 is used to form the channel region of the first transistor; the second active portion 172 is used to form the channel region of the second transistor; the third active portion 173 is used to form the channel region of the third transistor.
  • the fourth active portion 174 is used to form the channel region of the fourth transistor; the fifth active portion 175 is used to form the channel region of the fifth transistor; the sixth active portion 176 is used to form the channel of the sixth transistor.
  • the seventh active portion 177 is used to form the channel region of the seventh transistor; the eighth active portion 178 is used to form the channel region of the eighth transistor.
  • the first conductive layer includes conductive portion 181, conductive portion 182, conductive portion 183, conductive portion 184, conductive portion 185, conductive portion 186, and conductive portion 187. , The conductive portion 188, the conductive portion 189, and the conductive portion 190.
  • the conductive portion 181 is used to form the gate of the first transistor
  • the conductive portion 182 is used to form the gate of the second transistor
  • the conductive portion 183 is used to form the gate of the third transistor
  • the conductive portion 184 is used to form the gate of the fourth transistor.
  • the conductive portion 185 is used to form the gate of the fifth transistor, the conductive portion 186 is used to form the gate of the sixth transistor, the conductive portion 187 is used to form the gate of the seventh transistor, and the conductive portion 188 is used to form the eighth transistor.
  • the conductive portion 189 is used to form an electrode of the second capacitor, and the conductive portion 190 is used to form an electrode of the first capacitor.
  • FIG. 19 it is a schematic diagram of the structure of the second conductive layer in FIG. 16.
  • the second conductive layer includes a conductive portion 191 and a conductive portion 192.
  • the conductive portion 192 is used to form the other electrode of the second capacitor
  • the conductive portion 191 is used to form the other electrode of the first capacitor.
  • the third conductive layer includes a first clock signal line CK, a second clock signal line CB, a first power line VGL, a second power line VGH, and conductive portions 201 to 208.
  • the first clock signal line CK is electrically connected to the conductive part 181 through a via hole, so that the first clock signal line is connected to the gate of the first transistor;
  • the second power line VGH is connected to the conductive part 191 through a via hole, so that the The two power lines are connected to one electrode of the first capacitor;
  • the second power line VGH is electrically connected to one side of the fifth active part 175 through a via, so that the second power line VGH is connected to the first end of the fifth transistor;
  • the second clock The signal line CB is electrically connected to the conductive part 186 through a via hole, so that the second clock signal line is connected to the gate of the sixth transistor;
  • the first power line VGL is connected to the third active part 173 through a via hole, so that the first power source
  • the wire is connected to the first end of the third transistor;
  • the conductive portion 201 is connected to one side of the first active portion 171 through a via hole to form a signal input terminal;
  • One side, one side of the second active portion 172, and the conductive portion 190 are connected so that the second end of the second transistor, the first end of the third transistor, and one electrode of the first capacitor are connected to each other.
  • the conductive portion 204 is respectively connected to one side of the conductive portion 182 and the seventh active portion 177 through via holes, so that the gate of the second transistor is connected to the first end of the seventh transistor.
  • the conductive portion 205 is respectively connected to the other side of the conductive portion 188 and the seventh active portion 177 through via holes, so that the second electrode of the seventh transistor is connected to the gate of the eighth transistor.
  • the conductive portion 206 is respectively connected to the same side of the three eighth active portions 178 and the conductive portion 186 through via holes, so that the second clock signal line CB is connected to the first stage of the eighth transistor.
  • the conductive portion 207 is connected to the other side of the three eighth active portions 178 through via holes, and is used to form the output terminal OUT.
  • the conductive portion 208 is respectively connected to one side of the fourth active portion 174 and the conductive portion 191 through via holes, so that the first end of the fourth transistor is connected to the second power line.
  • the first signal line segment group 62 may be connected to the first shift register unit 61 through a first connecting line group extending in the row direction; the first signal line segment group may include: The clock signal line segment CK, the second clock signal line segment CB, the first power line segment VGL, and the second power line segment VGH.
  • the first power signal line segment VGL may be located on one side of the first shift register unit, and the first clock signal line segment CK, the second clock signal line segment CB, and the second power line segment The VGH may be located on a side of the first power signal line VGL segment away from the first shift register unit 61.
  • the first clock signal line segment CK, the second clock signal line segment CB, the first power supply line segment VGL, and the second power supply line segment VGH may be formed by a part of the third conductive layer.
  • the first connection line group may include: a first clock connection line 92, a second clock connection line 93, a first power connection line 91, and a second power connection line (including a first connection portion 941 and a second connection portion 942)
  • the first clock signal line segment CK may be connected to the gates of the first transistor and the second transistor through the first clock connection line 92, specifically, the first clock connection line 92 may be part of the first A conductive layer is formed, the first end of the first clock connection line 92 can be connected to the first clock signal line segment CK in FIG.
  • the second clock signal line segment CB may be connected to a source/drain of the fifth transistor through the second clock connection line 93.
  • the second clock connection line 93 may be formed by a part of the first conductive layer, The first end of the second clock connection line 93 may be connected to the second clock signal line segment CB in FIG. 4 through a via hole, and the second end of the second clock connection line 93 may be connected to the conductive portion 139 in FIG. 13.
  • the first power line segment VGL may be connected to a source/drain of the third transistor through the first power connection line 91.
  • the first power connection line 91 may be formed of a part of the third conductive layer.
  • the first end of a power connection line 91 can be connected to the first power line segment VGL, and the second end of the first power connection line 91 can be connected to the conductive portion 153 in FIG. 15.
  • the second power line segment VGH may be connected to the two electrodes of the first capacitor through the second power connection line.
  • the second power connection line may include a first connection part 941 and a second connection part 942.
  • the first connection part 941 may be connected to the second power line segment VGH through a via hole
  • the second connection part 942 may be connected to the second power line segment VGH through a via hole.
  • the two electrodes of the first capacitor are connected, where the first connection portion 941 and the second connection portion 942 can be connected through a via located between the second power line segment VGH and the first capacitor.
  • the pixel unit in the display panel includes a plurality of sub-pixel units, and each sub-pixel unit includes a pixel driving circuit.
  • the pixel driving circuit includes a switching transistor, and the gate of the switching transistor is used to receive the second pixel.
  • the gates of the switching transistors located in the same pixel row are connected to each other. Therefore, in this exemplary embodiment, when driving signals are provided to the same row of pixel units through the first shift register unit, only one adjacent pixel driving circuit needs to provide driving signals to the entire row of pixel driving circuits.
  • Drive signal As shown in FIGS. 4 and 11, the second terminal of the fifth transistor is connected to the output terminal OUT, and the output terminal OUT can be connected to the pixel unit on the right side thereof through a gate line.
  • a display device including the above-mentioned display panel.
  • the display device can be a mobile phone, a TV, a tablet computer, etc.

Abstract

一种显示面板、显示装置，显示面板包括过渡区（3），显示面板还包括：衬底基板（8）；多个像素单元（7），位于衬底基板（8）的一侧，且集成于过渡区（3）；第一栅极驱动电路，位于衬底基板（8）面向像素单元（7）的一侧，且集成于过渡区（3），第一栅极驱动电路包括第一移位寄存器单元（61）和第一信号线组，第一信号线组包括用于向第一移位寄存器单元（61）提供驱动信号的第一信号线段组（62）；其中，衬底基板（8）包括多个集成部（81），集成部（81）位于同一行两相邻像素单元（7）在衬底基板（8）的正投影之间，第一移位寄存器单元（61）在衬底基板（8）的正投影和第一信号线段组（62）在衬底基板（8）的正投影分别位于同一行的不同集成部（81），该显示面板能够避免过渡区（3）中像素驱动电路（5）偏移。

Description

显示面板、显示装置
交叉引用
本公开要求于2020年6月24日提交的申请号为202010590516.1、名称为“显示面板、显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板、显示装置。
背景技术
在相关技术中，四曲面屏显示面板的边角位置包括有拉伸区、正常显示区以及位于拉伸区和正常显示区之间设置有过渡区。过渡区中集成有栅极驱动电路。栅极驱动电路通常包括有级联的移位寄存器单元和用于向移位寄存器单元提供驱动信号的信号线组，相关技术中，移位寄存器单元和信号线组通常设置于同一行的两相邻像素单元之间。然而，由于移位寄存器单元和信号线组的面积较大，从而使得像素驱动电路需要偏移像素开口位置设置。因此，像素驱动电路需要通过延长阳极走线的方式与像素开口位置的阳极连接，延长的阳极走线具有一定的电阻，从而会导致发生偏移的像素驱动电路与未发生偏移的像素驱动电路向阳极提供不同的驱动电压，最终导致显示面板显示不均匀。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种显示面板，所述显示面板包括显示区、位于显示区周边的边框区、位于所述显示面板边角位置的拉伸区，位于显示区的正常显示区，以及位于所述拉伸区和所述正常显示区之间过渡区，所述显示面板还包括：衬底基板、多个像素单元、第一栅极驱动电路以及第二栅极驱动电路。多个像素单元位于所述衬底基板的一侧，且集成于所述过渡区，多个所述像素单元在所述过渡区行列分布；第一栅极驱动电路位于所述衬底基板面向所述像素单元的一侧，且集成于所述过渡区，所述第一栅极驱动电路包括第一移位寄存器单元和第一信号线组，所述第一信号线组包括用于向所述第一移位寄存器单元提供驱动信号的第一信号线段组；其中，所述衬底基板包括多个集成部，所述集成部位于同一行两相邻像素单元在所述衬底基板的正投影之间，所述第一移位寄存器单元在所述衬底基板的正投影和所述第一信号线段组在所述衬底基板的正投影分别位于同一行的不同所述集成部；第二栅极驱动电路位于所述衬底基板面向所 述像素单元的一侧，且集成于所述边框区，所述第二栅极驱动电路包括多个级联的第二移位寄存单元；所述第一移位寄存器单元中的晶体管个数小于所述第二移位寄存器单元中晶体管的个数。
本公开一种示例性实施例中，所述第一移位寄存器单元在所述衬底基板的正投影和所述第一信号线段组在所述衬底基板的正投影分别位于同一行的相邻两所述集成部。
本公开一种示例性实施例中，多个所述像素单元形成多个行列分布的像素岛，所述第一栅极驱动电路在所述衬底基板的正投影位于相邻所述像素岛在所述衬底基板所在平面的正投影之间。
本公开一种示例性实施例中，每个所述像素岛包括沿列方向分布的两个像素单元，且每个所述像素岛包括：位于第一像素开口行且相邻设置的B像素开口和R像素开口、位于第二像素开口行且沿列方向分布的两个G像素开口、位于第三像素开口行且相邻设置的B像素开口和R像素开口；其中，第二像素开口行位于所述第一像素开口行和第三像素开口行之间，且相同颜色像素开口位于同一像素开口列，不同颜色像素开口位于不同像素开口列。
本公开一种示例性实施例中，所述第一栅极驱动电路包括多个级联的第一移位寄存器单元，所述第一信号线组包括与所述第一栅极驱动电路一一对应设置的第一信号线段组，第一信号线段组分别用于向与其对应的所述第一移位寄存器单元提供驱动信号。
本公开一种示例性实施例中，所述过渡区包括沿曲线延伸的弯沿区，位于所述弯沿区的至少部分所述第一移位寄存器单元在所述衬底基板的正投影位于不同列，相应的，位于所述弯沿区的至少部分所述第一信号线段组在所述衬底基板的正投影位于不同列。
本公开一种示例性实施例中，位于不同列的所述第一信号线段组通过沿行方向延伸的连接线段组连接，所述连接线段组在所述衬底基板的正投影位于相邻所述像素岛在所述衬底基板所在平面的正投影之间。
本公开一种示例性实施例中，所述第一信号线组包括：时钟信号线、电源信号线中的一种或多种。
本公开一种示例性实施例中，所述显示面板还包括第二信号线组，第二信号线组用于向多个所述第二移位寄存器单元提供驱动信号；其中，所述第二移位寄存器单元和所述第一移位寄存器单元级联，所述第一信号线组和所述第二信号线组中的同种信号线相连接。
本公开一种示例性实施例中，所述第一移位寄存器单元包括：第一输入电路、第二输入电路、控制电路、第一输出电路、第二输出电路，第一输入电路连接第一时钟信号端、第一电源端、第一节点，用于响应所述第一时钟信号端的信号将所述第一电源端的 信号传输到所述第一节点；第二输入电路连接所述第一时钟信号端、信号输入端、第二节点，用于响应所述第一时钟信号端的信号将所述信号输入端的信号传输到所述第二节点；控制电路连接所述第一节点、第二节点、第一时钟信号端，用于响应所述第二节点的信号将所述第一时钟信号端的信号传输到所述第一节点；第一输出电路连接所述第一节点、第二电源端、输出端，用于响应所述第一节点的信号将所述第二电源端的信号传输到所述输出端；第二输出电路连接所述第二节点、第二时钟信号端、输出端，用于响应所述第二节点的信号将所述第二时钟信号端的信号传输到所述输出端。
本公开一种示例性实施例中，所述第一输入电路包括第一晶体管，第一晶体管的第一端连接所述第一电源端，第二端连接所述第一节点，控制端连接所述第一时钟信号端；第二输入电路包括第二晶体管，第二晶体管的第一端连接所述信号输入端，第二端连接所述第二节点，控制端连接所述第一时钟信号端；所述控制电路包括第三晶体管，第三晶体管的第一端连接所述第一节点，第二端连接所述第一时钟信号端，控制端连接所述第二节点；所述第一输出电路包括第四晶体管和第一电容，第四晶体管的第一端连接所述第二电源端，第二端连接所述输出端，控制端连接所述第一节点；第一电容连接于所述第二电源端和所述第一节点之间；第二输出电路包括第五晶体管和第二电容，第五晶体管的第一端连接所述第二时钟信号端，第二端连接所述输出端，控制端连接所述第二节点；第二电容连接于所述第二节点和所述输出端之间。
本公开一种示例性实施例中，所述第二移位寄存器单元包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第一电容、第五晶体管、第六晶体管、第七晶体管、第八晶体管、第二电容，第一晶体管的第一端连接信号输入端，第二端连接第一节点，控制端连接第一时钟信号端；第二晶体管的第一端连接所述第一时钟信号端，第二端连接第二节点，控制端连接所述第一节点；第三晶体管的第一端连接第一电源端，第二端连接所述第二节点，控制端连接所述第一时钟信号端；第四晶体管的第一端连接第二电源端，第二端连接输出端，控制端连接所述第二节点；第一电容连接于所述第二节点和所述第二电源端之间；第五晶体管的第一端连接所述第二电源端，第二端连接第三节点，控制端连接所述第二节点；第六晶体管的第一端连接所述第三节点，第二端连接所述第一节点，控制端连接第二时钟信号端；第七晶体管的第一端连接所述第一节点，第二端连接第四节点，控制端连接所述第一电源端；第八晶体管的第一端连接所述输出端，第二端连接第二时钟信号端，控制端连接所述第四节点；第二电容连接于所述第四节点和所述输出端之间。
本公开一种示例性实施例中，所述第一信号线段组通过沿行方向延伸的第一连接线组与所述第一移位寄存器单元连接；所述第一信号线段组包括：第一时钟信号线段、第 二时钟信号线段、第一电源线段、第二电源线段；所述第一连接线组包括：第一时钟连接线、第二时钟连接线、第一电源连接线、第二电源连接线；其中，所述第一时钟信号线通过所述第一时钟连接线与所述第一晶体管、第二晶体管的栅极连接，所述第二时钟信号线段通过所述第二时钟连接线与所述第五晶体管的一源/漏极连接，所述第一电源线段通过所述第一电源连接线与所述第三晶体管的一源/漏极连接，所述第二电源线段通过所述第二电源连接线与所述第一电容的一电极连接。
本公开一种示例性实施例中，所述显示面板包括依次层叠设置于所述衬底基板一侧的有源层、第一导电层、第二导电层、第三导电层；部分所述有源层用于形成所述第一移位寄存器单元中晶体管的沟道区，部分所述第一导电层用于形成所述第一移位寄存器单元中晶体管的栅极以及所述第一电容、第二电容的第一电极，部分所述第二导电层用于形成所述第一电容、第二电容的第二电极，部分所述第三导电层用于形成所述第一移位寄存器单元中晶体管的源/漏极；所述第一电源信号线段位于所述第一移位寄存器单元的一侧，所述第一时钟信号线段、第二时钟信号线段、第二电源线段位于所述第一电源信号线段远离所述第一移位寄存器单元的一侧；所述第一电源连接线由部分所述第三导电层形成，所述第一时钟连接线、第二时钟连接线由部分所述第一导电层形成；所述第二电源连接线包括第一连接部、第二连接部，所述第一连接部通过过孔与第二电源线段连接，第二连接部通过过孔与所述第一电容的第二电极连接，且第一连接部和第二连接部通过位于所述第二电源线段和第一电容之间的过孔连接，其中，所述第一连接部由部分所述第一导电层形成，所述第二导电部由部分所述第三导电层形成。
本公开一种示例性实施例中，所述显示面板包括位于第一移位寄存器单元和所述第一信号线段组之间的像素单元；
所述第一时钟连接线在所述衬底基板的正投影和所述第二时钟连接线在所述衬底基板的正投影分别位于该像素单元的相对两侧。
本公开一种示例性实施例中，所述第一晶体管、第二晶体管、第三晶体管位于所述第四晶体管、第五晶体管远离一像素单元的一侧，所述输出端通过栅线和该像素单元中与其邻近的像素驱动电路连接。
本公开一种示例性实施例中，所述第二电容位于所述第四晶体管、第五晶体管远离所述第一晶体管、第二晶体管、第三晶体管的一侧。
本公开一种示例性实施例中，所述像素单元包括开关晶体管，所述第五晶体管的第二端通过栅线和与其邻近的像素单元中开关晶体管的栅极连接；其中，所述开关晶体管的栅极、所述栅线由部分所述第一导电层形成。
本公开一种示例性实施例中，所述显示面板还包括位于所述显示面板的边角位置的 拉伸区，以及位于显示区的正常显示区，所述过渡区位于所述拉伸区和所述正常显示区之间。
本公开一种示例性实施例中，所述过渡区中的像素密度小于所述正常显示区中的像素密度。
本公开一种示例性实施例中，所述拉伸区包括位于显示区的第一拉伸区，所述第一拉伸区中的像素密度小于所述正常显示区中的像素密度。
本公开一种示例性实施例中，所述显示面板包括阵列基板和封装于所述阵列基板一侧的封装层，所述拉伸区设置有贯穿所述阵列基板和所述封装层的镂空开口。
根据本公开的一个方面，提供一种显示装置，该显示装置包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中一种四曲面屏显示面板的结构示意图；
图2为相关技术中四曲面屏显示面板过渡区的结构图；
图3为本公开显示面板一种示例性实施例的结构示意图；
图4为本公开显示面板一种示例性实施例中过渡区的结构示意图；
图5为图4中虚线A-A的剖视图；
图6为图3中虚线框10的局部放大图；
图7为本公开显示面板一种示例性实施例中过渡区的结构示意图；
图8为本公开显示面板一种示例性实施例中第一移位寄存器单元的结构示意图；
图9为本公开显示面板一种示例性实施例中第二移位寄存器单元的结构示意图；
图10a为图8所示的第一移位寄存器单元在一种驱动方法中各节点的时序图；
图10b为图9所示的第二移位寄存器单元在一种驱动方法中各节点的时序图；
图11为图4、6中第一移位寄存器单元的局部放大图；
图12为图11中有源层的结构示意图；
图13为图11中第一导电层的结构示意图；
图14为图11中第二导电层的结构示意图；
图15为图11中第三导电层的结构示意图；
图16为本公开显示面板中第二栅极驱动电路的设计版图；
图17为图16中有源层的结构示意图；
图18为图16中第一导电层的结构示意图；
图19为图16中第二导电层的结构示意图；
图20为图16中第三导电层的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为相关技术中一种四曲面屏显示面板的结构示意图。该四曲面屏显示面板包括显示区1和位于显示区1周边的边框区2，该显示面板还包括位于显示面板边角位置的拉伸区4，该拉伸区4包括位于显示区1的第一拉伸区41位于边框区2的第二拉伸区42，该显示面板还包括位于显示区1的正常显示区11以及位于正常显示区11、第一拉伸区41之间的过渡区3。相关技术中，过渡区3上的像素密度小于正常显示区11的像素密度，过渡区3上可以集成有栅极驱动电路，该栅极驱动电路可以用于向像素驱动电路提供栅极驱动信号或使能信号。
如图2所示，为相关技术中四曲面屏显示面板过渡区的结构图。过渡区3可以集成有行列分布的多个像素单元以及栅极驱动电路。如果2所示，该栅极驱动电路可以包括移位寄存器单元61和信号线组62，其中，移位寄存器单元61可以包括有多个晶体管和多个电容结构。如图2所示，移位寄存器单元61和信号线组62可以设置于同一行相邻的两像素单元之间。如图2所示，由于移位寄存器单元61和信号线组62的占用面积较大，因此，移位寄存器单元61和信号线组62一侧的像素驱动电路5需要偏移 像素开口71设置。相应的，像素驱动电路5需要通过延长阳极走线的方式与像素开口71位置的阳极连接。然而，其他像素单元中的像素驱动电路不需要偏移像素开口设置，其像素驱动电路位于像素开口的正下方。同时由于延长的阳极走线本身具有一定的电阻，发生偏移的像素驱动电路向阳极输出的驱动信号具有一定压降，从而会导致发生偏移的像素驱动电路与未发生偏移的像素驱动电路向阳极输出不同的驱动电压，最终导致显示面板显示不均匀。
基于此，本示例性实施例提供一种显示面板，如图3、4、5所示，图3为本公开显示面板一种示例性实施例的结构示意图，图4为本公开显示面板一种示例性实施例中过渡区的结构示意图，图5为图4中虚线A-A的剖视图。该显示面板包括位于显示区1的过渡区3，所述显示面板还包括：衬底基板8、多个像素单元7、第一栅极驱动电路。多个像素单元7位于所述衬底基板的一侧，且集成于所述过渡区3，多个所述像素单元7在所述过渡区行列分布，其中，虚线A-A可以沿行方向X延伸；第一栅极驱动电路位于所述衬底基板面向所述像素单元7的一侧，且集成于所述过渡区3，所述第一栅极驱动电路可以包括第一移位寄存器单元61和第一信号线组，所述第一信号线组可以包括用于向所述第一移位寄存器单元提供驱动信号的第一信号线段组62；其中，所述衬底基板8可以包括多个集成部81，所述集成部81可以位于同一行两相邻像素单元7在所述衬底基板的正投影之间，所述第一移位寄存器单元61在所述衬底基板的正投影和所述第一信号线段组62在所述衬底基板的正投影分别位于同一行的不同所述集成部。
本公开提供的显示面板通过将所述第一移位寄存器单元61在所述衬底基板的正投影和所述第一信号线段组62在所述衬底基板的正投影分别设置于同一行的不同所述集成部81，从而避免了由于过度区中像素驱动电路的偏移导致的显示不均匀。
本示例性实施例中，如图3所示，所述显示面板还可以包括位于所述显示面板的边角位置的拉伸区4，以及位于显示区的正常显示区11，所述过渡区3可以位于所述拉伸区4和所述正常显示区11之间。本示例性实施例中，所述过渡区3中的像素密度可以小于所述正常显示区中的像素密度，以预留出用于设置第一栅极驱动电路的空间。本示例性实施例中，所述显示面板可以包括阵列基板和封装于所述阵列基板一侧的封装层，所述拉伸区4设置有贯穿所述阵列基板和所述封装层的镂空开口。该镂空开口可以增强拉伸区4的弯折能力，以便于显示面板四边向背板方向弯折。所述拉伸区4可以包括位于显示区1的第一拉伸区41和第二拉伸区42，所述第一拉伸区41中的像素密度可以小于所述正常显示区中的像素密度，以预留用于设置镂空开口的空间。第二拉伸区42可以位于显示面板的边框区。
本示例性实施例中，如图5所示，所述第一移位寄存器单元61在所述衬底基板8的正投影和所述第一信号线段组62在所述衬底基板8的正投影可以分别位于同一行的相邻两所述集成部81。该设置可以减小第一信号线段组62和第一移位寄存器单元61之间信号连接线的长度。应该理解的是，在其他示例性实施例中，所述第一移位寄存器单元61 在所述衬底基板8的正投影和所述第一信号线段组62在所述衬底基板8的正投影还可以分别位于同一行中不相邻两所述集成部81。
本示例性实施例中，如图6所示，为图3中虚线框10的局部放大图。本示例性实施例中，过渡区3可以包括第一延伸区31、第二延伸区32，以及连接于第一延伸区31和第二延伸区32之间的第三延伸区33。如图6所示，第一延伸区31可以沿列方向Y直线延伸，第三延伸区33可以沿曲线延伸，第二延伸区32可以沿列方向Y直线延伸。其中，位于第三延伸区33的部分第一移位寄存器单元可以在所述衬底基板的正投影位于不同像素列。以使第一栅极驱动电路中的第一移位寄存器单元的级联方向与第三延伸区33的延伸方向相同。应该理解的是，在第一延伸区31和第二延伸区32中，第一移位寄存器单元可以沿列方向直线级联，即在第一延伸区31和第二延伸区32中的第一移位寄存器单元位于同一像素列。
本示例性实施例中，如图7所示，为本公开显示面板一种示例性实施例中过渡区第三延伸区的结构示意图。所述第一栅极驱动电路可以包括多个级联的第一移位寄存器单元61，如图7所示，本示例性实施例仅示例性的画出了4个级联的第一移位寄存器单元61，其中，相级联的两第一移位寄存器单元61可以通过连接线9级联。所述第一信号线组可以包括与所述第一栅极驱动电路一一对应设置的多个第一信号线段组62，第一信号线段组62用于向与其对应设置的第一移位寄存器单元61提供驱动信号。且多个所述第一信号线段组62中的同种信号线相连接。例如，如图4所述，第一信号线段组62可以包括第一时钟信号线段CK、第二时钟信号线段CB、第一电源线段VGL、第二电源线段VGH，每组第一信号线段组62中的第一时钟信号线段CK相互连接；每组第一信号线段组62中的第二时钟信号线段CB相互连接；每组第一信号线段组62中的第一电源线段VGL相互连接；每组第一信号线段组62中的第二电源线段VGH相互连接。图7中，第二像素行第一移位寄存器单元和第三像素行第一移位寄存器单元在所述衬底基板的正投影位于不同像素列，从而使得第一移位寄存器单元可以沿弯曲方向级联。应该理解的是，在其他示例性实施例中，所述第一信号线组还可以包括其他数量和种类的信号线，例如，所述第一信号线组可以包括时钟信号线、电源信号线中的一种或多种。
如图7所示，本示例性实施例中，多个所述像素单元7可以形成多个行列分布的像素岛07，所述第一栅极驱动电路在所述衬底基板的正投影可以位于相邻所述像素岛在所述衬底基板所在平面的正投影之间。位于所述弯沿区的至少部分所述第一信号线段组在所述衬底基板的正投影位于不同列。例如，如图7所示，第三像素行中的第一信号线段组和位于第二像素行的第一信号线段组位于不同列，如图7所示，位于不同列的所述第一信号线段组可以通过沿行方向延伸的连接线段组08连接，所述连接线段组08在所述衬底基板的正投影可以位于相邻所述像素岛在所述衬底基板所在平面的正投影之间。
如图7所示，每个所述像素岛07可以包括沿列方向分布的两个像素单元7，且每个所述像素岛包括：位于第一像素开口行且相邻设置的B像素开口71和R像素开口72、位 于第二像素开口行且沿列方向分布的两个G像素开口73、位于第三像素开口行且相邻设置的B像素开口71和R像素开口72；其中，第二像素开口行位于所述第一像素开口行和第三像素开口行之间，且相同颜色像素开口位于同一像素开口列，不同颜色像素开口位于不同像素开口列。
如图3所示，所述显示面板还可以包括位于所述显示区周边为边框区2，所述显示面板还包括第二栅极驱动电路12，第二栅极驱动电路12位于所述衬底基板面向所述像素单元的一侧，且集成于所述边框区2，所述第二栅极驱动电路12可以包括多个级联的第二移位寄存单元，以及用于向多个所述第二移位寄存器单元提供驱动信号的第二信号线组。其中，第一栅极驱动电路可以用于向与过渡区中像素单元同行的所有像素单元提供驱动信号。第二栅极驱动电路可以用于向其余像素单元提供驱动信号。所述第二移位寄存器单元可以和所述第一移位寄存器单元级联，所述第一信号线组可以和所述第二信号线组中的同种信号线相连接。即，第一移位寄存器单元和第二移位寄存器单元可以连接同一信号线组，该信号线组可以同时向第一移位寄存器单元和第二移位寄存器单元提供相同的时钟信号和电源信号，第一移位寄存器单元和第二移位寄存器单元可以在相同的时钟信号和电源信号作用下实现逐级驱动。
本示例性实施例中，所述第一移位寄存器单元中的晶体管个数可以小于所述第二移位寄存器单元中晶体管的个数。该设置可以使得位于过渡区中的第一移位寄存器单元在衬底基板上的正投影具有较小的面积，以便于显示面板设计版图。应该理解的是，在其他示例性实施例中，所述第一移位寄存器单元中的晶体管个数也可以等于或大于所述第二移位寄存器单元中晶体管的个数。
以下本示例性实施例提供一种第一移位寄存器单元和第二移位寄存器单元的具体结构。
本示例性实施例中，如图8所示，为本公开显示面板一种示例性实施例中第一移位寄存器单元的结构示意图。所述第一移位寄存器单元包括：第一输入电路1、第二输入电路2、控制电路3、第一输出电路4、第二输出电路5，第一输入电路1连接第一时钟信号端CK、第一电源端VGL、第一节点N1，用于响应所述第一时钟信号端CK的信号将所述第一电源端VGL的信号传输到所述第一节点N1；第二输入电路2连接所述第一时钟信号端CK、信号输入端Input、第二节点N2，用于响应所述第一时钟信号端CK的信号将所述信号输入端Input的信号传输到所述第二节点N2；控制电路3连接所述第一节点N1、第二节点N2、第一时钟信号端CK，用于响应所述第二节点N2的信号将所述第一时钟信号端CK的信号传输到所述第一节点N1；第一输出电路4连接所述第一节点N1、第二电源端VGH、输出端OUT，用于响应所述第一节点N1的信号将所述第二电源端VGH的信号传输到所述输出端OUT；第二输出电路5连接所述第二节点N2、第二时钟信号端CB、输出端OUT，用于响应所述第二节点N2的信号将所述第二时钟信号端CB的信号传输到所述输出端OUT。
本示例性实施例中，所述第一输入电路1可以包括第一晶体管T1，第一晶体管T1的第一端连接所述第一电源端VGL，第二端连接所述第一节点N1，控制端连接所述第一时钟信号端CK；第二输入电路2可以包括第二晶体管T2，第二晶体管T2的第一端连接所述信号输入端Input，第二端连接所述第二节点N2，控制端连接所述第一时钟信号端CK；所述控制电路包括第三晶体管T3，第三晶体管T3的第一端连接所述第一节点N1，第二端连接所述第一时钟信号端CK，控制端连接所述第二节点N2；所述第一输出电路4可以包括第四晶体管T4和第一电容C1，第四晶体管T4的第一端连接所述第二电源端VGH，第二端连接所述输出端OUT，控制端连接所述第一节点N1；第一电容C1可以连接于所述第二电源端VGH和所述第一节点N1之间；第二输出电路可以包括第五晶体管T5和第二电容C2，第五晶体管T5的第一端连接所述第二时钟信号端CB，第二端连接所述输出端OUT，控制端连接所述第二节点N2；第二电容C2可以连接于所述第二节点N2和所述输出端OUT之间。其中，第一到第五晶体管可以为P型晶体管。
本示例性实施例中，如图9所示，为本公开显示面板一种示例性实施例中第二移位寄存器单元的结构示意图。所述第二移位寄存器单元可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第一电容C1、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第二电容C2，第一晶体管T1的第一端连接信号输入端Input，第二端连接第一节点N1，控制端连接第一时钟信号端CK；第二晶体管T2的第一端连接所述第一时钟信号端CK，第二端连接第二节点N2，控制端连接所述第一节点N1；第三晶体管T3的第一端连接第一电源端VGL，第二端连接所述第二节点N2，控制端连接所述第一时钟信号端CK；第四晶体管T4的第一端连接第二电源端VGH，第二端连接输出端OUT，控制端连接所述第二节点N2；第一电容C1连接于所述第二节点N2和所述第二电源端VGH之间；第五晶体管T5的第一端连接所述第二电源端VGH，第二端连接第三节点N3，控制端连接所述第二节点N2；第六晶体管T6的第一端连接所述第三节点N3，第二端连接所述第一节点N1，控制端连接第二时钟信号端CB；第七晶体管T7的第一端连接所述第一节点N1，第二端连接第四节点N4，控制端连接所述第一电源端VGL；第八晶体管T8的第一端连接所述输出端OUT，第二端连接第二时钟信号端CB，控制端连接所述第四节点N4；第二电容C2连接于所述第四节点N4和所述输出端OUT之间。其中，第一到第八晶体管可以为P型晶体管。
如图10a所示，为图8所示第一移位寄存器单元在一种驱动方法中各节点的时序图。其中，第一到第五晶体管可以为P型晶体管。图8中第一电源端VGL输出持续低电平，第二电源端VGH持续输出高电平。图8所示的第一移位寄存器单元的驱动方法包括两个阶段：第一阶段、第二阶段。在第一阶段T1：第一时钟信号端CK输出低电平信号，第二时钟信号端CB输出高电平信号，信号输入端Input输出低电平信号，第一到第五开关晶体管均导通，输出端OUT输出高电平信号；在第二阶段T2：第一时钟信号端CK输出高电平信号，第二时钟信号端CB输出低电平信号，信号输入端Input输出高电平信号， 第五晶体管T5导通，第二晶体管、第一晶体管、第四晶体管均关断，输出端输出低电平。
如图10b所示，为图9所示第二移位寄存器单元在一种驱动方法中各节点的时序图。其中，第一到第八晶体管可以为P型晶体管。图9中第一电源端VGL输出持续低电平，第二电源端VGH持续输出高电平。图9所示的第二移位寄存器单元的驱动方法包括两个阶段：第一阶段、第二阶段。在第一阶段T1：第一时钟信号端CK输出低电平信号，第二时钟信号端CB输出高电平信号，信号输入端Input输出低电平信号，第一晶体管、第二晶体管、第四晶体管导通，输出端输出高电平。在第二阶段T2：第一时钟信号端CK输出高电平信号，第二时钟信号端CB输出低电平信号，信号输入端Input输出高电平信号，第一晶体管、第三晶体管、第四晶体管关断，第八晶体管导通，输出端输出低电平。
根据图10a、图10b可知，本示例性实施例中的第一移位寄存器单元和第二移位寄存器单元可以在相同的驱动信号作用下实现自身驱动，即第一移位寄存器单元和第二移位寄存器单元可以连接于同一信号线组。
应该理解的是，在其他示例性实施例中，第一移位寄存器单元和第二移位寄存器单元还可以有其他的结构可供选择，这些都属于本公开的保护范围。
本示例性实施例中，第一移位寄存器单元采用5T2C结构，第二移位寄存器单元采用8T2C结构。显然，所述第一移位寄存器单元中的晶体管个数可以小于所述第二移位寄存器单元中晶体管的个数。该设置可以使得位于过渡区中的第一移位寄存器单元在衬底基板上的正投影具有较小的面积，从而以便于显示面板设计版图。
本示例性实施例中，如图11所示，为图4、6中第一移位寄存器单元的局部放大图。该第一移位寄存器单元可以包括：第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第一电容C1、第二电容C2。该第一移位寄存器单元中晶体管和电容的连接结构与图8中的电路结构相同。
其中，该第一移位寄存器单元可以由依次层叠设置于衬底基板的有源层、第一导电层、第二导电层、第三导电层形成。
如图12所述为图11中有源层的结构示意图。该有源层包括第一有源部121、第二有源部122、第三有源部123、第四有源部124、第五有源部125，其中，第一有源部121用于形成第一晶体管T1的沟道区，第二有源部122用于形成第二晶体管T2的沟道区，第三有源部123用于形成第三晶体管T3的沟道区，第四有源部124用于形成第四晶体管T4的沟道区，第五有源部125用于形成第五晶体管T5的沟道区。
如图13所述为图11中第一导电层的结构示意图。该第一导电部包括导电部131、导电部132、导电部133、导电部134、导电部135、导电部136、导电部137、导电部138、导电部139、导电部140。其中，导电部131用于形成第一晶体管T1的栅极，导电部132用于形成第二晶体管T2的栅极，导电部133用于形成第三晶体管T3的栅极，导电部134用于形成第二晶体管T4的栅极，导电部135用于形成第五晶体管T5的栅极，导电部136用于形成第二电容的第一电极，导电部137用于形成第一电容的第一电极。导电部138与 导电部132连接用于形成第一时钟信号端，其中，在图4中，导电部138可以与第一时钟信号线段CK连接。导电部139用于形成第二时钟信号端，其中，在图4中，导电部139可以与第二时钟信号线段CB连接。导电部140与导电部137连接，用于形成第二电源端，其中，在图4中，导电部140可以与第二电源线段VGH连接。
如图14所示，为图11中第二导电层的结构示意图。该第二导电层包括导电部141和导电部142，导电部141用于形成第一电容的第二电极，导电部142用于形成第二电容的第二电极。
如图15所示，为图11中第三导电层的结构示意图。该第三导电层可以包括导电部151、导电部152、导电部153、导电部154、导电部155、导电部156、导电部157、导电部158。其中，导电部151通过过孔连接第二有源部122的一侧，用于形成信号输入端Input，以使信号输入端与第二晶体管的第一端连接。导电部152通过过孔分别与第二有源部122的另一侧、导电部133连接，以使第二晶体管的第二端与第三晶体管的栅极连接。导电部153可以通过过孔与第一有源部121的一侧连接，用于形成第一电源端，以使第一晶体管的的第一端连接第一电源端，其中，在图4中，导电部153可以连接第一电源线段VGL。导电部154分别通过过孔与第一有源部121的另一侧、第三有源部123的一侧、导电部137连接，以使第一晶体管的第二端、第三晶体管的第一端、第一电容的一电极相互连接。导电部155分别通过过孔与三个第五有源部125的同一侧以及导电部139连接，以使第五晶体管的第一端连接第二时钟信号端CB。导电部158与导电部156连接，用于形成输出端。导电部156分别通过过孔与三个第五有源部125的另一侧连接，以使第五晶体管的第二端连接输出端。导电部157分别通过过孔与第四有源部124一侧、导电部141连接，以使第四晶体管的第一端连接第二电源端VGH。
本示例性实施例中，如图4、11所示，所述显示面板可以包括位于第一移位寄存器单元和所述第一信号线段组之间的像素单元(例如，图4中位于中间的像素单元)；所述第一时钟连接线在所述衬底基板的正投影和所述第二时钟连接线在所述衬底基板的正投影分别位于该像素单元(例如，图4中位于中间的像素单元)的相对两侧。根据图10a、10b可以看出第一时钟信号线段和第二时钟信号线段输出的时钟信号极性相反，该设置可以避免所述第一时钟连接线92和所述第二时钟连接线93相邻设置，从而避免了第一时钟连接线92和所述第二时钟连接线93上的信号相互干扰。如图4所示，第一电源连接线91可以位于第一时钟连接线92远离该像素单元的一侧，第二电源连接线可以位于第二时钟连接线93远离该像素单元的一侧，该设置可以避免第一时钟连接线与上一像素行的第二时钟连接线相邻设置，同时可以避免第二时钟连接线与下一像素行的第一时钟连接线相邻设置。
本示例性实施例中，如图4、11所示，所述第一晶体管T1、第二晶体管T2、第三晶体管T3可以位于所述第四晶体管T4、第五晶体管T5远离一像素单元(例如，图4中最右侧像素单元)的一侧。该设置可以使得第四晶体管T4、第五晶体管T5的输出端(即输 出端)与该像素单元(图4中最右侧像素单元)相邻，即所述输出端可以与图4中最右侧像素单元相邻，该输出端可以通过较短的栅线和该像素单元中与其邻近的像素驱动电路连接。
本示例性实施例中，所述第二电容C2可以位于所述第四晶体管、第五晶体管远离所述第一晶体管、第二晶体管、第三晶体管的一侧。即第二电容C2可以位于第四晶体管、第五晶体管与图4中最右侧的像素单元之间。该设置可以通过第二电容C2将第一移位寄存器单元中的部分晶体管与图4中最右侧像素单元中的晶体管隔离，从而避免了该显示面板中晶体管各个功能结构层的构图过于密集，进而降低了该显示面板构图工艺中的工艺难度。
本示例性实施例中，如图16所示，为本公开显示面板中第二栅极驱动电路的设计版图，如图16所示，第二信号线组可以包括第一时钟信号线CK、第二时钟信号线CB、第一电源线VGL、第二电源线VGH。第二移位寄存器单元包括第一到第八晶体管T1-T8以及第一电容C1、第二电容C2。该第二移位寄存器单元中晶体管和电容的连接结构可以与图9中的电路结构相同。其中，该第二栅极驱动电路同样可以由依次层叠设置于衬底基板的上述有源层、第一导电层、第二导电层、第三导电层形成。
如图17所示，为图16中有源层的结构示意图，该有源层可以包括第一有源部171、第二有源部172、第三有源部173、第四有源部174、第五有源部175、第六有源部176、第七有源部177、第八有源部178。第一有源部171用于形成第一晶体管的沟道区；第二有源部172用于形成第二晶体管的沟道区；第三有源部173用于形成第三晶体管的沟道区；第四有源部174用于形成第四晶体管的沟道区；第五有源部175用于形成第五晶体管的沟道区；第六有源部176用于形成第六晶体管的沟道区；第七有源部177用于形成第七晶体管的沟道区；第八有源部178用于形成第八晶体管的沟道区。
如图18所示，为图16中第一导电层的结构示意图，第一导电层包括导电部181、导电部182、导电部183、导电部184、导电部185、导电部186、导电部187、导电部188、导电部189、导电部190。导电部181用于形成第一晶体管的栅极、导电部182用于形成第二晶体管的栅极，导电部183用于形成第三晶体管的栅极，导电部184用于形成第四晶体管的栅极，导电部185用于形成第五晶体管的栅极，导电部186用于形成第六晶体管的栅极，导电部187用于形成第七晶体管的栅极，导电部188用于形成第八晶体管的栅极，导电部189用于形成第二电容的一电极，导电部190用于形成第一电容的一电极。
如图19所示，为图16中第二导电层的结构示意图，第二导电层包括导电部191、导电部192。其中，导电部192用于形成第二电容的另一电极，导电部191用于形成第一电容的另一电极。
如图20所示，为图16中第三导电层的结构示意图。该第三导电层包括第一时钟信号线CK、第二时钟信号线CB、第一电源线VGL、第二电源线VGH，导电部201到导电部208。其中，第一时钟信号线CK通过过孔与导电部181电连接，以使第一时钟信号线连 接第一晶体管的栅极；第二电源线VGH通过过孔与导电部191连接，以使第二电源线连接第一电容的一电极；第二电源线VGH通过过孔电连接第五有源部175的一侧，以使第二电源线VGH连接第五晶体管的第一端；第二时钟信号线CB通过过孔与导电部186电连接，以使第二时钟信号线连接第六晶体管的栅极；第一电源线VGL通过过孔与第三有源部173连接，以使第一电源线连接第三晶体管的第一端；导电部201通过过孔与第一有源部171的一侧连接，用于形成信号输入端；导电部202通过过孔分别连接第一有源部171的另一侧、导电部182，以使第一晶体管的第二端、第六晶体管的第二端、第二晶体管的栅极相互连接；导电部203分别通过过孔与第三有源部173的一侧、第二有源部172的一侧、导电部190连接，以使第二晶体管的第二端、第三晶体管的第一端、第一电容的一电极相互连接。导电部204分别通过过孔与导电部182、第七有源部177的一侧连接，以使第二晶体管的栅极连接第七晶体管的第一端。导电部205分别通过过孔与导电部188、第七有源部177的另一侧连接，以使第七晶体管第二极连接第八晶体管的栅极连接。导电部206分别通过过孔与三个第八有源部178的同一侧、导电部186连接，以使第二时钟信号线CB与第八晶体管的第一级连接。导电部207通过过孔与三个第八有源部178的另一侧连接，用于形成输出端OUT。导电部208分别通过过孔与第四有源部174的一侧、导电部191连接，以使第四晶体管的第一端连接第二电源线。
如图4所示，所述第一信号线段组62可以通过沿行方向延伸的第一连接线组与所述第一移位寄存器单元61连接；所述第一信号线段组可以包括：第一时钟信号线段CK、第二时钟信号线段CB、第一电源线段VGL、第二电源线段VGH。其中，如图4所示，所述第一电源信号线段VGL可以位于所述第一移位寄存器单元的一侧，所述第一时钟信号线段CK、第二时钟信号线段CB、第二电源线段VGH可以位于所述第一电源信号线VGL段远离所述第一移位寄存器单元61的一侧。第一时钟信号线段CK、第二时钟信号线段CB、第一电源线段VGL、第二电源线段VGH可以由部分第三导电层形成。所述第一连接线组可以包括：第一时钟连接线92、第二时钟连接线93、第一电源连接线91、第二电源连接线(包括第一连接部941和第二连接部942)；其中，所述第一时钟信号线段CK可以通过所述第一时钟连接线92与所述第一晶体管、第二晶体管的栅极连接，具体的，第一时钟连接线92可以由部分第一导电层形成，第一时钟连接线92的第一端可以通过过孔与图4中的第一时钟信号线段CK连接，第一时钟连接线92的第二端可以与图13中的导电部138连接。所述第二时钟信号线段CB可以通过所述第二时钟连接线93与所述第五晶体管的一源/漏极连接，具体的，第二时钟连接线93可以由部分第一导电层形成，第二时钟连接线93的第一端可以通过过孔与图4中的第二时钟信号线段CB连接，第二时钟连接线93的第二端可以与图13中的导电部139连接。所述第一电源线段VGL可以通过所述第一电源连接线91与所述第三晶体管的一源/漏极连接，具体的，第一电源连接线91可以由部分第三导电层形成，第一电源连接线91的第一端可以与所述第一电源线段VGL连接，第一电源连接线91的第二端可以与图15中的导电部153连接。所述第二电 源线段VGH可以通过所述第二电源连接线与所述第一电容的二电极连接。所述第二电源连接线可以包括第一连接部941、第二连接部942，所述第一连接部941可以通过过孔与第二电源线段VGH连接，第二连接部942可以通过过孔与所述第一电容的二电极连接，其中，第一连接部941和第二连接部942可以通过位于所述第二电源线段VGH和第一电容之间的过孔连接。
本示例性实施例中，显示面板中的像素单元包括有多个子像素单元，每个子像素单元包括一个像素驱动电路，该像素驱动电路中包括有开关晶体管，该开关晶体管的栅极用于接收第一栅极驱动电路提供的栅极驱动信号或使能信号。本示例性实施例中，位于同一像素行的开关晶体管的栅极本身相互连接。因此，本示例性实上施例中在通过第一移位寄存器单元向同一行像素单元提供驱动信号时，仅需要向一个邻近的像素驱动电路提供驱动信号即可实现向整行像素驱动电路提供驱动信号。如图4、11所示，第五晶体管的第二端连接输出端OUT，输出端OUT可以通过栅线与其右侧的像素单元连接。
根据本公开的一个方面，提供一种显示装置，该显示装置包括上述的显示面板。该显示装置可以为手机、电视、平板电脑等。
本领域技术人员在考虑说明书及实践这里公开的公开后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性远离并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (21)

  1. 一种显示面板，其中，所述显示面板包括显示区、位于显示区周边的边框区、位于所述显示面板边角位置的拉伸区，位于显示区的正常显示区，以及位于所述拉伸区和所述正常显示区之间过渡区，所述显示面板还包括：
    衬底基板；
    多个像素单元，位于所述衬底基板的一侧，且集成于所述过渡区，多个所述像素单元在所述过渡区行列分布；
    第一栅极驱动电路，位于所述衬底基板面向所述像素单元的一侧，且集成于所述过渡区，所述第一栅极驱动电路包括第一移位寄存器单元和第一信号线组，所述第一信号线组包括用于向所述第一移位寄存器单元提供驱动信号的第一信号线段组；
    其中，所述衬底基板包括多个集成部，所述集成部位于同一行两相邻所述像素单元在所述衬底基板的正投影之间，所述第一移位寄存器单元在所述衬底基板的正投影和所述第一信号线段组在所述衬底基板的正投影分别位于同一行的不同集成部；
    第二栅极驱动电路，位于所述衬底基板面向所述像素单元的一侧，且集成于所述边框区，所述第二栅极驱动电路包括多个级联的第二移位寄存单元；
    所述第一移位寄存器单元中的晶体管个数小于所述第二移位寄存器单元中晶体管的个数。
  2. 根据权利要求1所述的显示面板，其中，所述第一移位寄存器单元在所述衬底基板的正投影和所述第一信号线段组在所述衬底基板的正投影分别位于同一行的相邻两所述集成部。
  3. 根据权利要求1所述的显示面板，其中，多个所述像素单元形成多个行列分布的像素岛，所述第一栅极驱动电路在所述衬底基板的正投影位于相邻所述像素岛在所述衬底基板所在平面的正投影之间。
  4. 根据权利要求3所述的显示面板，其中，每个所述像素岛包括沿列方向分布的两个像素单元，且每个所述像素岛包括：位于第一像素开口行且相邻设置的B像素开口和R像素开口、位于第二像素开口行且沿列方向分布的两个G像素开口、位于第三像素开口行且相邻设置的B像素开口和R像素开口；
    其中，第二像素开口行位于所述第一像素开口行和第三像素开口行之间，且相同颜色像素开口位于同一像素开口列，不同颜色像素开口位于不同像素开口列。
  5. 根据权利要求3所述的显示面板，其中，所述第一栅极驱动电路包括多个 级联的第一移位寄存器单元，所述第一信号线组包括与所述第一栅极驱动电路一一对应设置的多个第一信号线段组，第一信号线段组分别用于向与其对应的所述第一移位寄存器单元提供驱动信号。
  6. 根据权利要求5所述的显示面板，其中，所述过渡区包括沿曲线延伸的弯沿区，位于所述弯沿区的至少部分所述第一移位寄存器单元在所述衬底基板的正投影位于不同列，相应的，位于所述弯沿区的至少部分所述第一信号线段组在所述衬底基板的正投影位于不同列。
  7. 根据权利要求6所述的显示面板，其中，位于不同列的所述第一信号线段组通过沿行方向延伸的连接线段组连接，所述连接线段组在所述衬底基板的正投影位于相邻所述像素岛在所述衬底基板所在平面的正投影之间。
  8. 根据权利要求1所述的显示面板，其中，所述第一信号线组包括：时钟信号线、电源信号线中的一种或多种。
  9. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    第二信号线组，用于向多个所述第二移位寄存器单元提供驱动信号；
    其中，所述第二移位寄存器单元和所述第一移位寄存器单元级联，所述第一信号线组和所述第二信号线组中的同种信号线相连接。
  10. 根据权利要求1所述的显示面板，其中，所述第一移位寄存器单元包括：
    第一输入电路，连接第一时钟信号端、第一电源端、第一节点，用于响应所述第一时钟信号端的信号将所述第一电源端的信号传输到所述第一节点；
    第二输入电路，连接所述第一时钟信号端、信号输入端、第二节点，用于响应所述第一时钟信号端的信号将所述信号输入端的信号传输到所述第二节点；
    控制电路，连接所述第一节点、第二节点、第一时钟信号端，用于响应所述第二节点的信号将所述第一时钟信号端的信号传输到所述第一节点；
    第一输出电路，连接所述第一节点、第二电源端、输出端，用于响应所述第一节点的信号将所述第二电源端的信号传输到所述输出端；
    第二输出电路，连接所述第二节点、第二时钟信号端、输出端，用于响应所述第二节点的信号将所述第二时钟信号端的信号传输到所述输出端。
  11. 根据权利要求10所述的显示面板，其中，
    所述第一输入电路包括：
    第一晶体管，第一端连接所述第一电源端，第二端连接所述第一节点，控制端连接所述第一时钟信号端；
    第二输入电路包括：
    第二晶体管，第一端连接所述信号输入端，第二端连接所述第二节点，控制端连接所述第一时钟信号端；
    所述控制电路包括：
    第三晶体管，第一端连接所述第一节点，第二端连接所述第一时钟信号端，控制端连接所述第二节点；
    所述第一输出电路包括：
    第四晶体管，第一端连接所述第二电源端，第二端连接所述输出端，控制端连接所述第一节点；
    第一电容，连接于所述第二电源端和所述第一节点之间；
    第二输出电路包括：
    第五晶体管，第一端连接所述第二时钟信号端，第二端连接所述输出端，控制端连接所述第二节点；
    第二电容，连接于所述第二节点和所述输出端之间。
  12. 根据权利要求1所述的显示面板，其中，所述第二移位寄存器单元包括：
    第一晶体管，第一端连接信号输入端，第二端连接第一节点，控制端连接第一时钟信号端；
    第二晶体管，第一端连接所述第一时钟信号端，第二端连接第二节点，控制端连接所述第一节点；
    第三晶体管，第一端连接第一电源端，第二端连接所述第二节点，控制端连接所述第一时钟信号端；
    第四晶体管，第一端连接第二电源端，第二端连接输出端，控制端连接所述第二节点；
    第一电容，连接于所述第二节点和所述第二电源端之间；
    第五晶体管，第一端连接所述第二电源端，第二端连接第三节点，控制端连接所述第二节点；
    第六晶体管，第一端连接所述第三节点，第二端连接所述第一节点，控制端连接第二时钟信号端；
    第七晶体管，第一端连接所述第一节点，第二端连接第四节点，控制端连接所述第一电源端；
    第八晶体管，第一端连接所述输出端，第二端连接第二时钟信号端，控制端连接所述第四节点；
    第二电容，连接于所述第四节点和所述输出端之间。
  13. 根据权利要求11所述的显示面板，其中，所述第一信号线段组通过沿行方向延伸的第一连接线组与所述第一移位寄存器单元连接；
    所述第一信号线段组包括：第一时钟信号线段、第二时钟信号线段、第一电源线段、第二电源线段；
    所述第一连接线组包括：第一时钟连接线、第二时钟连接线、第一电源连接线、第二电源连接线；
    其中，所述第一时钟信号线通过所述第一时钟连接线与所述第一晶体管、第二晶体管的栅极连接，所述第二时钟信号线段通过所述第二时钟连接线与所述第五晶体管的一源/漏极连接，所述第一电源线段通过所述第一电源连接线与所述第三晶体管的一源/漏极连接，所述第二电源线段通过所述第二电源连接线与所述第一电容的一电极连接。
  14. 根据权利要求13所述的显示面板，其中，所述显示面板包括依次层叠设置于所述衬底基板一侧的有源层、第一导电层、第二导电层、第三导电层；
    部分所述有源层用于形成所述第一移位寄存器单元中晶体管的沟道区，部分所述第一导电层用于形成所述第一移位寄存器单元中晶体管的栅极以及所述第一电容、第二电容的第一电极，部分所述第二导电层用于形成所述第一电容、第二电容的第二电极，部分所述第三导电层用于形成所述第一移位寄存器单元中晶体管的源/漏极；
    所述第一电源信号线段位于所述第一移位寄存器单元的一侧，所述第一时钟信号线段、第二时钟信号线段、第二电源线段位于所述第一电源信号线段远离所述第一移位寄存器单元的一侧；
    所述第一电源连接线由部分所述第三导电层形成，所述第一时钟连接线、第二时钟连接线由部分所述第一导电层形成；
    所述第二电源连接线包括第一连接部、第二连接部，所述第一连接部通过过孔与第二电源线段连接，第二连接部通过过孔与所述第一电容的第二电极连接，且第一连接部和第二连接部通过位于所述第二电源线段和第一电容之间的过孔连接，其中，所述第一连接部由部分所述第一导电层形成，所述第二导电部由部分所述第三导电层形成。
  15. 根据权利要求13所述的显示面板，其中，所述显示面板包括位于第一移位寄存器单元和所述第一信号线段组之间的像素单元；
    所述第一时钟连接线在所述衬底基板的正投影和所述第二时钟连接线在所述衬底基板的正投影分别位于该像素单元的相对两侧。
  16. 根据权利要求11所述的显示面板，其中，所述第一晶体管、第二晶体管、第三晶体管位于所述第四晶体管、第五晶体管远离一像素单元的一侧，所述输出端通过栅线和该像素单元中与其邻近的像素驱动电路连接。
  17. 根据权利要求16所述的显示面板，其中，所述第二电容位于所述第四晶体管、第五晶体管远离所述第一晶体管、第二晶体管、第三晶体管的一侧。
  18. 根据权利要求1所述的显示面板，其中，所述过渡区中的像素密度小于所述正常显示区中的像素密度。
  19. 根据权利要求1所述的显示面板，其中，所述拉伸区包括位于显示区的第一拉伸区，所述第一拉伸区中的像素密度小于所述正常显示区中的像素密度。
  20. 根据权利要求1所述的显示面板，其中，所述显示面板包括阵列基板和封装于所述阵列基板一侧的封装层，所述拉伸区设置有贯穿所述阵列基板和所述封装层的镂空开口。
  21. 一种显示装置，其中，包括权利要求1-20任一项所述的显示面板。
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