WO2021254406A1 - 电平转换电路、显示面板 - Google Patents

电平转换电路、显示面板 Download PDF

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Publication number
WO2021254406A1
WO2021254406A1 PCT/CN2021/100460 CN2021100460W WO2021254406A1 WO 2021254406 A1 WO2021254406 A1 WO 2021254406A1 CN 2021100460 W CN2021100460 W CN 2021100460W WO 2021254406 A1 WO2021254406 A1 WO 2021254406A1
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WO
WIPO (PCT)
Prior art keywords
control signal
circuit
terminal
signal
level conversion
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PCT/CN2021/100460
Other languages
English (en)
French (fr)
Inventor
张银龙
姚树林
孙志华
李琦
马文鹏
胡鹏飞
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/908,561 priority Critical patent/US11715403B2/en
Publication of WO2021254406A1 publication Critical patent/WO2021254406A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a level conversion circuit and a display panel.
  • the gate driving circuit needs to input a gate driving signal to the gate line under the control of a clock signal.
  • the clock signal is usually generated by the level conversion circuit according to the clock control signal output by the timing controller.
  • the level conversion circuit generally includes a signal generation circuit and an operational amplifier circuit.
  • the signal generation circuit is used to output original clock signals to multiple signal output terminals according to the clock control signal output by the timing controller;
  • the operational amplifier circuit includes multiple The input terminals and the multiple output terminals corresponding to the input terminals one-to-one are used for level conversion of the voltage at the input terminal and output through the output terminal.
  • the signal output terminal of the signal generating circuit can be connected to the input terminal of the operational amplifier circuit in a one-to-one correspondence, and the operational amplifier circuit can perform level conversion on the original clock signal to obtain the clock signal.
  • the number of clock signals output by the level conversion circuit is fixed.
  • gate drive circuits of different structures require different numbers of clock signals. Therefore, various gate drive circuits need to be configured with different structures. Level conversion circuit, thereby increasing the design cost of the level conversion circuit.
  • a level conversion circuit including: a signal generation circuit, a first operational amplifier circuit, and a plurality of switch circuits.
  • the signal generating circuit is used to output driving signals through a plurality of signal output terminals respectively;
  • the first operational amplifier circuit is used to level-convert the voltage of an input terminal and output it through the output terminal, and the signal output terminal of the signal generating circuit and the first operation
  • the input terminals of the amplifying circuit are arranged in one-to-one correspondence;
  • the switch circuit is connected between the signal output terminal of the corresponding signal generating circuit and the input terminal of the first operational amplifier circuit, and is connected to the control signal terminal.
  • the switch circuit is used to respond to the control signal terminal
  • the signal is connected to the signal output terminal of the signal generating circuit and the input terminal of the first operational amplifier circuit; wherein at least part of the switch circuit is connected to different control signal terminals.
  • the level conversion circuit further includes: a register and a control circuit, where the register is used to store a control signal group; the control circuit is connected to the register and a plurality of control signal terminals for The control signal group inputs corresponding control signals to a plurality of the control signal terminals respectively.
  • the register is connected to a control signal generating circuit, and the control signal generating circuit is used to configure the control signal group to the register.
  • the switch circuit is used to respond to a high-level signal to connect the signal output terminal of the signal generating circuit and the input terminal of the first operational amplifier circuit;
  • the control signal group includes a first A control signal and a second control signal.
  • the multiple control signal terminals include: a first control signal terminal, a second control signal terminal, a third control signal terminal, and a fourth control signal terminal.
  • the control circuit includes: AND gate, OR gate, second AND gate, third AND gate.
  • the first input terminal and the second input terminal of the first AND gate are connected to the high-level signal terminal, and the output terminal is connected to the first control signal terminal;
  • the first input terminal of the OR gate receives the first control signal, and the second output Terminal receives the second control signal, and the output terminal is connected to the second control signal terminal;
  • the first input terminal of the second AND gate receives the first control signal, the second input terminal receives the first control signal, and outputs The terminal is connected to the third control signal terminal;
  • the first input terminal of the third AND gate receives the first control signal, the second input terminal receives the second control signal, and the output terminal is connected to the fourth control signal terminal.
  • At least one of the control signal terminals is connected to a plurality of the switch circuits.
  • the plurality of switch circuits include first to tenth switch circuits; the first control signal terminal is connected to the first to fourth switch circuits, and the second control signal terminal The fifth switch circuit and the sixth switch circuit are connected, the third control signal terminal is connected to the seventh switch circuit and the eighth switch circuit, and the fourth control signal terminal is connected to the ninth switch circuit and the tenth switch circuit. Switch circuit.
  • the switch circuit includes a switch transistor, the first end of the switch transistor is connected to the input end of the first operational amplifier circuit, and the second end is connected to the signal output of the signal generating circuit Terminal, the control terminal is connected to the control signal terminal.
  • the level conversion circuit is applied to a display panel, the display panel includes a gate drive circuit, and the output terminal of the first operational amplifier circuit is used to provide Clock signal.
  • the display panel further includes a timing controller, and the signal generation circuit is configured to generate the driving signal under the control of the timing controller, and the driving signal is an original clock signal ,
  • the first operational amplifier circuit is used to perform level conversion on the original clock signal to form the clock signal.
  • the register is connected to a control signal generating circuit, and the control signal generating circuit shares the timing controller.
  • control signal group includes a plurality of control signals
  • the register includes a plurality of flip-flops, and each of the flip-flops stores one of the control signals.
  • control signal generating circuit and the register are connected through an I2C bus.
  • the display panel further includes a power management circuit
  • the power management circuit includes a first low-level output terminal, a high-level output terminal, and the power supply terminal of the first operational amplifier circuit
  • the first low-level output terminal and the high-level output terminal are respectively connected
  • the first operational amplifier circuit further includes a first low-level output terminal.
  • the power management circuit further includes a second low-level output terminal
  • the level conversion circuit further includes a second operational amplifier circuit
  • the second operational amplifier circuit includes a low-level output terminal
  • the power supply terminal of the second operational amplifier circuit is respectively connected to the second low-level output terminal and the high-level output terminal.
  • a display panel including the above-mentioned level conversion circuit.
  • FIG. 1 is a schematic diagram of a partial structure of a display panel in the related art
  • FIG. 2 is a schematic structural diagram of an exemplary embodiment of the level conversion circuit of the present disclosure
  • FIG. 3 is a schematic structural diagram of another exemplary embodiment of the level conversion circuit of the present disclosure.
  • FIG. 5 is a schematic structural diagram of another exemplary embodiment of the level conversion circuit of the present disclosure.
  • FIG. 6 is a schematic structural diagram of an exemplary embodiment of a display panel of the present disclosure.
  • FIG. 1 it is a schematic diagram of a partial structure of a display panel in the related art.
  • the display panel includes a power management circuit 1, a timing controller 3, a level conversion circuit 2, a gate driving circuit 4.
  • the gate driving circuit 4 needs to input a gate driving signal to the gate line under the control of a clock signal.
  • the level conversion circuit 2 is used to provide the above-mentioned clock signal to the gate drive circuit 4 according to the clock control signal provided by the timing controller 3 under the power drive provided by the power management circuit 1.
  • the level conversion circuit 2 includes a signal generation circuit 21 and an operational amplifier circuit 22.
  • the signal generation circuit 21 is used to output original clock signals to multiple signal output terminals of the timing controller 3 according to the timing signals output by the timing controller 3;
  • the operational amplifier circuit 22 includes a plurality of input terminals and a plurality of output terminals corresponding to the input terminals one-to-one, and is used for level conversion of the voltage at the input terminal and output through the output terminal.
  • the signal output terminal of the signal generating circuit 21 can be connected to the input terminal of the operational amplifier circuit 22 in a one-to-one correspondence, and the operational amplifier circuit can perform level conversion on the original clock signal to output the clock signal to the gate driving circuit 4.
  • the number of clock signals output by the level conversion circuit 2 is the number of clock signals output by the operational amplifier circuit 22.
  • the number of clock signals output by the level conversion circuit 2 is a fixed value.
  • the gate drive circuits 4 of different structures require different numbers of clock signals. Therefore, the gate drive circuits of different structures need to be configured with level conversion circuits of different structures. Therefore, in the related art, the level conversion The design cost of the circuit is relatively high.
  • the exemplary embodiment provides a level conversion circuit, as shown in FIG. 2, which is a schematic structural diagram of an exemplary embodiment of the level conversion circuit of the present disclosure.
  • the level conversion circuit may include: a signal generation circuit 21, a first operational amplifier circuit 22, and a plurality of switch circuits 23.
  • the signal generation circuit 21 may include a plurality of signal output terminals, and the signal generation circuit 21 is used to pass a plurality of the signals.
  • the output terminals respectively output the original clock signal;
  • the first operational amplifier circuit 22 may include a plurality of input terminals, and a plurality of output terminals corresponding to the plurality of input terminals one-to-one, and are used for level-converting the voltage of an input terminal and combining Through the output terminal corresponding to the input terminal, the signal output terminal of the signal generating circuit 21 and the input terminal of the first operational amplifier circuit 22 are arranged in a one-to-one correspondence, so that the first operational amplifier circuit 22 can generate signals.
  • the original clock signal output by the circuit 21 undergoes level conversion to generate a clock signal;
  • the switch circuit 23 can be connected to the corresponding signal output terminal of the signal generating circuit 21 and the input terminal of the first operational amplifier circuit 22 And connected to the control signal terminal, the switch circuit 23 can be used to respond to the signal of the control signal terminal to connect the signal output terminal of the signal generating circuit 21 and the input terminal of the first operational amplifier circuit 22; wherein, at least Some of the switch circuits can be connected to different control signal terminals. For example, as shown in FIG. 2, there are different switch circuits connected to the control signal terminals CN1, CN2, CN3, and CN4, respectively.
  • the level conversion circuit can control the number of communication channels between the first operational amplifier circuit and the signal generating circuit by controlling the opening of the switch circuit, that is, control the number of output terminals of the first operational amplifier circuit outputting the clock signal, and then the The level conversion circuit can match different gate drive circuits.
  • the level conversion circuit also includes a register 24 and a control circuit 25.
  • the register 24 can be used to store a control signal group; the control circuit 25 can be connected to the register 24 and multiple control signal terminals to control The circuit 25 may be used to input corresponding control signals to the multiple control signal terminals according to the control signal group, so as to control the on or off of different switch circuits.
  • the level conversion circuit can be applied not only to display panels, but also to other electronic devices. At the same time, the level conversion circuit can not only output clock signals, but also output other driving signals. Accordingly, the electrical The level conversion circuit can control the output quantity of other driving signals.
  • the register 24 may be connected to a control signal generating circuit 27, and the control signal generating circuit 27 may be used to configure the control signal group to the register.
  • the control signal generation circuit can be a circuit other than the level conversion circuit.
  • the control signal generation circuit can share the timing controller in the display panel, and the display panel can configure the control signal group to the register through the timing controller every time the display panel is turned on. . This arrangement can avoid the provision of extra storage space and processing units in the level conversion circuit, thereby reducing the cost of the level conversion circuit.
  • the control signal generating circuit may be connected to the register through an I2C bus.
  • the switch circuit 23 may be used to respond to a high-level signal to connect the signal output terminal of the signal generating circuit 21 and the input terminal of the first operational amplifier circuit 22.
  • the switch circuit may include N-type transistor, the first terminal of the N-type transistor is connected to the input terminal of the first operational amplifier circuit, the second terminal is connected to the signal output terminal of the signal generating circuit, and the control terminal is connected to the control signal terminal.
  • the register may be composed of multiple flip-flops, each flip-flop may store a control signal, and the control signals stored by the multiple flip-flops may form the control signal group.
  • the register 24 may be a two-bit register, that is, the register includes two flip-flops, and the output terminals of the two flip-flops respectively store two control signals: the first control signal CN1 and the second control signal.
  • Signal CN2 The plurality of switching circuits 23 may include first to tenth switching circuits, the first switching circuit may include an N-type transistor T1, the second switching circuit may include an N-type transistor T2, and the third switching circuit may include an N-type transistor T3, By analogy, the tenth switch circuit may include an N-type transistor T10.
  • the first terminal of the above-mentioned N-type switching transistor may be connected to the input terminal of the first operational amplifier circuit 22, the second terminal may be connected to the signal output terminal of the signal generating circuit 21, and the control terminal may be connected to the control signal terminal.
  • the signal generating circuit 21 can respectively output ten original clock signals through ten signal output terminals CLK1', CLK2', CLK3'...CLK10'.
  • the first operational amplifier circuit 22 can include ten input terminals and ten output terminals.
  • the ten input terminals of the first operational amplifier circuit 22 are set in one-to-one correspondence with the ten output terminals of the signal generating circuit 21.
  • the first operational amplifier circuit 22 may include ten input terminals CLK1, CLK2, CLK3...CLK10 .
  • the N-type transistor T1 is connected to the input terminal CLK1 and the output terminal CLK1' correspondingly, the N-type transistor T2 is correspondingly connected to the input terminal CLK2 and the output terminal CLK2', and the N-type transistor T3 is correspondingly connected to the input terminal CLK3 and the output terminal CLK3', and so on ,
  • the N-type transistor T10 is correspondingly connected to the input terminal CLK10 and the output terminal CLK10'.
  • Ten switch circuits can be connected to four different control signal terminals: first control signal terminal CN11, second control signal terminal CN12, third control signal terminal CN13, fourth control signal terminal CN14, for example, N-type transistors T1-T4
  • the gates of the N-type transistors T5-T6 may be connected to the first control signal terminal CN11, the gates of the N-type transistors T5-T6 may be connected to the second control signal terminal CN12, and the gates of the N-type transistors T7-T8 may be connected to the third control signal terminal CN13.
  • the gates of the transistors T9-T10 can be connected to the fourth control signal terminal CN14. As shown in FIG.
  • the control circuit 25 may include: a first AND gate ANDG1, an OR gate ORG, a second AND gate ANDG2, and a third AND gate ANDG3.
  • the first input terminal and the second input terminal of the first AND gate ANDG1 are connected to the high-level signal terminal VGH, and the output terminal is connected to the first control signal terminal CN11;
  • the first input terminal of the OR gate ORG receives the first control signal CN1,
  • the second output terminal receives the second control signal CN2, and the output terminal is connected to the second control signal terminal CN12;
  • the first input terminal of the second AND gate ANDG2 receives the first control signal CN1, and the second input terminal receives the first control signal CN1.
  • a control signal CN1 the output terminal is connected to the third control signal terminal CN13; the first input terminal of the third AND gate ANDG3 receives the first control signal CN1, the second input terminal receives the second control signal CN2, and the output terminal is connected The fourth control signal terminal CN14.
  • the N-type transistors T1, T2, T3, and T4 are turned on, and the N-type transistors T5, T6, and T7 are turned on. , T8, T9, and T10 are turned off.
  • the signal output terminals CLK1', CLK2', CLK3', CLK4' of the signal generating circuit 21 and the input terminals CLK1, CLK2, CLK3, and CLK4 of the first operational amplifier circuit 22 are one by one.
  • the first operational amplifier circuit 22 outputs four clock signals.
  • the N-type transistors T1, T2, T3, T4, T5, and T6 are turned on, and the N-type transistors T7, T8, T9, T10 Turn off, at this time, the signal output terminals CLK1', CLK2', CLK3', CLK4', CLK5', CLK6' of the signal generating circuit 21 and the input terminals CLK1, CLK2, CLK3, CLK4, CLK5 of the first operational amplifier circuit 22 CLK6 is connected in one-to-one correspondence, and correspondingly, the first operational amplifier circuit 22 outputs six clock signals.
  • the N-type transistors T1, T2, T3, T4, T5, T6, T7, and T8 are turned on, and the N-type transistors T9, T10 Turn off, at this time, the signal output terminals CLK1', CLK2', CLK3', CLK4', CLK5', CLK6', CLK7', CLK8' of the signal generating circuit 21 and the input terminals CLK1, CLK2 of the first operational amplifier circuit 22 CLK3, CLK4, CLK5, CLK6, CLK7, CLK8 are connected in a one-to-one correspondence, and correspondingly, the first operational amplifier circuit 22 outputs eight clock signals.
  • the N-type transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10 are turned on, at this time .
  • the signal output terminals CLK1', CLK2', CLK3', CLK4', CLK5', CLK6', CLK7', CLK8', CLK9', CLK10' of the signal generating circuit 21 and the input terminals CLK1 of the first operational amplifier circuit 22 CLK2, CLK3, CLK4, CLK5, CLK6, CLK7, CLK8, CLK9, CLK10 are connected in a one-to-one correspondence, and correspondingly, the first operational amplifier circuit 22 outputs ten clock signals.
  • the number of signal output terminals in the signal generating circuit 21 may also be other numbers.
  • the first operational amplifier circuit 22 may have the same number of input terminals and the number of switching circuits. The number can be the same as the number of signal output terminals in the signal generating circuit 21.
  • the first control signal terminal CN11, the second control signal terminal CN12, the third control signal terminal CN13, and the fourth control signal terminal CN14 can also control other numbers of switch circuits, respectively.
  • the first control signal terminal CN11 can also control three switch circuits to correspondingly control the disconnection of three signal channels; the second control signal terminal CN12 can also control four switch circuits to correspondingly control the disconnection of four signal channels.
  • the signal generating circuit may generate multiple original clock signals according to the clock control signal output by the timing controller in the display panel.
  • the clock control signal may include clock signals CLK in1, CLK in2,
  • the signal generating circuit can generate clock signals CLK1', CLK2', CLK3'...CLK10' according to the above-mentioned clock control signal.
  • the clock control signal may also include a cutoff signal TERMINATE, which is used to output an effective level between adjacent frames of the display panel, so that the output terminal of the signal generating circuit stops outputting clock signals CLK1', CLK2', CLK3' ...CLK10', so as to avoid signal interference between frames.
  • TERMINATE a cutoff signal
  • control circuit may also have other structures, and correspondingly, the control circuit may control the first operational amplifier circuit 22 to output other numbers of clock signals.
  • the control signal group may also include other numbers of control signals, the register may include a corresponding number of flip-flops, and each of the flip-flops may store one of the control signals.
  • FIG. 5 it is a schematic structural diagram of another exemplary embodiment of the level conversion circuit of the present disclosure.
  • the level conversion circuit can be applied to a display panel.
  • the display panel can also include a power management circuit 1.
  • the power management circuit 1 can include a first low-level output terminal LVGL, a second low-level output terminal VGL, and a high-voltage output terminal.
  • the power supply terminal of the first operational amplifier circuit 22 can be connected to the first low-level output terminal LVGL and the high-level output terminal VGH, respectively.
  • the first low-level output terminal LVGL can be used as a clock signal.
  • the low-level signal of the square wave and the high-level output terminal VGH can be used as the high-level signal of the square wave in the clock signal.
  • the first operational amplifier circuit 22 may also include a low-level output terminal LS-LVGL.
  • the voltage of the low-level output terminal LS-LVGL may be the same as the voltage of the first low-level output terminal LVGL.
  • the flat output terminal LS-LVGL can control the switching of the transistor during the driving process of the gate drive circuit.
  • the level conversion circuit may further include: a second operational amplifier circuit 26, and the second operational amplifier circuit 26 may include a second low-level output terminal LS-VGL, so
  • the power supply terminal of the second operational amplifier circuit 26 is respectively connected to the second low-level output terminal VGL and the high-level output terminal VGH, and the voltage of the low-level output terminal LS-VGL can be the same as that of the second low-level output terminal.
  • the voltage of VGL is the same, and the second low-level output terminal VGL can be used to discharge the display panel when the display panel is closed.
  • the signal generating circuit 21 may also generate an original initialization signal under the control of the timing controller, and the original initialization signal may generate an initialization signal acting on the gate driving circuit under the amplification of the first operational amplifier circuit 22.
  • the level conversion circuit may further include other registers, and other registers may configure the overcurrent and overtemperature parameters of the level conversion circuit.
  • An exemplary embodiment of the present disclosure further provides a display panel, as shown in FIG. 6, which is a schematic structural diagram of an exemplary embodiment of the display panel of the present disclosure.
  • the display panel includes the above-mentioned level conversion circuit, power management circuit 1, and timing controller 3.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

涉及显示技术领域，提出一种电平转换电路（2）、显示面板，电平转换电路（2）包括：信号生成电路（21）、第一运算放大电路（22）、多个开关电路（23）。信号生成电路（21）用于通过多个信号输出端分别输出驱动信号；第一运算放大电路（22）用于将输入端的电压进行电平转换并通过输出端输出，且信号生成电路（21）的信号输出端与第一运算放大电路（22）的输入端一一对应设置；开关电路（23）连接于相对应的信号生成电路（21）的信号输出端与第一运算放大电路（22）的输入端之间，且连接控制信号端，开关电路（23）用于响应控制信号端的信号以连通信号生成电路（21）的信号输出端和第一运算放大电路（22）的输入端；其中，至少部分开关电路（23）连接不同的控制信号端。

Description

电平转换电路、显示面板
相关申请的交叉引用
本申请要求于2020年06月18日递交的、名称为《电平转换电路、显示面板》的中国专利申请第202010557500.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，尤其涉及一种电平转换电路、显示面板。
背景技术
在显示面板中，栅极驱动电路需要在时钟信号的控制下向栅线输入栅极驱动信号。该时钟信号通常由电平转换电路根据时序控制器输出的时钟控制信号生成。
相关技术中，电平转换电路一般包括有信号生成电路和运算放大电路，信号生成电路用于根据时序控制器输出的时钟控制信号向其多个信号输出端输出原始时钟信号；运算放大电路包括多个输入端和与所述输入端一一对应的多个输出端，用于将输入端的电压进行电平转换并通过输出端输出。信号生成电路的信号输出端可以与运算放大电路的输入端一一对应连接，运算放大电路可以对原始时钟信号进行电平转换以获取时钟信号。
相关技术中，电平转换电路输出的时钟信号个数固定，然而，在显示面板中，不同结构的栅极驱动电路需要不同数量的时钟信号，因此，各种栅极驱动电路需要配置不同结构的电平转换电路，从而增加了电平转换电路的设计成本。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
根据本公开的一个方面，提供一种电平转换电路，该电平转换电路包括：信号生成电路、第一运算放大电路、多个开关电路。信号生成电路用于通过多个信号输出端分别输出驱动信号；第一运算放大电路用于将一输入端的电压进行电平转换并通过输出端输出，且信号生成电路的信号输出端与第一运算放大电路的输入端一一对应设置；开关电路连接于相对应的信号生成电路的信号输出端与第一运算放大电路的输入端之间，且连接控制信号端，开关电路用于响应控制信号端的信号以连通信号生成电路的信号输出端和所第一运算放大电路的输入端；其中，至少部分开关电路连接不同的控制信号端。
本公开一种示例性实施例中，所述电平转换电路还包括：寄存器、控制电路，寄存器用于存储控制信号组；控制电路连接所述寄存器、多个所述控制信号端，用于根 据所述控制信号组分别向多个所述控制信号端输入相应的控制信号。
本公开一种示例性实施例中，所述寄存器连接一控制信号生成电路，所述控制信号生成电路用于向所述寄存器配置所述控制信号组。
本公开一种示例性实施例中，所述开关电路用于响应高电平信号以连通所述信号生成电路的信号输出端和所第一运算放大电路的输入端；所述控制信号组包括第一控制信号和第二控制信号，多个所述控制信号端包括：第一控制信号端、第二控制信号端、第三控制信号端、第四控制信号端，所述控制电路包括：第一与门、或门、第二与门、第三与门。第一与门的第一输入端和第二输入端连接高电平信号端，输出端连接所述第一控制信号端；或门的第一输入端接收所述第一控制信号，第二输出端接收所述第二控制信号，输出端连接所述第二控制信号端；第二与门的第一输入端接收所述第一控制信号，第二输入端接收所述第一控制信号，输出端连接所述第三控制信号端；第三与门的第一输入端接收所述第一控制信号，第二输入端接收所述第二控制信号，输出端连接所述第四控制信号端。
本公开一种示例性实施例中，至少存在一个所述控制信号端连接多个所述开关电路。
本公开一种示例性实施例中，多个所述开关电路包括第一到第十开关电路；所述第一控制信号端连接所述第一到第四开关电路，所述第二控制信号端连接所述第五开关电路、第六开关电路，所述第三控制信号端连接所述第七开关电路、第八开关电路，所述第四控制信号端连接所述第九开关电路、第十开关电路。
本公开一种示例性实施例中，所述开关电路包括开关晶体管，开关晶体管的第一端连接所述所述第一运算放大电路的输入端，第二端连接所述信号生成电路的信号输出端，控制端连接所述控制信号端。
本公开一种示例性实施例中，所述电平转换电路应用于显示面板，该显示面板包括栅极驱动电路，所述第一运算放大电路的输出端用于向所述栅极驱动电路提供时钟信号。
本公开一种示例性实施例中，所述显示面板还包括时序控制器，所述信号生成电路用于在所述时序控制器控制下生成所述驱动信号，所述驱动信号为原始时钟时钟信号，所述第一运算放大电路用于对所述原始时钟信号进行电平转换以形成所述时钟信号。
本公开一种示例性实施例中，所述寄存器连接一控制信号生成电路，所述控制信号生成电路共用所述时序控制器。
本公开一种示例性实施例中，所述控制信号组包括多个控制信号，所述寄存器包括多个触发器，每个所述触发器存储有一个所述控制信号。
本公开一种示例性实施例中，所述控制信号生成电路与所述寄存器通过I2C总线连接。
本公开一种示例性实施例中，所述显示面板还包括电源管理电路，所述电源管理电路包括第一低电平输出端、高电平输出端，所述第一运算放大电路的供电端分别连接所述第一低电平输出端和高电平输出端，所述第一运算放大电路还包括第一低电平输出端。
本公开一种示例性实施例中，所述电源管理电路还包括第二低电平输出端，所述电平转换电路还包括第二运算放大电路，第二运算放大电路包括低电平输出端，所述第二运算放大电路的供电端分别连接所述第二低电平输出端和高电平输出端。
根据本公开的一个方面，提供一种显示面板，该显示面板包括上述的电平转换电路。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中一种显示面板部分结构示意图；
图2为本公开电平转换电路一种示例性实施例的结构示意图；
图3为本公开电平转换电路另一种示例性实施例的结构示意图；
图4为本公开电平转换电路一种示例性实施例中信号生成电路各节点的时序图；
图5为本公开电平转换电路另一种示例性实施例的结构示意图；
图6为本公开显示面板一种示例性实施例的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包 括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
如图1所示，为相关技术中一种显示面板部分结构示意图。该显示面板包括电源管理电路1、时序控制器3、电平转换电路2、栅极驱动电路4。栅极驱动电路4需要在时钟信号的控制下向栅线输入栅极驱动信号。电平转换电路2用于在电源管理电路1提供的电源驱动下根据时序控制器3提供的时钟控制信号向栅极驱动电路4提供上述时钟信号。如图1所示，该电平转换电路2包括信号生成电路21和运算放大电路22，信号生成电路21用于根据时序控制器3输出的时序信号向其多个信号输出端输出原始时钟信号；运算放大电路22包括多个输入端和与所述输入端一一对应的多个输出端，用于将输入端的电压进行电平转换并通过输出端输出。信号生成电路21的信号输出端可以与运算放大电路22的输入端一一对应连接，运算放大电路可以对原始时钟信号进行电平转换以向栅极驱动电路4输出时钟信号。相关技术中，电平转换电路2输出时钟信号的个数即为运算放大电路22输出输出时钟信号的个数，该相关技术中电平转换电路2输出时钟信号的个数为固定值。然而，在显示面板中，不同结构的栅极驱动电路4需要不同数量的时钟信号，因此，不同结构的栅极驱动电路需要配置不同结构的电平转换电路，从而在相关技术中，电平转换电路的设计成本较高。
基于此，本示例性实施例提供一种电平转换电路，如图2所示，为本公开电平转换电路一种示例性实施例的结构示意图。该电平转换电路可以包括：信号生成电路21、第一运算放大电路22、多个开关电路23，信号生成电路21可以包括多个信号输出端，信号生成电路21用于通过多个所述信号输出端分别输出原始时钟信号；第一运算放大电路22可以包括多个输入端，以及与多个所述输入端一一对应的多个输出端，用于将一输入端的电压进行电平转换并通过与该输入端对应的输出端输出，且所述信号生成电路21的信号输出端与所述第一运算放大电路22的输入端一一对应设置，从而第一运算放大电路22可以对信号生成电路21输出的原始时钟信号进行电平转换从而生成时钟信号；所述开关电路23可以连接于相对应的所述信号生成电路21的信号输出端与所述第一运算放大电路22的输入端之间，且连接控制信号端，所述开关电路23可以用于响应所述控制信号端的信号以连通所述信号生成电路21的信号输出端和所第一运算放大电路22的输入端；其中，至少部分所述开关电路可以连接不同的所述控制信号端，例如，如图2所示，存在不同的开关电路分别连接控制信号端CN1、CN2、CN3、CN4。
该电平转换电路可以通过控制所述开关电路的断通，从而控制第一运算放大电路与信号生成电路连通通道的数量，即控制了第一运算放大电路输出时钟信号的输出端数量，进而该电平转换电路可以匹配不同的栅极驱动电路。
如图2所示，该电平转换电路还包括包括寄存器24、控制电路25，寄存器24可以用于存储控制信号组；控制电路25可以连接所述寄存器24、多个所述控制信号端， 控制电路25可以用于根据所述控制信号组分别向多个所述控制信号端输入相应的控制信号，以控制不同开关电路的导通或关断。
应该理解的是，该电平转换电路不仅可以应用于显示面板，还可以应用于其他电子装置，同时，该电平转换电路不仅可以输出时钟信号，还可以输出其他驱动信号，相应的，该电平转换电路可以控制其他驱动信号输出的数量。
本示例性实施例中，所述寄存器24可以连接一控制信号生成电路27，所述控制信号生成电路27可以用于向所述寄存器配置所述控制信号组。该控制信号生成电路可以为电平转换电路以外的电路，例如，该控制信号生成电路可以共用显示面板中的时序控制器，显示面板在每一次开机时可以通过时序控制器向寄存器配置控制信号组。该设置可以避免电平转换电路中设置额外的存储空间以及处理单元，从而降低了电平转换电路的成本。其中，所述控制信号生成电路可以与所述寄存器通过I2C总线连接。
以下本示例性实施例提供一种控制电路根据控制信号组控制不同开关电路断通的一种实施方式。本示例性实施例中，所述开关电路23可以用于响应高电平信号以连通所述信号生成电路21的信号输出端和所第一运算放大电路22的输入端，例如，开关电路可以包括N型晶体管，N型晶体管的第一端连接所述所述第一运算放大电路的输入端，第二端连接所述信号生成电路的信号输出端，控制端连接所述控制信号端。所述寄存器可以由多个触发器组成，每个触发器可以存储一个控制信号，多个触发器存储的控制信号可以组成所述控制信号组。
如图3所示，为本公开电平转换电路另一种示例性实施例的结构示意图。本示例性实施例中，寄存器24可以为两位寄存器，即该寄存器包括有两个触发器，该两个触发器的输出端分别储存有两个控制信号：第一控制信号CN1和第二控制信号CN2。多个所述开关电路23可以包括第一到第十开关电路，第一开关电路可以包括N型晶体管T1，第二开关电路可以包括N型晶体管T2，第三开关电路可以包括N型晶体管T3，依次类推第十开关电路可以包括N型晶体管T10。上述N型开关晶体管的第一端可以连接所述所述第一运算放大电路22的输入端，第二端可以连接所述信号生成电路21的信号输出端，控制端连接所述控制信号端。信号生成电路21可以通过十个信号输出端CLK1’、CLK2’、CLK3’……CLK10’分别输出十个原始时钟信号，相应的，第一运算放大电路22可以包括十个输入端和十个输出端，第一运算放大电路22的十个输入端与信号生成电路21的十个输出端一一对应设置，其中，第一运算放大电路22可以包括十个输入端CLK1、CLK2、CLK3……CLK10。N型晶体管T1与输入端CLK1、输出端CLK1’对应连接，N型晶体管T2与输入端CLK2、输出端CLK2’对应连接，N型晶体管T3与输入端CLK3、输出端CLK3’对应连接，依次类推，N型晶体管T10与输入端CLK10、输出端CLK10’对应连接。十个开关电路可以连接四个不同的控制信号端：第一控制信号端CN11、第二控制信号端CN12、第三控制信号端CN13、第四控制信号端CN14，例如，N型晶体管T1-T4的栅极可以连接第一控制信 号端CN11，N型晶体管T5-T6的栅极可以连接第二控制信号端CN12，N型晶体管T7-T8的栅极可以连接第三控制信号端CN13，N型晶体管T9-T10的栅极可以连接第四控制信号端CN14。如图3所示，所述控制电路25可以包括：第一与门ANDG1、或门ORG、第二与门ANDG2、第三与门ANDG3。第一与门ANDG1的第一输入端和第二输入端连接高电平信号端VGH，输出端连接第一控制信号端CN11；或门ORG的第一输入端接收所述第一控制信号CN1，第二输出端接收所述第二控制信号CN2，输出端连接第二控制信号端CN12；第二与门ANDG2的第一输入端接收所述第一控制信号CN1，第二输入端接收所述第一控制信号CN1，输出端连接第三控制信号端CN13；第三与门ANDG3的第一输入端接收所述第一控制信号CN1，第二输入端接收所述第二控制信号CN2，输出端连接第四控制信号端CN14。
如图3所示，当寄存器储存的第一控制信号CN1和第二控制信号CN2分别为逻辑0、0时，N型晶体管T1、T2、T3、T4导通，N型晶体管T5、T6、T7、T8、T9、T10关断，此时，信号生成电路21的信号输出端CLK1’、CLK2’、CLK3’、CLK4’与第一运算放大电路22的输入端CLK1、CLK2、CLK3、CLK4一一对应连接，相应的，第一运算放大电路22输出四个时钟信号。当寄存器储存的第一控制信号CN1和第二控制信号CN2分别为逻辑0、1时，N型晶体管T1、T2、T3、T4、T5、T6导通，N型晶体管T7、T8、T9、T10关断，此时，信号生成电路21的信号输出端CLK1’、CLK2’、CLK3’、CLK4’、CLK5’、CLK6’与第一运算放大电路22的输入端CLK1、CLK2、CLK3、CLK4、CLK5、CLK6一一对应连接，相应的，第一运算放大电路22输出六个时钟信号。当寄存器储存的第一控制信号CN1和第二控制信号CN2分别为逻辑1、0时，N型晶体管T1、T2、T3、T4、T5、T6、T7、T8导通，N型晶体管T9、T10关断，此时，信号生成电路21的信号输出端CLK1’、CLK2’、CLK3’、CLK4’、CLK5’、CLK6’、CLK7’、CLK8’与第一运算放大电路22的输入端CLK1、CLK2、CLK3、CLK4、CLK5、CLK6、CLK7、CLK8一一对应连接，相应的，第一运算放大电路22输出八个时钟信号。当寄存器储存的第一控制信号CN1和第二控制信号CN2分别为逻辑1、1时，N型晶体管T1、T2、T3、T4、T5、T6、T7、T8、T9、T10导通，此时，信号生成电路21的信号输出端CLK1’、CLK2’、CLK3’、CLK4’、CLK5’、CLK6’、CLK7’、CLK8’、CLK9’、CLK10’与第一运算放大电路22的输入端CLK1、CLK2、CLK3、CLK4、CLK5、CLK6、CLK7、CLK8、CLK9、CLK10一一对应连接，相应的，第一运算放大电路22输出十个时钟信号。
应该理解的是，在其他示例性实施例中，信号生成电路21中信号输出端还可以为其他个数，相应的，第一运算放大电路22可以具有相同个数的输入端，开关电路的个数可以与信号生成电路21中信号输出端的个数相同。第一控制信号端CN11、第二控制信号端CN12、第三控制信号端CN13、第四控制信号端CN14还可以分别控制其他数量的开关电路。例如，第一控制信号端CN11还可以控制三个开关电路，以对应控 制三条信号通道的断通；第二控制信号端CN12还可以控制四个开关电路，以对应控制四条信号通道的断通。
如图4所示，为本公开电平转换电路一种示例性实施例中信号生成电路各节点的时序图。本示例性实施例中，信号生成电路可以根据显示面板中时序控制器输出的时钟控制信号生成多个原始时钟信号，如图4所示，该时钟控制信号可以包括时钟信号CLK in1、CLK in2，初始化信号STV in，信号生成电路可以根据上述时钟控制信号生成时钟信号CLK1’、CLK2’、CLK3’……CLK10’。此外，时钟控制信号还可以包括截止信号TERMINATE，截止信号TERMINATE用于在显示面板相邻帧之间输出有效电平，以使信号生成电路的输出端停止输出时钟信号CLK1’、CLK2’、CLK3’……CLK10’，从而避免帧与帧之间信号干扰。
应该理解的是，在其他示例性实施例中，控制电路还可以有其他的结构，相应的，控制电路可以控制第一运算放大电路22输出其他数量的时钟信号。所述控制信号组还可以包括其他数量的控制信号，所述寄存器可以包括相应数量的触发器，每个所述触发器可以存储有一个所述控制信号。
本示例性实施例中，如图5所示，为本公开电平转换电路另一种示例性实施例的结构示意图。该电平转换电路可以应用于显示面板，该显示面板还可以包括电源管理电路1，所述电源管理电路1可以包括第一低电平输出端LVGL、第二低电平输出端VGL、高电平输出端VGH，所述第一运算放大电路22的供电端可以分别连接所述第一低电平输出端LVGL和高电平输出端VGH，第一低电平输出端LVGL可以作为时钟信号中方波的低电平信号，高电平输出端VGH可以作为时钟信号中方波的高电平信号。所述第一运算放大电路22还可以包括低电平输出端LS-LVGL，该低电平输出端LS-LVGL的电压可以与第一低电平输出端LVGL的电压相同，该第一低电平输出端LS-LVGL可以在栅极驱动电路驱动过程中控制晶体管的开关。
本示例性实施例中，如图5所示，所述电平转换电路还可以包括：第二运算放大电路26，第二运算放大电路26可以包括第二低电平输出端LS-VGL，所述第二运算放大电路26的供电端分别连接所述第二低电平输出端VGL和高电平输出端VGH，该低电平输出端LS-VGL的电压可以与第二低电平输出端VGL的电压相同，该第二低电平输出端VGL可以用于在显示面板关闭时给显示面板放电。
本示例性实施例中，信号生成电路21还可以在时序控制器控制下生成原始初始化信号，该原始初始化信号可以在第一运算放大电路22放大作用下生成作用于栅极驱动电路的初始化信号。
本示例性实施例中，该电平转换电路还可以包括其他寄存器，其他寄存器可以对该电平转换电路的过流、过温参数进行配置。
本公开的一示例性实施例还提供一种显示面板，如图6所示，为本公开显示面板一种示例性实施例的结构示意图。该显示面板包括上述的电平转换电路以及电源管理 电路1、时序控制器3。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (15)

  1. 一种电平转换电路，其中，包括：
    信号生成电路，包括多个信号输出端，用于通过多个所述信号输出端分别输出驱动信号；
    第一运算放大电路，包括多个输入端和与所述输入端一一对应的多个输出端，用于将一输入端的电压进行电平转换并通过与该输入端对应的输出端输出，且所述信号生成电路的信号输出端与所述第一运算放大电路的输入端一一对应设置；
    多个开关电路，所述开关电路连接于相对应的所述信号生成电路的信号输出端与所述第一运算放大电路的输入端之间，且连接控制信号端，所述开关电路用于响应所述控制信号端的信号以连通所述信号生成电路的信号输出端和所第一运算放大电路的输入端；
    其中，至少部分所述开关电路连接不同的所述控制信号端。
  2. 根据权利要求1所述的电平转换电路，其中，所述电平转换电路还包括：
    寄存器，用于存储控制信号组；
    控制电路，连接所述寄存器、多个所述控制信号端，用于根据所述控制信号组分别向多个所述控制信号端输入相应的控制信号。
  3. 根据权利要求2所述的电平转换电路，其中，所述寄存器连接一控制信号生成电路，所述控制信号生成电路用于向所述寄存器配置所述控制信号组。
  4. 根据权利要求3所述的电平转换电路，其中，所述电平转换电路应用于显示面板，所述显示面板还包括时序控制器，所述控制信号生成电路共用所述时序控制器。
  5. 根据权利要求2所述的电平转换电路，其中，所述开关电路用于响应高电平信号以连通所述信号生成电路的信号输出端和所第一运算放大电路的输入端；
    所述控制信号组包括第一控制信号和第二控制信号，多个所述控制信号端包括：第一控制信号端、第二控制信号端、第三控制信号端、第四控制信号端，所述控制电路包括：
    第一与门，第一输入端和第二输入端连接高电平信号端，输出端连接所述第一控制信号端；
    或门，第一输入端接收所述第一控制信号，第二输出端接收所述第二控制信号，输出端连接所述第二控制信号端；
    第二与门，第一输入端接收所述第一控制信号，第二输入端接收所述第一控制信号，输出端连接所述第三控制信号端；
    第三与门，第一输入端接收所述第一控制信号，第二输入端接收所述第二控制信号，输出端连接所述第四控制信号端。
  6. 根据权利要求1所述的电平转换电路，其中，至少存在一个所述控制信号端连接多个所述开关电路。
  7. 根据权利要求5所述的电平转换电路，其中，多个所述开关电路包括第一到第十开关电路；
    所述第一控制信号端连接所述第一到第四开关电路，所述第二控制信号端连接所述第五开关电路、第六开关电路，所述第三控制信号端连接所述第七开关电路、第八开关电路，所述第四控制信号端连接所述第九开关电路、第十开关电路。
  8. 根据权利要求1所述的电平转换电路，其中，所述开关电路包括：
    开关晶体管，第一端连接所述所述第一运算放大电路的输入端，第二端连接所述信号生成电路的信号输出端，控制端连接所述控制信号端。
  9. 根据权利要求1所述的电平转换电路，其中，所述电平转换电路应用于显示面板，该显示面板包括栅极驱动电路，所述第一运算放大电路的输出端用于向所述栅极驱动电路提供时钟信号。
  10. 根据权利要求9所述的电平转换电路，其中，所述显示面板还包括时序控制器，所述信号生成电路用于在所述时序控制器控制下生成所述驱动信号，所述驱动信号包括原始时钟时钟信号，所述第一运算放大电路用于对所述原始时钟信号进行电平转换以形成所述时钟信号。
  11. 根据权利要求2所述的电平转换电路，其中，所述控制信号组包括多个控制信号，所述寄存器包括多个触发器，每个所述触发器存储有一个所述控制信号。
  12. 根据权利要求3所述的电平转换电路，其中，所述控制信号生成电路与所述寄存器通过I2C总线连接。
  13. 根据权利要求1所述的电平转换电路，其中，所述电平转换电路应用于显示面板，所述显示面板还包括电源管理电路，所述电源管理电路包括第一低电平输出端、高电平输出端，所述第一运算放大电路的供电端分别连接所述第一低电平输出端和高电平输出端，所述第一运算放大电路还包括第一低电平输出端。
  14. 根据权利要求13所述的电平转换电路，其中，所述电源管理电路还包括第二低电平输出端，所述电平转换电路还包括：
    第二运算放大电路，包括第二低电平输出端，所述第二运算放大电路的供电端分别连接所述第二低电平输出端和高电平输出端。
  15. 一种显示面板，其中，包括权利要求1-14任一项所述的电平转换电路。
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