WO2023019561A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2023019561A1
WO2023019561A1 PCT/CN2021/113810 CN2021113810W WO2023019561A1 WO 2023019561 A1 WO2023019561 A1 WO 2023019561A1 CN 2021113810 W CN2021113810 W CN 2021113810W WO 2023019561 A1 WO2023019561 A1 WO 2023019561A1
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Prior art keywords
output
signal
voltage
terminal
node
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PCT/CN2021/113810
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English (en)
French (fr)
Inventor
青海刚
肖云升
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to CN202180002238.6A priority Critical patent/CN115997249A/zh
Priority to PCT/CN2021/113810 priority patent/WO2023019561A1/zh
Publication of WO2023019561A1 publication Critical patent/WO2023019561A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements

Definitions

  • Embodiments of the present disclosure relate to a shift register and its driving method, a gate driving circuit, and a display device.
  • the gate-driver circuit substrate (Gate-driver on Array, GOA) technology is to directly integrate the gate-driver circuit on the array substrate of the display device through a photolithography process.
  • the GOA circuit usually includes multiple cascaded shift registers, each The shift registers correspond to gate lines corresponding to a row of pixels (for example, each shift register provides a scan driving signal to a gate line connected to a row of pixels), so as to realize scan driving of the display panel.
  • GOA technology can save the space of the bonding (Bonding) area and fan-out (Fan-out) area of the gate integrated circuit (Integrated Circuit, IC), so as to realize the narrow border of the display panel, reduce product cost, and improve product efficiency. yield.
  • At least one embodiment of the present disclosure provides a shift register, including: an input circuit, a first control circuit, a second control circuit and an output circuit, wherein the input circuit is respectively connected to the input voltage terminal, the first clock signal terminal and the The first node is electrically connected, configured to input the input voltage provided by the input voltage terminal to the first node under the control of the first clock signal provided by the first clock signal terminal; the first control a circuit, respectively electrically connected to the first clock signal terminal, the second clock signal terminal, the first node and the first output node, and configured to provide the first clock signal, the voltage of the first node and Under the control of the second clock signal provided by the second clock signal terminal, the first control signal is output to the first output node; the second control circuit is connected with the first node and the second clock respectively.
  • the signal terminal is electrically connected to the second output node, and is configured to output a second control signal to the second output node under the control of the voltage of the first node; the output circuit is respectively connected to the first The voltage terminal, the second voltage terminal, the first output node, the second output node and the first output terminal are electrically connected, configured to be controlled by the first control signal and the second control signal, Writing the first voltage signal provided by the first voltage terminal or the second voltage signal provided by the second voltage terminal into the first output terminal as the first output signal.
  • the first control circuit is configured to control the output circuit to output the first voltage signal in the first stage;
  • the second control circuit is configured to It is configured to control the output circuit to output the second voltage signal in the second stage, and the first output signal includes the first voltage signal in the first stage and the voltage signal in the second stage second voltage signal.
  • the output circuit is further configured to, under the control of the first control signal and the second control signal, in the second stage, writing a third voltage signal into the first output terminal, wherein the first output signal further includes a third voltage signal, and the absolute voltage value of the third voltage signal is smaller than the absolute voltage value of the second voltage signal .
  • the first control circuit includes a first control input subcircuit, and the first control input subcircuit is connected to the first clock signal terminal and the second clock signal terminal respectively.
  • the nodes are electrically connected and configured to write a third control signal into the second node under the control of the first clock signal.
  • the first control circuit is further electrically connected to the first voltage terminal and the input circuit
  • the second control input sub-circuit is respectively connected to the The input circuit, the second clock signal terminal, the first voltage terminal and the second node are electrically connected, and are configured to, under the control of the input voltage and the second clock signal, turn the first voltage terminal A voltage signal is written into the second node.
  • the first control circuit includes a first bootstrap subcircuit, a first control output subcircuit and a second control output subcircuit, and the first bootstrap The sub-circuits are respectively electrically connected to the second node, the third node and the second clock signal terminal, and are configured to write a first intermediate signal into the first clock signal terminal under the control of the voltage of the second node.
  • the first control output subcircuit is electrically connected to the second clock signal terminal, the third node and the first output node respectively, and is configured to be controlled by the second clock signal , writing the second intermediate signal determined based on the first intermediate signal into the first output node;
  • the second control output sub-circuit is connected with the first node, the first voltage terminal and the first output node respectively
  • An output node is electrically connected and configured to write the first voltage signal into the first output node under the control of the voltage of the first node, wherein the first control signal includes the first two intermediate signals and the first voltage signal.
  • the input circuit includes an input terminal connected to the input voltage terminal and an output terminal connected to the first node, and the second control input subcircuit It is electrically connected to the output end of the input circuit, or the second control input sub-circuit is electrically connected to the input end of the input circuit.
  • the first control input subcircuit includes a first pull-down transistor, and the first pole of the first pull-down transistor is connected to the first clock signal terminal The second pole of the first pull-down transistor is electrically connected to the second node, and the gate of the first pull-down transistor is electrically connected to the first clock signal terminal.
  • the second control input subcircuit includes a first pull-up transistor and a second pull-up transistor, the first pole of the first pull-up transistor is connected to the The second pole of the second pull-up transistor is electrically connected, the second pole of the first pull-up transistor is electrically connected to the second node, and the gate of the first pull-up transistor is connected to the second clock signal
  • the gate of the second pull-up transistor is electrically connected to the input terminal of the input circuit or the output terminal of the input circuit, and the first pole of the second pull-up transistor is connected to the first voltage electrical connection.
  • the first bootstrap subcircuit includes a first capacitor and a first bootstrap transistor, and the gate of the first bootstrap transistor is electrically connected to the The second node and the first end of the first capacitor, the second pole of the first bootstrap transistor is electrically connected to the second end of the first capacitor and the third node, the first bootstrap The first pole of the transistor is electrically connected to the second clock signal terminal; the first control output sub-circuit includes a first control output transistor, and the gate of the first control output transistor is electrically connected to the second clock signal terminal.
  • the circuit includes a second control output transistor, the gate of the second control output transistor is electrically connected to the first node, the first pole of the second control output transistor is electrically connected to the first voltage terminal, the The second pole of the second control output transistor is electrically connected to the first output node.
  • the first control circuit further includes a holding subcircuit, and the holding subcircuit is respectively connected to the first voltage terminal, the first node, and the The first output node is electrically connected and configured to maintain the level of the first node in the first phase.
  • the holding subcircuit includes a holding transistor, the first pole of the holding transistor is electrically connected to the first voltage terminal, and the second electrode of the holding transistor The pole is electrically connected to the first node, and the gate of the holding transistor is electrically connected to the first output node.
  • the first control circuit is further electrically connected to the second voltage terminal, the first control circuit further includes a first isolation subcircuit, and the first The input terminal of an isolation subcircuit is electrically connected to the second node, the output terminal of the first isolation subcircuit is electrically connected to the first bootstrap subcircuit, and the control terminal of the first isolation subcircuit is connected to the The second voltage terminal is electrically connected.
  • the first isolation subcircuit includes a first isolation transistor, the first pole of the first isolation transistor is electrically connected to the second node, and the The second pole of the first isolation transistor is electrically connected to the first bootstrap sub-circuit, and the gate of the first isolation transistor is electrically connected to the second voltage terminal.
  • the first control circuit further includes a storage subcircuit, and the storage subcircuit is electrically connected to the first voltage terminal and the first output node respectively. , and configured to store the voltage of the first output node.
  • the storage subcircuit includes a storage capacitor, the first terminal of the storage capacitor is electrically connected to the first voltage terminal, and the second terminal of the storage capacitor is electrically connected to the first voltage terminal.
  • the first output node is electrically connected.
  • the second control circuit includes a second bootstrap subcircuit, and the second bootstrap subcircuit is connected to the first node, the second The clock signal terminal is electrically connected to the second output node.
  • the second bootstrap subcircuit includes a second capacitor and a second bootstrap transistor, and the first pole of the second bootstrap transistor is connected to the first pole of the second bootstrap transistor.
  • the two clock signal terminals are electrically connected, the first end of the second capacitor is electrically connected to the gate of the second bootstrap transistor and the second output node, and the second end of the second capacitor is connected to the second output node.
  • the second poles of the two bootstrap transistors are electrically connected.
  • the second control circuit further includes a second isolation subcircuit, the input terminal of the second isolation subcircuit is electrically connected to the first node, so The output terminal of the second isolation subcircuit is electrically connected to the second output node, and the control terminal of the second isolation subcircuit is electrically connected to the second voltage terminal.
  • the second isolation subcircuit includes a second isolation transistor, the first pole of the second isolation transistor is electrically connected to the first node, and the The second pole of the second isolation transistor is electrically connected to the second output node, and the gate of the second isolation transistor is electrically connected to the second voltage terminal.
  • the output circuit includes a first output subcircuit and a second output subcircuit, and the first output subcircuit is connected to the first output node, the The first voltage terminal is electrically connected to the first output terminal, and is configured to write the first voltage signal into the first output terminal in the first stage under the control of the first control signal terminal; the second output sub-circuit is electrically connected to the second output node, the second voltage terminal and the first output terminal respectively, and is configured to, under the control of the second control signal, The second stage writes the second voltage signal into the first output terminal.
  • the first output subcircuit includes a first output transistor, the gate of the first output transistor is electrically connected to the first output node, and the The first pole of the first output transistor is electrically connected to the first voltage terminal, and the second pole of the first output transistor is electrically connected to the first output terminal;
  • the second output sub-circuit includes a second output transistor , the gate of the second output transistor is electrically connected to the second output node, the first pole of the second output transistor is electrically connected to the second voltage terminal, and the second pole of the second output transistor Electrically connected to the first output end.
  • the shift register further includes an output inverting circuit, and the output inverting circuit is respectively connected to the first output node, the first voltage terminal, The second voltage terminal, the first output terminal and the second output terminal are electrically connected, and are configured to invert the first output signal to obtain a second output signal, and convert the second output signal output to the second output terminal.
  • the output inversion circuit includes a first output inversion subcircuit, a second output inversion subcircuit and an output inversion control subcircuit, and the output inversion
  • the phase control subcircuit is electrically connected to the first voltage terminal, the first output node, the second voltage terminal and the fourth node, and is configured to Under the control of the signal, output the fourth control signal to the fourth node
  • the first output inverting sub-circuit is electrically connected to the first voltage terminal, the first output terminal and the second output terminal respectively , and is configured to write the first voltage signal into the second output terminal in the second stage under the control of the first output signal
  • the second output inverting subcircuit is respectively connected with the The second voltage terminal, the fourth node and the second output terminal are electrically connected, and are configured to write the second voltage signal in the first stage under the control of the fourth control signal input to the second output terminal, the second output signal includes the second voltage signal at the first stage and the first voltage signal at the second stage.
  • the output inversion control subcircuit includes a pull-up subcircuit, a pull-down subcircuit and a third bootstrap subcircuit, and the pull-up subcircuit is respectively connected to the The first voltage terminal, the first output terminal and the fourth node are electrically connected, and are configured to write the first voltage signal into the fourth node under the control of the first output signal ;
  • the pull-down sub-circuit is electrically connected to the first output node, the second voltage terminal and the fourth node, and is configured to, under the control of the first control signal, based on the first
  • the third intermediate signal determined by the two voltage signals is written into the fourth node;
  • the third bootstrap sub-circuit is electrically connected to the fourth node and the first clock signal terminal respectively, and is configured to be connected to the fourth node. Under the control of the voltages of the four nodes, the fourth intermediate signal determined based on the third intermediate signal and the first clock signal is written into the fourth node, wherein the fourth
  • the first output inversion subcircuit includes a first output inversion transistor
  • the second output inversion subcircuit includes a second output inversion transistor
  • the gate of the first output inverting transistor is electrically connected to the first output terminal
  • the first pole of the first output inverting transistor is electrically connected to the first voltage terminal
  • the first output is inverting
  • the second pole of the transistor is electrically connected to the second output terminal
  • the gate of the second output inverting transistor is electrically connected to the fourth node
  • the first pole of the second output inverting transistor is electrically connected to the The second voltage end is electrically connected
  • the second pole of the second output inverting transistor is electrically connected to the second output end.
  • the pull-up subcircuit includes a third pull-up transistor, the gate of the third pull-up transistor is electrically connected to the first output terminal, so The first pole of the third pull-up transistor is electrically connected to the first voltage terminal, and the second pole of the third pull-up transistor is electrically connected to the fourth node;
  • the pull-down sub-circuit includes a second pull-down transistor , the gate of the second pull-down transistor is electrically connected to the first output node, the first pole of the second pull-down transistor is electrically connected to the second voltage terminal, and the second pole of the second pull-down transistor Electrically connected to the fourth node;
  • the third bootstrap sub-circuit includes a third capacitor and a third bootstrap transistor, the first terminal of the third capacitor and the gate of the third bootstrap transistor are electrically connected connected to the fourth node, the second pole of the third bootstrap transistor is electrically connected to the second end of the third capacitor, the first pole of the third bootstrap transistor is electrically
  • the input circuit includes an input transistor, the first pole of the input transistor is electrically connected to the input voltage terminal, and the second pole of the input transistor is electrically connected to the input voltage terminal.
  • the first node is electrically connected, and the gate of the input transistor is electrically connected to the first clock signal terminal.
  • At least one embodiment of the present disclosure further provides a gate driving circuit, including the shift register described in any embodiment of the present disclosure.
  • the gate drive circuit includes a plurality of shift registers cascaded, wherein, in addition to the shift register of the first stage, the Mth stage The first output terminal of the shift register is used as an input voltage terminal connected to the M+1th shift register, where M is a positive integer and M is greater than 1.
  • the gate driving circuit provided in at least one embodiment of the present disclosure further includes a signal generating circuit, wherein the signal generating circuit is configured to generate a first signal and a second signal, and the first signal is applied to the 2Nth -the first clock signal end connected to the 1st stage shift register and the second clock signal end connected to the 2N stage shift register; the second signal is applied to the 2N-1 stage shift register connected The second clock signal terminal of the first clock signal terminal connected to the 2Nth stage shift register; wherein, N is a positive integer, and N is greater than or equal to 1.
  • At least one embodiment of the present disclosure further provides a display device including the gate driving circuit according to any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides a shift register driving method, which is used to drive the shift register according to any embodiment of the present disclosure
  • the output circuit outputs the first voltage signal in the first stage, and outputting the second voltage signal in a second stage
  • the second stage includes an input stage and a stabilization stage
  • the driving method includes: in the input stage, inputting the input voltage to the first node; In the first stage, under the control of the first control signal, output the first voltage signal to the first output terminal; in the stable stage, under the control of the second control signal , outputting the second voltage signal to the first output terminal.
  • the second stage further includes a buffering stage
  • the driving method further includes: in the buffering stage, under the control of the second control signal, A third voltage signal is output to the first output terminal, wherein the first output signal further includes the third voltage signal, and the absolute voltage value of the third voltage signal is smaller than the absolute voltage value of the second voltage signal value.
  • the pulse width of the input voltage at the first level is greater than the Periods of the first clock signal and the second clock signal.
  • FIG. 1A is a schematic structural diagram of a shift register circuit
  • FIG. 1B is a driving timing diagram corresponding to the shift register circuit shown in FIG. 1A;
  • FIG. 2A is a schematic block diagram of a shift register provided by at least one embodiment of the present disclosure.
  • Fig. 2B is a schematic block diagram of another shift register provided by at least one embodiment of the present disclosure.
  • FIG. 3A is a schematic structural diagram of a shift register provided by at least one embodiment of the present disclosure.
  • Fig. 3B is a schematic structural diagram of another shift register provided by at least one embodiment of the present disclosure
  • FIG. 3C is a schematic structural diagram of another shift register provided by at least one embodiment of the present disclosure.
  • FIG. 3D is a schematic structural diagram of another shift register provided by at least one embodiment of the present disclosure.
  • FIG. 4A is a driving timing diagram of a shift register provided by at least one embodiment of the present disclosure.
  • FIG. 4B is a driving timing diagram of another shift register provided by at least one embodiment of the present disclosure.
  • FIG. 5A is a schematic block diagram of another shift register provided by at least one embodiment of the present disclosure.
  • FIG. 5B is a schematic structural diagram of another shift register provided by at least one embodiment of the present disclosure.
  • FIG. 5C is a driving timing diagram of another shift register provided by at least one embodiment of the present disclosure.
  • FIG. 5D is a schematic block diagram of another shift register provided by at least one embodiment of the present disclosure.
  • Fig. 6 is a schematic block diagram of a gate driving circuit provided by at least one embodiment of the present disclosure.
  • FIG. 7A is a schematic structural diagram of a gate drive circuit provided by at least one embodiment of the present disclosure.
  • FIG. 7B is a schematic structural diagram of another gate driving circuit provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • Fig. 9 is a flowchart of a driving method provided by at least one embodiment of the present disclosure.
  • the existing shift register circuits integrated on the display panel can generally realize the following functions: use N-type transistors to realize shift output of high-level pulse signals, and use P-type transistors to realize shift output of low-level pulse signals.
  • FIG. 1A is a schematic structural diagram of a shift register circuit constructed based on P-type transistors
  • FIG. 1B is a driving timing diagram corresponding to the shift register circuit shown in FIG. 1A .
  • the shift register circuit can output a low-level signal.
  • the first signal terminal GCK is a low-level signal
  • the second signal terminal GCB is a high-level signal
  • the transistor T1 is turned on
  • the input signal terminal GSTV inputs a low-level signal through the transistor T1
  • the signal is stored in the capacitor C2, so that the transistor T7 is turned on.
  • the second signal terminal GCB is a low-level signal
  • the first signal terminal GCK is a high-level signal
  • the low-level signal of the second signal terminal GCB (for example, it can be connected with the low-level The level signal VL is equal) is output to the output terminal Output, that is, the output terminal Output outputs a low level signal.
  • the signals of the input signal terminal GSTV are all at high level
  • the first signal terminal GCK turns on the transistor T3 every half cycle
  • the low-level signal VL is written into the capacitor through the transistor T3 In C1
  • the transistor T6 and the transistor T8 remain normally open
  • the high-level signal VGH is written into the capacitor C2 through the transistor T6 and the transistor T5 , so that the transistor T7 is turned off.
  • the high-level signal VGH is output to the output terminal Output through the transistor T8, that is, the output terminal Output outputs the high-level signal VGH.
  • P-type transistor technology is generally used to implement all backplane circuits, and gate drive circuits (eg, GOA circuits) often need to output high-level pulse signals. That is to say, it is necessary to use P-type transistors to construct a shift register circuit that outputs a high-level pulse signal.
  • the key difficulty is that the initial signal at the input signal terminal is a high level, which cannot make the transistor T7 turn on in advance like the shift register in Figure 1A, and the transistors that build the circuit are all P-type transistors, P A type transistor needs a low level to turn on, which makes it impossible to realize the shift function of the level opposite to the turn-on level of the transistor using existing ideas.
  • the shift register includes an input circuit, a first control circuit, a second control circuit and an output circuit, wherein the input circuit is electrically connected to the input voltage terminal, the first clock signal terminal and the first node respectively, and is configured to be connected at the first Under the control of the first clock signal provided by the clock signal end, the input voltage provided by the input voltage end is input to the first node; the first control circuit is respectively connected with the first clock signal end, the second clock signal end, the first node and The first output node is electrically connected and configured to output the first control signal to the first output node under the control of the first clock signal, the voltage of the first node and the second clock signal provided by the second clock signal terminal; the second The control circuit is electrically connected to the first node, the second clock signal terminal and the second output node respectively, and is configured to output a second control signal to the second output node under the control of the voltage of the first no
  • the shift register controls the output circuit to output a level opposite to the turn-on level of the transistor through the first control circuit and the second control circuit, for example, when the transistor is a P-type transistor, a high level signal is output.
  • the shift register circuit can realize that the P-type transistor outputs a low-level signal without threshold value loss, thereby improving the display quality of the display panel; on the other hand, the shift register has a simple structure and low production cost.
  • a transistor refers to an element including at least a gate electrode, a drain electrode and a source electrode.
  • a transistor has a channel between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel, and the source electrode.
  • the channel refers to the part of the active layer corresponding to the orthographic projection of the gate of the transistor on the active layer, that is, the region where the current mainly flows.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • the two poles of the transistor except the gate it is directly described that one of them is the first pole and the other is the second pole, so the first pole of all or part of the transistors in the embodiments of the present disclosure and second pole are interchangeable as required.
  • the first pole of the transistor described in the embodiments of the present disclosure may be the source, and the second pole may be the drain; or, the first pole of the transistor may be the drain, and the second pole may be the source.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on level is a low level, that is, the turn-on voltage is a low-level voltage (for example, 0V, -5V or other values)
  • the turn-off level is a high level, that is, the turn-off voltage is a high level.
  • the turn-on level is a high level, that is, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other values)
  • the turn-off power Level is a low level, that is, the off voltage is a low level voltage (for example, 0V, -5V or other values).
  • a P-type transistor for example, a thin film transistor transmits a low-level signal and has a threshold loss
  • a signal at a low level is transmitted from the first pole of the P-type transistor to the second pole of the P-type transistor
  • the P-type transistor transmits a high-level signal without threshold loss, when a signal at a high level is transmitted from the first pole of the P-type transistor to the second pole of the P-type transistor, the second pole of the P-type transistor There is no voltage difference between the voltage and the voltage of the first pole of the P-type transistor. That is to say, in the present disclosure, after the low-level signal is “transmitted” through the P-type transistor, threshold voltage loss will occur, and after the high-level signal is “transmitted” through the P-type transistor, the voltage remains unchanged.
  • the type of the transistor is an N-type transistor
  • the N-type transistor transmits a high-level signal and has a threshold loss, which will not be repeated here.
  • Fig. 2A is a schematic block diagram of a shift register provided by at least one embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a shift register.
  • the shift register includes an input circuit 100 , a first control circuit 200 , a second control circuit 300 and an output circuit 400 .
  • the input circuit 100 is electrically connected to the input voltage terminal ESTV, the first clock signal terminal ECK and the first node n1 respectively, and is configured to be connected to the first clock signal VECK provided by the first clock signal terminal ECK.
  • the input voltage Vin provided by the input voltage terminal ESTV is input to the first node n1. That is to say, under the control of the first clock signal VECK, when the input circuit 100 is turned on, that is, when one end of the input circuit 100 connected to the input voltage end ESTV and the other end connected to the first node n1 are turned on, the input voltage Vin may be transmitted to the first node n1.
  • the first control circuit 200 is electrically connected to the first clock signal terminal ECK, the second clock signal terminal ECB, the first node n1, and the first output node OP1 respectively, and is configured to be connected between the first clock signal VECK and the first node n1 Under the control of the voltage and the second clock signal VECB provided by the second clock signal terminal ECB, the first control signal Vctr1 is output to the first output node OP1, and the first control signal Vctr1 is configured to realize the first voltage terminal VGH and the first output The conduction and cutoff between the terminals Eout.
  • the second control circuit 300 is electrically connected to the first node n1, the second clock signal terminal ECB and the second output node OP2 respectively, and is configured to output the second control signal Vctr2 to The second output node OP2, the second control signal Vctr2 is configured to realize the conduction and cut-off between the second voltage terminal VGL and the first output terminal Eout.
  • the output circuit is electrically connected to the first voltage terminal VGH, the second voltage terminal VGL, the first output node OP1, the second output node OP2 and the first output terminal Eout respectively, and is configured to be controlled by the first control signal Vctr1 and the second control signal Vctr1. Under the control of the signal Vctr2, the first voltage signal VH provided by the first voltage terminal VGH or the second voltage signal VL provided by the second voltage terminal VGL is written into the first output terminal Eout as the first output signal Vout.
  • the first control circuit 200 is configured to control the output circuit 400 to output the first voltage signal VH as the first output signal Vout in the first stage.
  • the second control circuit 300 is configured to control the output circuit 400 to output the second voltage signal VL as the first output signal Vout in the second stage. That is, the first output signal Vout includes the first voltage signal VH in the first stage and the second voltage signal VL in the second stage.
  • the first control circuit 200 is also electrically connected to the first voltage terminal VGH and the input circuit 100 .
  • the first control circuit 200 includes a first control input subcircuit 201, a second control input subcircuit 202, a first bootstrap subcircuit 203, a first control output subcircuit 204, a second control output subcircuit 205 and a holding subcircuit circuit 206.
  • the first control input sub-circuit 201 is electrically connected to the first clock signal terminal ECK and the second node n2 respectively, and is configured to write the third control signal Vctr3 into the second node under the control of the first clock signal VECK n2.
  • the first control input subcircuit 201 is turned on, that is, when one end of the first control input subcircuit 201 connected to the first signal terminal ECK and one end of the first control input subcircuit 201 connected to the second node n2
  • the first clock signal VECK at the second level is written into the second node n2 as the third control signal Vctr3 , so that the voltage of the second node n2 is at the second level.
  • the second control input sub-circuit 202 is electrically connected to the input circuit 100, the second clock signal terminal ECB, the first voltage terminal VGH and the second node n2 respectively, and is configured to be controlled by the input voltage Vin and the second clock signal VECB , write the first voltage signal VH into the second node n2.
  • the second control input sub-circuit 202 is turned on, that is, when one end of the second control input sub-circuit 202 connected to the first voltage terminal VGH and one end of the second control input sub-circuit 202 connected to the second node n2
  • the first voltage signal VH is written into the second node n2, so that the voltage of the second node n2 is at the first level.
  • the first level and the second level are different, eg opposite to each other.
  • the first level is a high level
  • the second level is a low level.
  • the present disclosure is not limited thereto. According to actual application requirements, the first level may be a low level, and the second level may be a high level. In the description of the present disclosure, it is taken as an example that the first level is a high level and the second level is a low level.
  • the first voltage terminal VGH may be a high voltage terminal to output a first voltage signal VH with a first level
  • the second voltage terminal VGL may be a low voltage terminal to output a second voltage signal VL with a second level. That is, the first voltage signal VH is a high-level signal (such as 5V, 10V or other voltages), and the second voltage signal VL is a low-level signal (such as 0V, ⁇ 1V or other voltages).
  • the second voltage terminal VGL may be grounded.
  • both the first voltage signal VH and the second voltage signal VL are DC signals.
  • the low-level signal and the high-level signal are relative terms, and the voltage value of the low-level signal is smaller than the voltage value of the high-level signal.
  • the voltage value of the high-level signal may be different, and the voltage value of the low-level signal may also be different.
  • the first control circuit 200 may not be connected to the first voltage terminal VGH, but may be connected to another voltage terminal, as long as the other voltage terminal outputs a high voltage signal.
  • the high voltage signal output from the additionally provided voltage terminal and the high voltage signal output from the first voltage terminal VGH may be the same or different.
  • the first control circuit 200 may not be connected to the first voltage terminal VGH, but may be connected to another voltage terminal, as long as the other voltage terminal outputs a high voltage signal.
  • the high voltage signal output from the additionally provided voltage terminal and the high voltage signal output from the first voltage terminal VGH may be the same or different.
  • the input circuit 100 includes an input terminal connected to the input voltage terminal ESTV and an output terminal connected to the first node n1, and the second control input sub-circuit 202 may be electrically connected to the output terminal of the input circuit 100, that is, to the first node n1 is electrically connected, or, the second control input sub-circuit 202 may be electrically connected to the input end of the input circuit 100 , that is, to be electrically connected to the input voltage end ESVT.
  • the first bootstrap sub-circuit 203 is respectively electrically connected to the second node n2, the third node n3 and the second clock signal terminal ECB, and is configured to write the first intermediate signal into the second clock signal terminal under the control of the third control signal Vctr3.
  • the first bootstrap sub-circuit 203 is in an off state, and the voltage of the third node n3 remains unchanged.
  • the first bootstrap sub-circuit 203 is in conduction On state, that is, when one end of the first bootstrap subcircuit 203 connected to the second clock signal terminal ECB and the other end of the first bootstrap subcircuit 203 connected to the third node n3 are turned on, the second clock signal VECB is transmitted to the third node n3.
  • the first bootstrap subcircuit 203 produces a bootstrap effect, so that the level of the second node n2 changes with the level of the third node n3, that is, the level of the second node n2 also jumps, and the level of the second node n2 level is lower than the second level (for example, at this time, the level of the second node n2 is (2*first level-second level)), thus, the second clock signal VECB at the second level
  • the output can be bootstrapped via the first bootstrap sub-circuit 203 and written into the third node n3 as the first intermediate signal. That is, the first intermediate signal is the second clock signal VECB at the second level.
  • the first control output sub-circuit 204 is electrically connected to the second clock signal terminal ECB, the third node n3 and the first output node OP1 respectively, and is configured to determine based on the first intermediate signal under the control of the second clock signal VECB
  • the second intermediate signal Vmid2 is written into the first output node OP1.
  • the first control output sub-circuit 204 is turned on under the control of the second clock signal VECB, that is, when one end connected to the third node n3 and the other end connected to the first output node OP1 are turned on, based on the first
  • a second intermediate signal Vmid2 determined by an intermediate signal is written into the first output node OP1, and the second intermediate signal Vmid2 is also at the second level.
  • the absolute value of the voltage of the second intermediate signal Vmid2 is smaller than the absolute value of the voltage of the first intermediate signal, and the absolute value of the signal difference between the first intermediate signal and the second intermediate signal Vmid2 is the same as the transistor in the first control output sub-circuit 204
  • the absolute values of the threshold voltages are equal.
  • the second control output sub-circuit 205 is respectively electrically connected to the first node n1, the first voltage terminal VGH and the first output node OP1, and is configured to write the first voltage signal VH under the control of the voltage of the first node n1 into the first output node OP1.
  • the second control output sub-circuit 205 is turned on under the control of the voltage of the first node n1, that is, the end of the second control output sub-circuit 205 connected to the first voltage terminal VGH is connected to the first output node
  • the other end of OP1 is turned on, the first voltage signal VH is written into the first output node OP1.
  • the first control signal includes the second intermediate signal Vmid2 and the first voltage signal VH.
  • the first control signal is the second intermediate signal Vmid2, that is, at the second level, and the output circuit 400 realizes the first voltage terminal VGH and the first output terminal under the control of the second intermediate signal Vmid2.
  • the connection between Eout is turned on to output the first voltage signal VH to the first output terminal Eout; in the second stage, the first control signal is the first voltage signal VH, that is, at the first level, and the output circuit 400 is in Under the control of the first voltage signal VH, the connection between the first voltage terminal VGH and the first output terminal Eout is disconnected, so as to avoid outputting the first voltage signal VH to the first output terminal Eout in the second stage.
  • the holding sub-circuit 206 is electrically connected to the first voltage terminal VGH, the first node n1 and the first output node OP1 respectively, and is configured to maintain the level of the first node in the first stage.
  • the second control signal Vctr2 is a signal of the first level
  • the second output sub-circuit 402 is turned off under the control of the second control signal Vctr2.
  • the holding sub-circuit 206 is turned on under the voltage control of the first output node OP1, that is, one end of the holding sub-circuit 206 connected to the first voltage terminal VGH and the other end of the holding sub-circuit 206 connected to the first node n1 One end is turned on, and the first voltage signal VH is written into the first node n1 to control the voltage of the first node n1 to always be at the first level in the first stage, thereby maintaining the second control signal Vctr2 at the first level in the first stage. level, avoid circuit fluctuations, and maintain output stability.
  • the second control circuit 300 includes a second bootstrap sub-circuit 301, and the second bootstrap sub-circuit 301 is electrically connected to the first node n1, the second clock signal terminal ECB and the second output node n2 respectively. , and is configured to control the voltage of the second output node OP2 under the control of the voltage of the first node n1.
  • the voltage of the second output node OP2 may be lower than the voltage when the second clock signal VECB is at the second level.
  • the second control signal Vctr2 includes a first level signal, a second level signal, and a third level signal obtained based on the second clock signal VECB at the second level.
  • the first level signal is the input voltage Vin at the first level, for example, the voltage value of the first level signal is the same as the voltage value of the first voltage signal VH, and the voltage value of the first level signal is greater than that of the second level signal.
  • the voltage value of the flat signal, the second level signal is obtained based on the input voltage Vin at the second level, for example, the voltage value of the input voltage Vin at the second level is the same as the voltage value of the second voltage signal VL,
  • the absolute voltage value of the second level signal is smaller than the voltage absolute value of the third level signal.
  • the output circuit 400 includes a first output sub-circuit 401 and a second output sub-circuit 402 .
  • the first output sub-circuit 401 is electrically connected to the first output node n1, the first voltage terminal VGH and the first output terminal Eout respectively, and is configured to, under the control of the first control signal Vctr1, convert the first A voltage signal VH is written into the first output terminal Eout.
  • the first output subcircuit 401 is turned on under the control of the first control signal Vctr1, that is, one terminal of the first output subcircuit 401 connected to the first voltage terminal VGH and connected to the first output terminal
  • the other end of the first output sub-circuit 401 of Eout is turned on, the first voltage signal VH is written into the first output end Eout, and at this time, the second output sub-circuit 402 is turned off under the control of the second control signal Vctr2.
  • the second output sub-circuit 402 is electrically connected to the second output node OP2, the second voltage terminal VGL and the first output terminal Eou respectively, and is configured to, under the control of the second control signal Vctr2, convert the second voltage to The signal VL is written into the first output terminal Eout.
  • the second output subcircuit 402 is turned on under the control of the second control signal Vctr2, that is, one terminal of the second output subcircuit 402 connected to the second voltage terminal VGL and connected to the first output terminal
  • Vctr2 the second control signal
  • the other end of the second output sub-circuit 402 of Eout is turned on, the second voltage signal VL is written into the first output end Eout, and at this time, the first output sub-circuit 401 is turned off under the control of the first control signal Vctr1.
  • the first output signal further includes a third voltage signal
  • the output circuit 400 is further configured to, under the control of the first control signal Vctr1 and the second control signal Vctr2 , in the second stage, based on the second voltage signal VL obtained
  • the third voltage signal VL1 is written into the first output terminal Eout, for example, the absolute value of the voltage of the third voltage signal VL1 is smaller than the absolute value of the voltage of the second voltage signal VL.
  • the second output sub-circuit 402 may write the third voltage signal VL1 obtained based on the second voltage signal VL into the first output terminal Eout.
  • the absolute value of the signal difference between the second voltage signal VL and the third voltage signal VL1 is equal to the absolute value of the threshold voltage of a transistor in the second output sub-circuit 402 (such as the second output transistor T10 to be described later).
  • the absolute value of the voltage of the third level signal included in the second control signal Vctr2 is greater than the absolute value of the voltage of the second voltage signal VL, so that the second output sub-circuit 402 can output the second voltage signal VL without threshold voltage loss. to the first output terminal Eout.
  • the first output signal Vout includes the third voltage signal VL1 and the second voltage signal VL, and finally the first output signal Vout remains in the state of the second voltage signal VL.
  • Fig. 2B is a schematic block diagram of another shift register provided by at least one embodiment of the present disclosure.
  • the shift register includes an input circuit 100, a first control circuit 200, a second control circuit 300 and an output circuit 400, and, compared to the shift register shown in Figure 2A, the shift register
  • the first control circuit 200 further includes a storage sub-circuit 207 and a first isolation sub-circuit 208
  • the second control circuit 200 further includes a second isolation sub-circuit 302 .
  • the rest of the sub-circuits of the shift register shown in FIG. 2B are the same as those of the shift register shown in FIG. 2A , and repeated descriptions are omitted.
  • the storage sub-circuit 207 is electrically connected to the first voltage terminal VGH and the first output node OP1 respectively, and is configured to store the voltage of the first output node OP1.
  • the first control circuit 200 is also electrically connected to the second voltage terminal VGL, the input end of the first isolation sub-circuit 208 is electrically connected to the second node n2, and the output end of the first isolation sub-circuit 208 is electrically connected to the first bootstrap sub-circuit 203 is electrically connected, and the control terminal of the first isolation sub-circuit 208 is electrically connected to the second voltage terminal VGL.
  • the first isolation sub-circuit 208 is in the conduction state, that is, one end of the first isolation sub-circuit 208 connected to the second node n2 and the first isolation sub-circuit connected to the first bootstrap sub-circuit 203 The other end of the circuit 208 is turned on.
  • the second An isolation sub-circuit 208 switches from the on state to the off state, thereby preventing the voltage of the second node n2 from fluctuating and affecting the transistors in the second control input sub-circuit 202 (such as the first pull-up transistor T2 described below ) performance.
  • the first control circuit 200 may not be connected to the second voltage terminal VGL, but be connected to another voltage terminal, as long as the other voltage terminal outputs a low voltage signal.
  • the low voltage signal output by the additionally provided voltage terminal and the low voltage signal output by the second voltage terminal VGL may be the same or different.
  • the second control circuit further includes a second isolation subcircuit 302, the input terminal of the second isolation subcircuit 302 is electrically connected to the first node n1, and the output terminal of the second isolation subcircuit 302 is connected to the second bootstrap subcircuit 301 and The second output node OP2 is electrically connected, and the control terminal of the second isolation sub-circuit 302 is electrically connected to the second voltage terminal VGL.
  • the second isolation sub-circuit 302 is in the conduction state, that is, one end of the second isolation sub-circuit 302 connected to the first node n1 and the second isolation sub-circuit connected to the second bootstrap sub-circuit 301 The other end of the circuit 302 is turned on.
  • the second isolation connected to the second bootstrap sub-circuit 301 When the voltage of the second bootstrap sub-circuit 301 fluctuates, for example, due to the bootstrap effect of the second bootstrap sub-circuit 301, the second isolation connected to the second bootstrap sub-circuit 301 The voltage at one end of the sub-circuit 302 will suddenly drop, and at this time the second isolation sub-circuit 302 is switched from the on state to the off state, thereby preventing the voltage of the first node n1 from fluctuating accordingly and avoiding abnormal output.
  • the second control input sub-circuit 202 when the second control input sub-circuit 202 is connected to the first node n1, if the voltage of the first node n1 drops following the voltage change of the second output node OP2, the second control input sub-circuit 202 may be turned on, resulting in The output is abnormal.
  • all transistors are P-type transistors.
  • FIG. 3A is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure.
  • the circuit structure diagram shown in FIG. 3A is a specific example of the schematic block diagram of the shift register shown in FIG. 2A .
  • the first control input sub-circuit 201 includes a first pull-down transistor T3, the first pole of the first pull-down transistor T3 is electrically connected to the first clock signal terminal ECK, and the second pole of the first pull-down transistor T3 The pole is electrically connected to the second node n2, and the gate of the first pull-down transistor T3 is electrically connected to the first clock signal terminal ECK.
  • the second control input sub-circuit 202 includes a first pull-up transistor T2 and a second pull-up transistor T5, the first pole of the first pull-up transistor T2 is electrically connected to the second pole of the second pull-up transistor T5, and the first pull-up transistor T5
  • the second pole of the transistor T2 is electrically connected to the second node n2
  • the gate of the first pull-up transistor T2 is electrically connected to the second clock signal terminal ECB
  • the first pole of the second pull-up transistor T5 is electrically connected to the first voltage terminal VGH.
  • the gate of the second pull-up transistor T5 is electrically connected to the output terminal of the input circuit 100, that is, is electrically connected to the first node n1.
  • the first bootstrap sub-circuit 203 includes a first capacitor C1 and a first bootstrap transistor T6, the gate of the first bootstrap transistor T6 is electrically connected to the second node n2 and the first end of the first capacitor C1, the first bootstrap The second terminal of the transistor T6 is electrically connected to the second terminal of the first capacitor C1 and the third node n3, and the first terminal of the first bootstrap transistor T6 is electrically connected to the second clock signal terminal ECB.
  • the first control output sub-circuit 204 includes a first control output transistor T7, the gate of the first control output transistor T7 is electrically connected to the second clock signal terminal ECB, and the first electrode of the first control output transistor T7 is electrically connected to the third node n3. connected, the second pole of the first control output transistor T7 is electrically connected to the first output node OP1.
  • the second control output sub-circuit 205 includes a second control output transistor T8, the gate of the second control output transistor T8 is electrically connected to the first node n1, and the first pole of the second control output transistor T8 is electrically connected to the first voltage terminal VGH , the second pole of the second control output transistor T8 is electrically connected to the first output node OP1.
  • the holding sub-circuit 206 includes a holding transistor T4, the first electrode of the holding transistor T4 is electrically connected to the first voltage terminal VGH, the second electrode of the holding transistor T4 is electrically connected to the first node n1, and the gate of the holding transistor T4 is connected to the first output Node OP1 is electrically connected.
  • the storage sub-circuit 207 includes a storage capacitor C3, the first terminal of the storage capacitor C3 is electrically connected to the first voltage terminal VGH, and the second terminal of the storage capacitor C3 is electrically connected to the first output node OP1.
  • the second bootstrap sub-circuit 301 includes a second capacitor C2 and a second bootstrap transistor T13, the first pole of the second bootstrap transistor T13 is electrically connected to the second clock signal terminal ECB, and the first terminal of the second capacitor C2 is electrically connected to To the gate of the second bootstrap transistor T13 and the second output node OP2, the second end of the second capacitor C2 is electrically connected to the second pole of the second bootstrap transistor T13.
  • the first output sub-circuit 401 includes a first output transistor T9, the gate of the first output transistor T9 is electrically connected to the first output node OP1, the first pole of the first output transistor T9 is electrically connected to the first voltage terminal VGH, and the first The second pole of the output transistor T9 is electrically connected to the first output terminal Eout.
  • the second output sub-circuit 402 includes a second output transistor T10, the gate of the second output transistor T10 is electrically connected to the second output node OP2, the first pole of the second output transistor T10 is electrically connected to the second voltage terminal VGL, and the second The second pole of the output transistor T10 is electrically connected to the first output terminal Eout.
  • the input circuit 100 is used to transmit the input voltage Vin to the first node n1 to trigger the shift register to work.
  • the input circuit 100 includes an input transistor T1.
  • the first pole of the input transistor T1 is electrically connected to the input voltage terminal ESTV
  • the second pole of the input transistor T1 is electrically connected to the first node n1
  • the gate of the input transistor T1 is electrically connected to the first clock signal terminal ECK.
  • FIG. 3B is a schematic structural diagram of another shift register provided by an embodiment of the present disclosure.
  • the circuit structure diagram shown in FIG. 3B is a specific example of the schematic block diagram of the shift register shown in FIG. 2B .
  • the shift register shown in FIG. 2B further includes a first isolation sub-circuit 208 and a second isolation sub-circuit 302 .
  • the first isolation sub-circuit 208 includes a first isolation transistor T12, the first pole of the first isolation transistor T12 is electrically connected to the second node n2, and the gate of the first isolation transistor T12 is connected to the second voltage
  • the terminal VGL is electrically connected
  • the second pole of the first isolation transistor T12 is electrically connected to the first bootstrap sub-circuit 203.
  • the second pole of the first isolation transistor T12 is electrically connected to the first bootstrap transistor T6.
  • the grid is electrically connected.
  • the second isolation sub-circuit 302 includes a second isolation transistor T11, the first pole of the second isolation transistor T11 is electrically connected to the first node n1, the second pole of the second isolation transistor T11 is electrically connected to the second output node OP2, and the second The gate of the isolation transistor T11 is electrically connected to the second voltage terminal VGL.
  • FIG. 3C is a schematic structural diagram of another shift register provided by an embodiment of the present disclosure.
  • the circuit structure diagram shown in FIG. 3C is another specific example of the schematic block diagram of the shift register shown in FIG. 2B .
  • the difference between the circuit structure diagrams shown in Figure 3B and Figure 3C is that: the gate of the second pull-up transistor T5 of the shift register shown in Figure 3B is electrically connected to the first node n1, and the shift register shown in Figure 3C The gate of the second pull-up transistor T5 is electrically connected to the input voltage terminal ESTV.
  • the connection relationship between other circuit structures refer to the description of the structure of the shift register shown in FIG. 3A and FIG. 3B , which will not be repeated here.
  • the input voltage Vin can directly control the turn-on and cut-off of the second pull-up transistor T5, so that the second pull-up transistor T5 can be activated before the input stage.
  • the early cut-off is controlled by the high level of the input voltage Vin.
  • the input circuit 100, the first control circuit 200, the second control circuit 300, and the output circuit 400 shown in FIG. 3A, FIG. 3B, and FIG. 3C are only an example of an embodiment of the present disclosure. Examples include, but are not limited to, the situations shown in Figures 3A, 3B and 3C.
  • the high level of the first clock signal VECK and the second clock signal VECB is the same as the level of the first voltage signal VH
  • the low level of the first clock signal VECK and the second clock signal VECB is the same as the level of the second voltage signal VL same level.
  • the high level of the first clock signal VECK and the second clock signal VECB may also be different from the level of the first voltage signal VH, and the low level of the first clock signal VECK and the second clock signal VECB may also be different from the level of the first voltage signal VH. It may be different from the level of the second voltage signal VL, as long as the first clock signal VECK and the second clock signal VECB can perform their own functions, which is not limited in the present disclosure.
  • the high levels of the first clock signal VECK and the second clock signal VECB are equal to the level of the first voltage signal VH, and the low levels of the first clock signal VECK and the second clock signal VECB are equal to those of the first voltage signal VH.
  • the level of the second voltage signal VL is the same as an example to describe the shift register provided by the present disclosure.
  • Fig. 3D is a schematic structural diagram of another shift register provided by at least one embodiment of the present disclosure.
  • the circuit structure diagram shown in FIG. 3D is another specific example of the schematic block diagram of the shift register shown in FIG. 2A .
  • the difference between the circuit structure diagrams shown in FIG. 3D and FIG. 3A is that the gate of the second pull-up transistor T5 of the shift register shown in FIG. 3A is electrically connected to the first node n1, and the shift register shown in FIG. 3D
  • the gate of the second pull-up transistor T5 is electrically connected to the input voltage terminal ESTV.
  • connection relationship between other circuit structures refer to the description of the structure of the shift register shown in FIG. 3A , which will not be repeated here.
  • FIG. 4A is a driving sequence diagram of a shift register provided by an embodiment of the present disclosure. The following uses the shift register shown in FIG. 3B and the driving sequence shown in FIG. 4A as examples to introduce the working principle of the shift register provided by the embodiment of the present disclosure.
  • the working process of the shift register includes an input stage A, a first stage B, a buffer stage C and a stabilization stage D, wherein the input stage A, the buffer stage C and the stabilization stage D belongs to the second stage.
  • the high-level input voltage Vin, the high-level first clock signal VECK, and the high-level second clock signal VECB are all equal to the first voltage signal VH
  • the low-level input voltage Vin, the low-level first clock signal VECK, and the low-level second clock signal VECB are all equal to the second voltage signal VL.
  • Vout represents the first output signal
  • Vn3 represents the voltage of the third node n3
  • Vctr1 represents the first control signal
  • Vctr2 represents the second control signal.
  • the first isolation transistor T12 is in the normally-on state under the control of the second voltage signal VL
  • the second isolation transistor T11 is also in the normally-on state under the control of the second voltage signal VL.
  • the input voltage Vin is input to the first node n1.
  • the first clock signal VECK output from the first clock signal terminal ECK is a low-level signal
  • the second clock signal VECB output from the second clock signal terminal ECB is high Level signal
  • the input voltage Vin output from the input voltage terminal ESTV is a high level signal.
  • the input transistor T1 Since the first clock signal VECK is a low-level signal, the input transistor T1 is turned on, the input voltage Vin (high-level signal) is transmitted to the first node n1 through the input transistor T1, and the second isolation transistor T11 is also turned on, so that the input The voltage Vin is also transmitted to the second output node OP2 via the second isolation transistor T11 , so that both the first node n1 and the second output node OP2 are at a high level.
  • the second control signal Vctr2 includes a first level signal, and the first level signal is the voltage of the second output node OP2 in the input phase A, that is, the input voltage Vin, because the input voltage Vin and the voltage of the first voltage signal VH at this time are equal, that is, the first level signal is the first voltage signal VH, that is, the second control signal Vctr2 is the first voltage signal VH.
  • the second pull-up transistor T5, the second control output transistor T8, the second output transistor T10, and the second bootstrap transistor T13 are all in an off state. Since the second clock signal VECB is a high-level signal, both the first pull-up transistor T2 and the first output control transistor T7 are in an off state under the control of the high-level of the second clock signal VECB.
  • the first pull-down transistor T3 is in the conduction state under the control of the low level of the first clock signal VECK, and the low level of the first clock signal VECK is transmitted to the second node n2 through the first pull-down transistor T3, so that The second node n2 is at a low level.
  • the voltage of the second node n2 is VECK1-Vth3, wherein, Vth3 represents the threshold voltage of the first pull-down transistor T3, and VECK1 is the first pull-down transistor T3 at a low level.
  • a clock signal VECK, VECK1 VL, that is, the voltage of the second node n2 is VL-Vth3. Since the first isolation transistor T12 is turned on, the voltage of the second node n2 is transmitted to the gate of the first bootstrap transistor T6 through the first isolation transistor T12 , so that the gate of the first bootstrap transistor T6 is also at a low level.
  • the threshold voltage of the first isolation transistor T12 is expressed as Vth12.
  • the gate voltage of the first bootstrap transistor T6 is VL-VthN, wherein, VthN is the smaller threshold voltage of Vth3 and Vth12.
  • the voltage VL-VthN received by the gate of the first bootstrap transistor T6 can control the first bootstrap transistor T6 to turn on, and the high level signal of the second clock signal VECB is written into the third node n3 through the first bootstrap transistor T6 , so that the third node n3 is at a high level.
  • the voltage Vn3 of the third node n3 in the input stage A is the second clock signal VECB of high level, that is, the first voltage signal VH.
  • the voltage of the first output node OP1 remains unchanged, and the first control signal Vctr1 is a high-level signal, that is, the gate of the first output transistor T9
  • the voltage remains unchanged from the previous stage, and is still at a high level, so the first output terminal Eout remains unchanged from the previous stage, and the first output signal Vout is still a low-level signal.
  • the first voltage signal VH is output to the first output terminal Eout.
  • the first clock signal VECK output from the first clock signal terminal ECK is a high-level signal
  • the second clock signal VECB output from the second clock signal terminal ECB is Low-level signal
  • the input voltage Vin output from the input voltage terminal ESTV is a low-level signal.
  • the input transistor T1 is turned off, and the voltages of the first node n1 and the second output node OP2 remain unchanged, that is, the voltage of the first node n1 and the voltage of the second output node OP2 are still equal to The first voltage signal VH.
  • the second control signal Vctr2 is still the first level signal, and the second pull-up transistor T5, the second control output transistor T8, the second output transistor T10, and the second bootstrap transistor T13 are all connected between the first node n1 and the second The second output node OP2 is still in the cut-off state under high-level control.
  • the first pull-down transistor T3 is in the cut-off state, although the first pull-up transistor T2 is in the turn-on state under the control of the second clock signal VECB, but because the second pull-up transistor T5 In the cut-off state, the voltage of the second node n2 remains unchanged, that is, the voltage of the second node n2 is still VL-Vth3.
  • the first bootstrap transistor T6 is still on, and the low-level signal of the second clock signal VECB (that is, the second voltage signal VL) is written into the third node n3 through the first bootstrap transistor T6, so that the voltage of the third node n3 Vn3 jumps from high level to low level.
  • the voltage of the gate of the first bootstrap transistor T6 also jumps, and the first bootstrap transistor T6
  • the voltage of the gate of the VL-VthN- ⁇ V jumps to VL-VthN- ⁇ V, where ⁇ V represents the potential difference from a high level to a low level, and VL-VthN- ⁇ V is smaller than VL-VthN, so that the gate of the first bootstrap transistor T6
  • the voltage of the pole becomes lower, so that the first bootstrap transistor T6 can be turned on better, so that the low-level second clock signal VECB can be transmitted to the third node n3 without threshold loss, that is, the third node at this time
  • the voltage of n3 is the second low-level clock signal VECB, that is, the second voltage signal VL
  • the low-level second clock signal VECB is the first intermediate signal, that is, the first intermediate
  • the first control output transistor T7 is turned on under the control of the low-level signal of the second clock signal VECB, and writes the second intermediate signal Vmid2 determined based on the first intermediate signal into the first output node OP1. Since the first control output transistor T7 transmits a low-level signal with a threshold loss, the voltage of the second intermediate signal Vmid2 is VL-Vth7, where Vth7 represents the threshold voltage of the first control output transistor T7, that is, in the first stage B , the voltage of the first output node OP1 is VL-Vth7, and the first control signal Vctr1 is the second intermediate signal Vmid2, that is, VL-Vth7.
  • the first control signal Vctr1 is the second intermediate signal Vmid2, and the second intermediate signal Vmid2 is a low-level signal, so in the first stage B, under the control of the first control signal Vctr1 (that is, the second intermediate signal Vmid2), the first output The transistor T9 and the holding transistor T4 are turned on, and the first voltage signal VH is written into the first output terminal Eout through the first output transistor T9 to complete the high-level output.
  • the first output signal Vout is the first voltage signal VH; the first The voltage signal VH is written into the first node n1 through the holding transistor T4 to maintain the high level of the first node, so as to prevent the second pull-up transistor T5 from being mistakenly turned on in the first phase B.
  • the third voltage signal VL1 obtained based on the second voltage signal VL is output to the first output terminal Eout.
  • the first clock signal VECK output from the first clock signal terminal ECK is a low-level signal
  • the second clock signal VECB output from the second clock signal terminal ECB is high Level signal
  • the input voltage Vin output from the input voltage terminal ESTV is a low level signal.
  • the first pull-down transistor T3 is in the conduction state under the control of the low level of the first clock signal VECK, and the low-level first clock signal VECK is transmitted to the second node n2 through the first pull-down transistor T3, so that the second node n2 remains at a low level, and at the same time, since the first isolation transistor T12 is turned on, the voltage of the second node n2 is transferred to the gate of the first bootstrap transistor T6 through the first isolation transistor T12, so that the first bootstrap transistor T6
  • the gate is also at a low level, so that the first bootstrap transistor T6 is in an on state, and the high level of the second clock signal VECB is written into the third node n3, so that the third node n3 is at a high level, that is, the third The voltage Vn3 of the node n3 is the high level second clock signal VECB.
  • the first control output transistor T7 is in the cut-off state under the control of the high level of the second clock signal VECB, and the input transistor T1 is turned on under the control of the low level of the first clock signal VECK, and the low-level input voltage Vin is passed through
  • the input transistor T1 is transmitted to the first node n1, so that the first node n1 is at a low level
  • the second control output transistor T8 is turned on under the control of the voltage of the first node n1, and the first voltage signal VH is output through the second control
  • the transistor T8 transmits to the first output node OP1, and charges the storage capacitor C3 so that the first output node OP1 is at a high level, that is, the first control signal Vctr1 is the first voltage signal VH at this time
  • the transistors T4 are all in a cut-off state under the control of the first control signal Vctr1.
  • the input transistor T1 Since the first clock signal VECK is a low-level signal, the input transistor T1 is turned on, and the low-level VL of the input voltage Vin is transmitted to the first node n1 through the input transistor T1, and the second isolation transistor T11 is also turned on, so that the input voltage Vin Vin is also transmitted to the second output node OP2 via the second isolation transistor T11 , so that both the first node n1 and the second output node OP2 are at low level. Since the input transistor T1 transmits a low-level signal and has a threshold loss, the voltage of the first node n1 is Vin-Vth1, that is, VL-Vth1, wherein Vth1 represents the threshold voltage of the input transistor T1.
  • the threshold voltage of the second isolation transistor T11 is expressed as Vth11.
  • the voltage of the second output node OP2 is VL-VthM, where VthM is Vth1 and The one with the smaller threshold voltage among Vth11.
  • the second control signal Vctr2 includes a second level signal (VL2 as shown in FIG. 4A ), and the second level signal VL2 is the voltage of the second output node OP2 in the input phase C, that is, VL-VthM, that is, FIG. 4A
  • the level of VL2 is shown as VL-VthM.
  • the second pull-up transistor T5 , the second control output transistor T8 , the second output transistor T10 , and the second bootstrap transistor T13 are all in a conduction state. Both the first pull-up transistor T2 and the first output control transistor T7 are turned off under the control of the high level of the second clock signal VECB.
  • the second output transistor T10 is in the conduction state under the control of the low level of the second control signal Vctr2 (that is, the second level signal VL2), and the second voltage signal VL is transmitted to the second output transistor T10 through the second output transistor T10.
  • An output terminal Eout because the second output transistor T10 transmits a low-level signal and has a threshold loss, the second voltage signal VL cannot be completely output to the first output terminal Eout, at this time, the first output terminal Eout is the third voltage signal VL1, the voltage of the third voltage signal VL1 is VL-Vth10-VthM, wherein Vth10 represents the threshold voltage of the second output transistor T10.
  • the second voltage signal VL is output to the first output terminal Eout, so that the final first output signal Vout decreases from the third voltage signal VL1 to the second voltage signal VL.
  • the first clock signal VECK output from the first clock signal terminal ECK is a high-level signal
  • the second clock signal VECB output from the second clock signal terminal ECB is low Level signal
  • the input voltage Vin output from the input voltage terminal ESTV is a low level signal.
  • the input transistor T1 is turned off, the voltages of the first node n1 and the second output node OP2 maintain the low level of the buffer stage C, and the second pull-up transistor T5 and the second control
  • the output transistor T8 is turned on under the low level control of the first node n1
  • the second output transistor T10 and the second bootstrap transistor T13 are turned on under the low level control of the second output node OP2.
  • the first pull-up transistor T2 is also in the conduction state under the low level control of the second clock signal VECB, and the first voltage signal VH is transmitted to the second node n2 through the first pull-up transistor T2 and the second pull-up transistor T5,
  • the second node n2 is at a high level, and the voltage of the second node n2 is transmitted to the gate of the first bootstrap transistor T6 through the first isolation transistor T12, so that the first bootstrap transistor T6 is in an off state, and the first control output transistor T7 is also in the conduction state under the control of the low level of the second clock signal VECB.
  • the first voltage signal VH is transmitted to the first output node OP1 through the second control output transistor T8, and charges the storage capacitor C3 so that the first output node OP1 maintains a high level.
  • the first control signal Vctr1 is the first voltage signal VH
  • the first output transistor T9 and the holding transistor T4 are both in the cut-off state under the control of the first control signal Vctr1.
  • the second bootstrap transistor T13 Since the second bootstrap transistor T13 is in the on state and the input transistor T1 and the holding transistor T4 are in the off state, the voltage of the second output node OP2 is only affected by the second capacitor C2. From the buffer phase C to the stabilization phase D, the second clock signal VECB produces a voltage transition from high level to low level, and since the second bootstrap transistor T13 is turned on, the voltage at the second terminal of the second capacitor C2 is also A jump from high level to low level is generated, and under the coupling effect of the second capacitor C2, the voltage at the first end of the second capacitor C2, that is, the second output node OP2, jumps, so that the second output The voltage of the node OP2 drops even lower, and under the control of the voltage of the second output node OP2, the second bootstrap transistor T13 is fully turned on, so that the low-level second clock signal VECB can pass through the second bootstrap transistor T13 without any delay.
  • Threshold loss is transmitted to the second end of the second capacitor C2. It can be seen that the voltage at the second end of the second capacitor C2 jumps from the high level second clock signal VECB (that is, the first voltage signal VH) to For the low-level second clock signal VECB (second voltage signal VL), the voltage difference of the voltage jump is VH-VL.
  • the second control signal Vctr2 is a third-level signal (that is, VL3 shown in FIG. 4A ), and the voltage of the second output node OP2 jumps from the second-level signal VL2 to the third-level signal VL3.
  • the voltage of the three-level signal VL3 is (VL-VthM- ⁇ V), that is, the level of VL3 shown in FIG. 4A is (VL-VthM- ⁇ V), the third level signal VL3 and the second level signal VL2
  • the absolute value difference of the voltage between is the voltage difference of the voltage jump.
  • the second output transistor T10 can be turned on better, so that the second voltage signal VL can be output to the first output terminal Eout without threshold loss, at this time , the first output signal Vout can reach the second voltage signal VL.
  • the voltage of the first node n1 maintains a low level, so the second pull-up transistor T8 is always in an on state, thereby maintaining the high level of the first output node OP1,
  • the first output transistor T9 is always in the cut-off state; in addition, under the control of the second clock signal VECB, the voltage of the second output node OP2 is periodically pulled down, that is, the second control signal Vctr2 is periodically at the second voltage
  • the signal VL2 and the third voltage signal VL3 vary, so as to ensure that the first output signal Vout maintains the second voltage signal VL at a low level, and the entire circuit continues to maintain the output state of the stable stage D, and the subsequent stages will not be repeated.
  • the first control signal Vctr1 includes the voltage of the first output node OP1 in each phase (namely, the input phase A, the first phase B, the buffer phase C and the stabilization phase D),
  • the second control signal Vctr2 includes the voltage of the second output node OP2 at various stages.
  • FIG. 4B is a driving timing diagram of a shift register provided by another embodiment of the present disclosure, and the driving timing diagram is used to drive the shift register shown in FIG. 3C . That is to say, when the second control input sub-circuit 202 is electrically connected to the input terminal of the input circuit 100 , that is, is electrically connected to the input voltage terminal ESTV, the driving timing diagram shown in FIG. 4B needs to be adopted. At this time, it is required that the pulse width of the input voltage Vin at the first level (for example, high level) is greater than the period of the first clock signal VECK and the period of the second clock signal VECB.
  • the first level for example, high level
  • the period of the first clock signal VECK is the same as that of the second clock signal VECB, and the pulse width of the input voltage Vin at a high level is greater than the period of the first clock signal VECK and the period of the second clock signal VECB.
  • the circuit function of the shift register corresponding to the driving timing diagram shown in Figure 4B is exactly the same as the shift register shown in Figure 3A and Figure 3B, as shown in Figure 4B, the working process of the shift register also includes the input stage A, The first stage B, the buffer stage C and the stabilization stage D, regarding the input stage A, the buffer stage C and the stabilization stage D, its circuit operation is exactly the same as the preceding process, and will not be repeated here; regarding the first stage B, in the first stage The first control signal Vctr1 generated by B is still a low-level signal, and the second control signal Vctr1 is still a high-level signal, so that the first output terminal can be controlled to output the first voltage signal VH.
  • the specific circuit operation process is similar to the foregoing, I won't go into details here.
  • FIG. 5A is a schematic block diagram of a shift register provided by at least one embodiment of the present disclosure.
  • the shift register further includes an output inversion circuit 500, and the output inversion circuit 500 is connected to the first output node OP1, the first voltage terminal VGH, and the first output node OP1, respectively.
  • the two voltage terminals VGL, the first output terminal Eout and the second output terminal REout are electrically connected, and are configured to invert the first output signal Vout to obtain a second output signal Rout, and output the second output signal Rout to the first Two output terminals REout.
  • an output inverting circuit 500 can also be added on the basis of the shift register shown in FIG. 2A to obtain a second output signal Rout that is inverse to the first output signal Vout. The specific connection relationship will not be repeated here. .
  • the output inversion circuit includes a first output inversion subcircuit 501 , a second output inversion subcircuit 502 and an output inversion control subcircuit 503 .
  • the output inversion control sub-circuit 503 is electrically connected to the first voltage terminal VGH, the first output node OP1, the second voltage terminal VGL and the fourth node n4 respectively, and is configured to be controlled by the first control signal Vctr1, the first output signal Vout Under the control of , the fourth control signal Vctr4 is output to the fourth node n4, and the fourth control signal Vctr4 is used to control the on and off between the second voltage terminal VGL and the second output terminal REout.
  • the first output inverting sub-circuit 501 is electrically connected to the first voltage terminal VGH, the first output terminal Eout and the second output terminal REout respectively, and is configured to convert the first output terminal REout in the second stage under the control of the first output signal Vout A voltage signal VH is written into the second output terminal REout.
  • the first output inverting sub-circuit 501 is turned on under the control of the first output signal Vout, that is, one terminal of the first output inverting sub-circuit 501 connected to the first voltage terminal VGH and connected to The other end of the first output inverting subcircuit 501 of the second output terminal REout is turned on, and the first voltage signal VH is written into the second output terminal REout, and at this time, the second output inverting subcircuit 502 is controlled by the fourth control signal Cutoff under the control of Vctr4.
  • the second output inverting sub-circuit 502 is respectively electrically connected to the second voltage terminal VGL, the fourth node n4 and the second output terminal REout, and is configured to convert the second The voltage signal VL is written into the second output terminal REout.
  • the second output inverting sub-circuit 502 is turned on under the control of the fourth control signal Vctr4, that is, one terminal of the second output inverting sub-circuit 502 connected to the second voltage terminal VGL and connected to The other end of the second output inverting subcircuit 502 of the second output terminal REout is turned on, the second voltage signal VL is written into the second output terminal REout, and at this time, the first output inverting subcircuit 501 Cutoff under the control of Vout.
  • the second output signal Rout includes the second voltage signal VL in the first stage and the first voltage signal VH in the second stage.
  • the output inversion control sub-circuit 503 includes a pull-up sub-circuit 5031 , a second pull-down sub-circuit 5032 and a third bootstrap sub-circuit 5033 .
  • the pull-up sub-circuit 5031 is electrically connected to the first voltage terminal VGH, the first output terminal Eout and the fourth node n4 respectively, and is configured to write the first voltage signal VH into the fourth node under the control of the first output signal Vout. Node n4.
  • the pull-up sub-circuit 5031 is turned on under the control of the first output signal Vout, that is, one end of the pull-up sub-circuit 5031 connected to the first voltage terminal VGH and the pull-up sub-circuit connected to the fourth node n4
  • the first voltage signal VH is written into the fourth node n4, so that the fourth node n4 is at a high level.
  • the pull-down sub-circuit 5032 is electrically connected to the first output node OP1, the second voltage terminal VGL and the fourth node n4 respectively, and is configured to, under the control of the first control signal Vctr1, set the third voltage determined based on the second voltage signal VL
  • the intermediate signal Vmid3 is written into the fourth node n4.
  • the pull-down sub-circuit 5032 when the pull-down sub-circuit 5032 is turned on under the control of the first control signal Vctr1, that is, one end of the pull-down sub-circuit 5032 connected to the second voltage terminal VGL and the other end of the pull-down sub-circuit 5032 connected to the fourth node n4 When one terminal is turned on, the third intermediate signal Vmid3 determined based on the second voltage signal VL is written into the fourth node n4, so that the fourth node n4 is at a low level.
  • the third bootstrap sub-circuit 5033 is electrically connected to the fourth node n4 and the first clock signal terminal ECK respectively, and is configured to determine the The fourth intermediate signal Vmid4 is written into the fourth node n4.
  • the voltage Vn4 of the fourth node n4 may be lower than the voltage when the second clock signal VECK is at a low level, and the fourth The absolute value of the voltage of the intermediate signal Vmid4 is greater than the absolute value of the voltage of the third intermediate signal Vmid3.
  • the fourth control signal includes a first voltage signal, a third intermediate signal Vmid3 and a fourth intermediate signal Vmid4.
  • FIG. 5B is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure.
  • the shift register is based on the shift register shown in Figure 3C on the basis of an increase of the output inverting circuit 500, therefore, the structure of the input circuit 100, the first control circuit 200, the second control circuit 300 and the output circuit 400
  • the relevant structural descriptions of the schematic structural diagrams shown in FIG. 3A to FIG. 3C which will not be repeated here.
  • the shift register including the output inverting circuit 500 is not limited to the structure shown in FIG. 5B , and the input circuit 100, the first control circuit 200, the second control circuit 300 and the output circuit 400 can be implemented with reference to the present disclosure. Examples are modified and combined, and this disclosure is not limited thereto.
  • the output inverting circuit 500 may also be added on the basis of the shift register, which is not limited in the present disclosure.
  • the first output inverting sub-circuit 501 includes a first output inverting transistor T17
  • the second output inverting sub-circuit 502 includes a second output inverting transistor T16.
  • the gate of the first output inverting transistor T17 is electrically connected to the first output terminal Eout, the first pole of the first output inverting transistor T17 is electrically connected to the first voltage terminal VGH, and the second pole of the first output inverting transistor T17 It is electrically connected with the second output terminal REout.
  • the gate of the second output inverting transistor T16 is electrically connected to the fourth node n4, the first pole of the second output inverting transistor T16 is electrically connected to the second voltage terminal VGL, and the second pole of the second output inverting transistor T16 is electrically connected to the second voltage terminal VGL.
  • the second output terminal REout is electrically connected.
  • the pull-up sub-circuit 5031 includes a third pull-up transistor T15, the gate of the third pull-up transistor T15 is electrically connected to the first output terminal Eout, the first pole of the third pull-up transistor T15 is electrically connected to the first voltage terminal VGH, The second pole of the third pull-up transistor T15 is electrically connected to the fourth node n4.
  • the pull-down sub-circuit 5032 includes a second pull-down transistor T14, the gate of the second pull-down transistor T14 is electrically connected to the first output node OP1, the first pole of the second pull-down transistor T14 is electrically connected to the second voltage terminal VGL, and the second pull-down transistor T14 is electrically connected to the second voltage terminal VGL.
  • the second pole of T14 is electrically connected to the fourth node n4.
  • the third bootstrap sub-circuit 5033 includes a third capacitor C4 and a third bootstrap transistor T18, the first terminal of the third capacitor C4 and the gate of the third bootstrap transistor T18 are both electrically connected to the fourth node n4, the third bootstrap transistor T18 The second pole of the bootstrap transistor T18 is electrically connected to the second end of the third capacitor C4, and the first pole of the third bootstrap transistor T18 is electrically connected to the first clock signal terminal ECK.
  • FIG. 5C is a driving sequence diagram of another shift register provided by an embodiment of the present disclosure.
  • the working principle of the shift register provided by the embodiment of the present disclosure will be introduced by taking the shift register shown in FIG. 5B and the driving sequence shown in FIG. 5C as examples.
  • the working process of the shift register includes an input stage A, a first output stage B1, a second output stage B2, a buffer stage C and a stabilization stage D, wherein the first stage Including the first output stage B1, the second output stage B2, the second stage includes input stage A, buffer stage C and stabilization stage D.
  • the first control circuit 200 , the second control circuit 300 and the output circuit 400 their working processes in the input phase A, the buffer phase C and the stabilization phase D can refer to the foregoing description, and will not be repeated here.
  • the first stage B in the aforementioned working process is divided into the first output stage B1 and the second output stage B2.
  • the working process of the circuit 400 in the first output stage B1 and the second output stage B2 reference may be made to the foregoing description about the first stage B, and details are not repeated here.
  • the first clock signal VECK output from the first clock signal terminal ECK is a low-level signal
  • the second clock signal VECB output from the second clock signal terminal ECB is a high-level signal
  • the input voltage terminal ESTV outputs
  • the input voltage Vin is a high-level signal
  • the first output signal Vout is a low-level signal.
  • the first control output transistor T7 and the second control output transistor T8 are both in the cut-off state, the voltage of the first output node OP1 does not change and is still at a high level, so the second pull-down transistor T14 It is in an off state under the control of the voltage of the first output node OP1.
  • the first output terminal Eout maintains the state of the previous stage in the input stage A.
  • the first output signal Vout is a low-level signal, so under the control of the first output signal Vout, the third pull-up transistor T15 And the first output inverting transistor T17 is in the conduction state, the first voltage signal VH is written into the fourth node n4 through the third pull-up transistor T15, so that the fourth node n4 is at a high level, that is, the voltage Vn4 of the fourth node is a high level VH, thereby controlling the second output inverting transistor T16 to be in the cut-off state; the first voltage signal VH is written into the second output terminal REout through the first output inverting transistor T17, that is, the second output signal Rout at this time is The first voltage signal VH.
  • the first clock signal VECK output from the first clock signal terminal ECK is a high-level signal
  • the second clock signal VECB output from the second clock signal terminal ECB is a low-level signal
  • the input voltage terminal ESTV outputs
  • the input voltage Vin is a high-level signal
  • the first output signal Vout is a high-level signal.
  • the first output signal Vout is the first voltage signal VH at this time, so the third pull-up transistor T15 and the first output inverting transistor T17 are in the cut-off state, and the voltage Vn4 of the fourth node n4 No longer affected by the first voltage terminal VGH.
  • the voltage of the first output node OP1 is VL-Vth7, that is, the first control signal Vctrl1 is at low level at this time.
  • the third intermediate signal Vmid3 determined by the voltage signal VL is written into the fourth node n4.
  • the voltage of the third intermediate signal Vmid3 is VL-Vth7-Vth14, wherein Vth7 represents the threshold voltage of the first control output transistor T7, and Vth14 represents the second pull-down transistor
  • Vth7 represents the threshold voltage of the first control output transistor T7
  • Vth14 represents the second pull-down transistor
  • the threshold voltage of T14 that is, the voltage Vn4 of the fourth node n4 at this time is VL-Vth7-Vth14, and when the voltage Vn4 of the fourth node n4 reaches VL-Vth7-Vth14, the second pull-down transistor T14 is turned off.
  • the third bootstrap transistor T18 is turned on under the control of the voltage Vn4 of the fourth node n4, and transmits the high level of the first clock signal VECK to the second terminal of the third capacitor C4, so that the first terminal of the third capacitor C4 Both terminals are at high level.
  • the second output inverting transistor T16 Since the voltage Vn4 of the fourth node n4 is VL-Vth7-Vth14, the second output inverting transistor T16 is turned on to a certain extent, and the second output inverting transistor T16 transmits a low-level signal with a threshold loss.
  • the second output terminal When the second output terminal When the voltage of the second output signal Rout output by REout reaches VL-Vth14-Vth16, the second output inverting transistor T16 is turned off, and the voltage of the second output signal Rout no longer drops, so that in the first output stage B1, the second output signal The voltage of Rout is VL-Vth14-Vth16, and the low level output by the second output terminal REout cannot reach the potential of the second voltage signal VL.
  • the first clock signal VECK output from the first clock signal terminal ECK is a low level signal
  • the second clock signal VECB output from the second clock signal terminal ECB is high Level signal
  • the first clock signal VECK output from the first clock signal terminal ECK is a high level signal
  • the second clock signal VECB output from the second clock signal terminal ECB is a low level signal
  • the first output signal Vout is a high-level signal in the second output stage B2.
  • the first control signal Vctrl1 is a low level signal
  • the first output signal Vout is a high level signal
  • the third pull-up transistor T15 and the first output inverting transistor T17 are still at In the cut-off state
  • the second pull-down transistor T14 and the second output inverting transistor T16 are also in the cut-off state.
  • the first clock signal VECK jumps from high level to low level, and due to the coupling effect of the third capacitor C4, the voltage Vn4 of the fourth node n4 drops to Vmid3- ⁇ V, that is, the voltage of the fourth intermediate signal Vmid4 is Vmid3 ⁇ V, and ⁇ V represents a potential difference from a high level to a low level. Since the voltage Vn4 of the fourth node n4 drops to a voltage value much lower than VL, the second output inverting transistor T16 is better turned on, so that the second voltage signal VL can be output to the second output terminal without threshold loss REout, that is, the second output signal Rout reaches the voltage of the second voltage signal VL.
  • the second output signal Rout is still the second voltage signal VL.
  • the first clock signal VECK output from the first clock signal terminal ECK is a low-level signal
  • the second clock signal VECB output from the second clock signal terminal ECB is a high-level signal
  • the input voltage output from the input voltage terminal ESTV The voltage Vin is a low-level signal
  • the first output signal Vout is a low-level signal, that is, the third voltage signal.
  • the first control signal Vctr1 is the first voltage signal VH, that is, the first output node OP1 is at a high level at this time, so the second pull-down transistor T14 is in a cut-off state.
  • the first output signal Vout is the third voltage signal VL1, the absolute value of the voltage of the third voltage signal VL1 is smaller than the second voltage signal VL, under the control of the third voltage signal VL1, the third pull-up transistor T15 and the first output are inverted Both transistors T17 are turned on.
  • the first voltage signal VH is written into the fourth node n4 via the third pull-up transistor T15, so that the fourth node n4 is at a high level.
  • the voltage Vn4 of the fourth node n4 is the first voltage signal VH
  • the second output The phase transistor T16 is in the cut-off state; the first voltage signal VH is written into the second output terminal REout through the first output inverting transistor T17, and the second output terminal REout outputs a high level signal, that is, the second output signal Rout at this time is the first A voltage signal VH.
  • the first clock signal VECK output from the first clock signal terminal ECK is a high-level signal
  • the second clock signal VECB output from the second clock signal terminal ECB is a low-level signal
  • the input voltage output from the input voltage terminal ESTV The voltage Vin is a low-level signal
  • the first output signal Vout is a low-level signal, that is, the second voltage signal VL.
  • the second pull-down transistor T14 is in an off state, and under the control of the second voltage signal VL, the third pull-up transistor T15 and the first output are inverted Transistors T17 are all turned on, so that the second output inverting transistor T16 is also in the off state; the first voltage signal VH is written into the second output terminal REout through the first output inverting transistor T17, and the second output terminal REout still outputs a high level signal, that is, the second output signal Rout at this time is the first voltage signal VH.
  • Fig. 5D is a schematic block diagram of another shift register provided by at least one embodiment of the present disclosure.
  • the shift register further includes an output inverting circuit 500, which is connected to the first output node OP1, the first voltage terminal VGH, and the first output node OP1, respectively.
  • the two voltage terminals VGL, the first output terminal Eout and the second output terminal REout are electrically connected, and are configured to invert the first output signal Vout to obtain a second output signal Rout, and output the second output signal Rout to the first Two output terminals REout.
  • FIG. 6 is a schematic block diagram of a gate driving circuit provided by an embodiment of the present disclosure
  • FIG. 7A is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • At least one embodiment of the present disclosure further provides a gate driving circuit.
  • the gate driving circuit 1 includes the shift register 10 described in any one of the above-mentioned embodiments of the present disclosure.
  • the gate drive circuit provided in the present disclosure can output a level opposite to the turn-on level of the transistor through the shift register 10 , for example, when the transistor is a P-type transistor, output a high-level pulse.
  • the gate drive circuit 1 includes a plurality of cascaded shift registers SR1 , SR2 , SR3 . . . SRn.
  • These shift registers SR1 , SR2 , SR3 . . . SRn can all be the shift registers described in any one of the above-mentioned embodiments of the present disclosure.
  • the first output terminals Eout of these shift registers SR1 , SR2 , SR3 . . . SRn are respectively connected to a plurality of gate lines G1 , G2 , G3 . . . Gn (not shown) in one-to-one correspondence.
  • the first output terminal of the M-th stage shift register is used as the input voltage terminal connected to the M+1-th stage shift register, where M is a positive integer, and M is greater than 1 . Therefore, the working state of the next-stage shift register is controlled by the first output signal of the upper-stage shift register, so as to output pulse scanning signals sequentially.
  • the input voltage terminal ESTV of the first-stage shift register SR1 is connected to the trigger signal terminal STV0 (which is configured to provide a trigger signal to control the gate driving circuit to start working) to receive the trigger signal as the input voltage Vin.
  • the gate drive circuit 1 further includes a signal generation circuit 20 .
  • the signal generation circuit 20 is configured to generate a first signal CK and a second signal CB.
  • the first signal CK is the first clock signal VECK in the embodiment of the above-mentioned shift register
  • the second signal CB is the second clock signal in the embodiment of the above-mentioned shift register VECB.
  • the first signal CK is the second clock signal VECB in the above embodiment of the shift register
  • the second signal CB is the first clock signal VECK in the above embodiment of the shift register.
  • the first signal CK and the second signal CB alternately control the odd-numbered and even-numbered shift registers, thereby reducing the number of signals and reducing production costs.
  • the first signal CK is applied to the first clock signal end ECK connected to the 2N-1st stage shift register and the second clock signal end ECB connected to the 2Nth stage shift register;
  • the second signal CB is applied to the second clock signal terminal ECB connected to the 2N-1 stage shift register and the first clock signal terminal ECK connected to the 2N stage shift register, wherein, N is a positive integer, and N is greater than Equal to 1 and less than n/2.
  • n may be an even number or an odd number, which is not limited in the present disclosure. In the example shown in FIG. 7A , n is an even number.
  • upper level and lower level do not refer to the upper level and the lower level in the scanning timing, but refer to the upper level and the lower level in the physical connection.
  • the trigger signal terminal STV0 provides the trigger signal STV0 to the first-stage shift register SR1 as the input voltage Vin, thereby controlling the first-stage shift register SR1 starts to work.
  • the first-stage shift register SR1 Under the control of the first signal CK and the second signal CB, the first-stage shift register SR1 outputs the first output signal Vout(1) to the gate line G1 as a scanning signal, and the first-stage shift register The first output signal Vout(1) output by SR1 is transmitted to the second-stage shift register SR2 as an input voltage of the second-stage shift register SR2, thereby controlling the second-stage shift register SR2 to start working.
  • the second-stage shift register SR2 Under the control of the first signal CK and the second signal CB, the second-stage shift register SR2 outputs the second output signal Vout(2) to the gate line G2 as a scanning signal, and the second-stage shift register SR2 outputs the second An output signal Vout ( 2 ) is transmitted to the next-stage shift register as an input voltage of the next-stage shift register, and so on, and finally the gate driving circuit completes the scanning work of one frame.
  • FIG. 7B is a schematic structural diagram of another gate driving circuit provided by an embodiment of the present disclosure.
  • the gate driving circuit 1 includes a shift register including an output inverting circuit in the above embodiments of the present disclosure, for example, the shift register shown in FIG. 5A and FIG. 5B .
  • these shift registers SR1, SR2, SR3...SRn have a second output terminal REout in addition to the first output terminal Eout.
  • Two output signals Rout for example, the second output signal Rout(1) is a signal that is inverse to the first output signal Vout(1), and the second output signal Rout(2) is a signal that is inverse to the first output signal Vout(2) signal, and so on.
  • FIG. 8 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • Embodiments of the present disclosure also provide a display device 50 .
  • a display device 50 includes the gate driving circuit 1 provided by any embodiment of the present disclosure.
  • the display device 50 provided by the embodiment of the present disclosure further includes a gate line 2, a data line 3, and a plurality of pixel units 4 defined by intersections of the gate line 2 and the data line 3, and the gate driving circuit 1 is It is configured to provide a gate driving signal to the gate line 2 .
  • each stage of the shift registers SR1, SR2, SR3...SRn is used to output a row of gate driving signals to the corresponding gate lines G1, G2, G3...Gn.
  • the display device 50 may be any product or component with a display function applied to a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • At least one embodiment of the present disclosure further provides a driving method of a shift register, which is used for driving the shift register provided according to at least one embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a driving method provided by an embodiment of the present disclosure.
  • Embodiments of the present disclosure also provide a driving method of a shift register, as shown in FIG. 9 , the driving method includes the following steps:
  • Step S10 In the input phase, input the input voltage to the first node.
  • Step S20 In the first stage, under the control of the first control signal, output the first voltage signal to the first output terminal.
  • Step S30 In the stable stage, under the control of the second control signal, output the second voltage signal to the first output terminal.
  • the driving method of the shift register provided by the embodiments of the present disclosure can realize that the P-type transistor outputs a level opposite to the turn-on level of the P-type transistor, for example, a high-level pulse.

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。该移位寄存器包括：输入电路，被配置为在第一时钟信号的控制下，将输入电压输入到第一节点；第一控制电路，被配置为在第一时钟信号、第一节点的电压和第二时钟信号的控制下，输出第一控制信号至第一输出节点；第二控制电路，被配置为在第一节点的电压的控制下，输出第二控制信号至第二输出节点；输出电路，被配置为在第一控制信号以及第二控制信号的控制下，将第一电压信号或第二电压信号写入第一输出端作为第一输出信号。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示装置 技术领域
本公开的实施例涉及一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。
背景技术
随着显示技术的飞速发展，显示面板越来越向着高集成度和低成本的方向发展。栅极驱动电路基板(Gate-driver on Array，GOA)技术是通过光刻工艺将栅极驱动电路直接集成在显示装置的阵列基板上，GOA电路通常包括多个级联的移位寄存器，每个移位寄存器均对应于一行像素所对应的栅线(例如，每个移位寄存器给与一行像素均连接的栅线提供扫描驱动信号)，以实现对显示面板的扫描驱动。GOA技术可以节省栅极集成电路(Integrated Circuit，IC)的绑定(Bonding)区域以及扇出(Fan-out)区域的空间，从而实现显示面板的窄边框，同时可以降低产品成本、提高产品的良率。
发明内容
本公开至少一实施例提供一种移位寄存器，包括：输入电路、第一控制电路、第二控制电路和输出电路，其中，所述输入电路，分别与输入电压端、第一时钟信号端和第一节点电连接，被配置为在所述第一时钟信号端提供的第一时钟信号的控制下，将所述输入电压端提供的输入电压输入到所述第一节点；所述第一控制电路，分别与所述第一时钟信号端、第二时钟信号端、所述第一节点和第一输出节点电连接，被配置为在所述第一时钟信号、所述第一节点的电压和所述第二时钟信号端提供的第二时钟信号的控制下，输出第一控制信号至所述第一输出节点；所述第二控制电路，分别与所述第一节点、所述第二时钟信号端和第二输出节点电连接，且被配置为在所述第一节点的电压的控制下，输出第二控制信号至所述第二输出节点；所述输出电路，分别与所述第一电压端、第二电压端、所述第一输出节点、所述第二输出节点和第一输出端电连接，被配置为在所述第一控制信号以及所述第二控制信号的控制下，将所述第一电压端提供的第一电压信号或所述第二电压端提供的第二电压信号写入所述第一输出端作为第一输出信号。
例如，在本公开至少一实施例提供的移位寄存器中，所述第一控制电路被配置为，控制所述输出电路在第一阶段输出所述第一电压信号；所述第二控制电路被配置为，控制所述输出电路在第二阶段输出所述第二电压信号，所述第一输出信号包括位于所述第一阶段的所述第一电压信号和位于所述第二阶段的所述第二电压信号。
例如，在本公开至少一实施例提供的移位寄存器中，所述输出电路还被配置为，在所述第一控制信号以及所述第二控制信号的控制下，在所述第二阶段，将第三电压信号写入所述第一输出端，其中，所述第一输出信号还包括第三电压信号，所述第三电压信号的电压绝对值小于所述第二电压信号的电压绝对值。
例如，在本公开至少一实施例提供的移位寄存器中，所述第一控制电路包括第一控制输入子电路，所述第一控制输入子电路分别与所述第一时钟信号端和第二节点电连接，且被配置为在所述第一时钟信号的控制下，将第三控制信号写入所述第二节点。
例如，在本公开至少一实施例提供的移位寄存器中，所述第一控制电路还与所述第一电压端和所述输入电路电连接，所述第二控制输入子电路分别与所述输入电路、所述第二时钟信号端、所述第一电压端以及所述第二节点电连接，且被配置为在所述输入电压、所述第二时钟信号的控制下，将所述第一电压信号写入所述第二节点。
例如，在本公开至少一实施例提供的移位寄存器中，所述第一控制电路包括第一自举子电路、第一控制输出子电路和第二控制输出子电路，所述第一自举子电路分别与所述第二节点、第三节点和所述第二时钟信号端电连接，且被配置为在所述第二节点的电压的控制下，将第一中间信号写入所述第三节点；所述第一控制输出子电路分别与所述第二时钟信号端、所述第三节点和所述第一输出节点电连接，且被配置为在所述第二时钟信号的控制下，将基于所述第一中间信号确定的第二中间信号写入所述第一输出节点；所述第二控制输出子电路分别与所述第一节点、所述第一电压端和所述第一输出节点电连接，且被配置为在所述第一节点的电压的控制下，将所述第一电压信号写入所述第一输出节点，其中，所述第一控制信号包括所述第二中间信号和所述第一电压信号。
例如，在本公开至少一实施例提供的移位寄存器中，所述输入电路包括连接至所述输入电压端的输入端和连接至所述第一节点的输出端，所述第二控制输入子电路与所述输入电路的输出端电连接，或者，所述第二控制输入子电路与所述输入电路的输入端电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述第一控制输入子电路包括第一下拉晶体管，所述第一下拉晶体管的第一极与所述第一时钟信号端电连接，所述第一下拉晶体管的第二极与所述第二节点电连接，所述第一下拉晶体管的栅极与所述第一时钟信号端电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述第二控制输入子电路包括第一上拉晶体管和第二上拉晶体管，所述第一上拉晶体管的第一极与所述第二上拉晶体管的第二极电连接，所述第一上拉晶体管的第二极与所述第二节点电连接，所述第一上拉晶体管的栅极与所述第二时钟信号端电连接，所述第二上拉晶体管的栅极与所述输入电路的输入端或所述输入电路的输出端电连接，所述第二上拉晶体管的第一极与所述第一电压端电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述第一自举子电路包括第一电容和第一自举晶体管，所述第一自举晶体管的栅极电连接至所述第二节点和所述第一电容的第一端，所述第一自举晶体管的第二极电连接至所述第一电容的第二端和所述第三节点，所述第一自举晶体管的第一极与所述第二时钟信号端电连接；所述第一控制输出子电路包括第一控制输出晶体管，所述第一控制输出晶体管的栅极与所述第二时钟信号端电连接，所述第一控制输出晶体管的第一极与所述第三节点电连接，所述第一控制输出晶体管的第二极与所述第一输出节点电连接；所述第二控制输出子电路包括第二控制输出晶体 管，所述第二控制输出晶体管的栅极与所述第一节点电连接，所述第二控制输出晶体管的第一极与所述第一电压端电连接，所述第二控制输出晶体管的第二极与所述第一输出节点电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述第一控制电路还包括保持子电路，所述保持子电路分别与所述第一电压端、所述第一节点和所述第一输出节点电连接，且被配置为在所述第一阶段，维持所述第一节点的电平。
例如，在本公开至少一实施例提供的移位寄存器中，所述保持子电路包括保持晶体管，所述保持晶体管的第一极与所述第一电压端电连接，所述保持晶体管的第二极与所述第一节点电连接，所述保持晶体管的栅极与所述第一输出节点电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述第一控制电路还与所述第二电压端电连接，所述第一控制电路还包括第一隔离子电路，所述第一隔离子电路的输入端与所述第二节点电连接，所述第一隔离子电路的输出端与所述第一自举子电路电连接，所述第一隔离子电路的控制端与所述第二电压端电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述第一隔离子电路包括第一隔离晶体管，所述第一隔离晶体管的第一极与所述第二节点电连接，所述第一隔离晶体管的第二极与所述第一自举子电路电连接，所述第一隔离晶体管的栅极与所述第二电压端电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述第一控制电路还包括存储子电路，所述存储子电路分别与所述第一电压端和所述第一输出节点电连接，且被配置为存储所述第一输出节点的电压。
例如，在本公开至少一实施例提供的移位寄存器中，存储子电路包括存储电容，所述存储电容的第一端与所述第一电压端电连接，所述存储电容的第二端与所述第一输出节点电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述第二控制电路包括第二自举子电路，所述第二自举子电路分别与所述第一节点、所述第二时钟信号端和所述第二输出节点电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述第二自举子电路包括第二电容和第二自举晶体管，所述第二自举晶体管的第一极与所述第二时钟信号端电连接，所述第二电容的第一端电连接至所述第二自举晶体管的栅极和所述第二输出节点，所述第二电容的第二端与所述第二自举晶体管的第二极电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述第二控制电路还包括第二隔离子电路，所述第二隔离子电路的输入端与所述第一节点电连接，所述第二隔离子电路的输出端与所述第二输出节点电连接，所述第二隔离子电路的控制端与所述第二电压端电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述第二隔离子电路包括第二隔离晶体管，所述第二隔离晶体管的第一极与所述第一节点电连接，所述第二隔离晶体管的 第二极与所述第二输出节点电连接，所述第二隔离晶体管的栅极与所述第二电压端电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述输出电路包括第一输出子电路和第二输出子电路，所述第一输出子电路分别与所述第一输出节点、所述第一电压端和所述第一输出端电连接，且被配置为在所述第一控制信号的控制下，在所述第一阶段将所述第一电压信号写入所述第一输出端；所述第二输出子电路分别与所述第二输出节点、所述第二电压端和所述第一输出端电连接，且被配置为在所述第二控制信号的控制下，在所述第二阶段将所述第二电压信号写入所述第一输出端。
例如，在本公开至少一实施例提供的移位寄存器中，所述第一输出子电路包括第一输出晶体管，所述第一输出晶体管的栅极与所述第一输出节点电连接，所述第一输出晶体管的第一极与所述第一电压端电连接，所述第一输出晶体管的第二极与所述第一输出端电连接；所述第二输出子电路包括第二输出晶体管，所述第二输出晶体管的栅极与所述第二输出节点电连接，所述第二输出晶体管的第一极与所述第二电压端电连接，所述第二输出晶体管的第二极与所述第一输出端电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述移位寄存器还包括输出反相电路，所述输出反相电路分别与所述第一输出节点、所述第一电压端、所述第二电压端、所述第一输出端和第二输出端电连接，且被配置为将所述第一输出信号进行反相以得到第二输出信号，并将所述第二输出信号输出至所述第二输出端。
例如，在本公开至少一实施例提供的移位寄存器中，所述输出反相电路包括第一输出反相子电路、第二输出反相子电路和输出反相控制子电路，所述输出反相控制子电路分别与所述第一电压端、所述第一输出节点、所述第二电压端以及第四节点电连接，且被配置为在所述第一控制信号、所述第一输出信号的控制下，输出第四控制信号至所述第四节点；所述第一输出反相子电路分别与所述第一电压端、所述第一输出端和所述第二输出端电连接，且被配置为在所述第一输出信号的控制下，在所述第二阶段将所述第一电压信号写入所述第二输出端；所述第二输出反相子电路分别与所述第二电压端、所述第四节点和所述第二输出端电连接，且被配置为在所述第四控制信号的控制下，在所述第一阶段将所述第二电压信号写入所述第二输出端，所述第二输出信号包括位于所述第一阶段的第二电压信号和位于所述第二阶段的所述第一电压信号。
例如，在本公开至少一实施例提供的移位寄存器中，所述输出反相控制子电路包括上拉子电路、下拉子电路和第三自举子电路，所述上拉子电路分别与所述第一电压端、所述第一输出端和所述第四节点电连接，且被配置为在所述第一输出信号的控制下，将所述第一电压信号写入所述第四节点；所述下拉子电路分别与所述第一输出节点、所述第二电压端和所述第四节点电连接，且被配置为在所述第一控制信号的控制下，将基于所述第二电压信号确定的第三中间信号写入所述第四节点；所述第三自举子电路分别与所述第四节点、所述第一时钟信号端电连接，被配置为在所述第四节点的电压的控制下，将基于所述第三中间信号和所述第一时钟信号确定的第四中间信号写入所述第四节点，其中，所述第 四控制信号包括所述第一电压信号、所述第三中间信号和所述第四中间信号。
例如，在本公开至少一实施例提供的移位寄存器中，所述第一输出反相子电路包括第一输出反相晶体管，所述第二输出反相子电路包括第二输出反相晶体管，所述第一输出反相晶体管的栅极与所述第一输出端电连接，所述第一输出反相晶体管的第一极与所述第一电压端电连接，所述第一输出反相晶体管的第二极与所述第二输出端电连接；所述第二输出反相晶体管的栅极与所述第四节点电连接，所述第二输出反相晶体管的第一极与所述第二电压端电连接，所述第二输出反相晶体管的第二极与所述第二输出端电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述上拉子电路包括第三上拉晶体管，所述第三上拉晶体管的栅极与所述第一输出端电连接，所述第三上拉晶体管的第一极与所述第一电压端电连接，所述第三上拉晶体管的第二极与所述第四节点电连接；所述下拉子电路包括第二下拉晶体管，所述第二下拉晶体管的栅极与所述第一输出节点电连接，所述第二下拉晶体管的第一极与所述第二电压端电连接，所述第二下拉晶体管的第二极与所述第四节点电连接；所述第三自举子电路包括第三电容和第三自举晶体管，所述第三电容的第一端和所述第三自举晶体管的栅极均电连接至所述第四节点，所述第三自举晶体管的第二极与所述第三电容的第二端电连接，所述第三自举晶体管的第一极与所述第一时钟信号端电连接。
例如，在本公开至少一实施例提供的移位寄存器中，所述输入电路包括输入晶体管，所述输入晶体管的第一极与所述输入电压端电连接，所述输入晶体管的第二极与所述第一节点电连接，所述输入晶体管的栅极与所述第一时钟信号端电连接。
本公开至少一实施例还提供一种栅极驱动电路，包括本公开任一实施例所述的移位寄存器。
例如，在本公开至少一实施例提供的栅极驱动电路中，所述栅极驱动电路包括级联的多个所述移位寄存器，其中，除第一级移位寄存器之外，第M级移位寄存器的第一输出端作为第M+1级移位寄存器所连接的输入电压端，其中，M为正整数，且M大于1。
例如，在本公开至少一实施例提供的栅极驱动电路还包括信号生成电路，其中，所述信号生成电路被配置为生成第一信号和第二信号，所述第一信号被施加至第2N-1级移位寄存器所连接的第一时钟信号端和第2N级移位寄存器所连接的第二时钟信号端；所述第二信号被施加至所述第2N-1级移位寄存器所连接的第二时钟信号端和所述第2N级移位寄存器所连接的第一时钟信号端；其中，N为正整数，且N大于等于1。
本公开至少一实施例还提供一种显示装置，包括如本公开任一实施例所述的栅极驱动电路。
本公开至少一实施例还提供一种移位寄存器的驱动方法，用于驱动如本公开任一实施例所述的移位寄存器，所述输出电路在第一阶段输出所述第一电压信号，以及在第二阶段输出所述第二电压信号，所述第二阶段包括输入阶段和稳定阶段，所述驱动方法包括：在所述输入阶段，将所述输入电压输入至所述第一节点；在所述第一阶段，在所述第一控制信号的控制下，将所述第一电压信号输出至所述第一输出端；在所述稳定阶段，在所述第 二控制信号的控制下，将所述第二电压信号输出至所述第一输出端。
例如，在本公开至少一实施例提供的驱动方法中，所述第二阶段还包括缓冲阶段，所述驱动方法还包括：在所述缓冲阶段，在所述第二控制信号的控制下，将第三电压信号输出至所述第一输出端，其中，所述第一输出信号还包括所述第三电压信号，所述第三电压信号的电压绝对值小于所述第二电压信号的电压绝对值。
例如，在本公开至少一实施例提供的驱动方法中，在所述第一控制电路与所述输入电压端电连接的情况下，所述输入电压处于第一电平下的脉冲宽度大于所述第一时钟信号和所述第二时钟信号的周期。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为一种移位寄存器电路的结构示意图；
图1B为图1A所示的移位寄存器电路对应的驱动时序图；
图2A为本公开至少一实施例提供的一种移位寄存器的示意性框图；
图2B为本公开至少一实施例提供的另一种移位寄存器的示意性框图；
图3A为本公开至少一实施例提供的一种移位寄存器的结构示意图；
图3B为本公开至少一实施例提供的另一种移位寄存器的结构示意图
图3C为本公开至少一实施例提供的另一种移位寄存器的结构示意图；
图3D为本公开至少一实施例提供的另一种移位寄存器的结构示意图；
图4A是本公开至少一实施例提供的一种移位寄存器的驱动时序图；
图4B是本公开至少一实施例提供的另一种移位寄存器的驱动时序图；
图5A为本公开至少一实施例提供的又一种移位寄存器的示意性框图；
图5B为本公开至少一实施例提供的再一种移位寄存器的结构示意图；
图5C是本公开至少一实施例提供的又一种移位寄存器的驱动时序图；
图5D为本公开至少一实施例提供的再一种移位寄存器的示意性框图；
图6为本公开至少一实施例提供的一种栅极驱动电路的示意性框图；
图7A本公开至少一实施例提供的一种栅极驱动电路的结构示意图；
图7B为本公开至少一实施例提供的另一种栅极驱动电路的结构示意图；
图8为本公开至少一实施例提供的一种显示装置的示意图；
图9本公开至少一实施例提供的一种驱动方法的流程图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通 技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。
现有的集成于显示面板上的移位寄存电路一般都能实现如下功能：利用N型晶体管实现高电平脉冲信号的移位输出，利用P型晶体管实现低电平脉冲信号的移位输出。
图1A为一种基于P型晶体管构建的移位寄存器电路的结构示意图，图1B为图1A所示的移位寄存器电路对应的驱动时序图。
如图1A和图1B所示，该移位寄存电路可以实现输出低电平信号。例如，在图1B所示的阶段t1，此时第一信号端GCK为低电平信号，第二信号端GCB为高电平信号，晶体管T1开启，输入信号端GSTV通过晶体管T1输入低电平信号并存在电容C2中，从而使得晶体管T7开启。在阶段t2，第二信号端GCB为低电平信号，第一信号端GCK为高电平信号，通过处于开启状态的晶体管T7将第二信号端GCB的低电平信号(例如可以与低电平信号VL相等)输出至输出端Output，也即输出端Output输出低电平信号。在不需要输出低电平信号的时间段，输入信号端GSTV的信号均处于高电平，第一信号端GCK每半个周期将晶体管T3开启，低电平信号VL通过晶体管T3写入到电容C1中，从而使得晶体管T6、晶体管T8保持常开状态，当晶体管T5在第二信号端GCB提供的信号的控制下开启时，高电平信号VGH通过晶体管T6和晶体管T5被写入电容C2中，从而控制晶体管T7关闭，此时，高电平信号VGH通过晶体管T8被输出至输出端Output，即输出端Output输出高电平信号VGH。
目前，在有机发光二极管显示面板(OLED)，一般都使用P型晶体管工艺来实现所有背板电路，并且，栅极驱动电路(例如，GOA电路)经常存在需要输出高电平脉冲信号的情况，也就是说，需要利用P型晶体管来构建输出高电平脉冲信号的移位寄存电路。然而，关键的困难在于，输入信号端的起始信号是高电平，这个高电平无法像图1A中的移位寄存器一样使得晶体管T7提前开启，而构建电路的晶体管均是P型晶体管，P型晶体管需要低电平才能开启，这就导致使用现有的思路去实现与晶体管开启电平相反的电平的移位功能无法实现。
本公开至少一实施例提供一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。该移位寄存器包括输入电路、第一控制电路、第二控制电路和输出电路，其中，输入电路， 分别与输入电压端、第一时钟信号端和第一节点电连接，被配置为在第一时钟信号端提供的第一时钟信号的控制下，将输入电压端提供的输入电压输入到第一节点；第一控制电路，分别与第一时钟信号端、第二时钟信号端、第一节点和第一输出节点电连接，被配置为在第一时钟信号、第一节点的电压和第二时钟信号端提供的第二时钟信号的控制下，输出第一控制信号至第一输出节点；第二控制电路，分别与第一节点、第二时钟信号端和第二输出节点电连接，且被配置为在第一节点的电压的控制下，输出第二控制信号至第二输出节点；输出电路，分别与第一电压端、第二电压端、第一输出节点、第二输出节点和第一输出端电连接，被配置为在第一控制信号以及第二控制信号的控制下，将第一电压端提供的第一电压信号或第二电压端提供的第二电压信号写入第一输出端作为第一输出信号。
该移位寄存器通过第一控制电路和第二控制电路控制输出电路输出与晶体管的开启电平相反的电平，例如，当晶体管为P型晶体管时，输出高电平信号。此外，该移位寄存器电路可以实现P型晶体管输出无阈值损失的低电平信号，提升显示面板的显示质量；另一方面，该移位寄存器的结构简单，生产成本较低。
在本公开实施例中，晶体管是指至少包括栅电极、漏电极以及源电极的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道，并且电流能够流过漏电极、沟道以及源电极。需要说明的是，在本公开中，沟道是指晶体管的栅极在有源层上的正投影所对应的部分有源层，也即电流主要流过的区域。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电平为低电平，即开启电压为低电平电压(例如，0V、-5V或其他数值)，关闭电平为高电平，即关闭电压为高电平电压(例如，5V、10V或其他数值)；当晶体管为N型晶体管时，开启电平为高电平，即开启电压为高电平电压(例如，5V、10V或其他数值)，关闭电平为低电平，即关闭电压为低电平电压(例如，0V、-5V或其他数值)。
需要说明的是，由于P型晶体管(例如，薄膜晶体管)传递低电平信号具有阈值损失，当处于低电平下的信号从P型晶体管的第一极传输至P型晶体管的第二极时，P型晶体管的第二极的电压与P型晶体管的第一极的电压之间存在电压差，该电压差为该P型晶体管的阈值电压。由于P型晶体管传递高电平信号不存在阈值损失，因而当处于高电平下的信号从P型晶体管的第一极传输至P型晶体管的第二极时，P型晶体管的第二极的电压与P型晶体管的第一极的电压之间不存在电压差。也就是说，在本公开中，低电平信号经由P型晶体管“传输”后，会产生阈值电压损失，高电平信号经由P型晶体管“传输”后， 电压保持不变。
类似的，当晶体管的类型为N型晶体管时，类似地，N型晶体管传递高电平信号具有阈值损失，这里不再赘述。
下面结合附图对本公开的实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图2A为本公开至少一实施例提供的一种移位寄存器的示意性框图。
本公开的实施例提供一种移位寄存器。例如，如图2A所示，该移位寄存器包括输入电路100、第一控制电路200、第二控制电路300和输出电路400。
例如，如图2A所示，输入电路100分别与输入电压端ESTV、第一时钟信号端ECK和第一节点n1电连接，被配置为在第一时钟信号端ECK提供的第一时钟信号VECK的控制下，将输入电压端ESTV提供的输入电压Vin输入到第一节点n1。也就是说，在第一时钟信号VECK的控制下，当输入电路100导通时，即当连接输入电压端ESTV的输入电路100的一端和连接第一节点n1的另一端导通时，输入电压Vin可以被传输至第一节点n1。
第一控制电路200，分别与第一时钟信号端ECK、第二时钟信号端ECB、第一节点n1和第一输出节点OP1电连接，被配置为在第一时钟信号VECK、第一节点n1的电压和第二时钟信号端ECB提供的第二时钟信号VECB的控制下，输出第一控制信号Vctr1至第一输出节点OP1，第一控制信号Vctr1被配置为实现第一电压端VGH和第一输出端Eout之间的导通和截止。
第二控制电路300，分别与第一节点n1、第二时钟信号端ECB和第二输出节点OP2电连接，且被配置为在第一节点n1的电压的控制下，输出第二控制信号Vctr2至第二输出节点OP2，第二控制信号Vctr2被配置为实现第二电压端VGL和第一输出端Eout之间的导通和截止。
输出电路，分别与第一电压端VGH、第二电压端VGL、第一输出节点OP1、第二输出节点OP2和第一输出端Eout电连接，被配置为在第一控制信号Vctr1以及第二控制信号Vctr2的控制下，将第一电压端VGH提供的第一电压信号VH或第二电压端VGL提供的第二电压信号VL写入第一输出端Eout作为第一输出信号Vout。
例如，第一控制电路200被配置为控制输出电路400在第一阶段输出第一电压信号VH作为第一输出信号Vout。例如，第二控制电路300被配置为控制输出电路400在第二阶段输出第二电压信号VL作为第一输出信号Vout。即第一输出信号Vout包括位于第一阶段的第一电压信号VH和位于第二阶段的第二电压信号VL。
例如，如图2A所示，第一控制电路200还与第一电压端VGH和输入电路100电连接。例如，第一控制电路200包括第一控制输入子电路201、第二控制输入子电路202、第一自举子电路203、第一控制输出子电路204、第二控制输出子电路205和保持子电路206。
例如，第一控制输入子电路201分别与第一时钟信号端ECK和第二节点n2电连接， 且被配置为在第一时钟信号VECK的控制下，将第三控制信号Vctr3写入第二节点n2。例如，当第一控制输入子电路201导通时，也即当连接至第一信号端ECK的第一控制输入子电路201的一端和连接至第二节点n2的第一控制输入子电路201的另一端导通时，处于第二电平的第一时钟信号VECK被作为第三控制信号Vctr3写入第二节点n2，使得第二节点n2的电压处于第二电平。
第二控制输入子电路202分别与输入电路100、第二时钟信号端ECB、第一电压端VGH以及第二节点n2电连接，且被配置为在输入电压Vin、第二时钟信号VECB的控制下，将第一电压信号VH写入第二节点n2。例如，当第二控制输入子电路202导通时，也即当连接至第一电压端VGH的第二控制输入子电路202的一端和连接至第二节点n2的第二控制输入子电路202的另一端导通时，第一电压信号VH被写入第二节点n2，使得第二节点n2的电压处于第一电平。
例如，第一电平和第二电平不相同，例如彼此相反。在一些示例中，第一电平为高电平，第二电平为低电平。但本公开不限于此，根据实际应用需求，第一电平可以为低电平，第二电平为高电平。在本公开的描述中，以第一电平为高电平，第二电平为低电平为例。
例如，第一电压端VGH可以为高电压端以输出具有第一电平的第一电压信号VH，第二电压端VGL可以为低电压端以输出具有第二电平的第二电压信号VL。即第一电压信号VH为高电平信号(例如5V、10V或其他电压)，第二电压信号VL为低电平信号(例如0V、-1V或其他电压)。例如，在一些实施例中，第二电压端VGL可以接地。例如，第一电压信号VH和第二电压信号VL均为直流信号。需要说明的是，低电平信号和高电平信号是相对而言的，低电平信号的电压值小于高电平信号的电压值。在不同的实施方式中，高电平信号的电压数值可能不同，低电平信号的电压数值也可能不同。
需要说明的是，第一控制电路200也可以不与第一电压端VGH连接，而与另外提供的电压端连接，只要该另外提供的电压端输出高电压信号即可。此外，该另外提供的电压端输出的高电压信号和第一电压端VGH输出的高电压信号可以相同，也可以不相同。需要说明的是，第一控制电路200也可以不与第一电压端VGH连接，而与另外提供的电压端连接，只要该另外提供的电压端输出高电压信号即可。此外，该另外提供的电压端输出的高电压信号和第一电压端VGH输出的高电压信号可以相同，也可以不相同。
例如，输入电路100包括连接至输入电压端ESTV的输入端和连接至第一节点n1的输出端，第二控制输入子电路202可以与输入电路100的输出端电连接，也即与第一节点n1电连接，或者，第二控制输入子电路202可以与输入电路100的输入端电连接，也即与输入电压端ESVT电连接。
第一自举子电路203分别与第二节点n2、第三节点n3和第二时钟信号端ECB电连接，且被配置为在第三控制信号Vctr3的控制下，将第一中间信号写入第三节点n3。
例如，当第二节点n2的电压处于第一电平时，在第二节点n2的电压的控制下，第一自举子电路203处于截止状态，第三节点n3的电压维持不变。
例如，当第二节点n2的电压处于第二电平，即当第三控制信号Vctr3写入第二节点 n2时，在第二节点n2的电压的控制下，第一自举子电路203处于导通状态，也即连接至第二时钟信号端ECB的第一自举子电路203的一端和连接至第三节点n3的第一自举子电路203的另一端导通时，第二时钟信号VECB被传输至第三节点n3。当第二时钟信号VECB出现第一电平至第二电平的跳变时，且使得第三节点n3的电压也出现第一电平至第二电平的跳变，第一自举子电路203产生自举效应，从而使得第二节点n2的电平随着第三节点n3的电平的变化而产生变化，即第二节点n2的电平也会产生跳变，第二节点n2的电平低于第二电平(例如，此时，第二节点n2的电平为(2*第一电平-第二电平))，由此，处于第二电平的第二时钟信号VECB可以经由第一自举子电路203自举输出，并被写入第三节点n3以作为第一中间信号。即第一中间信号为处于第二电平的第二时钟信号VECB。
第一控制输出子电路204分别与第二时钟信号端ECB、第三节点n3和第一输出节点OP1电连接，且被配置为在第二时钟信号VECB的控制下，将基于第一中间信号确定的第二中间信号Vmid2写入第一输出节点OP1。例如，当第一控制输出子电路204在第二时钟信号VECB的控制下导通时，也即连接至第三节点n3的一端和连接至第一输出节点OP1的另一端导通时，基于第一中间信号确定的第二中间信号Vmid2被写入第一输出节点OP1，第二中间信号Vmid2也处于第二电平。例如，第二中间信号Vmid2的电压绝对值小于第一中间信号的电压绝对值，第一中间信号和第二中间信号Vmid2之间的信号差的绝对值与第一控制输出子电路204中的晶体管(例如后面将要描述的第一控制输出晶体管T7)的阈值电压的绝对值相等。
第二控制输出子电路205分别与第一节点n1、第一电压端VGH和第一输出节点OP1电连接，且被配置为在第一节点n1的电压的控制下，将第一电压信号VH写入第一输出节点OP1。例如，当第二控制输出子电路205在第一节点n1的电压的控制下导通时，也即第二控制输出子电路205的连接至第一电压端VGH的一端和连接至第一输出节点OP1的另一端导通时，第一电压信号VH被写入第一输出节点OP1。
例如，第一控制信号包括第二中间信号Vmid2和第一电压信号VH。例如，在第一阶段，第一控制信号为第二中间信号Vmid2，也即处于第二电平，输出电路400在第二中间信号Vmid2的控制下，实现第一电压端VGH和第一输出端Eout之间的连接导通，以输出第一电压信号VH至第一输出端Eout；在第二阶段，第一控制信号为第一电压信号VH，也即处于第一电平，输出电路400在第一电压信号VH的控制下实现第一电压端VGH和第一输出端Eout之间的连接断开，从而避免在第二阶段输出第一电压信号VH至第一输出端Eout。
例如，保持子电路206分别与第一电压端VGH、第一节点n1和第一输出节点OP1电连接，且被配置为在第一阶段，维持第一节点的电平。例如，在第一阶段，第二控制信号Vctr2为第一电平信号，第二输出子电路402在第二控制信号Vctr2的控制下截止。此时，保持子电路206在第一输出节点OP1的电压控制下导通，也即连接至第一电压端VGH的保持子电路206的一端和连接至第一节点n1的保持子电路206的另一端导通，第一电 压信号VH被写入第一节点n1，以控制第一节点n1的电压在第一阶段始终处于第一电平，从而维持第二控制信号Vctr2在第一阶段处于第一电平，避免电路波动，保持输出的稳定性。
例如，如图2A所示，第二控制电路300包括第二自举子电路301，第二自举子电路301分别与第一节点n1、第二时钟信号端ECB和第二输出节点n2电连接，且被配置为在第一节点n1的电压的控制下，控制第二输出节点OP2的电压。例如，由于第二自举子电路301的自举效应，第二输出节点OP2的电压可以低于第二时钟信号VECB处于第二电平时的电压。
例如，第二控制信号Vctr2包括第一电平信号、第二电平信号以及基于处于第二电平下的第二时钟信号VECB所得到的第三电平信号。例如，第一电平信号为处于第一电平的输入电压Vin，例如第一电平信号的电压值与第一电压信号VH的电压值相同，第一电平信号的电压值大于第二电平信号的电压值，第二电平信号基于处于第二电平下的输入电压Vin得到，例如，处于第二电平下的输入电压Vin的电压值与第二电压信号VL的电压值相同，第二电平信号的电压绝对值小于第三电平信号的电压绝对值。
例如，如图2A所示，输出电路400包括第一输出子电路401和第二输出子电路402。
例如，第一输出子电路401分别与第一输出节点n1、第一电压端VGH和第一输出端Eout电连接，且被配置为在第一控制信号Vctr1的控制下，在第一阶段将第一电压信号VH写入第一输出端Eout。例如，在第一阶段，第一输出子电路401在第一控制信号Vctr1的控制下导通，也即连接至第一电压端VGH的第一输出子电路401的一端和连接至第一输出端Eout的第一输出子电路401的另一端导通，第一电压信号VH被写入第一输出端Eout，并且此时，第二输出子电路402在第二控制信号Vctr2的控制下截止。
第二输出子电路402分别与第二输出节点OP2、第二电压端VGL和第一输出端Eou电连接，且被配置为在第二控制信号Vctr2的控制下，在第二阶段将第二电压信号VL写入第一输出端Eout。例如，在第二阶段，第二输出子电路402在第二控制信号Vctr2的控制下导通，也即连接至第二电压端VGL的第二输出子电路402的一端和连接至第一输出端Eout的第二输出子电路402的另一端导通，第二电压信号VL被写入第一输出端Eout，并且此时，第一输出子电路401在第一控制信号Vctr1的控制下截止。
例如，第一输出信号还包括第三电压信号，输出电路400还被配置为在第一控制信号Vctr1以及第二控制信号Vctr2的控制下，在第二阶段，将基于第二电压信号VL得到的第三电压信号VL1写入第一输出端Eout，例如，第三电压信号VL1的电压绝对值小于第二电压信号VL的电压绝对值。由于P型晶体管输出的低电平信号存在阈值损失，第二输出子电路402可能将基于第二电压信号VL得到的第三电压信号VL1写入第一输出端Eout。第二电压信号VL和第三电压信号VL1之间的信号差的绝对值与第二输出子电路402中的晶体管(例如后面将要描述的第二输出晶体管T10)的阈值电压的绝对值相等。
例如，第二控制信号Vctr2包括的第三电平信号的电压绝对值大于第二电压信号VL的电压绝对值，从而可以使得第二输出子电路402将无阈值电压损失的第二电压信号VL 输出至第一输出端Eout。在第二阶段，第一输出信号Vout包括第三电压信号VL1和第二电压信号VL，最终第一输出信号Vout保持处于第二电压信号VL的状态。
图2B为本公开至少一实施例提供的另一种移位寄存器的示意性框图。
如图2B所示，该移位寄存器包括输入电路100、第一控制电路200、第二控制电路300和输出电路400，并且，相比于图2A所示的移位寄存器，该移位寄存器的第一控制电路200还包括存储子电路207、第一隔离子电路208，第二控制电路200还包括第二隔离子电路302。图2B所示的移位寄存器的其余子电路与图2A所示的移位寄存器相同，重复之处不再赘述。
例如，存储子电路207分别与第一电压端VGH和第一输出节点OP1电连接，且被配置为存储第一输出节点OP1的电压。
例如，第一控制电路200还与第二电压端VGL电连接，第一隔离子电路208的输入端与第二节点n2电连接，第一隔离子电路208的输出端与第一自举子电路203电连接，第一隔离子电路208的控制端与第二电压端VGL电连接。例如，在一般情况下，第一隔离子电路208处于导通状态，也即连接至第二节点n2的第一隔离子电路208的一端和连接至第一自举子电路203的第一隔离子电路208的另一端导通，当第一自举子电路203的电压发生波动时，例如，当连接至第一自举子电路203的第一隔离子电路208的一端的电压突然下降时，第一隔离子电路208从导通状态转换为截止状态，从而避免第二节点n2的电压随之发生波动而影响第二控制输入子电路202中的晶体管(例如下文所述的第一上拉晶体管T2)的性能。
需要说明的是，第一控制电路200也可以不与第二电压端VGL连接，而与另外提供的电压端连接，只要该另外提供的电压端输出低电压信号即可。此外，该另外提供的电压端输出低电压信号和第二电压端VGL输出的低电压信号可以相同，也可以不相同。
例如，第二控制电路还包括第二隔离子电路302，第二隔离子电路302的输入端与第一节点n1电连接，第二隔离子电路302的输出端与第二自举子电路301和第二输出节点OP2电连接，第二隔离子电路302的控制端与第二电压端VGL电连接。例如，在一般情况下，第二隔离子电路302处于导通状态，也即连接至第一节点n1的第二隔离子电路302的一端和连接至第二自举子电路301的第二隔离子电路302的另一端导通，当第二自举子电路301的电压发生波动时，例如，由于第二自举子电路301的自举效应，连接至第二自举子电路301的第二隔离子电路302的一端的电压会突然下降，此时第二隔离子电路302从导通状态转换为截止状态，从而避免第一节点n1的电压随之发生波动，避免输出异常。例如，当第二控制输入子电路202连接至第一节点n1时，若第一节点n1的电压跟随第二输出节点OP2的电压变化而下降，可能使得第二控制输入子电路202导通，造成输出异常。
例如，在本公开中，所有晶体管(下面将要描述的晶体管T1～T18)为P型晶体管。
图3A为本公开一实施例提供的一种移位寄存器的结构示意图。图3A所示的电路结构图为图2A所示的移位寄存器的示意性框图的一个具体示例。
如图3A所示，第一控制输入子电路201包括第一下拉晶体管T3，第一下拉晶体管T3的第一极与第一时钟信号端ECK电连接，第一下拉晶体管T3的第二极与第二节点n2电连接，第一下拉晶体管T3的栅极与第一时钟信号端ECK电连接。
第二控制输入子电路202包括第一上拉晶体管T2和第二上拉晶体管T5，第一上拉晶体管T2的第一极与第二上拉晶体管T5的第二极电连接，第一上拉晶体管T2的第二极与第二节点n2电连接，第一上拉晶体管T2的栅极与第二时钟信号端ECB电连接，第二上拉晶体管T5的第一极与第一电压端VGH电连接，第二上拉晶体管T5的栅极与输入电路100的输出端电连接，也即与第一节点n1电连接。
第一自举子电路203包括第一电容C1和第一自举晶体管T6，第一自举晶体管T6的栅极电连接至第二节点n2和第一电容C1的第一端，第一自举晶体管T6的第二极电连接至第一电容C1的第二端和第三节点n3，第一自举晶体管T6的第一极与第二时钟信号端ECB电连接。
第一控制输出子电路204包括第一控制输出晶体管T7，第一控制输出晶体管T7的栅极与第二时钟信号端ECB电连接，第一控制输出晶体管T7的第一极与第三节点n3电连接，第一控制输出晶体管T7的第二极与第一输出节点OP1电连接。
第二控制输出子电路205包括第二控制输出晶体管T8，第二控制输出晶体管T8的栅极与第一节点n1电连接，第二控制输出晶体管T8的第一极与第一电压端VGH电连接，第二控制输出晶体管T8的第二极与第一输出节点OP1电连接。
保持子电路206包括保持晶体管T4，保持晶体管T4的第一极与第一电压端VGH电连接，保持晶体管T4的第二极与第一节点n1电连接，保持晶体管T4的栅极与第一输出节点OP1电连接。
存储子电路207包括存储电容C3，存储电容C3的第一端与第一电压端VGH电连接，存储电容C3的第二端与第一输出节点OP1电连接。
第二自举子电路301包括第二电容C2和第二自举晶体管T13，第二自举晶体管T13的第一极与第二时钟信号端ECB电连接，第二电容C2的第一端电连接至第二自举晶体管T13的栅极和第二输出节点OP2，第二电容C2的第二端与第二自举晶体管T13的第二极电连接。
第一输出子电路401包括第一输出晶体管T9，第一输出晶体管T9的栅极与第一输出节点OP1电连接，第一输出晶体管T9的第一极与第一电压端VGH电连接，第一输出晶体管T9的第二极与第一输出端Eout电连接。
第二输出子电路402包括第二输出晶体管T10，第二输出晶体管T10的栅极与第二输出节点OP2电连接，第二输出晶体管T10的第一极与第二电压端VGL电连接，第二输出晶体管T10的第二极与第一输出端Eout电连接。
例如，输入电路100用于向第一节点n1传输输入电压Vin，以触发移位寄存器进行工作。如图3A所示，输入电路100包括输入晶体管T1。输入晶体管T1的第一极与输入电压端ESTV电连接，输入晶体管T1的第二极与第一节点n1电连接，输入晶体管T1的 栅极与第一时钟信号端ECK电连接。
图3B为本公开一实施例提供的另一种移位寄存器的结构示意图。图3B所示的电路结构图为图2B所示的移位寄存器的示意性框图的一个具体示例。图2B所示的移位寄存器还包括第一隔离子电路208和第二隔离子电路302。
例如，如图3B所示，第一隔离子电路208包括第一隔离晶体管T12，第一隔离晶体管T12的第一极与第二节点n2电连接，第一隔离晶体管T12的栅极与第二电压端VGL电连接，第一隔离晶体管T12的第二极与第一自举子电路203电连接，例如，如图3B所示，第一隔离晶体管T12的第二极与第一自举晶体管T6的栅极电连接。
第二隔离子电路302包括第二隔离晶体管T11，第二隔离晶体管T11的第一极与第一节点n1电连接，第二隔离晶体管T11的第二极与第二输出节点OP2电连接，第二隔离晶体管T11的栅极与第二电压端VGL电连接。
图3C为本公开一实施例提供的另一种移位寄存器的结构示意图。图3C所示的电路结构图为图2B所示的移位寄存器的示意性框图的另一个具体示例。
例如，图3B和图3C所示电路结构图的区别在于：图3B所示的移位寄存器的第二上拉晶体管T5的栅极与第一节点n1电连接，图3C所示的移位寄存器的第二上拉晶体管T5的栅极与输入电压端ESTV电连接。其他电路结构之间的连接关系参见对图3A和图3B所示的移位寄存器的结构的描述，这里不再赘述。
例如，当第二上拉晶体管T5与输入电压端ESTV电连接时，输入电压Vin可以直接控制第二上拉晶体管T5的导通和截止，从而可以使得第二上拉晶体管T5在输入阶段之前在输入电压Vin的高电平控制下提前截止。
此外，需要说明的是，图3A、图3B和图3C所示的输入电路100、第一控制电路200、第二控制电路300和输出电路400仅为本公开实施例的一个示例，本公开的实施例包括但不局限于图3A、图3B和图3C所示的情形。
例如，第一时钟信号VECK以及第二时钟信号VECB的高电平与第一电压信号VH的电平相同，第一时钟信号VECK以及第二时钟信号VECB的低电平与第二电压信号VL的电平相同。
需要说明的是，第一时钟信号VECK和第二时钟信号VECB的高电平也可以与第一电压信号VH的电平不相同，第一时钟信号VECK和第二时钟信号VECB的低电平也可以与第二电压信号VL的电平不相同，只要第一时钟信号VECK和第二时钟信号VECB能够执行其自身的功能即可，本公开对此不作限制。在本公开实施例中，以第一时钟信号VECK和第二时钟信号VECB的高电平均与第一电压信号VH的电平相同，第一时钟信号VECK和第二时钟信号VECB的低电平均与第二电压信号VL的电平相同为例描述本公开提供的移位寄存器。
图3D为本公开至少一实施例提供的另一种移位寄存器的结构示意图。图3D所示的电路结构图为图2A所示的移位寄存器的示意性框图的另一个具体示例。
例如，图3D和图3A所示电路结构图的区别在于：图3A所示的移位寄存器的第二 上拉晶体管T5的栅极与第一节点n1电连接，图3D所示的移位寄存器的第二上拉晶体管T5的栅极与输入电压端ESTV电连接。其他电路结构之间的连接关系参见对图3A所示的移位寄存器的结构的描述，这里不再赘述。
图4A是本公开一实施例提供的一种移位寄存器的驱动时序图。下面以图3B所示的移位寄存器和图4A所示的驱动时序为例介绍本公开实施例提供的移位寄存器的工作原理。
例如，如图4A所示，本公开实施例提供的移位寄存器的工作过程包括输入阶段A、第一阶段B、缓冲阶段C和稳定阶段D，其中，输入阶段A、缓冲阶段C和稳定阶段D属于第二阶段。
例如，如图4A所示，高电平的输入电压Vin、高电平的第一时钟信号VECK和高电平的第二时钟信号VECB均与第一电压信号VH相等，低电平的输入电压Vin、低电平的第一时钟信号VECK和低电平的第二时钟信号VECB均与第二电压信号VL相等。
例如，如图4A所示，Vout表示第一输出信号，Vn3表示第三节点n3的电压，Vctr1表示第一控制信号，Vctr2表示第二控制信号。
例如，第一隔离晶体管T12在第二电压信号VL的控制下处于常开状态，第二隔离晶体管T11在第二电压信号VL的控制下也处于常开状态。
在输入阶段A，将输入电压Vin输入至第一节点n1。例如，如图4A和图3B所示，在输入阶段A，第一时钟信号端ECK输出的第一时钟信号VECK为低电平信号，第二时钟信号端ECB输出的第二时钟信号VECB为高电平信号，输入电压端ESTV输出的输入电压Vin为高电平信号。
由于第一时钟信号VECK为低电平信号，输入晶体管T1导通，输入电压Vin(高电平信号)经由输入晶体管T1传输至第一节点n1，而第二隔离晶体管T11也导通，从而输入电压Vin还经由第二隔离晶体管T11传输至第二输出节点OP2，从而使得第一节点n1和第二输出节点OP2均处于高电平。第二控制信号Vctr2包括第一电平信号，第一电平信号为在输入阶段A时第二输出节点OP2的电压，即输入电压Vin，由于此时输入电压Vin与第一电压信号VH的电压相等，也即第一电平信号为第一电压信号VH，也即第二控制信号Vctr2为第一电压信号VH。
在第一节点n1和第二输出节点OP2的高电平控制下，第二上拉晶体管T5、第二控制输出晶体管T8、第二输出晶体管T10、第二自举晶体管T13均处于截止状态。由于第二时钟信号VECB为高电平信号，第一上拉晶体管T2和第一输出控制晶体管T7在第二时钟信号VECB的高电平控制下也均处于截止状态。
由于第一上拉晶体管T2和第二上拉晶体管T5均处于截止状态，第二节点n2的电压不会受到第一电压端VGH的影响。此时，第一下拉晶体管T3在第一时钟信号VECK的低电平控制下处于导通状态，第一时钟信号VECK的低电平经由第一下拉晶体管T3传输至第二节点n2，使得第二节点n2处于低电平。由于第一下拉晶体管T3传递低电平信号具有阈值损失，从而第二节点n2的电压为VECK1-Vth3，其中，Vth3表示第一下拉晶体 管T3的阈值电压，VECK1为处于低电平的第一时钟信号VECK，VECK1＝VL，即第二节点n2的电压为VL-Vth3。由于第一隔离晶体管T12导通，第二节点n2的电压经由第一隔离晶体管T12传递至第一自举晶体管T6的栅极，使得第一自举晶体管T6的栅极也处于低电平。例如，第一隔离晶体管T12的阈值电压表示为Vth12，同理，由于第一隔离晶体管T12传递低电平信号具有阈值损失，第一自举晶体管T6的栅极的电压为VL-VthN，其中，VthN为Vth3和Vth12中阈值电压较小的一个。
第一自举晶体管T6的栅极接收到的电压VL-VthN可以控制第一自举晶体管T6导通，第二时钟信号VECB的高电平信号经由第一自举晶体管T6写入第三节点n3，使得第三节点n3处于高电平。例如，第三节点n3的电压Vn3在输入阶段A为高电平的第二时钟信号VECB，即第一电压信号VH。
由于第一控制输出晶体管T7和第二控制输出晶体管T8均处于截止状态，第一输出节点OP1的电压不变，第一控制信号Vctr1为高电平信号，也即第一输出晶体管T9的栅极电压维持上一阶段的状态不变，仍处于高电平，因而第一输出端Eout仍维持上一阶段的状态保持不变，第一输出信号Vout仍为低电平信号。
在第一阶段B，在第一控制信号Vctr1的控制下，将第一电压信号VH输出至第一输出端Eout。例如，如图4A和图3B所示，在第一阶段B，第一时钟信号端ECK输出的第一时钟信号VECK为高电平信号，第二时钟信号端ECB输出的第二时钟信号VECB为低电平信号，输入电压端ESTV输出的输入电压Vin为低电平信号。
由于第一时钟信号VECK为高电平信号，输入晶体管T1截止，第一节点n1和第二输出节点OP2的电压不变，即第一节点n1的电压和第二输出节点OP2的电压仍然均为第一电压信号VH。此时，第二控制信号Vctr2仍为第一电平信号，第二上拉晶体管T5、第二控制输出晶体管T8、第二输出晶体管T10、第二自举晶体管T13均在第一节点n1和第二输出节点OP2的高电平控制下仍处于截止状态。
由于第一时钟信号VECK为高电平信号，第一下拉晶体管T3处于截止状态，虽然第一上拉晶体管T2在第二时钟信号VECB的控制下处于开启状态，但由于第二上拉晶体管T5处于截止状态，第二节点n2的电压不变，即第二节点n2的电压仍然为VL-Vth3。
第一自举晶体管T6仍处于开启状态，第二时钟信号VECB的低电平信号(即第二电压信号VL)经由第一自举晶体管T6写入第三节点n3，使得第三节点n3的电压Vn3由高电平跳变至低电平。由于第一电容C1的耦合作用，当第三节点n3的电压Vn3从高电平跳变至低电平时，第一自举晶体管T6的栅极的电压也发生跳变，第一自举晶体管T6的栅极的电压跳变为VL-VthN-ΔV，其中，ΔV表示高电平跳变至低电平的电位差，VL-VthN-ΔV小于VL-VthN，从而第一自举晶体管T6的栅极的电压变得更低，因而第一自举晶体管T6可以更好地打开，从而使得低电平的第二时钟信号VECB可以无阈值损失地传输至第三节点n3，即此时第三节点n3的电压为低电平的第二时钟信号VECB，即第二电压信号VL，该低电平的第二时钟信号VECB即为第一中间信号，也就是说，第一中间信号为第二电压信号VL。
第一控制输出晶体管T7在第二时钟信号VECB的低电平信号的控制下导通，将基于第一中间信号确定的第二中间信号Vmid2写入第一输出节点OP1。由于第一控制输出晶体管T7传递低电平信号具有阈值损失，从而第二中间信号Vmid2的电压为VL-Vth7，其中，Vth7表示第一控制输出晶体管T7的阈值电压，也即在第一阶段B，第一输出节点OP1的电压为VL-Vth7，第一控制信号Vctr1为第二中间信号Vmid2，也即VL-Vth7。
第一控制信号Vctr1为第二中间信号Vmid2，第二中间信号Vmid2为低电平信号，从而在第一阶段B，在第一控制信号Vctr1(即第二中间信号Vmid2)控制下，第一输出晶体管T9和保持晶体管T4导通，第一电压信号VH通过第一输出晶体管T9写入第一输出端Eout，完成高电平输出，此时第一输出信号Vout为第一电压信号VH；第一电压信号VH经由保持晶体管T4写入第一节点n1，维持第一节点的高电平，避免在第一阶段B第二上拉晶体管T5被错误地打开。
在缓冲阶段C，在第二输出节点OP2的电压的控制下，将基于第二电压信号VL得到的第三电压信号VL1输出至第一输出端Eout。
例如，如图4A和图3B所示，在缓冲阶段C，第一时钟信号端ECK输出的第一时钟信号VECK为低电平信号，第二时钟信号端ECB输出的第二时钟信号VECB为高电平信号，输入电压端ESTV输出的输入电压Vin为低电平信号。
第一下拉晶体管T3在第一时钟信号VECK的低电平控制下处于导通状态，低电平的第一时钟信号VECK经由第一下拉晶体管T3传输至第二节点n2，使得第二节点n2保持在低电平，同时，由于第一隔离晶体管T12导通，第二节点n2的电压经由第一隔离晶体管T12传递至第一自举晶体管T6的栅极，使得第一自举晶体管T6的栅极也处于低电平，从而第一自举晶体管T6处于开启状态，将第二时钟信号VECB的高电平写入第三节点n3，使得第三节点n3处于高电平，也即第三节点n3的电压Vn3为高电平的第二时钟信号VECB。
第一控制输出晶体管T7在第二时钟信号VECB的高电平的控制下处于截止状态，输入晶体管T1在第一时钟信号VECK的低电平的控制下导通，低电平的输入电压Vin经由输入晶体管T1传输至第一节点n1，从而使得第一节点n1处于低电平，第二控制输出晶体管T8在第一节点n1的电压的控制下导通，第一电压信号VH经由第二控制输出晶体管T8传输至第一输出节点OP1，并对存储电容C3充电使得第一输出节点OP1处于高电平，也即此时第一控制信号Vctr1为第一电压信号VH，第一输出晶体管T9和保持晶体管T4在第一控制信号Vctr1的控制下均处于截止状态。
由于第一时钟信号VECK为低电平信号，输入晶体管T1导通，输入电压Vin的低电平VL经由输入晶体管T1传输至第一节点n1，而第二隔离晶体管T11也导通，从而输入电压Vin还经由第二隔离晶体管T11传输至第二输出节点OP2，从而使得第一节点n1和第二输出节点OP2均处于低电平。由于输入晶体管T1传递低电平信号具有阈值损失，从而第一节点n1的电压为Vin-Vth1，即VL-Vth1，其中，Vth1表示输入晶体管T1的阈值电压。例如，第二隔离晶体管T11的阈值电压表示为Vth11，同理，由于第二隔离晶体管 T11传递低电平信号具有阈值损失，第二输出节点OP2的电压为VL-VthM，其中，VthM为Vth1和Vth11中阈值电压较小的一个。第二控制信号Vctr2包括第二电平信号(如图4A所示的VL2)，第二电平信号VL2为在输入阶段C时第二输出节点OP2的电压，即VL-VthM，也即图4A所示的VL2的电平为VL-VthM。
在第一节点n1和第二输出节点OP2的低电平控制下，第二上拉晶体管T5、第二控制输出晶体管T8、第二输出晶体管T10、第二自举晶体管T13均处于导通状态。第一上拉晶体管T2和第一输出控制晶体管T7在第二时钟信号VECB的高电平控制下均处于截止状态。
在缓冲阶段C，第二输出晶体管T10在第二控制信号Vctr2的低电平(即第二电平信号VL2)控制下处于导通状态，第二电压信号VL经由第二输出晶体管T10传输至第一输出端Eout，由于第二输出晶体管T10传递低电平信号具有阈值损失，第二电压信号VL并不能完全被输出至第一输出端Eout，此时，第一输出端Eout为第三电压信号VL1，第三电压信号VL1的电压为VL-Vth10-VthM，其中，Vth10表示第二输出晶体管T10的阈值电压。
在稳定阶段D，在第二输出节点OP2的电压的控制下，将第二电压信号VL输出至第一输出端Eout，使得最终第一输出信号Vout从第三电压信号VL1降低至第二电压信号VL。
例如，如图4A和图3B所示，在稳定阶段D，第一时钟信号端ECK输出的第一时钟信号VECK为高电平信号，第二时钟信号端ECB输出的第二时钟信号VECB为低电平信号，输入电压端ESTV输出的输入电压Vin为低电平信号。
由于第一时钟信号VECK为高电平信号，输入晶体管T1截止，第一节点n1和第二输出节点OP2的电压维持缓冲阶段C的低电平不变，第二上拉晶体管T5和第二控制输出晶体管T8在第一节点n1的低电平控制下处于导通状态，第二输出晶体管T10和第二自举晶体管T13在第二输出节点OP2的低电平控制下处于导通状态。
第一上拉晶体管T2在第二时钟信号VECB的低电平控制下也处于导通状态，第一电压信号VH经由第一上拉晶体管T2和第二上拉晶体管T5传输至第二节点n2，使得第二节点n2处于高电平，第二节点n2的电压经由第一隔离晶体管T12传输至第一自举晶体管T6的栅极，从而第一自举晶体管T6处于截止状态，第一控制输出晶体管T7在第二时钟信号VECB的低电平控制下也处于导通状态。
第一电压信号VH经由第二控制输出晶体管T8传输至第一输出节点OP1，并对存储电容C3充电使得第一输出节点OP1保持高电平，此时第一控制信号Vctr1为第一电压信号VH，第一输出晶体管T9和保持晶体管T4在第一控制信号Vctr1的控制下均处于截止状态。
由于第二自举晶体管T13处于导通状态，输入晶体管T1和保持晶体管T4处于截止状态，第二输出节点OP2的电压仅受到第二电容C2的影响。从缓冲阶段C到稳定阶段D，第二时钟信号VECB产生了从高电平到低电平的电压跳变，由于第二自举晶体管T13导 通，从而第二电容C2的第二端的电压也产生从高电平到低电平的跳变，在第二电容C2的耦合作用下，第二电容C2的第一端，即第二输出节点OP2，的电压产生跳变，从而使得第二输出节点OP2的电压降得更低，在第二输出节点OP2的电压的控制下，第二自举晶体管T13充分开启，从而使得低电平的第二时钟信号VECB可以经由第二自举晶体管T13无阈值损失地传输至第二电容C2的第二端，由此可知，此时第二电容C2的第二端的电压从高电平的第二时钟信号VECB(即第一电压信号VH)跳变至低电平的第二时钟信号VECB(第二电压信号VL)，电压跳变的电压差为VH-VL。此时，第二控制信号Vctr2为第三电平信号(也即图4A所示的VL3)，第二输出节点OP2的电压从第二电平信号VL2跳变至第三电平信号VL3，第三电平信号VL3的电压为(VL-VthM-ΔV)，也即图4A所示的VL3的电平为(VL-VthM-ΔV)，第三电平信号VL3与第二电平信号VL2之间的电压绝对值差为电压跳变的电压差。
此时，由于第三电平信号低于第二电平信号，第二输出晶体管T10可以更好地打开，使得第二电压信号VL可以被无阈值损失地输出至第一输出端Eout，此时，第一输出信号Vout可以达到第二电压信号VL。
之后，在下一个输入电压Vin的高电平到来之前，第一节点n1的电压维持低电平，因此第二上拉晶体管T8一直处于导通状态，从而维持第一输出节点OP1的高电平，第一输出晶体管T9一直处于截止状态；此外，在第二时钟信号VECB的控制下，第二输出节点OP2的电压周期性地被拉低，也即第二控制信号Vctr2周期性地在第二电压信号VL2和第三电压信号VL3之间变化，从而保证第一输出信号Vout保持为低电平的第二电压信号VL，整个电路持续维持稳定阶段D的输出状态，后续阶段不再赘述。
需要说明的是，在本公开的实施例中，第一控制信号Vctr1包括在各个阶段(即输入阶段A、第一阶段B、缓冲阶段C和稳定阶段D)下第一输出节点OP1的电压，第二控制信号Vctr2包括在各个阶段下第二输出节点OP2的电压。
图4B是本公开另一实施例提供的一种移位寄存器的驱动时序图，该驱动时序图用于驱动图3C所示的移位寄存器。也就是说，当第二控制输入子电路202与输入电路100的输入端电连接，也就是与输入电压端ESTV电连接时，需要采用图4B所示的驱动时序图。此时，要求输入电压Vin处于第一电平(例如是高电平)下的脉冲宽度大于第一时钟信号VECK的周期和第二时钟信号VECB的周期。
如图4B所示，第一时钟信号VECK的周期和第二时钟信号VECB的周期相同，输入电压Vin处于高电平下的脉冲宽度大于第一时钟信号VECK的周期和第二时钟信号VECB的周期。
图4B所示的驱动时序图对应的移位寄存器的电路功能与图3A和图3B所示的移位寄存器完全相同，如图4B所示，该移位寄存器的工作过程也包括输入阶段A、第一阶段B、缓冲阶段C和稳定阶段D，关于输入阶段A、缓冲阶段C和稳定阶段D，其电路操作与前述过程完全相同，这里不再赘述；关于第一阶段B，在第一阶段B生成的第一控制信号Vctr1仍为低电平信号，第二控制信号Vctr1仍为高电平信号，从而可以控制第一输出端 输出第一电压信号VH，具体电路操作过程与前述内容相似，这里不再赘述。
图5A为本公开至少一实施例提供的移位寄存器的示意性框图。如图5A所示，在图2B所示的移位寄存器基础上，该移位寄存器还包括输出反相电路500，输出反相电路500分别与第一输出节点OP1、第一电压端VGH、第二电压端VGL、第一输出端Eout和第二输出端REout电连接，且被配置为将第一输出信号Vout进行反相以得到第二输出信号Rout，并将第二输出信号Rout输出至第二输出端REout。
需要说明的是，也可以在图2A所示的移位寄存器的基础上添加输出反相电路500，以得到与第一输出信号Vout反相的第二输出信号Rout，具体连接关系这里不再赘述。
如图5A所示，输出反相电路包括第一输出反相子电路501、第二输出反相子电路502和输出反相控制子电路503。
输出反相控制子电路503分别与第一电压端VGH、第一输出节点OP1、第二电压端VGL以及第四节点n4电连接，且被配置为在第一控制信号Vctr1、第一输出信号Vout的控制下，输出第四控制信号Vctr4至第四节点n4，利用第四控制信号Vctr4控制第二电压端VGL和第二输出端REout之间的导通和截止。
第一输出反相子电路501分别与第一电压端VGH、第一输出端Eout和第二输出端REout电连接，且被配置为在第一输出信号Vout的控制下，在第二阶段将第一电压信号VH写入第二输出端REout。例如，在第二阶段，第一输出反相子电路501在第一输出信号Vout的控制下导通，也即连接至第一电压端VGH的第一输出反相子电路501的一端和连接至第二输出端REout的第一输出反相子电路501的另一端导通，第一电压信号VH写入第二输出端REout，并且此时，第二输出反相子电路502在第四控制信号Vctr4的控制下截止。
第二输出反相子电路502分别与第二电压端VGL、第四节点n4和第二输出端REout电连接，且被配置为在第四控制信号Vctr4的控制下，在第一阶段将第二电压信号VL写入第二输出端REout。例如，在第一阶段，第二输出反相子电路502在第四控制信号Vctr4的控制下导通，也即连接至第二电压端VGL的第二输出反相子电路502的一端和连接至第二输出端REout的第二输出反相子电路502的另一端导通，第二电压信号VL写入第二输出端REout，并且此时，第一输出反相子电路501在第一输出信号Vout的控制下截止。
例如，第二输出信号Rout包括位于第一阶段的第二电压信号VL和位于第二阶段的第一电压信号VH。
例如，输出反相控制子电路503包括上拉子电路5031、第二下拉子电路5032和第三自举子电路5033。
上拉子电路5031分别与第一电压端VGH、第一输出端Eout和第四节点n4电连接，且被配置为在第一输出信号Vout的控制下，将第一电压信号VH写入第四节点n4。例如，当上拉子电路5031在第一输出信号Vout的控制下导通时，也即连接至第一电压端VGH的上拉子电路5031的一端和连接至第四节点n4的上拉子电路5031的另一端导通时，第一电压信号VH被写入第四节点n4，使得第四节点n4处于高电平。
下拉子电路5032分别与第一输出节点OP1、第二电压端VGL和第四节点n4电连接，且被配置为在第一控制信号Vctr1的控制下，将基于第二电压信号VL确定的第三中间信号Vmid3写入第四节点n4。例如，当下拉子电路5032在第一控制信号Vctr1的控制下导通时，也即连接至第二电压端VGL的下拉子电路5032的一端和连接至第四节点n4的下拉子电路5032的另一端导通时，基于第二电压信号VL确定的第三中间信号Vmid3被写入第四节点n4，使得第四节点n4处于低电平。
第三自举子电路5033分别与第四节点n4、第一时钟信号端ECK电连接，被配置为在第四节点的电压的控制下，将基于第三中间信号Vmid3和第一时钟信号VECK确定的第四中间信号Vmid4写入第四节点n4。例如，在第三自举子电路5033的自举作用下，第四节点n4的电压Vn4可以低于第二时钟信号VECK在低电平下时的电压，并且，基于自举作用得到的第四中间信号Vmid4的电压绝对值大于第三中间信号Vmid3的电压绝对值。
第四控制信号包括第一电压信号、第三中间信号Vmid3和第四中间信号Vmid4。
图5B为本公开一实施例提供的移位寄存器的结构示意图。该移位寄存器为在基于图3C所示的移位寄存器的基础上增加了输出反相电路500，因此，关于输入电路100、第一控制电路200、第二控制电路300以及输出电路400的结构描述参考图3A至图3C所示的结构示意图的相关的结构描述，这里不再赘述。
需要说明的是，对于包含输出反相电路500的移位寄存器不限于图5B所示的结构，输入电路100、第一控制电路200、第二控制电路300以及输出电路400可以参考本公开任意实施例进行变形、组合，本公开对此不作限制。例如，也可以基于图3A以及图3B所示的移位寄存器，在其基础上增加输出反相电路500，本公开对此不作限制。
下面以图5B为例，具体说明包含输出反相电路500的移位寄存器的结构关系。
第一输出反相子电路501包括第一输出反相晶体管T17，第二输出反相子电路502包括第二输出反相晶体管T16。
第一输出反相晶体管T17的栅极与第一输出端Eout电连接，第一输出反相晶体管T17的第一极与第一电压端VGH电连接，第一输出反相晶体管T17的第二极与第二输出端REout电连接。
第二输出反相晶体管T16的栅极与第四节点n4电连接，第二输出反相晶体管T16的第一极与第二电压端VGL电连接，第二输出反相晶体管T16的第二极与第二输出端REout电连接。
上拉子电路5031包括第三上拉晶体管T15，第三上拉晶体管T15的栅极与第一输出端Eout电连接，第三上拉晶体管T15的第一极与第一电压端VGH电连接，第三上拉晶体管T15的第二极与第四节点n4电连接。
下拉子电路5032包括第二下拉晶体管T14，第二下拉晶体管T14的栅极与第一输出节点OP1电连接，第二下拉晶体管T14的第一极与第二电压端VGL电连接，第二下拉晶体管T14的第二极与第四节点n4电连接。
第三自举子电路5033包括第三电容C4和第三自举晶体管T18，第三电容C4的第一 端和第三自举晶体管T18的栅极均电连接至第四节点n4，第三自举晶体管T18的第二极与第三电容C4的第二端电连接，第三自举晶体管T18的第一极与第一时钟信号端ECK电连接。
图5C是本公开一实施例提供的另一种移位寄存器的驱动时序图。接下来以图5B所示的移位寄存器和图5C所示的驱动时序为例介绍本公开实施例提供的移位寄存器的工作原理。
例如，如图5C所示，本公开实施例提供的移位寄存器的工作过程包括输入阶段A、第一输出阶段B1、第二输出阶段B2、缓冲阶段C和稳定阶段D，其中，第一阶段包括第一输出阶段B1、第二输出阶段B2，第二阶段包括输入阶段A、缓冲阶段C和稳定阶段D。
对于输入电路100、第一控制电路200、第二控制电路300以及输出电路400，其在输入阶段A、缓冲阶段C和稳定阶段D的工作过程可以参考前述内容的描述，这里不再赘述。前述工作过程中的第一阶段B在这里被划分为第一输出阶段B1和第二输出阶段B2，工作过程完全相同，因此关于输入电路100、第一控制电路200、第二控制电路300以及输出电路400在第一输出阶段B1和第二输出阶段B2的工作过程的描述可以参考前述关于第一阶段B的描述，这里不再赘述。
下面针对输出反相电路500的工作过程进行描述。
例如，在输入阶段A，第一时钟信号端ECK输出的第一时钟信号VECK为低电平信号，第二时钟信号端ECB输出的第二时钟信号VECB为高电平信号，输入电压端ESTV输出的输入电压Vin为高电平信号，第一输出信号Vout为低电平信号。
根据前述关于输入阶段A的描述，由于第一控制输出晶体管T7和第二控制输出晶体管T8均处于截止状态，第一输出节点OP1的电压不变，仍处于高电平，因此第二下拉晶体管T14在第一输出节点OP1的电压的控制下处于截止状态。第一输出端Eout在输入阶段A维持上一阶段的状态保持不变，此时，第一输出信号Vout为低电平信号，因此在第一输出信号Vout的控制下，第三上拉晶体管T15和第一输出反相晶体管T17处于导通状态，第一电压信号VH经由第三上拉晶体管T15写入第四节点n4，使得第四节点n4处于高电平，也即第四节点的电压Vn4为高电平VH，从而控制第二输出反相晶体管T16处于截止状态；第一电压信号VH经由第一输出反相晶体管T17写入第二输出端REout，也即此时第二输出信号Rout为第一电压信号VH。
在第一输出阶段B1，第一时钟信号端ECK输出的第一时钟信号VECK为高电平信号，第二时钟信号端ECB输出的第二时钟信号VECB为低电平信号，输入电压端ESTV输出的输入电压Vin为高电平信号，第一输出信号Vout为高电平信号。
根据前述关于第一阶段B的描述，此时第一输出信号Vout为第一电压信号VH，因此第三上拉晶体管T15和第一输出反相晶体管T17处于截止状态，第四节点n4的电压Vn4不再受第一电压端VGH的影响。第一输出节点OP1的电压为VL-Vth7，也即此时第一控制信号Vctrl1为低电平，在第一控制信号Vctrl1的控制下，第二下拉晶体管T14处于导通状态，将基于第二电压信号VL确定的第三中间信号Vmid3写入第四节点n4。由 于第二下拉晶体管T14传递低电平信号具有阈值损失，从而第三中间信号Vmid3的电压为VL-Vth7-Vth14，其中，Vth7表示第一控制输出晶体管T7的阈值电压，Vth14表示第二下拉晶体管T14的阈值电压，也即此时第四节点n4的电压Vn4为VL-Vth7-Vth14，并且，当第四节点n4的电压Vn4达到VL-Vth7-Vth14时，第二下拉晶体管T14截止。
第三自举晶体管T18在第四节点n4的电压Vn4的控制下处于开启状态，并将第一时钟信号VECK的高电平传输至第三电容C4的第二端，使得第三电容C4的第二端处于高电平。
由于第四节点n4的电压Vn4为VL-Vth7-Vth14，第二输出反相晶体管T16处于一定程度的开启状态，第二输出反相晶体管T16传递低电平信号具有阈值损失，当第二输出端REout输出的第二输出信号Rout的电压达到VL-Vth14-Vth16时，第二输出反相晶体管T16截止，第二输出信号Rout的电压不再下降，从而在第一输出阶段B1，第二输出信号Rout的电压为VL-Vth14-Vth16，第二输出端REout输出的低电平不能达到第二电压信号VL的电位。
在第二输出阶段B2，当输入电压Vin处于高电平时，第一时钟信号端ECK输出的第一时钟信号VECK为低电平信号，第二时钟信号端ECB输出的第二时钟信号VECB为高电平信号；当输入电压Vin处于低电平时，第一时钟信号端ECK输出的第一时钟信号VECK为高电平信号，第二时钟信号端ECB输出的第二时钟信号VECB为低电平信号；第一输出信号Vout在第二输出阶段B2均为高电平信号。
当输入电压Vin处于高电平时，此时第一控制信号Vctrl1为低电平信号，第一输出信号Vout为高电平信号，因此第三上拉晶体管T15和第一输出反相晶体管T17仍处于截止状态，第二下拉晶体管T14和第二输出反相晶体管T16也均处于截止状态。
从第一输出阶段B1至第二输出阶段B2，第一时钟信号VECK从高电平跳变至低电平，由于第三电容C4的耦合作用，使得第四节点n4的电压Vn4降为Vmid3-ΔV，也即第四中间信号Vmid4的电压为Vmid3-ΔV，ΔV表示高电平跳变至低电平的电位差。由于第四节点n4的电压Vn4下降到比VL还要低很多的电压值，第二输出反相晶体管T16被更好地打开，从而第二电压信号VL可以无阈值损失地输出至第二输出端REout，也即第二输出信号Rout达到第二电压信号VL的电压。
当输入电压Vin处于低电平时，由于第一控制信号Vctrl1、第一输出信号Vout和第四节点n4的电压Vn4状态维持不变，因而第二输出信号Rout仍为第二电压信号VL。
在缓冲阶段C，第一时钟信号端ECK输出的第一时钟信号VECK为低电平信号，第二时钟信号端ECB输出的第二时钟信号VECB为高电平信号，输入电压端ESTV输出的输入电压Vin为低电平信号，第一输出信号Vout为低电平信号，也即第三电压信号。
根据前述缓冲阶段C的描述，第一控制信号Vctr1为第一电压信号VH，也即此时第一输出节点OP1处于高电平，因而第二下拉晶体管T14处于截止状态。第一输出信号Vout为第三电压信号VL1，第三电压信号VL1的电压绝对值小于第二电压信号VL，在第三电压信号VL1的控制下，第三上拉晶体管T15和第一输出反相晶体管T17均导通。第一电 压信号VH经由第三上拉晶体管T15写入第四节点n4，使得第四节点n4处于高电平，此时，第四节点n4的电压Vn4为第一电压信号VH，第二输出反相晶体管T16处于截止状态；第一电压信号VH经由第一输出反相晶体管T17写入第二输出端REout，第二输出端REout输出高电平信号，也即此时第二输出信号Rout为第一电压信号VH。
在稳定阶段D，第一时钟信号端ECK输出的第一时钟信号VECK为高电平信号，第二时钟信号端ECB输出的第二时钟信号VECB为低电平信号，输入电压端ESTV输出的输入电压Vin为低电平信号，第一输出信号Vout为低电平信号，也即第二电压信号VL。
与缓冲阶段C类似，在第一输出节点OP1的高电平控制下，第二下拉晶体管T14处于截止状态，在第二电压信号VL的控制下，第三上拉晶体管T15和第一输出反相晶体管T17均导通，从而第二输出反相晶体管T16也处于截止状态；第一电压信号VH经由第一输出反相晶体管T17写入第二输出端REout，第二输出端REout仍输出高电平信号，也即此时第二输出信号Rout为第一电压信号VH。
图5D为本公开至少一实施例提供的再一种移位寄存器的示意性框图。如图5D所示，在图2A所示的移位寄存器基础上，该移位寄存器还包括输出反相电路500，输出反相电路500分别与第一输出节点OP1、第一电压端VGH、第二电压端VGL、第一输出端Eout和第二输出端REout电连接，且被配置为将第一输出信号Vout进行反相以得到第二输出信号Rout，并将第二输出信号Rout输出至第二输出端REout。
关于图5D所示的输出反相电路500的移位寄存器的结构关系以及驱动时序图可以参考前述内容，重复之处不再赘述。
图6为本公开一实施例提供的一种栅极驱动电路的示意性框图，图7A本公开一实施例提供的一种栅极驱动电路的结构示意图。
本公开至少一实施例还提供一种栅极驱动电路，如图6所示，该栅极驱动电路1包括本公开上述实施例中任一项所述的移位寄存器10。本公开提供的栅极驱动电路可以通过移位寄存器10输出与晶体管的开启电平相反的电平，例如，当晶体管为P型晶体管时，输出高电平脉冲。
例如，如图7A所示，栅极驱动电路1包括级联的多个移位寄存器SR1、SR2、SR3……SRn。这些移位寄存器SR1、SR2、SR3……SRn均可以是本公开上述实施例中任一项所述的移位寄存器。这些移位寄存器SR1、SR2、SR3……SRn的第一输出端Eout分别与多条栅线G1、G2、G3……Gn(未示出)一一对应连接。
例如，除第一级移位寄存器之外，第M级移位寄存器的第一输出端作为第M+1级移位寄存器所连接的输入电压端，这里，M为正整数，且M大于1。从而通过上一级移位寄存器的第一输出信号控制下一级移位寄存器的工作状态，以实现依次输出脉冲扫描信号。
例如，第一级移位寄存器SR1的输入电压端ESTV与触发信号端STV0(其被配置为提供触发信号，以控制栅极驱动电路开始工作)连接，以接收触发信号作为输入电压Vin。
例如，如图6所示，栅极驱动电路1还包括信号生成电路20。如图7A所示，信号生 成电路20被配置为生成第一信号CK和第二信号CB。例如，对于第2N-1级移位寄存器，第一信号CK为上述移位寄存器的实施例中的第一时钟信号VECK，第二信号CB为上述移位寄存器的实施例中的第二时钟信号VECB。对于第2N级移位寄存器，第一信号CK为上述移位寄存器的实施例中的第二时钟信号VECB，第二信号CB为上述移位寄存器的实施例中的第一时钟信号VECK。第一信号CK和第二信号CB交替控制奇数级和偶数级的移位寄存器，从而减少信号数量，降低生产成本。
例如，如图7A所示，第一信号CK被施加至第2N-1级移位寄存器所连接的第一时钟信号端ECK和第2N级移位寄存器所连接的第二时钟信号端ECB；第二信号CB被施加至第2N-1级移位寄存器所连接的第二时钟信号端ECB和第2N级移位寄存器所连接的第一时钟信号端ECK，其中，N为正整数，且N大于等于1，且小于n/2。需要说明的是，n可以为偶数，也可以为奇数，本公开对此不作限制，在图7A所示的示例中，n为偶数。
需要说明的是，上述的“上一级”和“下一级”并不是指扫描时序上的上一级和下一级，而是指物理连接上的上一级和下一级。
例如，以第一级移位寄存器SR1和第二级移位寄存器SR2为例，触发信号端STV0向第一级移位寄存器SR1提供触发信号STV0作为输入电压Vin，从而控制第一级移位寄存器SR1开始工作，在第一信号CK、第二信号CB的控制下，第一级移位寄存器SR1向栅线G1输出第一输出信号Vout(1)作为扫描信号，并将第一级移位寄存器SR1输出的第一输出信号Vout(1)传输至第二级移位寄存器SR2以作为第二级移位寄存器SR2的输入电压，从而控制第二级移位寄存器SR2开始工作。在第一信号CK、第二信号CB的控制下，第二级移位寄存器SR2向栅线G2输出第二输出信号Vout(2)作为扫描信号，并将第二级移位寄存器SR2输出的第一输出信号Vout(2)传输至其下一级移位寄存器以作为其下一级移位寄存器的输入电压，依次类推，最终栅极驱动电路完成一帧的扫描工作。
图7B为本公开一实施例提供的另一种栅极驱动电路的结构示意图。
该栅极驱动电路1包括本公开上述实施例中包含输出反相电路的移位寄存器，例如，如图5A及图5B所示的移位寄存器。
如图7B所示，这些移位寄存器SR1、SR2、SR3……SRn除第一输出端Eout外，还具有第二输出端REout，第二输出端REout输出与第一输出信号Vout反相的第二输出信号Rout，例如，第二输出信号Rout(1)为与第一输出信号Vout(1)反相的信号，第二输出信号Rout(2)为与第一输出信号Vout(2)反相的信号，以此类推。
栅极驱动电路1中的移位寄存器SR1、SR2、SR3……SRn的连接关系和扫描工作过程如前所述，这里不再赘述。
图8为本公开一实施例提供的一种显示装置的示意图。
本公开的实施例还提供一种显示装置50。如图8所示，显示装置50包括本公开任一实施例提供的栅极驱动电路1。
例如，如图8所示，本公开实施例提供的显示装置50还包括栅线2、数据线3以及由栅线2和数据线3交叉限定的多个像素单元4，栅极驱动电路1被配置为向栅线2提供 栅极驱动信号。
例如，移位寄存器SR1、SR2、SR 3……SRn中的每一级移位寄存器用于向对应的栅线G1、G2、G3……Gn输出一行栅极驱动信号。
例如，显示装置50可以为应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一实施例还提供一种移位寄存器的驱动方法，用于驱动根据本公开至少一实施例提供的移位寄存器。
图9本公开一实施例提供的一种驱动方法的流程图。
本公开的实施例还提供一种移位寄存器的驱动方法，如图9所示，该驱动方法包括如下步骤：
步骤S10：在输入阶段，将输入电压输入至第一节点。
步骤S20：在第一阶段，在第一控制信号的控制下，将第一电压信号输出至第一输出端。
步骤S30：在稳定阶段，在第二控制信号的控制下，将第二电压信号输出至第一输出端。
本公开的实施例提供的移位寄存器的驱动方法可以实现P型晶体管输出与P型晶体管的开启电平相反的电平，例如，高电平脉冲。
需要说明的是，本公开实施例提供的驱动方法的具体操作过程可以参考上述移位寄存器的实施例中对输入阶段A、第一阶段B、缓冲阶段C和稳定阶段D的相关描述，重复之处在此不再赘述。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (35)

  1. 一种移位寄存器，包括：输入电路、第一控制电路、第二控制电路和输出电路，其中，
    所述输入电路，分别与输入电压端、第一时钟信号端和第一节点电连接，被配置为在所述第一时钟信号端提供的第一时钟信号的控制下，将所述输入电压端提供的输入电压输入到所述第一节点；
    所述第一控制电路，分别与所述第一时钟信号端、第二时钟信号端、第一电压端、所述第一节点和第一输出节点电连接，被配置为在所述第一时钟信号、所述第一节点的电压和所述第二时钟信号端提供的第二时钟信号的控制下，输出第一控制信号至所述第一输出节点；
    所述第二控制电路，分别与所述第一节点、所述第二时钟信号端和第二输出节点电连接，且被配置为在所述第一节点的电压的控制下，输出第二控制信号至所述第二输出节点；
    所述输出电路，分别与所述第一电压端、第二电压端、所述第一输出节点、所述第二输出节点和第一输出端电连接，被配置为在所述第一控制信号以及所述第二控制信号的控制下，将所述第一电压端提供的第一电压信号或所述第二电压端提供的第二电压信号写入所述第一输出端作为第一输出信号。
  2. 根据权利要求1所述的移位寄存器，其中，所述第一控制电路被配置为，控制所述输出电路在第一阶段输出所述第一电压信号；
    所述第二控制电路被配置为，控制所述输出电路在第二阶段输出所述第二电压信号，
    所述第一输出信号包括位于所述第一阶段的所述第一电压信号和位于所述第二阶段的所述第二电压信号。
  3. 根据权利要求2所述的移位寄存器，其中，
    所述输出电路还被配置为，在所述第一控制信号以及所述第二控制信号的控制下，在所述第二阶段，将第三电压信号写入所述第一输出端，其中，所述第一输出信号还包括所述第三电压信号，所述第三电压信号的电压绝对值小于所述第二电压信号的电压绝对值。
  4. 根据权利要求1所述的移位寄存器，其中，所述第一控制电路包括第一控制输入子电路，
    所述第一控制输入子电路分别与所述第一时钟信号端和第二节点电连接，且被配置为在所述第一时钟信号的控制下，将第三控制信号写入所述第二节点。
  5. 根据权利要求1所述的移位寄存器，其中，所述第一控制电路还与所述输入电路电连接，
    所述第一控制电路包括第二控制输入子电路，
    所述第二控制输入子电路分别与所述输入电路、所述第二时钟信号端、所述第一电压端以及第二节点电连接，且被配置为在所述输入电压、所述第二时钟信号的控制下，将所述第一电压信号写入所述第二节点。
  6. 根据权利要求1所述的移位寄存器，其中，
    所述第一控制电路包括第一自举子电路、第一控制输出子电路和第二控制输出子电路，
    所述第一自举子电路分别与第二节点、第三节点和所述第二时钟信号端电连接，且被配置为在所述第二节点的电压的控制下，将第一中间信号写入所述第三节点；
    所述第一控制输出子电路分别与所述第二时钟信号端、所述第三节点和所述第一输出节点电连接，且被配置为在所述第二时钟信号的控制下，将第二中间信号写入所述第一输出节点；
    所述第二控制输出子电路分别与所述第一节点、所述第一电压端和所述第一输出节点电连接，且被配置为在所述第一节点的电压的控制下，将所述第一电压信号写入所述第一输出节点，
    其中，所述第一控制信号包括所述第二中间信号和所述第一电压信号。
  7. 根据权利要求5所述的移位寄存器，其中，所述输入电路包括连接至所述输入电压端的输入端和连接至所述第一节点的输出端，
    所述第二控制输入子电路与所述输入电路的输出端电连接，或者，所述第二控制输入子电路与所述输入电路的输入端电连接。
  8. 根据权利要求4所述的移位寄存器，其中，
    所述第一控制输入子电路包括第一下拉晶体管，所述第一下拉晶体管的第一极与所述第一时钟信号端电连接，所述第一下拉晶体管的第二极与所述第二节点电连接，所述第一下拉晶体管的栅极与所述第一时钟信号端电连接。
  9. 根据权利要求5所述的移位寄存器，其中，
    所述第二控制输入子电路包括第一上拉晶体管和第二上拉晶体管，所述第一上拉晶体管的第一极与所述第二上拉晶体管的第二极电连接，所述第一上拉晶体管的第二极与所述第二节点电连接，所述第一上拉晶体管的栅极与所述第二时钟信号端电连接，所述第二上拉晶体管的栅极与所述输入电路的输入端或所述输入电路的输出端电连接，所述第二上拉晶体管的第一极与所述第一电压端电连接。
  10. 根据权利要求6所述的移位寄存器，其中，
    所述第一自举子电路包括第一电容和第一自举晶体管，所述第一自举晶体管的栅极电连接至所述第二节点和所述第一电容的第一端，所述第一自举晶体管的第二极电连接至所述第一电容的第二端和所述第三节点，所述第一自举晶体管的第一极与所述第二时钟信号端电连接；
    所述第一控制输出子电路包括第一控制输出晶体管，所述第一控制输出晶体管的栅极与所述第二时钟信号端电连接，所述第一控制输出晶体管的第一极与所述第三节点电连接，所述第一控制输出晶体管的第二极与所述第一输出节点电连接；
    所述第二控制输出子电路包括第二控制输出晶体管，所述第二控制输出晶体管的栅极与所述第一节点电连接，所述第二控制输出晶体管的第一极与所述第一电压端电连接，所 述第二控制输出晶体管的第二极与所述第一输出节点电连接。
  11. 根据权利要求4-10任一项所述的移位寄存器，其中，所述第一控制电路还包括保持子电路，
    所述保持子电路分别与所述第一电压端、所述第一节点和所述第一输出节点电连接，且被配置为在所述第一阶段，维持所述第一节点的电平。
  12. 根据权利要求11所述的移位寄存器，其中，所述保持子电路包括保持晶体管，所述保持晶体管的第一极与所述第一电压端电连接，所述保持晶体管的第二极与所述第一节点电连接，所述保持晶体管的栅极与所述第一输出节点电连接。
  13. 根据权利要求4-12任一项所述的移位寄存器，其中，所述第一控制电路还与所述第二电压端电连接，
    所述第一控制电路还包括第一隔离子电路，所述第一隔离子电路的输入端与所述第二节点电连接，所述第一隔离子电路的输出端与所述第一自举子电路电连接，所述第一隔离子电路的控制端与所述第二电压端电连接。
  14. 根据权利要求13所述的移位寄存器，其中，所述第一隔离子电路包括第一隔离晶体管，所述第一隔离晶体管的第一极与所述第二节点电连接，所述第一隔离晶体管的第二极与所述第一自举子电路电连接，所述第一隔离晶体管的栅极与所述第二电压端电连接。
  15. 根据权利要求4-14任一项所述的移位寄存器，其中，所述第一控制电路还包括存储子电路，所述存储子电路分别与所述第一电压端和所述第一输出节点电连接，且被配置为存储所述第一输出节点的电压。
  16. 根据权利要求15所述的移位寄存器，其中，存储子电路包括存储电容，所述存储电容的第一端与所述第一电压端电连接，所述存储电容的第二端与所述第一输出节点电连接。
  17. 根据权利要求1-16任一项所述的移位寄存器，其中，所述第二控制电路包括第二自举子电路，所述第二自举子电路分别与所述第一节点、所述第二时钟信号端和所述第二输出节点电连接。
  18. 根据权利要求17所述的移位寄存器，其中，所述第二自举子电路包括第二电容和第二自举晶体管，所述第二自举晶体管的第一极与所述第二时钟信号端电连接，所述第二电容的第一端电连接至所述第二自举晶体管的栅极和所述第二输出节点，所述第二电容的第二端与所述第二自举晶体管的第二极电连接。
  19. 根据权利要求1-18任一项所述的移位寄存器，其中，所述第二控制电路还包括第二隔离子电路，所述第二隔离子电路的输入端与所述第一节点电连接，所述第二隔离子电路的输出端与所述第二输出节点电连接，所述第二隔离子电路的控制端与所述第二电压端电连接。
  20. 根据权利要求19所述的移位寄存器，其中，所述第二隔离子电路包括第二隔离晶体管，所述第二隔离晶体管的第一极与所述第一节点电连接，所述第二隔离晶体管的第 二极与所述第二输出节点电连接，所述第二隔离晶体管的栅极与所述第二电压端电连接。
  21. 根据权利要求1-20任一项所述的移位寄存器，其中，所述输出电路包括第一输出子电路和第二输出子电路，
    所述第一输出子电路分别与所述第一输出节点、所述第一电压端和所述第一输出端电连接，且被配置为在所述第一控制信号的控制下，在所述第一阶段将所述第一电压信号写入所述第一输出端；
    所述第二输出子电路分别与所述第二输出节点、所述第二电压端和所述第一输出端电连接，且被配置为在所述第二控制信号的控制下，在所述第二阶段将所述第二电压信号写入所述第一输出端。
  22. 根据权利要求21所述的移位寄存器，其中，
    所述第一输出子电路包括第一输出晶体管，所述第一输出晶体管的栅极与所述第一输出节点电连接，所述第一输出晶体管的第一极与所述第一电压端电连接，所述第一输出晶体管的第二极与所述第一输出端电连接；
    所述第二输出子电路包括第二输出晶体管，所述第二输出晶体管的栅极与所述第二输出节点电连接，所述第二输出晶体管的第一极与所述第二电压端电连接，所述第二输出晶体管的第二极与所述第一输出端电连接。
  23. 根据权利要求1-22任一项所述的移位寄存器，其中，所述移位寄存器还包括输出反相电路，所述输出反相电路分别与所述第一输出节点、所述第一电压端、所述第二电压端、所述第一输出端和第二输出端电连接，且被配置为将所述第一输出信号进行反相以得到第二输出信号，并将所述第二输出信号输出至所述第二输出端。
  24. 根据权利要求23所述的移位寄存器，其中，所述输出反相电路包括第一输出反相子电路、第二输出反相子电路和输出反相控制子电路，
    所述输出反相控制子电路分别与所述第一电压端、所述第一输出节点、所述第二电压端以及第四节点电连接，且被配置为在所述第一控制信号、所述第一输出信号的控制下，输出第四控制信号至所述第四节点；
    所述第一输出反相子电路分别与所述第一电压端、所述第一输出端和所述第二输出端电连接，且被配置为在所述第一输出信号的控制下，在所述第二阶段将所述第一电压信号写入所述第二输出端；
    所述第二输出反相子电路分别与所述第二电压端、所述第四节点和所述第二输出端电连接，且被配置为在所述第四控制信号的控制下，在所述第一阶段将所述第二电压信号写入所述第二输出端，
    所述第二输出信号包括位于所述第一阶段的第二电压信号和位于所述第二阶段的所述第一电压信号。
  25. 根据权利要求24所述的移位寄存器，其中，所述输出反相控制子电路包括上拉子电路、下拉子电路和第三自举子电路，
    所述上拉子电路分别与所述第一电压端、所述第一输出端和所述第四节点电连接，且 被配置为在所述第一输出信号的控制下，将所述第一电压信号写入所述第四节点；
    所述下拉子电路分别与所述第一输出节点、所述第二电压端和所述第四节点电连接，且被配置为在所述第一控制信号的控制下，将基于所述第二电压信号确定的第三中间信号写入所述第四节点；
    所述第三自举子电路分别与所述第四节点、所述第一时钟信号端电连接，被配置为在所述第四节点的电压的控制下，将基于所述第三中间信号和所述第一时钟信号确定的第四中间信号写入所述第四节点，
    其中，所述第四控制信号包括所述第一电压信号、所述第三中间信号和所述第四中间信号。
  26. 根据权利要求24或25所述的移位寄存器，其中，所述第一输出反相子电路包括第一输出反相晶体管，所述第二输出反相子电路包括第二输出反相晶体管，
    所述第一输出反相晶体管的栅极与所述第一输出端电连接，所述第一输出反相晶体管的第一极与所述第一电压端电连接，所述第一输出反相晶体管的第二极与所述第二输出端电连接；
    所述第二输出反相晶体管的栅极与所述第四节点电连接，所述第二输出反相晶体管的第一极与所述第二电压端电连接，所述第二输出反相晶体管的第二极与所述第二输出端电连接。
  27. 根据权利要求25所述的移位寄存器，其中，
    所述上拉子电路包括第三上拉晶体管，所述第三上拉晶体管的栅极与所述第一输出端电连接，所述第三上拉晶体管的第一极与所述第一电压端电连接，所述第三上拉晶体管的第二极与所述第四节点电连接；
    所述下拉子电路包括第二下拉晶体管，所述第二下拉晶体管的栅极与所述第一输出节点电连接，所述第二下拉晶体管的第一极与所述第二电压端电连接，所述第二下拉晶体管的第二极与所述第四节点电连接；
    所述第三自举子电路包括第三电容和第三自举晶体管，所述第三电容的第一端和所述第三自举晶体管的栅极均电连接至所述第四节点，所述第三自举晶体管的第二极与所述第三电容的第二端电连接，所述第三自举晶体管的第一极与所述第一时钟信号端电连接。
  28. 根据权利要求1-27任一项所述的移位寄存器，其中，所述输入电路包括输入晶体管，所述输入晶体管的第一极与所述输入电压端电连接，所述输入晶体管的第二极与所述第一节点电连接，所述输入晶体管的栅极与所述第一时钟信号端电连接。
  29. 一种栅极驱动电路，包括如权利要求1-28任一项所述的移位寄存器。
  30. 根据权利要求29所述的栅极驱动电路，其中，所述栅极驱动电路包括级联的多个所述移位寄存器，
    其中，除第一级移位寄存器之外，第M级移位寄存器的第一输出端作为第M+1级移位寄存器所连接的输入电压端，
    其中，M为正整数，且M大于1。
  31. 根据权利要求29或30所述的栅极驱动电路，还包括信号生成电路，
    其中，所述信号生成电路被配置为生成第一信号和第二信号，
    所述第一信号被施加至第2N-1级移位寄存器所连接的第一时钟信号端和第2N级移位寄存器所连接的第二时钟信号端；
    所述第二信号被施加至所述第2N-1级移位寄存器所连接的第二时钟信号端和所述第2N级移位寄存器所连接的第一时钟信号端；
    其中，N为正整数，且N大于等于1。
  32. 一种显示装置，包括如权利要求29-31任一项所述的栅极驱动电路。
  33. 一种移位寄存器的驱动方法，用于驱动如权利要求1-28任一项所述的移位寄存器，
    所述输出电路在第一阶段输出所述第一电压信号，以及在第二阶段输出所述第二电压信号，所述第二阶段包括输入阶段和稳定阶段，
    所述驱动方法包括：
    在所述输入阶段，将所述输入电压输入至所述第一节点；
    在所述第一阶段，在所述第一控制信号的控制下，将所述第一电压信号输出至所述第一输出端；
    在所述稳定阶段，在所述第二控制信号的控制下，将所述第二电压信号输出至所述第一输出端。
  34. 根据权利要求33所述的驱动方法，其中，所述第二阶段还包括缓冲阶段，
    所述驱动方法还包括：
    在所述缓冲阶段，在所述第二控制信号的控制下，将第三电压信号输出至所述第一输出端，
    其中，所述第一输出信号还包括所述第三电压信号，所述第三电压信号的电压绝对值小于所述第二电压信号的电压绝对值。
  35. 根据权利要求33或34所述的驱动方法，其中，在所述第一控制电路与所述输入电压端电连接的情况下，
    所述输入电压处于第一电平下的脉冲宽度大于所述第一时钟信号和所述第二时钟信号的周期。
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CN110164352A (zh) * 2019-04-28 2019-08-23 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路和显示面板
CN110313028A (zh) * 2019-05-16 2019-10-08 京东方科技集团股份有限公司 信号产生方法、信号发生电路以及显示装置
CN111445833A (zh) * 2020-05-09 2020-07-24 合肥京东方卓印科技有限公司 移位寄存器单元及其控制方法、和栅极驱动电路
CN111583850A (zh) * 2020-05-22 2020-08-25 昆山国显光电有限公司 移位寄存器、发光控制电路和显示面板

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