WO2021254319A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2021254319A1
WO2021254319A1 PCT/CN2021/100069 CN2021100069W WO2021254319A1 WO 2021254319 A1 WO2021254319 A1 WO 2021254319A1 CN 2021100069 W CN2021100069 W CN 2021100069W WO 2021254319 A1 WO2021254319 A1 WO 2021254319A1
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WIPO (PCT)
Prior art keywords
fan
sub
layer
lines
display
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PCT/CN2021/100069
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English (en)
French (fr)
Inventor
徐攀
张大成
林奕呈
李永谦
Original Assignee
京东方科技集团股份有限公司
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Priority to US17/771,659 priority Critical patent/US20220384558A1/en
Publication of WO2021254319A1 publication Critical patent/WO2021254319A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to a display substrate and a display device.
  • the current special-shaped display panel generally has a fan-out trace on the same layer as the film layer where the source and drain of the thin film transistor in the display area are located. The border of the display panel.
  • the fan-out wiring of the current special-shaped display panel can only be arranged on the periphery of the display panel Area, enlarged display panel border. And because the large-size high-resolution display panel requires more fan-out wiring, the frame of the display panel is further increased.
  • the present disclosure provides a display substrate and a display device.
  • the display substrate has a display area, and the display substrate includes: a base, a plurality of gate lines and a plurality of data lines on the base; the plurality of gate lines and the plurality of data lines are arranged crosswise In order to define a plurality of pixel regions, a plurality of pixel units are respectively arranged in the plurality of pixel regions; the pixel units include thin film transistors and light-emitting devices located in the display area; wherein, the display substrate further includes A plurality of fan-out traces in the area; and each fan-out trace of the plurality of fan-out traces is electrically connected to a corresponding data line, and is located at the plurality of data lines and the plurality of gate lines In different layers.
  • the display substrate further includes an interlayer insulating layer located on a side of the layer where the plurality of data lines are located away from the base; wherein, the plurality of fan-out traces are located on the interlayer insulating layer A side away from the plurality of data lines; and each fan-out line of the plurality of fan-out lines is electrically connected to the corresponding data line through a first via hole penetrating the interlayer insulating layer.
  • the display substrate further includes a binding area located on the first side of the display area, wherein the first via is provided on the display area opposite to the first side. The edge of the second side.
  • the data line and the source and drain of the thin film transistor are arranged in the same layer;
  • the display substrate further includes a passivation layer and a first A planarization layer, a second planarization layer, and a transit electrode provided between the first planarization layer and the second planarization layer; wherein the transit electrode passes through the passivation layer and The second via hole of the first planarization layer is connected to the drain of the thin film transistor; the first electrode of the light-emitting device is connected to the transfer electrode through a third via hole that penetrates the second planarization layer;
  • the fan-out wiring and the transfer electrode are insulated from each other, are arranged in the same layer, and have the same material.
  • each of the plurality of fan-out wires includes a first sub-connection wire, a second sub-connection wire, and a third sub-connection wire that are electrically connected in sequence; wherein, the plurality of fan-out wires The first end of each of the first sub-connecting lines out of the wiring is connected to the corresponding data line, and the second end is connected to the first end of the corresponding second sub-connecting line; each of the second sub-connecting lines The second end of the connecting line is connected to the first end of the corresponding third sub-connecting line; each first sub-connecting line of the plurality of fan-out wiring lines is far away from the fan-out area relative to each third sub-connecting line And the spacing between two adjacent third sub-connection lines in each of the plurality of fan-out wiring lines is smaller than the spacing between two adjacent first sub-connection lines.
  • the extension direction of each of the third sub-connection lines and/or each of the first sub-connection lines of the plurality of fan-out traces is the same as the extension direction of the plurality of data lines.
  • each of the first sub-connection lines of the plurality of fan-out wiring lines is arranged side by side in the middle area of the display area.
  • the light emitting device in each pixel area includes an organic light emitting diode, which has a first electrode, a second electrode, and an organic light emitting layer between the first electrode and the second electrode; the organic light emitting diode Located on the side of the plurality of fan-out traces away from the substrate; and each third sub-connection line of the plurality of fan-out traces extends in the same direction as the plurality of data lines, and is located far from the corresponding data line One side of the substrate and located on the side of the corresponding organic light-emitting layer close to the substrate; and the orthographic projection of the third sub-connection line on the substrate falls within the orthographic projection range of the corresponding organic light-emitting diode on the substrate .
  • the included angle between the second connecting subline and the first connecting subline and/or the included angle range between the second connecting subline and the third connecting subline Between 80 degrees and 100 degrees.
  • the pixel unit further includes a storage capacitor; the first plate of the storage capacitor and the gate of the thin film transistor are arranged in the same layer and have the same material; the second plate of the storage capacitor is The source and drain of the thin film transistor are arranged in the same layer and have the same material.
  • the pixel unit further includes a storage capacitor; the first plate of the storage capacitor and the gate of the thin film transistor are arranged in the same layer and have the same material; the second plate of the storage capacitor is The metal layers arranged on the gate insulating layer above the gate of the thin film transistor are arranged in the same layer and have the same material.
  • the plurality of pixel units include multiple rows and multiple columns of pixel units, and at least some rows of pixel units in the multiple rows and multiple columns of pixel units have different numbers of pixel units.
  • the number of pixel units in each row of pixel units in the plurality of rows of pixel units decreases.
  • the present disclosure also provides a display device including the above-mentioned display substrate.
  • the display device further includes a driving chip; the driving chip is located on a side of the substrate away from the plurality of pixel units, and is electrically connected to the plurality of fan-out wires in the bonding area. connect.
  • FIG. 1A is a schematic diagram of a cross-sectional structure of a display substrate in the related art
  • 1B is a schematic diagram of a cross-sectional structure of a display substrate in the related art
  • Fig. 2A is a schematic structural diagram of an exemplary pixel driving circuit
  • FIG. 2B is a schematic diagram of the structure of an exemplary display panel
  • FIG. 3 is a schematic diagram of a planar structure of a display substrate in the related art
  • FIG. 4A is a schematic diagram of a cross-sectional structure of a display substrate provided by an embodiment of the present disclosure
  • 4B is a schematic cross-sectional structure diagram of a display substrate provided by an embodiment of the disclosure.
  • 4C is a schematic diagram of a cross-sectional structure of a display substrate provided by an embodiment of the present disclosure.
  • 5A is a schematic structural diagram of a display substrate provided by an embodiment of the disclosure.
  • 5B is a schematic diagram of a planar structure of a display substrate provided by an embodiment of the disclosure.
  • 5C is a schematic diagram of a planar structure of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a cross-sectional structure of another display substrate provided by an embodiment of the present disclosure.
  • the thin film transistor in the display substrate described below may be any transistor in the pixel unit.
  • the thin film transistor is used as an example of the driving transistor in the pixel unit for description. It is understandable that the switching transistor/writing transistor can also be made with the same structure and manufacturing method as the driving transistor, and will not be described in detail here.
  • the light-emitting device may be specifically an organic electroluminescent diode in a pixel unit or other types of light-emitting devices. In the related art and various embodiments of the present disclosure, an organic electroluminescent diode is used as an example for description.
  • the organic electroluminescent diode has a first electrode and a second electrode, and a light-emitting layer between the first electrode and the second electrode.
  • the first electrode is, for example, the anode of the organic electroluminescent diode
  • the second electrode is, for example, an organic The cathode of a light-emitting diode.
  • FIG. 1A is a schematic cross-sectional structure diagram of a display substrate in the related art.
  • the display substrate has a display area and a peripheral area surrounding the display area.
  • the display substrate includes a base 101 and a plurality of grids on the base 101
  • the lines 05 and 06 (shown in FIG. 2B) and multiple data lines 01 (the data line 01 and the source of the thin film transistor 102 may be an integral structure.
  • the transistor is, for example, the switching transistor T1 shown in FIG. 2, the switch A part of the source of the transistor T1 can be used as a data line, such as the part encircled by a dashed line in FIG. 1A), and a plurality of fan-out traces 104 (as shown in FIG.
  • the pixel driving circuit includes: a switching transistor T1, a driving transistor T2, a storage capacitor C, and an organic electroluminescent diode OLED (hereinafter referred to as organic electroluminescent diode D); wherein the gate of the switching transistor T1
  • the electrode is connected to the gate line Scan, the source is connected to the data line Data, and the drain is connected to the first node N, where the first node N is the connection between the drain of the switching transistor T1, the gate of the driving transistor T2 and one end of the capacitor C point.
  • the gate of the driving transistor T2 is connected to the first node N, the source is connected to the first power supply voltage terminal VDD, and the drain is connected to the anode of the organic electroluminescent diode D.
  • One end of the storage capacitor C is connected to the first node N, and the other end is connected to the first power supply voltage terminal VDD.
  • the anode of the organic electroluminescent diode D is connected to the drain of the driving transistor T2, and the cathode is connected to the second power supply voltage terminal VSS. It should be noted that the potential input from the first power supply voltage terminal VDD is greater than the potential input from the second power supply voltage terminal VSS.
  • each pixel unit includes a thin film transistor 102 and a light emitting device 103 in the display area; the drain of the thin film transistor 102 is connected to the anode of the light emitting device 103, where the thin film transistor 102 is the above
  • the driving transistor T2 and the switching transistor T1 can also be made with the same structure and manufacturing method as the driving transistor T2, and will not be described in detail here.
  • the external driving chip can be connected to the data line through the fan-out wiring, and provide a data signal to the light emitting device 103 in the pixel unit through the data line, and be driven by the voltage between the first power supply voltage terminal VDD and the second power supply voltage terminal VSS The light-emitting device 103 is caused to emit light to realize the display function.
  • the display substrate of FIG. 1A also includes an interlayer insulating layer 105 provided on the side of the layer where the data line is located (that is, the layer where the source and drain electrodes are located) away from the substrate 101, and the anode of the light emitting device 103 passes through
  • the conductive material filled in the second via 1000 in the interlayer insulating layer 105 is electrically connected to the drain of the thin film transistor.
  • FIG. 3 is a schematic diagram of a plan structure of a display substrate in the related art.
  • the display substrate is a special-shaped display substrate, such as a heart shape, the inside of the heart shape is the display area, and the outside of the heart shape For the surrounding area. Since in the related art, only the layer where the gate and source (or drain) of the thin film transistor 102 are located in the display substrate is a metal conductive layer, in the manufacturing process, the fan-out wiring must use these two metal conductive layers. preparation. In this way, the fan-out wiring 104 must be arranged in the peripheral area outside the heart shape, and the shape of its edge is irregular, which easily causes the fan-out wiring 104 to occupy a larger frame.
  • embodiments of the present disclosure provide a display substrate and a display device.
  • the display substrate and the display device provided by the embodiments of the present disclosure will be described in further detail below with reference to the accompanying drawings and specific implementations.
  • FIG. 4A is a schematic cross-sectional structure diagram of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate has a display area (the heart-shaped display area AA shown in FIG. 5C), and the display substrate includes: Substrate 101, multiple gate lines (gate lines 05 and 06 in FIG. 5A) and multiple data lines (data line 01 in FIG.
  • data line 01 and the source electrode of thin film transistor 102 are integrated structure) on the substrate 101
  • Multiple gate lines and multiple data lines are intersected to define multiple pixel regions with multiple pixel units; each of the multiple pixel units includes a thin film transistor 102 and a light emitting device 103 located in the display area;
  • the display substrate further includes a plurality of fan-out wires 104 located in the display area; wherein, the fan-out wires 104 are electrically connected to the corresponding data wires, and are located in different layers with the data wires and the gate wires.
  • the fan-out wiring 104 is located in the display area of the display substrate, and is located in a different layer from the data line and the gate line. In this way, the fan-out wiring 104 can be performed in a separate wiring layer. Wiring, the data line and gate line can be avoided during the wiring process, so the wiring of the fan-out wiring 104 can be free from the limitation of the data line and the gate line.
  • Line 104 leads out the data line, and controls and reduces the area occupied by all fan-out lines 104 by controlling the spacing between adjacent fan-out lines 104 in the display area AA.
  • the fan-out wiring 104 only occupies a small frame in the display substrate (the area outside the heart shape in FIG. 5C), so that the frame of the display substrate can be reduced, and the screen-to-body ratio can be increased to improve the display effect.
  • an interlayer insulating layer 105 is provided on the side of the layer where the data line is located away from the substrate 101; the fan-out wiring 104 is located on the side of the interlayer insulating layer 105 away from the data line; The line 104 is connected to the data line through a first via hole penetrating the interlayer insulating layer 105.
  • the data line and the source and drain layers of the thin film transistor 102 are provided on the same layer, and an interlayer insulating layer 105 is provided on the side of the layer where the data line is located (ie, the layer where the source and drain layer is located) away from the substrate 101; Outgoing wiring 1050 is provided on the side of the interlayer insulating layer 105 away from the substrate 101, and then a flat isolation layer 1070 is provided on the interlayer insulating layer 105 to cover the fan-out wiring 1050 of the interlayer insulating layer, and the isolation layer 1070 is provided There is an organic light emitting diode 103 including an anode, an organic light emitting layer, and a cathode.
  • the anode of the organic light emitting diode 103 is electrically connected to the drain of the thin film transistor 102 through the conductive material filled in the second via 1000 in the interlayer insulating layer 105.
  • the fan-out wiring 1050 and the conductive material filled in the second via hole 1000 are considered to be disposed in the same layer. That is, in addition to the position where the second via hole 1000 is provided on the interlayer insulating layer 105 to electrically connect the anode of the light emitting diode and the drain of the thin film transistor, a fan-out wiring 1050 can be provided at any other position on the interlayer insulating layer 105. . As shown in FIGS. 4B and 4C, the orthographic projection of the fan-out wiring 1050 on the substrate 101 partially overlaps the orthographic projection of the organic light-emitting layer on the substrate 101. This is only the case of some pixel units on the display panel.
  • the display panel includes multiple rows and multiple columns of pixel units. Along the column direction, the number of pixel units in each row of pixel units is different.
  • a plurality of fan-out wiring lines 105 are provided in the display area AA of the display panel, and these fan-out wiring lines 105 correspond to a plurality of data lines of the display panel one-to-one, and each data line passes through a corresponding fan-out wiring line 105. Connect to the driver chip of the bonding area outside the display area AA.
  • the position where the data line and the fan-out wiring 105 are electrically connected can be set on the side with the larger width of the display panel.
  • a plurality of via holes may be provided on the side of the display area AA opposite to the binding area to electrically connect the plurality of fan-out wiring lines and the plurality of data lines in a one-to-one correspondence.
  • an interlayer insulating layer 105 is provided on the side of the data line away from the substrate 101, and the fan-out wiring 104 is located on the side of the interlayer insulating layer 105 away from the data line.
  • the inter-insulating layer 105 can insulate the data line and the fan-out wiring 104 to avoid short circuit between the fan-out wiring 104 and the data line, and can make the fan-out wiring 104 and the data line be located in different layers, avoiding the data line to fan
  • the area occupied by 104 can enable the fan-out wiring 104 to occupy only a small frame in the display substrate when it is led to an external driving chip.
  • the fan-out wiring 104 may be connected by a first via data line penetrating the interlayer insulating layer 105, so as to provide a driving signal to the light-emitting device 103 through the data line, so that the light-emitting device 104 emits light to achieve a display function.
  • FIG. 4A to 4C only show examples of how to arrange the fan-out wirings 104 and 105 in the display area AA.
  • the layout of the fan-out traces 104, 105 in each pixel area is different.
  • the fan-out wiring 105 is arranged to extend along the direction of the data line. In this case, as shown in FIG. 4B and FIG.
  • the fan-out wiring 105 in each pixel area is arranged under the organic light-emitting layer; On the narrower part of the display panel, that is, the side close to the binding area, the fan-out wiring 105 will be arranged closer, that is, the distance between adjacent fan-out wiring 105 will be narrower, and the fan-out wiring must be adjusted at this time. The position of the line 105 in each pixel area. Therefore, the electrical connection between the data line and the fan-out trace can be achieved through the first via 1060 on the side far from the bonding area.
  • the fan-out traces 104 and 105 can be regarded as being provided on the same layer as the second via 1000 that electrically connects the anode of the organic light-emitting diode and the drain of the thin film transistor, for a display panel with a special-shaped structure, When arranging the fan-out traces 104 and 105, it is only necessary to avoid the second via 1000, as shown in FIG. 5C.
  • the data line and the source electrode 1021 and the drain electrode 1022 of the thin film transistor 102 are arranged in the same layer; on the side of the data line away from the substrate 101, a passivation layer 106 and a first flat A transfer electrode 109 is provided between the first planarization layer 107 and the second planarization layer 108; wherein the transfer electrode 109 passes through the passivation layer 106 and the first planarization layer 108
  • the second via hole of the planarization layer 107 is connected to the drain electrode 1022 of the thin film transistor 102; the anode 1031 of the light emitting device 103 is connected to the transfer electrode 109 through a third via hole that penetrates the second planarization layer 108;
  • the connecting electrodes 109 are arranged in the same layer and have the same material.
  • the thin film transistor 102 may include an active layer 1023, a gate insulating layer 1024, a gate 1025, an insulating layer 1026, a source electrode 1021 and a drain electrode 1022 which are sequentially disposed on the substrate 101.
  • the source electrode 1021 and the drain electrode 1022 are arranged in the same layer, and are respectively connected to both ends of the active layer 1023 through via holes penetrating the insulating layer 1026.
  • the thin film transistor 102 in the display plate provided by the embodiment of the present disclosure may be a top gate thin film transistor or a bottom gate thin film transistor, which is not limited herein.
  • the passivation layer 106 can be provided on the source electrode 1021 and the drain electrode 1022 to prevent water and oxygen from penetrating into the source electrode 1021 and drain electrode 1022 of the thin film transistor 102 and other conductive film layers to prevent water and oxygen from affecting the thin film
  • the transistor 102 is damaged, thereby protecting the thin film transistor 102.
  • the first planarization layer 107 can planarize the source 1021 and the drain 1022 of the thin film transistor 102, so as to adhere to other layers thereon, and protect the source 1021 and drain 1022 of the thin film transistor 102 .
  • the second planarization layer 108 can planarize the transfer electrode 109 to facilitate adhesion to other film layers thereon.
  • the first planarization layer 107 and the second planarization layer 108 can be prepared as thicker layers.
  • the thickness of the first planarization layer 107 and the second planarization layer 109 can be 2 microns or more, so that the first planarization layer
  • the flattening layer 107 and the second flattening layer 108 can effectively reduce the capacitance resistance (RC Loading) on the film layer where the source electrode 1021 and the drain electrode 1022 are located and the film layer where the fan-out wiring 104 is located, thereby reducing the entire metal wire (by fan-out wiring).
  • 104 and the data line are connected to form RC Loading, which in turn can reduce the power consumption of the wiring in the display substrate to save energy.
  • the transfer electrode 109 can form a parallel double-layer structure with the anode 1031 of the original light-emitting device 103, so that the connection resistance can be reduced and energy consumption can be saved.
  • the light emitting device 103 includes an anode 1031, an organic functional layer 1032, and a cathode 1033 which are sequentially located on the second planarization layer 108.
  • the organic functional layer 1032 may include a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, an electron injection layer, and the like.
  • the organic functional layer 1032 emits light under the voltage drive between the anode 1031 and the cathode 1033 to realize the display function.
  • the material of the anode 1031 may include metal oxides such as ITO, IZO, or metals such as Ag, Al, Mo, or alloys thereof.
  • the material of the cathode 1033 may include metals such as Mg, Ca, Li, or Al or their alloys, or metal oxides such as IZO, ZTO, or PEDOT/PSS (poly3,4-ethylenedioxythiophene/polystyrene sulfonate ) And other organic materials with conductive properties.
  • the display substrate may further include a pixel defining layer for defining a position where the light emitting device 103 is formed, and an encapsulation layer provided on the cathode 1033 of the light emitting device 103.
  • the encapsulation layer may have a one-layer structure or a multilayer structure.
  • the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer.
  • the encapsulation layer can encapsulate the light-emitting device 103 to prevent water and oxygen from penetrating into each film layer of the light-emitting device 103, thereby protecting the light-emitting device.
  • the fan-out wiring 104 and the transfer electrode 109 can be arranged in the same layer and have the same material.
  • the arrangement of two or more functional layers in the same layer means that the functional layers arranged in the same layer can be made of the same material
  • the layers are formed by the same preparation process (for example, patterning process, etc.), so that the preparation process of the display substrate can be simplified.
  • a passivation layer can also be provided between the fan-out trace 104 and the second planarization layer 108, and the passivation layer can protect the film layer where the fan-out trace 104 is located to prevent the penetration of water and oxygen. Cause damage to the film.
  • the display substrate may also include a barrier layer and a buffer layer disposed on the base 101.
  • the barrier layer can prevent impurities such as water and oxygen from penetrating from the base 101 into the thin film transistor 102 and other functional structures, and the buffer layer can provide a flat surface , In order to display other functional layers of the substrate.
  • the barrier layer and the buffer layer can jointly protect other functional structures on the substrate 101.
  • each fan-out trace 104 includes a first sub-connection line 1041, a second sub-connection line 1042, and a third sub-connection line 1043 that are electrically connected;
  • the lines 1043 are arranged side by side in the middle area of the display area; the first end of each first sub-connection line 1041 is connected to the corresponding data line, and the second end is connected to the first end of the corresponding second sub-connection line 1042;
  • the first end of each second sub-connection line 1042 is connected to the second end of the corresponding first sub-connection line 1041, and the second end is connected to the first end of the corresponding third sub-connection line 1043; and
  • the distance between adjacent third sub-connection lines 1043 is smaller than the distance between adjacent first sub-connection lines 1041.
  • the fan-out wiring 104 can be divided into three sections, that is, the first sub-connection line 1041, the second sub-connection line 1042, and the third sub-connection line 1043 that are electrically connected; the first sub-connection line
  • the first end of the 1041 can be directly connected to the corresponding data line through a via, and extends in the direction of the second sub-connection line 1042 to connect to the corresponding second sub-connection line 1042.
  • the first end of the third sub-connection line 1043 is connected to the corresponding second sub-connection line 1042.
  • the first sub-connection line 1041 is connected to the third sub-connection line 1043 through the second sub-connection line 1042, and the third sub-connection line 1043 is arranged side by side in the middle of the display area, and the spacing between the third sub-connection lines 1043 is smaller than the first
  • the space between one sub-connection line 1041 can be reduced by reducing the space between adjacent third sub-connection lines 1043 to control the area occupied by all third sub-connection lines 1043, so that the entire fan-out wiring 104 is connected to the outside.
  • the driving chip can only occupy a small frame on the display substrate (the area outside the central shape of FIG. 5B), so that the frame of the display substrate can be reduced, and the screen-to-body ratio can be increased to improve the display effect.
  • connection point of the connection point between the first sub-connection line 1041 and the second sub-connection line 1042 increases monotonically from both sides to the middle, so that the spacing between the second sub-connection lines 1042 can be increased , To prevent signal crosstalk between adjacent second sub-connection lines 1042, thereby facilitating the wiring of the entire fan-out wiring 104.
  • the fan-out wiring 105 in the display area, can be divided into three sections, that is, the first sub-connection line 1051, the second sub-connection line 1052, and the third sub-connection line that are electrically connected. 1053;
  • the first end of the first sub-connection line 1051 can be directly connected to the corresponding data line through the first via 1060, and extends in the direction of the second sub-connection line 1052 to connect to the corresponding second sub-connection line 1052.
  • the first end of the third sub-connection line 1053 is connected to the corresponding second sub-connection line 1052.
  • the first sub-connection line 1051 is connected to the third sub-connection line 1053 through the second sub-connection line 1052, the third sub-connection line 1053 is arranged side by side in the middle of the display area, and the spacing between the third sub-connection lines 1053 is smaller than the first
  • the space between one sub-connection line 1051 can be reduced by reducing the space between adjacent third sub-connection lines 1053 to control the area occupied by all third sub-connection lines 1053, so that the entire fan-out wiring 105 is connected to the outside.
  • the driving chip can occupy only a small frame on the display substrate (the area outside the central shape of FIG. 5C), so that the frame of the display substrate can be reduced, and the screen-to-body ratio can be increased to improve the display effect.
  • the included angle between the first sub-connection line 1051 and the second sub-connection line 1052, and between the second connection line 1052 and the third connection line 1053 is approximately between 80 and 100 degrees, such as 90 degrees. In this way, the spacing between the second sub-connection lines 1052 can be increased to prevent signal crosstalk between adjacent second sub-connection lines 1052, thereby facilitating the wiring of the entire fan-out wiring 105.
  • each third sub-connection line 1043, 1053 is the same as the extension direction of the data line.
  • the gate lines are generally arranged in a row direction, and the data lines are generally arranged in a column direction.
  • the gate lines are used to input gate signals into the light-emitting devices 103 of the pixel units in each row.
  • the light emitting device 103 in the pixel unit of each row is turned on, and at the same time, the data line is used to input the data signal to the light emitting device 103 in the pixel unit of each column, so that the light emitting device 103 in the pixel unit of each row is illuminated row by row to achieve Display function.
  • the extension direction of the third sub-connecting line 1043 in the fan-out wiring 104 can be the same as the extension direction of the data line, so that the entire fan-out wiring 104 is led to one end of the display substrate to connect to an external driving chip.
  • the third sub-connection line 1042 can occupy only a small frame on the display substrate, so that the frame of the display substrate can be reduced, and the screen-to-body ratio can be increased to improve the display effect.
  • the pixel unit further includes a storage capacitor 110; the first plate 1101 of the storage capacitor 110 and the gate 1025 of the thin film transistor 102 are arranged in the same layer and have the same material; and the storage capacitor The second electrode plate 1102 of the 110 is arranged in the same layer as the source electrode 1021 and the drain electrode 1022 of the thin film transistor 102 and has the same material.
  • the pixel unit also includes a storage capacitor 110 for storing voltage, and the first plate 1101 of the storage capacitor 110 can be connected to the gate of the thin film transistor 102.
  • 1025 is arranged in the same layer, the second electrode plate 1102 can be arranged in the same layer as the source 1021 and drain 1022 of the thin film transistor 102.
  • the arrangement of two or more functional layers in the same layer refers to these same layers.
  • the functional layers of the layer arrangement can be formed by using the same material layer and using the same preparation process (for example, patterning process, etc.), so that the preparation process of the display substrate can be simplified.
  • the two plates of the storage capacitor 110 can also be arranged on the same layer as other conductive layers, or they can also be separately arranged on some insulating layers.
  • the first plate 1101 of the storage capacitor 110 can be arranged on the same layer as the thin film transistor 102.
  • the gate electrode 1025 is arranged in the same layer, and the second electrode plate may be located between the gate insulating layer 1024 and the insulating layer 1026. The positions of the two plates of the storage capacitor 110 can be set reasonably according to actual needs.
  • the pixel unit further includes a storage capacitor 110; the first plate 1101 of the storage capacitor 110 and the gate 1025 of the thin film transistor 102 are arranged in the same layer and have the same material; and the storage capacitor The second electrode plate 1102 of 110 and the metal layer provided on the gate insulating layer on the gate of the thin film transistor 102 are arranged in the same layer and have the same material.
  • the number of pixel units in at least some rows of the display substrate is different.
  • the display substrate provided by the embodiments of the present disclosure may be a regular-shaped display substrate, or a special-shaped display substrate, and is especially suitable for special-shaped display substrates with irregular edges, such as the heart-shaped display substrates shown in FIGS. 5B and 5C.
  • the number of pixel units in at least part of the rows of the display substrate is different. For example, in the heart-shaped display substrates in FIG. 5B and FIG.
  • the display substrate further has a binding area connected to one side of the display area; along the direction approaching the binding area, the number of pixel units in each row decreases.
  • the binding area of the display substrate corresponds to the area outside the central shape of FIG. 5B and FIG.
  • One pad the external driver chip is provided with a second pad, and the first pad and the second pad can be bonded and connected, so that the external driver chip can be used as the pixel unit through the fan-out wiring 104 and the data line
  • the light-emitting device provides data signals to control the brightness of the light-emitting device in each pixel unit in the display area, so as to realize colorful display.
  • FIGS. 5B and 5C in the direction close to the binding area, the number of pixel units in each row decreases, thereby forming a heart-shaped display substrate.
  • the embodiments of the present disclosure provide a display device, which includes the display substrate provided in the above-mentioned embodiments, and the display device may be a terminal device such as a mobile phone, a tablet computer, and a smart TV with a special shape.
  • the implementation principle is the same as the implementation principle of the display substrate provided in the foregoing embodiment, and will not be repeated here.
  • the display device further includes a driver chip; the driver chip is located on the side of the substrate 101 away from the pixel unit, and is connected to the fan-out traces 104 and 105 in the bonding area.
  • the driver chip can be bound and connected to the fan-out wiring 104, 105, and the fan-out wiring 104, 105 and the data line provide data signals for the light-emitting device in the pixel unit to control each pixel unit in the display area.
  • the brightness of the light-emitting device so as to achieve colorful display.
  • the driver chip is generally folded to the side of the substrate 101 away from the pixel unit, that is, the back of the display device, so that the driver chip does not occupy the frame of the display device to achieve a full-screen display effect.
  • the fan-out traces 104, 105 can pass through the heart-shaped display area to the top of the display area by the signal output by the driver chip, and connect to the pixel unit of the display area through the data line.
  • the order of the channels of the driver chip is related to the related technology.
  • the channel sequence of the middle driver chip remains the same, and there is no need to change the structure of the driver chip to save the cost of R&D and design of the driver chip.
  • the sequence of the driver chip can correspond to the sequence of the pixel unit in the display area one-to-one (that is, in Figure 5B and Figure 5C). Drive sequentially from left to right).

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Abstract

本公开提供一种显示基板及显示装置，属于显示技术领域，其可解决相关技术中的扇出走线必须设置在周边区，需要占用较大边框的技术问题。本公开的显示基板，具有显示区，显示基板包括：基底，位于基底上的多条栅线、多条数据线；多条栅线和多条数据线交叉设置以限定出多个像素区域，每个像素区域中设置有一个像素单元；每个像素单元均包括位于显示区的薄膜晶体管和发光器件；显示基板还包括位于显示区中的多条扇出走线；其中，多条扇出走线中的每一条扇出走线和与之对应的数据线电连接，且与数据线、栅线位于不同层中。

Description

显示基板及显示装置
相关申请的交叉引用
本公开要求于2021年6月18日提交的中国专利申请202010560547.2的优先权，在此通过引用将其整体并入本文。
技术领域
本公开属于显示技术领域，具体涉及一种显示基板及显示装置。
背景技术
随着应用场景越来越复杂，规则形状的显示面板已经不能满足用户的需要，因此异形显示面板越来越受到用户的欢迎。目前的异形显示面板一般在显示区中薄膜晶体管源、漏极所在的膜层同层设置一层扇出走线，扇出走线设置在环绕显示区的周边区的一侧，这样扇出走线占用了显示面板的边框。
由于显示区中一般仅有栅极和源、漏极两层金属层，那么扇出走线必须使用这两层金属层，因此，目前的异形显示面板的扇出走线只能设置在显示面板的周边区，增大的显示面板的边框。并且由于大尺寸高分辨率显示面板需要设置更多的扇出走线，进一步增大了显示面板的边框。
公开内容
本公开提供一种显示基板及显示装置。
所述一种显示基板，具有显示区，所述显示基板包括：基底，位于所述基底上的多条栅线、多条数据线；所述多条栅线和所述多条数据线交叉设置以限定出多个像素区域，所述多个像素区域中分别设置有多个像素单元；所述像素单元包括位于所述显示区的薄膜晶体管和发光器件；其中，所述显示基板还包括位于显示区中的多条扇出走线；以及所述多条扇出走线中的每一条扇出走线和与之对应的数据线电连接，且与所述多条数据线、所述多条栅线位于不同层中。
在一个实施例中，所述显示基板还包括位于所述多条数据线所在层背离所述基底的一侧的层间绝缘层；其中，所述多条扇出走线位于所述层间绝缘层背离所述多条数据线的一侧；以及所述多条扇出走线中的每一条扇出走线通过贯穿层间绝缘层的第一过孔与对应的数据线电连接。
在一个实施例中，所述显示基板，还包括位于所述显示区的第一侧的绑定区，其中，所述第一过孔设置在所述显示区的与所述第一侧相对的第二侧的边缘。
在一个实施例中，所述数据线与薄膜晶体管的源极和漏极同层设置；所述显示基板还包括在所述数据线背离所述基底的一侧依次设置的钝化层、第一平坦化层、第二平坦化层，以及在所述第一平坦化层和所述第二平坦化层之间设置的转接电极；其中，所述转接电极通过贯穿所述钝化层和第一平坦化层的第二过孔与所述薄膜晶体管的漏极连接；所述发光器件的第一电极通过贯穿所述第二平坦化层的第三过孔与所述转接电极连接；所述扇出走线与所述转接电极相互绝缘并且同层设置，且材料相同。
在一个实施例中，所述多条扇出走线中的每一条扇出走线包括依次电连接的第一子连接线、第二子连接线和第三子连接线；其中，所述多条扇出走线的各个所述第一子连接线的第一端和与之对应的所述数据线连接，第二端连接与之对应的第二子连接线的第一端；各个所述第二子连接线的第二端连接与之对应的第三子连接线的第一端连接；所述多条扇出走线的各个第一子连接线相对于各个第三子连接线远离所述扇出区；以及所述多条扇出走线的各个第三子连接线中相邻的两条第三子连接线之间的间距小于相邻的两条第一子连接线之间的间距。
在一个实施例中，所述多条扇出走线的各个所述第三子连接线和/或各个所述第一子连接线的延伸方向与所述多条数据线的延伸方向相同。
在一个实施例中，所述多条扇出走线的各个所述第一子连接线并排设置位 于所述显示区的中间区域。
在一个实施例中，每个像素区域内的所述发光器件包括有机发光二极管，其具有第一电极、第二电极以及第一电极和第二电极之间的有机发光层；所述有机发光二极管位于所述多条扇出走线远离所述基底的一侧；以及所述多条扇出走线的各个第三子连接线与所述多条数据线延伸方向相同，并且位于对应数据线的远离所述基底的一侧并且位于对应的有机发光层的靠近所述基底的一侧；以及所述第三子连接线在基底上的正投影落入对应的有机发光二极管在基底上的正投影范围内。
在一个实施例中，所述第二连接子线与所述第一连接子线之间的夹角和/或所述第二连接子线与所述第三连接子线之间的夹角范围在80度至100度之间。
在一个实施例中，所述像素单元还包括存储电容；所述存储电容的第一极板与所述薄膜晶体管的栅极同层设置，且材料相同；所述存储电容的第二极板与所述薄膜晶体管的源极和漏极同层设置，且材料相同。
在一个实施例中，所述像素单元还包括存储电容；所述存储电容的第一极板与所述薄膜晶体管的栅极同层设置，且材料相同；所述存储电容的第二极板与所述薄膜晶体管的栅极上方的栅极绝缘层上设置的金属层同层设置，且材料相同。
在一个实施例中，所述多个像素单元包括多行多列像素单元，以及所述多行多列像素单元中至少部分行像素单元具有不同数量的像素单元。
在一个实施例中，沿靠近所述绑定区的方向，所述多行像素单元中各行像素单元中像素单元的数量递减。
本公开还提供了一种显示装置，包括上述显示基板。
在一个实施例中，所述显示装置还包括驱动芯片；所述驱动芯片位于所述基底远离所述多个像素单元的一侧，且在所述绑定区与所述多条扇出走线电连 接。
附图说明
图1A为相关技术中一种显示基板的剖面结构示意图；
图1B为相关技术中一种显示基板的剖面结构示意图；
图2A为一种示例性的像素驱动电路的结构示意图；
图2B为一种示例性的显示面板的结构示意图；
图3为相关技术中一种显示基板的平面结构示意图；
图4A为本公开实施例提供的一种显示基板的剖面结构示意图；
图4B为本公开实施例提供的一种显示基板的剖面结构示意图；
图4C为本公开实施例提供的一种显示基板的剖面结构示意图；
图5A为本公开实施例提供的一种显示基板的结构示意图；
图5B为本公开实施例提供的一种显示基板的平面结构示意图；
图5C为本公开实施例提供的一种显示基板的平面结构示意图；以及
图6为本公开实施例提供的另一种显示基板剖面结构示意图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
下述的显示基板中的薄膜晶体管可以为像素单元中的任意一个晶体管，在相关技术中及本公开各个实施例中以薄膜晶体管为像素单元中的驱动晶体管为例进行说明。可以理解的是，开关晶体管/写入晶体管也可以采用与驱动晶体管同样的结构及制备方式制成，在此不再进行详述。发光器件可以具体为像素单元中的有机电致发光二极管或者其他种类的发光器件，在相关技术中以及本公开各个实施例中以有机电致发光二极管为例进行说明。其中，有机电致发光二极管具有第一电极和第二电极、以及第一电极和第二电极之间的发光层，第一电极例如为有机电致发光二极管的阳极，第二电极例如为有机电致发光二极管 的阴极。
图1A为相关技术中一种显示基板的剖面结构示意图，如图1A所示，该显示基板具有显示区和围绕显示区的周边区，该显示基板包括基底101、位于基底101上的多条栅线05、06(如图2B示出)和多条数据线01(数据线01与薄膜晶体管102的源极可以为一体结构。在该晶体管例如为图2所示的开关晶体管T1时，该开关晶体管T1的源极上一部分可作为数据线，例如图1A中虚线圈出的部分)、以及与多条数据线分别连接的多条扇出走线104(如图3所示)；多条栅线和多条数据线交叉设置，并在交叉位置处限定出多个像素区域，每个像素区域内设置有一个像素单元，多个像素单元中的每个像素单元均设置有像素驱动电路，如图2A和图2B所示，该像素驱动电路包括：开关晶体管T1、驱动晶体管T2、存储电容C和有机电致发光二极管OLED(以下称为有机电致发光二极管D)；其中，开关晶体管T1的栅极连接栅线Scan，源极连接数据线Data，漏极连接第一节点N，其中，第一节点N为开关晶体管T1的漏极、驱动晶体管T2的栅极和电容C的一端之间的连接点。驱动晶体管T2的栅极连接第一节点N，源极连接第一电源电压端VDD，漏极连接有机电致发光二极管D的阳极。存储电容C的一端连接第一节点N，另一端连接第一电源电压端VDD。有机电致发光二极管D的阳极连接驱动晶体管T2的漏极，阴极连接第二电源电压端VSS。需要说明的是，第一电源电压端VDD输入的电位大于第二电源电压端VSS输入的电位。图1A和图1B中仅示出了每个像素单元均包括位于显示区的薄膜晶体管102和发光器件103；薄膜晶体管102的漏极与发光器件103的阳极连接，此处的薄膜晶体管102为上述的驱动晶体管T2，开关晶体管T1也可以采用与驱动晶体管T2同样的结构及制备方式制成，在此不再进行详述。外部的驱动芯片可以通过扇出走线与数据线连接，并通过数据线向像素单元中的发光器件103提供数据信号，并在第一电源电压端VDD和第二电源电压端VSS之间的电压驱动下使得发光器件103发光，实现显示功能。
图1A和图1B的区别在于，图1A的显示基板还包括在数据线所在层(即，源漏极所在层)背离基底101的一侧设置的层间绝缘层105，发光器件103的阳 极通过层间绝缘层105中的第二过孔1000中填充的导电材料与薄膜晶体管的漏极电连接。
图3为相关技术中一种显示基板的平面结构示意图，如图3所示，该显示基板为一种异形显示基板，例如为心形形状，心形形状内部为显示区，心形形状之外为周边区。由于在相关技术中，显示基板中仅薄膜晶体管102的栅极和源极(或漏极)所在的层为金属导电层，因此在制备过程中，扇出走线必须利用这两层金属导电层来制备。这样，扇出走线104必须设置在心形形状之外周边区，其边缘的形状不规则，容易造成扇出走线104占用较大的边框。并且由于大尺寸高分辨率显示基板中需要设置更多的扇出走线104，进一步增大了显示基板的边框。为了解决相关技术中的扇出走线104必须设置在周边区，其需要占用较大边框的技术问题，本公开实施例提供了一种显示基板及显示装置。下面结合附图和具体实施方式对本公开实施例提供的显示基板及显示装置作进一步详细描述。
图4A为本公开实施例提供的一种显示基板的剖面结构示意图，如图4所示，该显示基板，具有显示区(如图5C所示的心形显示区AA)，该显示基板包括：基底101，位于基底101上的多条栅线(图5A中的栅线05、06)、多条数据线(图5A中的数据线01，数据线01与薄膜晶体管102的源极为一体结构)；多条栅线和多少条数据线交叉设置以限定出具有多个像素单元的多个像素区域；多个像素单元中的每个像素单元均包括位于显示区的薄膜晶体管102和发光器件103；显示基板还包括位于显示区中的多条扇出走线104；其中，扇出走线104和与之对应的数据线电连接，且与数据线、栅线位于不同层中。
本公开实施例提供的显示基板中，扇出走线104位于显示基板的显示区内，并且与数据线、栅线位于不同层中，这样，扇出走线104可以在单独的一层布线层中进行布线，在布线过程中可以避开数据线和栅线，因此扇出走线104的布线可以不受数据线和栅线的限制，如图5A至图5C所示，可以在显示区内利用扇出走线104将数据线引出，并在显示区AA内通过控制相邻的扇出走线104 之间的间距来控制并减少所有的扇出走线104所占用的面积，在引出至外部的驱动芯片时可以使得扇出走线104仅占用显示基板中较小的边框(如图5C中的心形形状之外的区域)，从而可以减小显示基板的边框，进而可以提高屏占比，以提高显示效果。
在一些实施例中，如图4A所示，在数据线所在层背离基底101的一侧设置有层间绝缘层105；扇出走线104位于层间绝缘层105背离数据线的一侧；扇出走线104通过贯穿层间绝缘层105的第一过孔与数据线连接。
在一些实施例中，数据线与薄膜晶体管102的源漏层设置在同一层，在数据线所在层(即，源漏层所在层)背离基底101的一侧设置有层间绝缘层105；扇出走线1050设置在层间绝缘层105的背离基底101的一侧上，然后在层间绝缘层105上设置有平坦的隔离层1070以覆盖层间绝缘层扇出走线1050，隔离层1070上设置有包括阳极、有机发光层和阴极的有机发光二极管103。图4B和图4C示出了两种结构不同的有机发光二极管103，但是无论哪种结构均不影响本公开的构思。有机发光二极管103的阳极通过层间绝缘层105中的第二过孔1000内填充的导电材料与薄膜晶体管102的漏极电连接。
如图4B和图4C所示，在该像素单元中，扇出布线1050与第二过孔1000内填充的导电材料视为设置在同一层。即，在层间绝缘层105上除了设置第二过孔1000以电连接发光二极管的阳极和薄膜晶体管的漏极的位置以外，可以在层间绝缘层105上的任何其他位置设置扇出走线1050。如图4B和图4C所示，扇出走线1050在基底101上的正投影与所述有机发光层在基底101上的正投影部分重叠。这仅仅是显示面板上的部分像素单元的情况。
如图5C所示，对于心形结构这种异形结构的显示面板而言，显示面板包括多行多列像素单元。沿着列方向，各行像素单元的像素单元的数量不同。在该实施例中，显示面板的显示区AA中设置了多条扇出走线105，这些扇出走线105与显示面板的多条数据线一一对应，每条数据线通过对应的扇出走线105连接至显示区AA外的绑定区的驱动芯片。由于该心形结构的显示面板的与绑定区相对的一侧的宽度比较大，因此可以将数据线与扇出走线105电连接的位置设置 在显示面板宽度较大的一侧。如图5A和图5C所示，可以在显示区AA的与绑定区相对的一侧设置多个过孔将多条扇出走线和多条数据线一一对应地电连接在一起。
需要说明的是，如图4A至图4C所示，在数据线所在层背离基底101的一侧设置层间绝缘层105，扇出走线104位于层间绝缘层105背离数据线的一侧，层间绝缘层105可以将数据线与扇出走线104之间绝缘设置，避免扇出走线104与数据线之间短路，并且可以使得扇出走线104与数据线位于不同层中，避免数据线对扇出走线105布线的影响，从而可以在显示区内利用扇出走线104将数据线引出，并在显示区内通过控制相邻的扇出走线104之间的间距来控制并减少所有的扇出走线104所占用的面积，在引出至外部的驱动芯片时可以使得扇出走线104仅占用显示基板中较小的边框。扇出走线104可以通过贯穿层间绝缘层105的第一过孔数据线连接，从而通过数据线为发光器件103提供驱动信号，使得发光器件104发光，以实现显示功能。
图4A至图4C仅仅示出了如何在显示区AA内布置扇出布线104和105的示例。然而，如图5C可以看出,扇出走线104、105在每个像素区域内的布置情况是不同的，在心形结构的显示面板的较宽部分，即背离绑定区的一侧，可以将扇出走线105布置为沿着数据线方向延伸，这种情况下可以如图4B和图4C所示，每个像素区内的扇出走线105设置在有机发光层的下方；而在心形结构的显示面板的较窄部分，即靠近绑定区的一侧，扇出走线105将会布置地比较紧密，即，相邻的扇出走线105之间的距离变窄，此时必须要调整扇出走线105在每个像素区域内的位置。因此，可以在远离绑定区的一侧通过第一过孔1060来实现数据线和扇出走线之间的电连接。在本公开中，由于扇出走线104,105可以视为与将有机发光二极管的阳极和薄膜晶体管的漏极电连接的第二过孔1000设置在同一层，因此在针对异形结构的显示面板而言，在布置扇出走线104,105时，仅仅需要避开第二过孔1000即可，如图5C所示。
在一些实施例中，如图6所示，数据线与薄膜晶体管102的源极1021和漏极1022同层设置；在数据线背离基底101的一侧依次设置有钝化层106、第一 平坦化层107、第二平坦化层108；在第一平坦化层107和第二平坦化层108之间设置有转接电极109；其中，转接电极109通过贯穿钝化层106和第一平坦化层107的第二过孔与薄膜晶体管102的漏极1022连接；发光器件103的阳极1031通过贯穿第二平坦化层108的第三过孔与转接电极109连接；扇出走线104与转接电极109同层设置，且材料相同。
需要说明的是，图6所示，薄膜晶体管102可以包括依次设置于基底101上的有源层1023、栅极绝缘层1024、栅极1025、绝缘层1026、源极1021和漏极1022。其中，源极1021和漏极1022同层设置，并通过贯穿绝缘层1026的过孔分别与有源层1023的两端连接。可以理解的是，本公开实施例提供的显示极板中的薄膜晶体管102可以为顶栅型薄膜晶体管，也可以为底栅型薄膜晶体管，在此不作限定。钝化层106可以设置在源极1021和漏极1022上，可以防止水氧等从外部渗透至薄膜晶体管102的源极1021和漏极1022，以及其他导电膜层中，避免水氧等对薄膜晶体管102造成损坏，从而对薄膜晶体管102起到保护作用。第一平坦化层107可以对薄膜晶体管102的源极1021和漏极1022进行平坦化，以便于与其上的其他膜层相贴合，并对薄膜晶体管102的源极1021和漏极1022进行保护。第二平坦化层108可以对转接电极109进行平坦化，以便于与其上的其他膜层相贴合。同时，第一平坦化层107和第二平坦化层108可以制备成较厚的膜层，例如第一平坦化层107和第二平坦化层109的厚度可以为2微米以上，这样第一平坦化层107和第二平坦化层108可以有效降低源极1021和漏极1022所在膜层及扇出走线104所在膜层上的电容电阻(RC Loading)，从而降低整个金属导线(由扇出走线104和数据线连接组成)上的RC Loading，进而可以降低显示基板中走线的功耗，以节约能耗。转接电极109可以与原有的发光器件103的阳极1031形成并联的双层结构，从而可以降低连接电阻，以节约能耗。发光器件103包括依次位于第二平坦化层108上的阳极1031、有机功能层1032和阴极1033。有机功能层1032可以包括空穴注入层、空穴传输层、有机发光层、电子传输层及电子注入层等。有机功能层1032在阳极1031和阴极1033之间的电压驱动下进行发光，以实现显示功能。阳极1031 的材料可以包括ITO、IZO等金属氧化物或者Ag、Al、Mo等金属或其合金。阴极1033的材料可以包括Mg、Ca、Li或Al等金属或其合金，或者IZO、ZTO等金属氧化物，又或者PEDOT/PSS(聚3，4-乙烯二氧噻吩/聚苯乙烯磺酸盐)等具有导电性能有机材料。显示基板还可以包括用于限定发光器件103形成位置的像素限定层，以及设置在发光器件103的阴极1033上的封装层。封装层可以为一层结构也可以多层结构，例如封装层包括第一无机封装层、有机封装层和第二无机封装层。封装层可以对发光器件103进行封装，防止水氧等深入发光器件103的各个膜层中，从而保护发光器件。扇出走线104可以与转接电极109同层设置，且材料相同，本公开实施例中，两个或更多个功能层同层设置指的是这些同层设置的功能层可以采用相同的材料层并利用相同制备工艺(例如构图工艺等)形成，从而可以简化显示基板的制备工艺。可以理解的是，在扇出走线104与第二平坦化层108之间也可以设置一层钝化层，该钝化层可以对扇出走线104所在的膜层进行保护，防止水氧等渗入对膜层造成损坏。在实际应用中，显示基板还可以包括设置在基底101上的阻挡层和缓冲层，阻挡层可以防止水氧等杂质从基底101渗入到薄膜晶体管102等功能结构中，缓冲层可以提供平坦的表面，以便于显示基板其他功能层的设置。阻挡层和缓冲层可以共同对基底101上的其他功能结构起到保护作用。
在一些实施例中，如图5B所示，每条扇出走线104包括电连接的第一子连接线1041、第二子连接线1042和第三子连接线1043；其中，各个第三子连接线1043并排设置位于显示区的中间区域；各个第一子连接线1041的第一端和与之对应的数据线连接，第二端连接与之对应的第二子连接线1042的第一端；各个第二子连接线1042的第一端和与之对应的第一子连接线1041的第二端连接，第二端连接与之对应的第三子连接线1043的第一端连接；且相邻的第三子连接线1043之间的间距小于相邻的第一子连接线1041之间的间距。
需要说明的是，在显示区内，扇出走线104可以分为三段，即电连接的第一子连接线1041、第二子连接线1042和第三子连接线1043；第一子连接线1041的第一端可以直接与对应的数据线通过过孔的方式连接，并向第二子连接线 1042的方向上延伸以连接对应的第二子连接线1042。第三子连接线1043的第一端连接对应的第二子连接线1042。这样第一子连接线1041通过第二子连接线1042连接至第三子连接线1043，第三子连接线1043并排设置于显示区的中间位置，第三子连接线1043之间的间距小于第一子连接线1041之间的间距，可以通过缩小相邻的第三子连接线1043之间的间距，来控制所有的第三子连接线1043所占面积，从而使得整个扇出走线104与外部的驱动芯片连接时可以仅占用显示基板上较小的边框(如图5B中心形形状之外的区域)，从而可以减小显示基板的边框，进而可以提高屏占比，以提高显示效果。在实际应用中，第一子连接线1041与第二子连接线1042之间的连接点的连线由两侧向中间呈单调递增，这样，可以增大第二子连接线1042之间的间距，防止相邻的第二子连接线1042之间发生信号串扰，从而便于整个扇出走线104的布线。
在一些实施例中，如图5C所示，在显示区内，扇出走线105可以分为三段，即电连接的第一子连接线1051、第二子连接线1052和第三子连接线1053；第一子连接线1051的第一端可以直接与对应的数据线通过第一过孔1060的方式连接，并向第二子连接线1052的方向上延伸以连接对应的第二子连接线1052。第三子连接线1053的第一端连接对应的第二子连接线1052。这样第一子连接线1051通过第二子连接线1052连接至第三子连接线1053，第三子连接线1053并排设置于显示区的中间位置，第三子连接线1053之间的间距小于第一子连接线1051之间的间距，可以通过缩小相邻的第三子连接线1053之间的间距，来控制所有的第三子连接线1053所占面积，从而使得整个扇出走线105与外部的驱动芯片连接时可以仅占用显示基板上较小的边框(如图5C中心形形状之外的区域)，从而可以减小显示基板的边框，进而可以提高屏占比，以提高显示效果。在实际应用中，第一子连接线1051与第二子连接线1052之间、第二连接线1052和第三连接线1053之间的夹角大约在80至100度之间，例如90度。这样，可以增大第二子连接线1052之间的间距，防止相邻的第二子连接线1052之间发生信号串扰，从而便于整个扇出走线105的布线。
在一些实施例中，各个第三子连接线1043，1053的延伸方向与数据线的延 伸方向相同。
需要说明的是，在显示基板的显示区内，栅线一般成行方向排布，数据线一般成列方向上排布，利用栅线向每一行的像素单元的发光器件103中输入栅极信号，使得每一行的像素单元中的发光器件103开启，同时利用数据线向每一列的像素单元中的发光器件103输入数据信号，从而逐行点亮每一行的像素单元中的发光器件103，以实现显示功能。扇出走线104中的第三子连接线1043的延伸方向可以与数据线的延伸方向相同，从而将整个扇出走线104引至显示基板的一端，以连接外部的驱动芯片。并且可以使得第三子连接线1042可以仅占用显示基板上较小的边框，从而可以减小显示基板的边框，进而可以提高屏占比，以提高显示效果。
在一些实施例中，如图4A和图6所示，像素单元还包括存储电容110；存储电容110的第一极板1101与薄膜晶体管102的栅极1025同层设置，且材料相同；存储电容110的第二极板1102与薄膜晶体管102的源极1021和漏极1022同层设置，且材料相同。
需要说明的是，在实际应用中，如图4A和图6所示，像素单元中还包括用于存储电压的存储电容110，存储电容110的第一极板1101可以与薄膜晶体管102的栅极1025同层设置，第二极板1102可以与薄膜晶体管102的源极1021和漏极1022同层设置，本公开的实施例中，两个或更多个功能层同层设置指的是这些同层设置的功能层可以采用相同的材料层并利用相同制备工艺(例如构图工艺等)形成，从而可以简化显示基板的制备工艺。可以理解的是，存储电容110的两个极板也可以与其他导电层同层设置，或者也可以某些绝缘层上单独设置，例如，存储电容110的第一极板1101可以与薄膜晶体管102的栅极1025同层设置，第二极板可以位于栅极绝缘层1024和绝缘层1026之间。可以根据实际需要，合理设置存储电容110两个极板的位置。
在一些实施例中，如图4B和图4C所示，像素单元还包括存储电容110；存储电容110的第一极板1101与薄膜晶体管102的栅极1025同层设置，且材料相同；存储电容110的第二极板1102与薄膜晶体管102的栅极上的栅极绝缘层 上设置的金属层同层设置，且材料相同。
在一些实施例中，显示基板中至少部分行的像素单元的数量不同。
需要说明的是，本公开实施例提供的显示基板可以为规则形状的显示基板，也可以为异形显示基板，尤其适用于边缘不规则的异形显示基板，例如图5B和图5C所示的心形显示基板。显示基板中至少部分行的像素单元的数量不同，例如图5B和图5C中的心形显示基板，靠近中间行的像素单元的数量较多，靠近心形底部行的像素单元的数量较少。
在一些实施例中，显示基板还具有与显示区的一侧连接的绑定区；沿靠近绑定区的方向，各行像素单元的数量递减。
需要说明的是，显示基板的绑定区与图5B和图5C中心形形状之外的区域对应，绑定区中设置有与扇出走线104的第二子连接线1042的另一端连接的第一焊盘，外部的驱动芯片上设置由第二焊盘，可以将第一焊盘与第二焊盘绑定连接，从而可以利用外部的驱动芯片通过扇出走线104与数据线为像素单元中的发光器件提供数据信号，以控制显示区中每个像素单元中发光器件的亮度，从而实现多彩显示。如图5B和图5C所述，靠近绑定区的方向上，各行像素单元的数量递减，从而形成心形形状的显示基板。
本公开实施例提供了一种显示装置，该显示装置包括如上述实施例提供的显示基板，该显示装置可以为特殊形状的手机、平板电脑、智能电视等终端设备。其实现原理与上述实施例提供的显示基板的实现原理相同，在此不再赘述。
在一些实施例中，该显示装置还包括驱动芯片；驱动芯片位于基底101远离像素单元的一侧，且在绑定区与扇出走线104、105连接。
需要说明的是，驱动芯片可以与扇出走线104、105绑定连接，通过扇出走线104、105和数据线为像素单元中的发光器件提供数据信号，以控制显示区中每个像素单元中发光器件的亮度，从而实现多彩显示。在实际应用中，一般将驱动芯片翻折至基底101远离像素单元的一侧，即显示装置的背部，从而可以使得驱动芯片不占用显示装置的边框，以实现全面屏显示效果。扇出走线104、 105可以由驱动芯片输出的信号经过心形形状的显示区达到显示区的顶端，并通过数据线连接至显示区的像素单元中，这样，驱动芯片的信道的顺序与相关技术中驱动芯片的信道顺序保持相同，不必改变驱动芯片的结构，以节约驱动芯片的研发及设计成本，可以使得驱动芯片顺序与显示区中的像素单元顺序一一对应(即图5B和图5C中为从左到右顺序驱动)。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (15)

  1. 一种显示基板，具有显示区，
    所述显示基板包括：基底，位于所述基底上的多条栅线、多条数据线；所述多条栅线和所述多条数据线交叉设置以限定出多个像素区域，所述多个像素区域中分别设置有多个像素单元；所述像素单元包括位于所述显示区的薄膜晶体管和发光器件；
    其中，所述显示基板还包括位于显示区中的多条扇出走线；以及所述多条扇出走线中的每一条扇出走线和与之对应的数据线电连接，且与所述多条数据线、所述多条栅线位于不同层中。
  2. 根据权利要求1所述的显示基板，还包括位于所述多条数据线所在层背离所述基底的一侧的层间绝缘层；
    其中，所述多条扇出走线位于所述层间绝缘层背离所述多条数据线的一侧；以及所述多条扇出走线中的每一条扇出走线通过贯穿层间绝缘层的第一过孔与对应的数据线电连接。
  3. 根据权利要求2所述的显示基板，还包括位于所述显示区的第一侧的绑定区，
    其中，所述第一过孔设置在所述显示区的与所述第一侧相对的第二侧的边缘。
  4. 根据权利要求1至3中任一项所述的显示基板，其中，所述数据线与薄膜晶体管的源极和漏极同层设置；
    所述显示基板还包括在所述数据线背离所述基底的一侧依次设置的钝化层、第一平坦化层、第二平坦化层，以及在所述第一平坦化层和所述第二平坦化层之间设置的转接电极；其中，
    所述转接电极通过贯穿所述钝化层和第一平坦化层的第二过孔与所述薄膜晶体管的漏极连接；所述发光器件的第一电极通过贯穿所述第二平坦化层的第三过孔与所述转接电极连接；
    所述扇出走线与所述转接电极相互绝缘并且同层设置，且材料相同。
  5. 根据权利要求3所述的显示基板，其中，所述多条扇出走线中的每一条扇出走线包括依次电连接的第一子连接线、第二子连接线和第三子连接线；其中，
    所述多条扇出走线的各个所述第一子连接线的第一端和与之对应的所述数据线连接，第二端连接与之对应的第二子连接线的第一端；各个所述第二子连接线的第二端连接与之对应的第三子连接线的第一端连接；
    所述多条扇出走线的各个第一子连接线相对于各个第三子连接线远离所述扇出区；以及
    所述多条扇出走线的各个第三子连接线中相邻的两条第三子连接线之间的间距小于相邻的两条第一子连接线之间的间距。
  6. 根据权利要求5所述的显示基板，其中，所述多条扇出走线的各个所述第三子连接线和/或各个所述第一子连接线的延伸方向与所述多条数据线的延伸方向相同。
  7. 根据权利要求6所述的显示基板，其中，所述多条扇出走线的各个所述第一子连接线并排设置位于所述显示区的中间区域。
  8. 根据权利要求7所述的显示基板，其中，
    每个像素区域内的所述发光器件包括有机发光二极管，其具有第一电极、第二电极以及第一电极和第二电极之间的有机发光层；
    所述有机发光二极管位于所述多条扇出走线远离所述基底的一侧；以及
    所述多条扇出走线的各个第三子连接线与所述多条数据线延伸方向相同，并且位于对应数据线的远离所述基底的一侧并且位于对应的有机发光层的靠近所述基底的一侧；以及
    所述第三子连接线在基底上的正投影落入对应的有机发光二极管在基底上的正投影范围内。
  9. 根据权利要求5至8中任一项所述的显示基板，其中，所述第二连接子线与所述第一连接子线之间的夹角和/或所述第二连接子线与所述第三连接子线之间的夹角范围在80度至100度之间。
  10. 根据权利要求1-9中任一项所述的显示基板，其中，所述像素单元还包括存储电容；所述存储电容的第一极板与所述薄膜晶体管的栅极同层设置，且材料相同；所述存储电容的第二极板与所述薄膜晶体管的源极和漏极同层设置，且材料相同。
  11. 根据权利要求1-9中任一项所述的显示基板，其中，所述像素单元还 包括存储电容；所述存储电容的第一极板与所述薄膜晶体管的栅极同层设置，且材料相同；所述存储电容的第二极板与所述薄膜晶体管的栅极上方的栅极绝缘层上设置的金属层同层设置，且材料相同。
  12. 根据权利要求1-9中任一项所述的显示基板，其中，所述多个像素单元包括多行多列像素单元，以及
    所述多行多列像素单元中至少部分行像素单元具有不同数量的像素单元。
  13. 根据权利要求12所述的显示基板，其中，沿靠近所述绑定区的方向，所述多行像素单元中各行像素单元中像素单元的数量递减。
  14. 一种显示装置，包括根据权利要求1-13任一项所述的显示基板。
  15. 根据权利要求14所述的显示装置，还包括驱动芯片；
    所述驱动芯片位于所述基底远离所述多个像素单元的一侧，且在所述绑定区与所述多条扇出走线电连接。
PCT/CN2021/100069 2020-06-18 2021-06-15 显示基板及显示装置 WO2021254319A1 (zh)

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