WO2021239538A3 - Verfahren zum simultanen fügen und isolieren eines leistungselektronischen halbleiterbauteils auf ein organisches und/oder keramisches substrat und entsprechender verbund - Google Patents

Verfahren zum simultanen fügen und isolieren eines leistungselektronischen halbleiterbauteils auf ein organisches und/oder keramisches substrat und entsprechender verbund Download PDF

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Publication number
WO2021239538A3
WO2021239538A3 PCT/EP2021/063280 EP2021063280W WO2021239538A3 WO 2021239538 A3 WO2021239538 A3 WO 2021239538A3 EP 2021063280 W EP2021063280 W EP 2021063280W WO 2021239538 A3 WO2021239538 A3 WO 2021239538A3
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WIPO (PCT)
Prior art keywords
film
semiconductor component
substrate
bonding
insulating
Prior art date
Application number
PCT/EP2021/063280
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English (en)
French (fr)
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WO2021239538A2 (de
Inventor
Bernd Müller
Christian NACHTIGALL-SCHELLENBERG
Jörg Strogies
Klaus Wilke
Original Assignee
Siemens Aktiengesellschaft
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Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to CN202180040352.8A priority Critical patent/CN115917716A/zh
Priority to US17/928,318 priority patent/US20230215838A1/en
Priority to EP21731049.9A priority patent/EP4115443A2/de
Publication of WO2021239538A2 publication Critical patent/WO2021239538A2/de
Publication of WO2021239538A3 publication Critical patent/WO2021239538A3/de

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

Um das Fügen und das Isolieren von leistungselektronischen Halbleiterbauteilen einfacher und effizienter zu gestalten, werden ein Verfahren zum Fügen und Isolieren eines leistungselektronischen Halbleiterbauteils (30) auf ein Substrat (10), das ein organischer und/oder keramischer Verdrahtungsträger ist, und ein gefügter Verbund aus einem leistungselektronischen Halbleiterbauteil (30) und einem Substrat (10), das ein organischer und/oder keramischer Verdrahtungsträger ist, vorgeschlagen, wobei das Verfahren folgende Schritte umfasst: Bereitstellen des Substrats (10) mit einer Metallisierung (12), das einen Einbauplatz mit Fügematerial (14, 15) aufweist; Anordnen einer elektrisch isolierenden Folie (20) und des Halbleiterbauteils (30) auf dem Substrat (10), sodass die dem Substrat (10) zugewandten Kontaktflächen (34, 35) des Halbleiterbauteils (30) von der Folie (20) ausgespart sind und von den Kontaktflächen (34, 35) freiliegende Bereiche des Halbleiterbauteils (30) zumindest teilweise durch die Folie (20) vom Substrat (10) und von den Kontaktflächen (34, 35) isoliert werden; und Fügen des Halbleiterbauteils (30) an das Substrat (10) und zumindest teilweises elektrisches Isolieren des Halbleiterbauteils (30) durch die Folie (20) in einem Arbeitsschritt. Das Verfahren kann weiterhin einen Schritt von Schließen eines verbleibenden Spalts (40) zwischen Metallisierung (12), Folie (20) und Halbleiterbauteil (30) durch ein Underfill-Material (25) umfassen. Zum Fügen des Halbleiterbauteils (30) kann ein Druck auf das Halbleiterbauteil (30) ausgeübt werden, sodass die Folie (20) dem Druck während des Fügens zumindest teilweise ausgesetzt ist. Die Folie (20) kann einen Guard-Ring-Bereich (36) des Halbleiterbauteils (30) isolieren. Die Folie (20) kann so dimensioniert sein, dass sie nach dem Fügen aus einem Spalt zwischen Metallisierung (12) des Substrats (10) und dem Halbleiterbauteil (30) herausragt. Alternativ kann die Folie (20) vollständig vom Halbleiterbauteil (30) abgedeckt sein, wobei der Guard-Ring-Bereich (36) über die Folie (20) oder über ein Underfill (25) isoliert ist. Die Folie (20) kann ein Elastomer, insbesondere ein Silikon-Elastomer, aufweisen oder daraus bestehen. Die Folie (20) kann einen Füllstoff, insbesondere einen keramischen Füllstoff, aufweisen, womit neben den Isolationseigenschaften der Folie (20) so auch weitere Eigenschaften wie Wärmeleitung und Ausdehnungskoeffizient angepasst werden können. Die Folie (20) kann eine Faserfüllung, insbesondere eine Glasfaserfüllung aufweisen. Die Folie (20) kann eine Haftschicht aufweisen.
PCT/EP2021/063280 2020-05-29 2021-05-19 Fügen und isolieren von leistungselektronischen halbleiterbauteilen WO2021239538A2 (de)

Priority Applications (3)

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CN202180040352.8A CN115917716A (zh) 2020-05-29 2021-05-19 在有机和/或陶瓷衬底上对功率电子半导体构件同时进行接合和绝缘的方法以及相应的复合结构体
US17/928,318 US20230215838A1 (en) 2020-05-29 2021-05-19 Joining and Insulating Power Electronic Semiconductor Components
EP21731049.9A EP4115443A2 (de) 2020-05-29 2021-05-19 Verfahren zum simultanen fügen und isolieren eines leistungselektronischen halbleiterbauteils auf ein organisches und/oder keramisches substrat und entsprechender verbund

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DE102020206763.5A DE102020206763A1 (de) 2020-05-29 2020-05-29 Fügen und Isolieren von leistungselektronischen Halbleiterbauteilen

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Citations (4)

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JPH0997815A (ja) * 1995-09-29 1997-04-08 Sumitomo Metal Mining Co Ltd フリップチップ接合方法およびそれにより得られる半導体パッケージ
US6399178B1 (en) * 1998-07-20 2002-06-04 Amerasia International Technology, Inc. Rigid adhesive underfill preform, as for a flip-chip device
US20100159644A1 (en) * 2008-12-19 2010-06-24 Rajiv Carl Dunne Low-cost flip-chip interconnect with an integrated wafer-applied photo-sensitive adhesive and metal-loaded epoxy paste system
US20120001200A1 (en) * 2009-03-02 2012-01-05 Panasonic Corporation Semiconductor device and manufacturing method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1732116B1 (de) 2005-06-08 2017-02-01 Imec Methode zum Bonden mikroelektronischer Bauteile und damit hergestellte Vorrichtung
DE102006013853B4 (de) 2006-03-23 2010-09-30 Infineon Technologies Ag Leistungshalbleiterbauelement mit großflächigen Außenkontakten sowie Verfahren zur Herstellung desselben
US7867878B2 (en) 2007-09-21 2011-01-11 Infineon Technologies Ag Stacked semiconductor chips
EP3618586A1 (de) 2018-08-31 2020-03-04 Siemens Aktiengesellschaft Schaltungsträger mit einem einbauplatz für elektronische bauelemente, elektronische schaltung und herstellungsverfahren

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0997815A (ja) * 1995-09-29 1997-04-08 Sumitomo Metal Mining Co Ltd フリップチップ接合方法およびそれにより得られる半導体パッケージ
US6399178B1 (en) * 1998-07-20 2002-06-04 Amerasia International Technology, Inc. Rigid adhesive underfill preform, as for a flip-chip device
US20100159644A1 (en) * 2008-12-19 2010-06-24 Rajiv Carl Dunne Low-cost flip-chip interconnect with an integrated wafer-applied photo-sensitive adhesive and metal-loaded epoxy paste system
US20120001200A1 (en) * 2009-03-02 2012-01-05 Panasonic Corporation Semiconductor device and manufacturing method thereof

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WO2021239538A2 (de) 2021-12-02
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US20230215838A1 (en) 2023-07-06
CN115917716A (zh) 2023-04-04

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