WO2021239538A3 - Method for simultaneously bonding to and insulating a power electronic semiconductor component on an organic and/or ceramic substrate, and corresponding composite unit - Google Patents

Method for simultaneously bonding to and insulating a power electronic semiconductor component on an organic and/or ceramic substrate, and corresponding composite unit Download PDF

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Publication number
WO2021239538A3
WO2021239538A3 PCT/EP2021/063280 EP2021063280W WO2021239538A3 WO 2021239538 A3 WO2021239538 A3 WO 2021239538A3 EP 2021063280 W EP2021063280 W EP 2021063280W WO 2021239538 A3 WO2021239538 A3 WO 2021239538A3
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WO
WIPO (PCT)
Prior art keywords
film
semiconductor component
substrate
bonding
insulating
Prior art date
Application number
PCT/EP2021/063280
Other languages
German (de)
French (fr)
Other versions
WO2021239538A2 (en
Inventor
Bernd Müller
Christian NACHTIGALL-SCHELLENBERG
Jörg Strogies
Klaus Wilke
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Priority to CN202180040352.8A priority Critical patent/CN115917716A/en
Priority to US17/928,318 priority patent/US20230215838A1/en
Priority to EP21731049.9A priority patent/EP4115443A2/en
Publication of WO2021239538A2 publication Critical patent/WO2021239538A2/en
Publication of WO2021239538A3 publication Critical patent/WO2021239538A3/en

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    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H01L23/295—Organic, e.g. plastic containing a filler
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2924/06—Polymers
    • H01L2924/0715—Polysiloxane

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Adhesives Or Adhesive Processes (AREA)

Abstract

In order to make the bonding and insulating of power electronic semiconductor components simpler and more efficient, the invention proposes: a method for bonding to and insulating a power electronic semiconductor component (30) on a substrate (10), which is an organic and/or ceramic wiring support; and a bonded composite unit consisting of a power electronic semiconductor component (30) and a substrate (10), which is an organic and/or ceramic wiring support. The method comprises the following steps: providing the substrate (10) which has a metallization (12) and an installation slot with bonding material (14, 15); arranging an electrically insulating film (20) and the semiconductor component (30) on the substrate (10) so that the contact faces (34, 35) of the semiconductor component (30) facing the substrate (10) are not covered by the film (20) and regions of the semiconductor component (30) exposed by the contact faces (34, 35) are insulated at least in part from the substrate (10) and from the contact surfaces (34, 35) by means of the film (20); and bonding the semiconductor component (30) to the substrate (10) and electrically insulating the semiconductor component (30) at least in part by means of the film (20) in one process step. The method can also comprise the step of closing a remaining gap (40) between the metallization (12), film (20) and semiconductor component (30) by means of an underfill material (25). In order to bond the semiconductor component (30) pressure can be exerted on the semiconductor component (30) so that the film (20) is at least partly subjected to the pressure during bonding. The film (20)can insulate a guard-ring region (36) of the semiconductor component (30). The film (20) can be dimensioned such that it protrudes from a gap between the metallization (12) of the substrate (10) and the semiconductor component (30) after bonding. Alternatively, the film (20) can be completely covered by the semiconductor component (30), the guard-ring region (36) being insulated by means of the film (20) or by means of an underfill (25). The film (20) can comprise or consist of an elastomer, in particular a silicone elastomer. The film (20) can comprise a filler, in particular a ceramic filler, and therefore, in addition to the insulating properties of the film (20), other properties such as thermal conduction and expansion coefficient can be adapted. The film (20) can comprise a fiber filling, in particular a glass fiber filling. The film (20) can have an adhesive layer.
PCT/EP2021/063280 2020-05-29 2021-05-19 Joining and insulating power electronic semiconductor components WO2021239538A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202180040352.8A CN115917716A (en) 2020-05-29 2021-05-19 Method for simultaneously joining and insulating power electronic semiconductor components on organic and/or ceramic substrates, and corresponding composite structure
US17/928,318 US20230215838A1 (en) 2020-05-29 2021-05-19 Joining and Insulating Power Electronic Semiconductor Components
EP21731049.9A EP4115443A2 (en) 2020-05-29 2021-05-19 Method for simultaneously bonding to and insulating a power electronic semiconductor component on an organic and/or ceramic substrate, and correponding composite unit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102020206763.5 2020-05-29
DE102020206763.5A DE102020206763A1 (en) 2020-05-29 2020-05-29 Joining and insulating power electronic semiconductor components

Publications (2)

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WO2021239538A2 WO2021239538A2 (en) 2021-12-02
WO2021239538A3 true WO2021239538A3 (en) 2022-02-03

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US (1) US20230215838A1 (en)
EP (1) EP4115443A2 (en)
CN (1) CN115917716A (en)
DE (1) DE102020206763A1 (en)
WO (1) WO2021239538A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0997815A (en) * 1995-09-29 1997-04-08 Sumitomo Metal Mining Co Ltd Flip-chip junction method and semiconductor package to be obtained thereby
US6399178B1 (en) * 1998-07-20 2002-06-04 Amerasia International Technology, Inc. Rigid adhesive underfill preform, as for a flip-chip device
US20100159644A1 (en) * 2008-12-19 2010-06-24 Rajiv Carl Dunne Low-cost flip-chip interconnect with an integrated wafer-applied photo-sensitive adhesive and metal-loaded epoxy paste system
US20120001200A1 (en) * 2009-03-02 2012-01-05 Panasonic Corporation Semiconductor device and manufacturing method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1732116B1 (en) 2005-06-08 2017-02-01 Imec Methods for bonding and micro-electronic devices produced according to such methods
DE102006013853B4 (en) 2006-03-23 2010-09-30 Infineon Technologies Ag Power semiconductor component with large-area external contacts and method for producing the same
US7867878B2 (en) 2007-09-21 2011-01-11 Infineon Technologies Ag Stacked semiconductor chips
EP3618586A1 (en) 2018-08-31 2020-03-04 Siemens Aktiengesellschaft Circuit carrier comprising a mounting place for electronic components, electronic circuit and manufacturing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0997815A (en) * 1995-09-29 1997-04-08 Sumitomo Metal Mining Co Ltd Flip-chip junction method and semiconductor package to be obtained thereby
US6399178B1 (en) * 1998-07-20 2002-06-04 Amerasia International Technology, Inc. Rigid adhesive underfill preform, as for a flip-chip device
US20100159644A1 (en) * 2008-12-19 2010-06-24 Rajiv Carl Dunne Low-cost flip-chip interconnect with an integrated wafer-applied photo-sensitive adhesive and metal-loaded epoxy paste system
US20120001200A1 (en) * 2009-03-02 2012-01-05 Panasonic Corporation Semiconductor device and manufacturing method thereof

Also Published As

Publication number Publication date
EP4115443A2 (en) 2023-01-11
WO2021239538A2 (en) 2021-12-02
DE102020206763A1 (en) 2021-12-02
US20230215838A1 (en) 2023-07-06
CN115917716A (en) 2023-04-04

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