CN104078454A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN104078454A
CN104078454A CN201310491324.5A CN201310491324A CN104078454A CN 104078454 A CN104078454 A CN 104078454A CN 201310491324 A CN201310491324 A CN 201310491324A CN 104078454 A CN104078454 A CN 104078454A
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CN
China
Prior art keywords
semiconductor device
chip
connecting portion
insert material
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201310491324.5A
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Chinese (zh)
Inventor
福吉宽
中尾淳一
远藤佳纪
三宅英太郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
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Toshiba Corp
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Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN104078454A publication Critical patent/CN104078454A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/049—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads being perpendicular to the base
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    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
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Abstract

An aspect of the present embodiment, there is provided a semiconductor device, including an insulating substrate, at least one semiconductor chip provided above the insulating substrate, a wiring terminal including a connection portion electrically connected to the semiconductor chip, a surrounding frame surrounding the semiconductor chip and the connection portion, an embedded material provided in the surrounding frame covering the semiconductor chip and the connection portion, and a pressing unit provided on a surface of the embedded material.

Description

Semiconductor device
The cross reference of related application
The application based on and require the priority of formerly Japanese patent application No.2013-061864 of submitting on March 25th, 2013, its full content is incorporated to herein by reference.
Technical field
Exemplary embodiment described herein is usually directed to a kind of semiconductor device.
Background technology
Conventional power semiconductor comprises at least one semiconductor chip and is wherein provided with the binding post of the connecting portion that is electrically connected to this semiconductor chip.
When carrying out temperature test, for example, when TFT (thermal fatigue test), this semiconductor device has at connecting portion and produces deteriorated possibility.
For example, in bell connection (bell connection) portion, produce warpage, or for example, produce and break in the grafting material (, scolder) of bond semiconductor chip and connecting portion.
Summary of the invention
An aspect of the present embodiment, a kind of semiconductor device is provided, comprise insulated substrate, be arranged at least one semiconductor chip on insulated substrate, comprise the connecting portion that is electrically connected to this semiconductor chip binding post, surround this semiconductor chip and connecting portion encirclement framework, be arranged on to surround in framework and cover the insert material of this semiconductor chip and connecting portion and be arranged on the lip-deep unit of pressing of this insert material.
Brief description of the drawings
Fig. 1 is the plane graph illustrating according to the structure of the semiconductor device of the first embodiment;
Fig. 2 is showing according to the sectional view along A-A line in Fig. 1 of the structure of the semiconductor device of the first embodiment;
Fig. 3 is the sectional view illustrating according to the structure of the semiconductor device of the first embodiment;
Fig. 4 is illustrating according to the sectional view along B-B line in Fig. 3 of the structure of the semiconductor device of the first embodiment;
Fig. 5 is the sectional view that the effect of the first embodiment is shown;
Fig. 6 is the chart illustrating respectively according to the result of the thermal fatigue test of the first embodiment and regular situation.
Embodiment
Describe embodiment in detail below with reference to above-mentioned accompanying drawing.
(the first embodiment)
Fig. 1 is the plane graph that the structure of semiconductor device is shown.Fig. 2 is the sectional view along A-A line.
According to the structure of the semiconductor device of the first embodiment mainly with reference to Fig. 1 and be described with reference to Fig. 2 if desired.
As shown in Figure 1, according to the semiconductor device of the first embodiment comprise heating panel 1, insulated substrate 2, front surface conducting film 3a-3e, with reference to the back of the body surface conductance film 4 shown in Fig. 2, IGBT (igbt) chip 11a, 11b, FRD (fast recovery diode) chip 12a-12d, binding post 13a13b, engage (bonding) line 14a, 14b, encirclement framework 21a, 21b and insert material 22a, 22b.
Front surface conducting film 3a-3e is formed on the front surface of insulated substrate 2, and back of the body surface conductance film 4 is formed on the back of the body surface of insulated substrate 2.Insulated substrate 2 is for example made up of ceramic substrate etc.Front surface conducting film 3a-3e and back of the body surface conductance film 4 are the metallic plates that are for example made up of metal.
Insulated substrate 2 is arranged on heating panel 1 via back of the body surface conductance film 4.With reference to Fig. 2, insulated substrate 2 joins heating panel 1 to by grafting material 6.Heating panel 1 is made up of the metal for example with high thermoconductivity.Grafting material 6 for example, is made up of scolder, the metal (silver slurry, copper slurry etc.) with excellent heat conductivity.Mark H 1-H 8show the screw hole being formed in heating panel 1.
Three directions have been shown in Fig. 1, and wherein, directions X and Y-direction are parallel to the first type surface of heating panel 1 and insulated substrate 2, and vertical setting mutually, and Z direction is towards vertical setting of first type surface of heating panel 1 and insulated substrate 2.+ Z direction and-Z direction relates separately to direction and lower direction in specification.Relation table example between heating panel 1 and the position of insulated substrate 2 is positioned at below insulated substrate 2 as heating panel 1.
Igbt chip 11a and FRD chip 12a, 12b are arranged on insulated substrate 2 by front surface conducting film 3a.Igbt chip 11b and FRD chip 12c, 12d are arranged on insulated substrate 2 by front surface conducting film 3c.
Each igbt chip 11a, 11b comprise the transistorized semiconductor chip that is called as IGBT.Each FRD chip 12a-12d is the semiconductor chip that comprises the diode that is called as FRD.With reference to Fig. 2, igbt chip 11a, 11b and FRD chip 12a-12d are electrically connected to front surface conducting film 3a, 3c by grafting material 5.Grafting material 5 for example, is made up of scolder, conducting metal (silver slurry, copper slurry etc.).
Binding post 13a comprises the connecting portion P that is electrically connected to igbt chip 11a 1, be electrically connected to the connecting portion P of FRD chip 12a 2, be electrically connected to the connecting portion P of FRD chip 12b 3.In addition, binding post 13a is electrically connected to front surface conducting film 3c.
Binding post 13b comprises the connecting portion P that is electrically connected to igbt chip 11b 4, be electrically connected to the connecting portion P of FRD chip 12c 5, and be electrically connected to the connecting portion P of FRD chip 12d 6.In addition, binding post 13b is electrically connected to front surface conducting film 3e.
Binding post 13a, 13b are for example made up of metal.With reference to Fig. 2, the connecting portion P of binding post 13a, 13b 1-P 6be electrically connected to igbt chip 11a, 11b and FRD chip 12a, 12d by grafting material 5.
Igbt chip 11a and FRD chip 12a, 12b are connected in parallel by front surface conducting film 3a and binding post 13a.In addition, igbt chip 11b and FRD chip 12c, 12d are connected in parallel by front surface conducting film 3c and binding post 13b.
Closing line 14a electrical connection igbt chip 11a and front surface conducting film 3b.In addition closing line 14b electrical connection igbt chip 11b and front surface conducting film 3d.Closing line 14a, 14b are connected respectively to the grid of igbt chip 11a, 11b.Closing line 14a, 14b made of aluminum, diameter is the closing line composition of 350 μ m.
Closing line 14a is not accurately shown in the sectional view of Fig. 2, but shown in Figure 2 for convenience of description.This section's situation is same in the Fig. 3 describing after a while.
Surrounding framework 21a, 21b has round-shaped.Surround framework 21a and be arranged on insulated substrate 2 by front surface conducting film 3a, and surround igbt chip 11a, FRD chip 12a, 12b and connecting portion P 1-P 3.Surround framework 21b and be arranged on insulated substrate 2 by front surface conducting film 3c, and surround igbt chip 11b, FRD chip 12c, 12d and connecting portion P 4-P 6.
In the first embodiment, surround framework 21a, 21b and formed by insulating material.Insulating material is for example resin or pottery.Surround framework 21a, 21b and for example, be connected to front surface conducting film 3a, 3c by grafting material, silicones, epoxy resin, scolder (silver slurry, copper slurry etc.).
Surrounding framework 21a, 21b can be made up of the electric conducting material such as metal.In this case, expect the distance of surrounding between framework 21a, 21b to be set as being wider than closing line 14a, 14b, to guarantee to surround the insulation quality between framework 21a, 21b and closing line 14a, 14b.
Insert material 22a is embedded in encirclement framework 21a, to cover igbt chip 11a, FRD chip 12a, 12b and connecting portion P 1-P 3.Insert material 22b is embedded in encirclement framework 21b, to cover igbt chip 11b, FRD chip 12c-12d and connecting portion P 4-P 6.
In the first embodiment, insert material 22a, 22b are made up of resin.Resin is for example epoxy resin.Form insert material 22a, 22b by the liquid of epoxy resin being injected into surround in framework 21a, 21b with the liquid of cured epoxy resin.Insert material 22a, 22b can be the insulating material except epoxy resin, and wherein this insulating material has the hardness that comprises traffic load ability.
After having connected closing line 14a, 14b, embed each insert material 22a, 22b.Because while being embedded into before insert material 22a, 22b are connecting closing line 14a, 14b, closing line 14a, 14b can not be connected to igbt chip 11a, 11b.Correspondingly, as shown in Figure 2, each closing line 14a, 14b are partly embedded in insert material 22a, 22b.
The region of insert material 22a, 22b is illustrated by the point in Fig. 1,2.In Fig. 1, igbt chip 11a, the 11b, FRD chip 12a-12d and the connecting portion P that are covered by insert material 22a, 22b 1-p 6profile not deleted and by being shown that mountain is to facilitate explanation.
Fig. 3 is the sectional view illustrating according to the structure of the semiconductor device of the first embodiment.Fig. 4 is the sectional view along the line B-B in Fig. 3.Semiconductor device shown in Fig. 3,4 is the feature after housing 31 is fixed on the heating panel 1 in Fig. 1,2.
According to the structure of the semiconductor device of the first embodiment mainly with reference to Fig. 3 and be described with reference to Fig. 4 if desired.
As shown in Figure 3, the semiconductor device in the first embodiment also comprises housing 31, self-tapping screw 32, hex nut 33, external power terminal 34 and external signal terminal 35.
Housing 31 is fixed to heating panel 1 to cover insulated substrate 2 and heating panel 1.Heating panel 1 and housing 31 are tightened by self-tapping screw 32.In addition,, as another embodiment, heating panel 1 and housing 31 also can be tightened by the screw except self-tapping screw 32.The sharp housing 31 of heating panel 1 has screw hole to use conventional screw tightening to housing 31.Hex nut 33, external power terminal 34 and external signal terminal 35 are fixed to housing 31.Housing 31 for example, is made up of insulating material (resin in the first embodiment).
Housing 31 in the first embodiment is included in presses unit 31a, 31b in the position relative with insert material 22a, 22b.Each length of pressing unit 31a, 31b is set to before heating panel 1 and housing 31 are tightened completely by self-tapping screw 32, and each unit 31a, 31b of pressing is connected respectively fully with each insert material 22a, 22b., each unit 31a, 31b of pressing projects upwards in the side of each insert material 22a, 22b respectively.In the time that heating panel 1 and housing 31 are fully tightened by self-tapping screw 32, each unit 31a, 31b of pressing presses each insert material 22a, 22b towards the upper surface of each insert material 22a, 22b.Each unit 31a, 31b of pressing is for example 0.1-0.2mm towards the overhang of each insert material 22a, 22b.
In the first embodiment, press unit 31a, 31b and be constructed to the part of housing 31.But it is not limited by above-mentioned situation.Can use the member except housing 31, as long as the surface that can press insert material 22a, 22b as this member of other embodiment.On the other hand, when pressing unit 31a, 31b, while being configured to the part of housing 31, do not need preparation to press unit 31a, 31b except housing 31, thereby can reduce the production cost of semiconductor device.
After heating panel 1 is tightened by self-tapping screw 32, silicon gel is injected into housing 31 and completes the semiconductor device in the first embodiment.
The effect of the first embodiment is described with reference to Fig. 5,6.
Fig. 5 is the sectional view that the effect of the first embodiment is shown.
Before being embedded by insert material 22a, figure 5 illustrates the connecting portion P pressing by pressing unit 31a 1.In this case, in the time carrying out the temperature cycling test of this semiconductor device, at connecting portion P 1produce warpage, thereby produce stress, this stress has removed connecting portion P 1and grafting material 5 between igbt chip 11a, as shown in Figure 5.Therefore,, when producing while breaking in grafting material 5, can produce such as conduction defect etc. deteriorated.
Therefore, as Figure 1-4, the semiconductor device in the first embodiment comprises encirclement connecting portion P 1-P 6encirclement framework 21a, 21b, be embedded into surround insert material 22a, the 22b in framework 21a, 21b and press insert material 22a, 22b surface press unit 31a, 31b.
Correspondingly, insert material 22a, the 22b in the first embodiment presses and applies compression pressure to its surface by pressing unit 31a, 31b.As a result of, this compression pressure acts on connecting portion P 1-P 6with grafting material 5.
Therefore, formed at connecting portion P 1-P 6middle generation warpage and the stress that removes grafting material 5 are offset by above-mentioned compression pressure.Therefore, can be controlled in connecting portion P 1-P 6the generation of middle warpage and the generation of breaking in grafting material 5.As a result of, in the time carrying out temperature cycling test in the first embodiment, can be controlled in connecting portion P 1-P 6the generation of middle defect.
Fig. 6 is the chart illustrating respectively according to the thermal fatigue test result of the first embodiment and regular situation.
Thermal fatigue test in Fig. 6 is that scope is carried out under the condition between 25-115 DEG C (△ Tc=90 DEG C).The number of 10,000 and 70,000 accumulation defects between circulation has been shown in Fig. 6.Judge in the following description whether semiconductor device has defect.After test, can be confirmed whether to produce by decomposing semiconductor device the electrical characteristics fault causing due to breaking of grafting material 5.
As shown in Figure 6, below 30,000 circulations, do not there is the framework 21a of encirclement, 21b, insert material 22a, 22b and press in the conventional semiconductor device of unit 31a, 31b and produced defect.Correspondingly, conventional semiconductor device can not be broken through the target of (clear) 60,000 circulations.
On the other hand, surround framework 21a, 21b comprising, insert material 22a, 22b and press in the semiconductor device of unit 31a, 31b do not produce any defect before 70,000 circulations.Therefore, the semiconductor device in the first embodiment can be broken through the target of 60,000 circulations in thermal fatigue test.
As mentioned above, the semiconductor device in the first embodiment comprises semiconductor chip 11a-12d, surrounds connecting portion P 1-P 6encirclement framework 21a, 21b, be embedded into and surround insert material 22a, the 22b in framework 21a, 21b and press surperficial unit 31a, the 31b of pressing of insert material 22a, 22b.
Therefore,, according to the first embodiment, can provide semiconductor device temperature cycling test to higher reliability.
Although described specific embodiment, but these embodiment only propose by way of example, and are not intended to limit the scope of the invention.In fact, the embodiment of novelty described herein can realize by various other modes; And, in the situation that not deviating from spirit of the present invention, can make various omissions, replacement and change with embodiment form described herein.Claims and equivalents thereof are intended to cover and will fall into such form profit amendment of scope and spirit of the present invention.

Claims (16)

1. a semiconductor device, comprising:
Insulated substrate;
At least one semiconductor chip, it is arranged on described insulated substrate;
Binding post, it comprises the connecting portion that is electrically connected to described semiconductor chip;
Surround framework, it surrounds described semiconductor chip and described connecting portion;
Insert material, it is arranged on and in described encirclement framework, covers described semiconductor chip and described connecting portion; And
Press unit, it is arranged on the surface of described insert material.
2. semiconductor device as claimed in claim 1, also comprises:
The first grafting material, described connecting portion is connected to described semiconductor chip by described the first grafting material.
3. semiconductor device as claimed in claim 1, wherein
Described insert material is made up of resin.
4. semiconductor device as claimed in claim 1, also comprises:
Cover the housing of described insulated substrate, described by a part for housing described in happy cell formation.
5. semiconductor device as claimed in claim 4, also comprises:
Heating panel and screw, described insulated substrate on described heating panel, heating panel and described housing described in described screw tightening.
6. semiconductor device as claimed in claim 1, also comprises:
Closing line, it is partly arranged in described insert material, and is electrically connected to described semiconductor chip.
7. semiconductor device as claimed in claim 1, also comprises:
Front surface conducting film and the second grafting material, described front surface conducting film is arranged in described insulation base stage, and described semiconductor chip is arranged on described front surface conducting film by described the second grafting material.
8. semiconductor device as claimed in claim 1, wherein
The described unit of pressing is made up of resin.
9. semiconductor device as claimed in claim 1, wherein
The described unit of pressing projects upwards in the side of described insert material.
10. semiconductor device as claimed in claim 9, wherein
Described length of pressing the overhang of unit in the direction of described insert material and have 1-2mm.
11. semiconductor device as claimed in claim 1, wherein
Described insert material is pressed and is applied in compression pressure by the described unit of pressing.
12. semiconductor device as claimed in claim 11, wherein
Described compression pressure acts on described connecting portion and described the first grafting material.
13. semiconductor device as claimed in claim 1, wherein
At least one chip that is selected from igbt chip and FRD chip is included in described semiconductor chip.
14. semiconductor device as claimed in claim 6, it is little
Described encirclement framework is arranged on described insulated substrate by described front surface conducting film.
15. semiconductor device as claimed in claim 1, wherein
Described encirclement framework has round-shaped.
16. semiconductor device as claimed in claim 1, wherein
Described encirclement framework is made up of insulating material or electric conducting material.
CN201310491324.5A 2013-03-25 2013-09-09 Semiconductor device Pending CN104078454A (en)

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