JPS59181033A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59181033A JPS59181033A JP58053545A JP5354583A JPS59181033A JP S59181033 A JPS59181033 A JP S59181033A JP 58053545 A JP58053545 A JP 58053545A JP 5354583 A JP5354583 A JP 5354583A JP S59181033 A JPS59181033 A JP S59181033A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- resin
- substrate
- semiconductor chip
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は例えば腕時計用ＩＣなどとして用いられる薄
型の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a thin semiconductor device used, for example, as an IC for a wristwatch.
半導体チップの外囲器としては種々のものが用いられて
いるが、最近の時計用ＩＣなどとしては極めて薄い形状
のものが要求されている。Various types of envelopes are used for semiconductor chips, but recent ICs for watches and the like require extremely thin envelopes.
第１図に示すものは、このような時計用ＩＣなどとして
用いられている薄型の装置の一例である。図において、
１１は表面に導体層のパターンｌｌｃが形成された絶縁
性の板からなる基板で、上記基板１１の所定部に接着剤
１２を用いて半導体チラノ１０を取着する。そして、上
記半導体チラノ１０の所定部位と基板１１の所定パター
ンｌｌｃとをボンディングワイヤ１４を用いて接続した
後、上記半導体チップ１０およびそのボンディング接続
部を囲むような枠部１３を基板１１に取り付け、上記半
導体チップ１０を封止するように溶融状態の例えばエポ
キシ樹脂などのポツティング嶺脂１５を上記枠部１３内
に流し込み硬化させる。そして上記のようにして製造し
た半導体装置を、枠部１３の外に引き出された基板１１
表面の導体Ｍパターンを接続部として例えば時計の回路
に組み込むようにするものである。What is shown in FIG. 1 is an example of a thin device used as such an IC for a watch. In the figure,
Reference numeral 11 denotes a substrate made of an insulating plate with a conductor layer pattern llc formed on its surface, and a semiconductor tyranno 10 is attached to a predetermined portion of the substrate 11 using an adhesive 12. After connecting a predetermined portion of the semiconductor tyranno 10 and a predetermined pattern llc of the substrate 11 using a bonding wire 14, a frame portion 13 surrounding the semiconductor chip 10 and its bonding connection portion is attached to the substrate 11, A potting resin 15 such as epoxy resin in a molten state is poured into the frame 13 so as to seal the semiconductor chip 10 and hardened. Then, the semiconductor device manufactured as described above is placed on the substrate 11 which is pulled out of the frame portion 13.
The conductor M pattern on the surface is used as a connection part to be incorporated into, for example, a watch circuit.
このような半導体装・Ｍは、基板１１の厚みが１００μ
ｍ程度、半導体チップ１０の厚みが２００μｍ程度で、
かなり薄く小型の半導体装置を実現できる。In such a semiconductor device M, the thickness of the substrate 11 is 100 μm.
m, the thickness of the semiconductor chip 10 is about 200 μm,
A fairly thin and compact semiconductor device can be realized.
しかしながら、上記のような装置では枠部１３に溶し込
まれるポツティング樹脂の量がかなり多く、溶けたポツ
ティング樹脂１５は、表面張力で図のようにかな）盛ｂ
ｆ、−ｐた状態となってから硬化する。そのため、半
導体装置の薄型化に限界があると共に、樹脂１５を多量
に必要とし、さらには硬化中に樹脂１５中に発生するガ
スが抜きにくくなるため樹脂１５中にボイド（気泡）が
残ったままとなりやすかった。このようなボイドの多い
ものは耐湿性、信頼性が悪いものである。However, in the above-mentioned device, the amount of potting resin melted into the frame 13 is quite large, and the melted potting resin 15 is caused by surface tension as shown in the figure.
After reaching f, -p state, it is cured. Therefore, there is a limit to how thin the semiconductor device can be made, a large amount of the resin 15 is required, and furthermore, it becomes difficult to remove the gas generated in the resin 15 during curing, leaving voids (bubbles) in the resin 15. It was easy to be next to him. A material with many such voids has poor moisture resistance and reliability.
マタ、デンディングワイヤ１４のがンディング工程が終
了した後樹脂１５を枠部１３内に流し込む手段として、
■溶融した樹脂を滴下する■エポキシ樹脂片を半導体チ
ラノ１０上に載せた状態で加熱処理しエポキシ樹脂片を
溶かすなどの方法が用いられているが、ポンディングワ
イヤ１４自体がねじれぐせを持っている場合が多く、特
に後者のエポキシ樹脂片を載せる方法により樹脂１５で
封止する際にポンディングワイヤ１４がつぶれ半導体チ
ップ１０や導体層パターンｌｌｃとショートする事故が
発生しやすいものであった。As a means for pouring the resin 15 into the frame part 13 after the ending process of the ending wire 14 is completed,
■Dropping molten resin■Methods such as heating an epoxy resin piece placed on the semiconductor tyranno 10 and melting the epoxy resin piece are used, but the bonding wire 14 itself has twisted curls. In particular, when sealing with the resin 15 using the latter method of placing an epoxy resin piece, the bonding wire 14 is likely to be crushed and short-circuited with the semiconductor chip 10 or the conductor layer pattern llc.
この発明は上記のような点に鑑みなされたもので、樹脂
封止部の外形の厚さが薄くポツティング樹脂の使用量が
少なくて済みぎイドの発生が低減されワイヤつぶれの発
生する恐れがない樹脂封止型の半導体装置を提供し、装
置の小型化、コストの低減と信頼性および歩留りの向上
とを実現しようとするものである。This invention was made in view of the above points, and the outer thickness of the resin-sealed part is thin, so the amount of potting resin used is small, the occurrence of girdling is reduced, and there is no risk of wire crushing. The present invention provides a resin-sealed semiconductor device, and aims to realize miniaturization of the device, reduction in cost, and improvement in reliability and yield.
すなわちこの発明に係る半導体装置では、基板の半導体
チップの取着される部位と基板上面のワイヤとの接続点
との間にポツティング樹脂の流れ止め用枠部を形成し、
上記枠部内の基板上に半導体チップを取着し、この半導
体チップの所定の部位と上記基板の上記接続点とを枠部
をまたぐようにワイヤで接続した後、枠部内にポツティ
ング樹脂を流し込んで硬化させたものである〇
〔発明の実施例〕
以下図面を参照してこの発明の一実施例を説明する。第
２図において、表面に導体層の／やターンｌｌｃが形成
された絶縁性の基板１１上に接着剤１２を用いて半導体
チップ１０を取着する。続いて、絶縁材からなる樹脂流
れ防止用の枠部１３を上記半導体チップ１０の周囲を囲
むように接着剤を用いて取り付ける。次いで上記枠部１
３をまたぐように、半導体チラノ１０上のメンディング
部１と基板１１上のポンディング部２との間を、？ンデ
ィングワイヤ１４を用いて接続する。続いて、上記ぎン
デイングワイヤ１４により形成されるループの頂点１４
ｐが低くなるように板などでがンデづングワイヤ１４を
軽く押さえる。That is, in the semiconductor device according to the present invention, a frame portion for preventing the potting resin from flowing is formed between the portion of the substrate where the semiconductor chip is attached and the connection point with the wire on the top surface of the substrate,
A semiconductor chip is mounted on the substrate within the frame, a predetermined portion of the semiconductor chip and the connection point of the substrate are connected with a wire across the frame, and then potting resin is poured into the frame. [Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings. In FIG. 2, a semiconductor chip 10 is attached using an adhesive 12 onto an insulating substrate 11 on which a conductive layer/turn llc is formed. Subsequently, a frame portion 13 made of an insulating material for preventing resin flow is attached using an adhesive so as to surround the semiconductor chip 10 . Next, the frame part 1
3, between the mending part 1 on the semiconductor tyranno 10 and the bonding part 2 on the substrate 11. The connection is made using the ending wire 14. Next, the apex 14 of the loop formed by the binding wire 14 is
Lightly press down the mounting wire 14 with a plate or the like so that p is low.
ここで、第２図に示す装置ではがンデイングワイヤ１４
の下に枠部１３が存在するため、ボンディングワイヤ１
４を板などで押しても、ボンディングワイヤ１４が過度
に押さえられ半導体チッｆｌＯに触れたり、基板１１の
導電層ツヤターン１１Ｃに触れる恐れがない。Here, in the apparatus shown in FIG.
Since the frame 13 exists under the bonding wire 1
Even if 4 is pressed with a plate or the like, there is no risk of the bonding wire 14 being excessively pressed and touching the semiconductor chip flO or the conductive layer glossy turn 11C of the substrate 11.
続いて、半導体チッ７″１０上にポツティング用エポキ
シ樹脂片を載せ、基板１１全体を加熱して上記樹脂片を
溶かし、半導体チップ１０を−うように溶融樹脂が枠部
１３内に流れた段階で、ポツティング樹脂１５を硬化さ
せる。Next, a piece of epoxy resin for potting is placed on the semiconductor chip 7''10, the entire substrate 11 is heated to melt the resin piece, and the molten resin flows into the frame 13 so as to cover the semiconductor chip 10. Then, the potting resin 15 is cured.
以上のようにして形成した半導体装置では、ビンディン
グワイヤ１４の高さも低く、枠部１３内の面積も小さい
ため、少量のポツティング樹脂１５で半導体チップ１０
を充分に封止することができる。このためポツティング
樹脂１５の厚みを薄くして装置の小型化を実現できると
ともに、ポツティング用樹脂の使用量が少なくて済み、
コストの低減を図れる。また樹脂量が少ないため気泡の
まき込みを生じにくく気泡を充分に抜くことがでも、さ
らにボッティンディングワイヤ１４の山を完全につぶす
ことも生じにくくなる。In the semiconductor device formed as described above, since the height of the binding wire 14 is low and the area within the frame 13 is small, a small amount of potting resin 15 is required to attach the semiconductor chip 10.
can be sufficiently sealed. Therefore, it is possible to reduce the thickness of the potting resin 15 and downsize the device, and the amount of potting resin used can be reduced.
Cost reduction can be achieved. Furthermore, since the amount of resin is small, it is difficult to entrain air bubbles, and even if the air bubbles are removed sufficiently, it is also difficult to completely crush the peaks of the botting wire 14.
なお、上記実施例では枠部１３内に樹脂１５を流し込む
場合につき述べたが、枠部１３から溢れるようにポツテ
ィング樹脂１５を流し込み基板１１のがンディング部２
側を樹脂で覆うようにしてもよい。In the above embodiment, the resin 15 is poured into the frame 13. However, the potting resin 15 is poured so as to overflow from the frame 13, and the substrate 11 is poured into the landing area 2.
The sides may be covered with resin.
また、上記装置をポリイミドチーブ等を用いたテープキ
ャリア方式によって形成することができる。この場合に
は銅箔などによる導電層のパターンの形成されたポリイ
ミドチーブを基板１１として、このテープの所定位置に
半導体チップ１０を接着剤等で取り付ける。その後、半
導体チップ１０の周囲に枠部１３を接着し、ボンディン
グワイヤ１４等の接続手段によってチッ７Ｄ１０と枠部
１３の外側に存在する導電層のノリーンｌｌａとを接続
した後、ポツティングｄ脂１５を流し込むようにするも
のである。Further, the above device can be formed by a tape carrier method using polyimide chips or the like. In this case, a polyimide chip on which a pattern of a conductive layer made of copper foil or the like is formed is used as the substrate 11, and the semiconductor chip 10 is attached to a predetermined position of this tape using an adhesive or the like. After that, the frame part 13 is bonded around the semiconductor chip 10, and the chip 7D10 and the conductive layer Noreen lla existing on the outside of the frame part 13 are connected by a connecting means such as a bonding wire 14, and then the potting d resin 15 is bonded. It is meant to flow in.
以上のようにこの発明によれば、樹脂封止部の外形の厚
さが薄くポツティング慰脂の使用量が少なくて済みがイ
ドの発生およびワイヤつぶれの発生が低減され、小型化
、コストの低減、信頼性および歩留りの向上を実現でき
る半導体装置を提供することができる。As described above, according to the present invention, the external thickness of the resin-sealed part is thin, the amount of potting grease used is small, and the occurrence of cracks and wire crushing is reduced, resulting in miniaturization and cost reduction. Accordingly, it is possible to provide a semiconductor device that can improve reliability and yield.
第１図は従来の半導体装置を示す断面図、第２図はこの
発明の一実施例に係る半導体装置を示す断面図である。
１０・・・半導体チップ、１１・・・基板、１２・・・
接着剤、Ｉ ｓ・・・枠部、１４・・・がンディングワ
イヤ、１５・・・ポツティング樹脂。FIG. 1 is a sectional view showing a conventional semiconductor device, and FIG. 2 is a sectional view showing a semiconductor device according to an embodiment of the present invention. 10... Semiconductor chip, 11... Substrate, 12...
Adhesive, Is... Frame portion, 14... Ending wire, 15... Potting resin.
Claims (1)
、上記半導体チップを囲むように上記基台に取着された
枠部と、枠部の外側の基台表面に形成された導電層ノぐ
ターンと、上記半導体チップの所定部位と上記枠部の外
側の基台面における所定の導電性パターンとを接続する
接続手段と、上記枠部内の半導体チップを封止するポツ
ティング樹脂とを具備することを特徴とする半導体装置
。A semiconductor chip, a base on which the semiconductor chip is attached, a frame attached to the base so as to surround the semiconductor chip, and a conductive layer formed on the surface of the base outside the frame. a connecting means for connecting a predetermined portion of the semiconductor chip to a predetermined conductive pattern on a base surface outside the frame portion; and a potting resin for sealing the semiconductor chip within the frame portion. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58053545A JPS59181033A (en) | 1983-03-31 | 1983-03-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58053545A JPS59181033A (en) | 1983-03-31 | 1983-03-31 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59181033A true JPS59181033A (en) | 1984-10-15 |
Family
ID=12945767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58053545A Pending JPS59181033A (en) | 1983-03-31 | 1983-03-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59181033A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014187264A (en) * | 2013-03-25 | 2014-10-02 | Toshiba Corp | Semiconductor device |
| JP2015185760A (en) * | 2014-03-25 | 2015-10-22 | 東芝ライテック株式会社 | Light emitting module |
-
1983
- 1983-03-31 JP JP58053545A patent/JPS59181033A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014187264A (en) * | 2013-03-25 | 2014-10-02 | Toshiba Corp | Semiconductor device |
| JP2015185760A (en) * | 2014-03-25 | 2015-10-22 | 東芝ライテック株式会社 | Light emitting module |
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