WO2021238781A1 - 位线引出结构及其制备方法 - Google Patents

位线引出结构及其制备方法 Download PDF

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Publication number
WO2021238781A1
WO2021238781A1 PCT/CN2021/095062 CN2021095062W WO2021238781A1 WO 2021238781 A1 WO2021238781 A1 WO 2021238781A1 CN 2021095062 W CN2021095062 W CN 2021095062W WO 2021238781 A1 WO2021238781 A1 WO 2021238781A1
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WIPO (PCT)
Prior art keywords
bit line
contact hole
layer
trench
axis direction
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PCT/CN2021/095062
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English (en)
French (fr)
Inventor
刘志拯
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长鑫存储技术有限公司
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Priority to US17/445,948 priority Critical patent/US11985813B2/en
Publication of WO2021238781A1 publication Critical patent/WO2021238781A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors

Definitions

  • the present invention relates to the field of semiconductors, in particular to a bit line lead-out structure and a preparation method of the bit line lead-out structure.
  • Semiconductor memory uses transistor arrays to control the charge and discharge of storage capacitors to achieve data access. Wherein, the drain region of the transistor is electrically connected to the bit line. After the bit line is formed on the substrate, a bit line extraction structure needs to be formed above the bit line, and the bit line is electrically connected to an external control circuit through the bit line extraction structure.
  • the area of the bit line extraction structure will also decrease correspondingly, so that the bit line extraction structure and the corresponding bit line are separated from each other.
  • the increase in contact resistance causes the current flowing through the bit line to be too small, thereby reducing the sensing margin of the semiconductor memory and the charging and discharging speed of the storage capacitor.
  • bit line extraction structure including: a bit line extending along the Y axis direction; a contact hole covering the bit line along the X axis direction, the X axis direction and the Y axis direction being perpendicular; metal Line, covering the contact hole, the contact hole is located between the bit line and the metal line and is in contact with the bit line and the metal line respectively; wherein the contact hole and the metal line The contact area is larger than the contact area between the contact hole and the bit line.
  • Another aspect of the present application provides a method for preparing a bit line extraction structure, which includes: forming a first dielectric layer on a substrate, the first dielectric layer is provided with a first trench; in the first trench Forming a bit line extending along the Y-axis direction, the top surface of the bit line is lower than the top surface of the first dielectric layer; formed on the bit line and the first dielectric layer outside the first trench A contact hole layer; a metal layer is formed on the contact hole layer; the metal layer and the contact hole layer are etched to form the above-mentioned bit line extraction structure.
  • FIG. 1 is a top view of the distribution of the bit line extraction structure of an embodiment
  • Fig. 2 is a side sectional view corresponding to the section line AA' in Fig. 1 according to an embodiment
  • FIG. 3 is a flowchart of steps of a method for manufacturing a bit line lead structure according to an embodiment
  • 4a is a top view of an embodiment after forming a bit line
  • Figure 4b is a side cross-sectional view of an embodiment corresponding to the section line AA' in Figure 4a;
  • Figure 5a is a top view of an embodiment after a second trench is formed on a second dielectric layer
  • Figure 5b is a side sectional view of an embodiment corresponding to the section line AA' in Figure 5a;
  • Fig. 6a is a top view of an embodiment after a contact hole layer is filled in the first trench and the second trench;
  • Figure 6b is a side sectional view of an embodiment corresponding to the section line AA' in Figure 6a;
  • Figure 7a is a top view of an embodiment after forming a metal layer
  • Figure 7b is a side sectional view of an embodiment corresponding to the section line AA' in Figure 7a;
  • Figure 8a is a top view of an embodiment after forming 2*N masks
  • Figure 8b is a side sectional view of an embodiment corresponding to the section line AA' in Figure 8a;
  • Figure 9a is a top view of an embodiment after 2*N metal wires are formed
  • Fig. 9b is a side sectional view corresponding to the section line AA' in Fig. 9a of an embodiment.
  • first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or portions, these elements, components, regions, layers, doping types and/or Parts should not be restricted by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be expressed as a second element, component, region, layer or portion.
  • Spatial relation terms such as “under”, “below”, “below”, “below”, “above”, “above”, etc., in This can be used to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms also include different orientations of devices in use and operation. For example, if the device in the drawings is turned over, elements or features described as “under” or “under” or “under” other elements will be oriented “on” the other elements or features. Therefore, the exemplary terms “below” and “below” can include both an orientation of above and below. In addition, the device may also include another orientation (for example, a 90-degree rotation or other orientation), and the space descriptors used herein are explained accordingly.
  • FIG. 1 is a top view of the bit line drawing structure in an embodiment of this application
  • FIG. 2 is a side cross-sectional view corresponding to the AA' section line in FIG. 1.
  • the bit line extraction structure includes a bit line 210, a contact hole 410 and a metal line 510.
  • bit line 210 extends along the Y-axis direction.
  • the contact hole 410 is located above the bit line 210 and covers the bit line 210 along the X-axis direction, and the X-axis direction and the Y-axis direction are perpendicular to each other.
  • the contact hole 410 covers the bit line 210 along the X axis direction, which means that the width of the contact hole 410 along the X axis direction is greater than or equal to the width of the bit line 210 along the X axis direction, and a segment of the bit line 210 along the Y axis direction is contacted Hole 410 is covered.
  • the metal line 510 is located on the contact hole 410 and covers the contact hole 410, that is, the contact hole 410 is located between the bit line 210 and the metal line 510, the bottom surface of the contact hole 410 is in contact with the bit line 210, and the top surface of the contact hole 410 is in contact with the metal line 510 touch.
  • the contact area between the contact hole 410 and the metal line 510 is larger than the contact area between the contact hole 410 and the bit line 210
  • the width of the contact surface between the contact hole 410 and the metal line 510 in the X-axis direction is larger than the contact area between the contact hole 410 and the bit line 210 The width of the face along the X axis.
  • the bit line 210 is formed inside the semiconductor device.
  • a contact hole 410 and a metal line 510 above the bit line 210, external electrical signals can be transmitted to the bit line 210 through the metal line 510 and the contact hole 410.
  • the semiconductor device is controlled.
  • the contact hole 410 covers the bit line 210 along the X-axis direction
  • the metal line 510 covers the contact hole 410.
  • the contact area between the contact hole 410 and the metal line 510 is larger than the contact area between the contact hole 410 and the bit line 210.
  • the contact area between the contact hole 410 and the bit line 210 and the metal line 510 is formed inside the semiconductor device.
  • the contact area between the contact hole 410 and the bit line 210 is small, which can reduce the influence of the contact hole 410 on the device integration.
  • the contact area between the contact hole 410 and the metal line 510 The larger contact area can reduce the contact resistance of the entire bit line lead structure, thereby improving the sensing margin of the semiconductor memory and the charging and discharging speed of the storage capacitor.
  • the cross-section of the contact hole 410 is a T-shaped structure, that is, the cross-section of the contact hole 410 in the Z-axis direction shown in FIG. It is perpendicular to the Z axis in pairs.
  • the contact hole 410 has a T-shaped structure, and the width of the top surface of the contact hole 410 along the X-axis direction is greater than the width of the bottom surface along the X-axis direction, so that the contact area between the contact hole 410 and the metal wire 510 is larger than that of the contact hole 410 The contact area with the bit line 210.
  • the bit line 210 is formed on the substrate 100, wherein a first dielectric layer 200 is formed on the substrate 100, and the first dielectric layer 200 is provided with a first trench 201 extending along the Y-axis direction, and the bit line 210 Specifically, it is filled in the first trench 201 and the top surface of the bit line 210 is lower than the top surface of the first dielectric layer 200, that is, the thickness of the bit line 210 is less than the depth of the first trench 201.
  • a part of the contact hole 410 is filled in the first trench 201, and the contact hole 410 located outside the first trench 201 extends along the X-axis direction to the first dielectric layer 200 on both sides of the bit line 210.
  • the contact hole 410 in a trench 201 and the contact hole 410 located outside the first trench 201 jointly form a contact hole 410 having a T-shaped structure. Further, the width of the metal wire 510 above the contact hole 410 in the X-axis direction is equal to the width of the contact hole 410 in the X-axis direction, and the side surfaces of the contact hole 410 and the metal wire 510 extending in the Y-axis direction are aligned with each other.
  • the bit line extraction structure includes 2*N bit lines 210, and the bit lines 210 are arranged side by side along the X-axis direction, and 2*N bit lines 210 are respectively formed with 2* N contact holes 410, 2*N contact holes 410 are respectively formed with 2*N metal lines 510, and each metal line 510 extends along the Y-axis direction; where N is a positive integer, and 2*N bit lines 210, 2 *N contact holes 410 and 2*N metal wires 510 are in one-to-one correspondence.
  • 2*N bit lines 210 arranged in parallel along the X axis are formed on the substrate 100, and a contact hole 410 and a metal line 510 corresponding to each bit line 210 are formed above each bit line 210, that is, each The bit line 210 corresponds to an independent bit line extraction structure, so that each bit line 210 can be independently controlled. Furthermore, the 2*N bit lines 210 are aligned in the X-axis direction, that is, the 2*N bit lines 210 have the same length along the Y-axis direction, and the end points of the bit lines 210 are aligned along the X-axis direction.
  • N metal lines 510 and N contact holes 410 are located on one side of the bit line 210 along the Y-axis direction, and another N metal lines 510 and another N contact holes 410 are located on the bit line.
  • 2*N lead-out structures formed by 2*N contact holes 410 and 2*N metal wires 510 are divided into two groups of lead-out structures.
  • the first group of lead-out structures includes N contact holes 410 and and The N metal lines 510 contacted by the N contact holes 410
  • the second set of lead-out structures includes another N contact holes 410 and another N metal lines 510 that are in contact with the N contact holes 410, wherein the first set of lead-out structures Close to one end of the bit line 210, the second set of lead structures is close to the other end of the bit line 210.
  • the contact hole 410 located on one side of the bit line 210 covers the odd-numbered bit line 210
  • the contact hole 410 located on the other side of the bit line 210 covers the even-numbered bit line 210.
  • the 2*N bit lines 210 are sequentially arranged along the X-axis direction, the first set of lead-out structures are set on the odd-numbered bit line 210, and the second set of lead-out structures are set on the even-numbered bit line 210 Therefore, the distance between adjacent contact holes 410 can be increased, and then the width of the contact holes 410 and the metal line 510 can be increased, the contact area can be increased, and the contact resistance can be reduced.
  • the contact hole 410 and the metal wire 510 have different conductivity, that is, the material of the metal wire 510 of the contact hole 410 is different.
  • the material of the contact hole 410 may be a metal alloy containing one or more of copper, aluminum, nickel, tungsten, silver, gold, etc.
  • the metal wire 510 may be a tungsten wire, aluminum wire, copper wire, silver wire, A kind of gold thread.
  • FIG. 3 shows the method for preparing the bit line lead structure in an embodiment of the application.
  • the preparation method of the bit line lead structure includes:
  • Step S100 forming a first dielectric layer on a substrate, and the first dielectric layer is provided with a first trench extending along the Y-axis direction.
  • Step S200 forming a bit line extending in the Y-axis direction in the first trench, and the top surface of the bit line is lower than the top surface of the first dielectric layer.
  • FIG. 4a is a top view after the bit line 210 is formed, and FIG. 4b corresponds to a side cross-sectional view of the AA' section line in FIG. 4a.
  • a first dielectric layer 200 is formed on the substrate 100, and the first dielectric layer 200 is provided with a first trench 201.
  • the first dielectric layer 200 is first deposited by a deposition process, and then the first dielectric layer 200 is etched to form the first trench 201 described above.
  • a bit line 210 extending in the Y-axis direction is formed in the first trench 201, and the top surface of the bit line 210 is lower than the top surface of the first dielectric layer 200, that is, the thickness of the bit line 210 is less than the depth of the first trench 201 .
  • the first dielectric layer 200 is provided with 2*N first trenches 201 extending in the Y-axis direction respectively, and the trenches are arranged side by side along the X-axis direction.
  • the 2*N first trenches 201 form 2*N bit lines 210 extending along the Y-axis direction, and the bit lines 210 are arranged side by side along the X-axis direction.
  • the aforementioned bit lines 210 are aligned in the X-axis direction, that is, 2*N bit lines 210 have the same length along the Y-axis direction, and the end points of the bit lines 210 are aligned along the X-axis direction.
  • the process of forming the bit line 210 includes:
  • Step S210 deposit a layer of bit line material on the first dielectric layer inside the first trench and outside the first trench.
  • bit line material layer is covered by a deposition process, and the bit line material layer has a certain thickness and covers the first trench 201 and the first dielectric layer 200.
  • Step S220 Perform a planarization process on the top surface of the bit line material layer and remove the bit line material layer on the first dielectric layer, leaving the bit line material layer in the first trench.
  • bit line material layer After depositing the bit line material layer, the bit line material layer has an uneven upper surface. Then, through a chemical mechanical polishing process, the upper surface of the bit line material layer is polished to flatten the upper surface of the bit line material layer. The bit line material layer is etched to expose the first dielectric layer 200, and the bit line material layer in the first trench 201 is retained.
  • Step S230 Re-etch the bit line material layer in the first trench, remove part of the bit line material layer at the top of the first trench, and retain a part of the bit line material layer at the bottom of the first trench to form the bit line.
  • bit line material layer in the first trench 201 is etched through an etching process to reduce the thickness of the bit line material layer so that the thickness of the bit line material layer is less than the depth of the first trench 201.
  • the retained bit line material layer forms the bit line 210.
  • the etch-back depth of the bit line material layer can be flexibly selected according to specific needs.
  • Step S300 forming a contact hole layer on the bit line and the first dielectric layer outside the first trench.
  • the contact hole layer 400 may be directly formed on the bit line 210 and the first dielectric layer 200 outside the first trench 201.
  • step S300 may also include the following sub-steps:
  • Step S311 forming a second dielectric layer on the first dielectric layer and the first trench.
  • the second dielectric layer 300 is deposited on the first dielectric layer 200 and the first trench 201, and the top surface of the second dielectric layer 300 is polished to flatten the top surface of the second dielectric layer 300.
  • Step S312 The second dielectric layer is etched to form a second trench extending along the X-axis direction.
  • the second trench penetrates the second dielectric layer and exposes the bit line and the first trench. Medium layer.
  • Fig. 5a is a top view after the second trench 301 is formed on the second dielectric layer 300
  • Fig. 5b corresponds to the side cross-sectional view of the section line AA' in Fig. 5a.
  • the second dielectric layer 300 is etched to form a second trench 301 extending along the X-axis direction on the second dielectric layer 300, the second trench 301 penetrates the second dielectric layer 300 along the Z-axis direction and exposes the second trench
  • the bit line 210 at the bottom of the groove 301 and the first dielectric layer 200.
  • the etching selection ratios of the second dielectric layer 300 and the first dielectric layer 200 are different. Therefore, during the etching of the second dielectric layer 300 to form the second trench 301, there is basically no The first dielectric layer 200 is etched.
  • the second dielectric layer 300 is provided with two second trenches 301 extending along the X-axis direction, and one of the second trenches 301 is located on the bit line 210 along the Y-axis.
  • the other second trench 301 is located on the other side of the bit line 210 extending along the Y-axis direction, that is, the two second trenches 301 are arranged side by side along the Y-axis direction.
  • the two second trenches 301 are respectively close to the two end points of the bit line 210 along the Y-axis direction.
  • Step S313 forming a contact hole layer in the first trench and the second trench.
  • FIG. 6a is a top view of the first trench 201 and the second trench 301 after the contact hole layer 400 is filled
  • FIG. 6b corresponds to the side cross-sectional view of the AA' section line in FIG. 6a .
  • a thicker layer of contact hole material is deposited by a deposition process, the contact hole material fills the exposed first trench 201 and second trench 301 and is higher than the second dielectric layer 300, and then the contact hole material is processed through a grinding process
  • the planarization process removes the contact hole material above the second dielectric layer 300, leaving only the contact hole material in the first trench 201 and the second trench 301, thereby forming the desired contact hole layer 400.
  • the required contact hole layer 400 can also be formed through the following substeps S321 to S323:
  • Step S321 deposit a contact hole material on the first dielectric layer 200 and the first trench 201.
  • Step S322 etching the contact hole material to remove the contact hole material on both sides to form a contact hole layer 400 extending along the X-axis direction.
  • Step S323 deposit a second dielectric material, and perform a planarization treatment on the second dielectric material, remove the second dielectric material layer above the contact hole layer 400 and expose the contact hole layer 400, leaving the contact hole layer
  • the second dielectric material on both sides of 400 forms a second dielectric layer 300.
  • Step S400 forming a metal layer on the contact hole layer.
  • Fig. 7a is a top view after forming the metal layer 500
  • Fig. 7b corresponds to the side cross-sectional view of the section line AA' in Fig. 7a.
  • a metal layer 500 is formed on the contact hole layer 400.
  • the contact hole layer 400 is formed in the second trench 301, and the metal layer 500 is formed on the contact hole layer 400 and the second dielectric layer 300.
  • Step S500 etching the metal layer and the contact hole layer to form the above-mentioned bit line extraction structure.
  • the metal layer 500 is formed on the contact hole layer 400, the metal layer 500 and the contact hole layer 400 are etched, the metal layer 500 is etched to form a metal line 510, and the contact hole layer 400 is etched to form a contact hole 410, thereby forming the aforementioned
  • the bit line extraction structure where the positional relationship of the bit line 210, the contact hole 410, and the metal line 510 in the bit line extraction structure has been introduced above, and will not be repeated here.
  • etching the metal layer 500 and the contact hole layer 400 specifically includes: forming a mask on the metal layer 500, and under the protection of the mask, etching the exposed metal layer 500 downward, A metal line 510 is formed, and under the protection of the metal line 510, the exposed contact hole layer 400 is continuously etched downward to form a contact hole 410. That is, the above-mentioned etching of the contact hole layer 400 belongs to self-aligned etching. The boundary of the contact hole 410 and the metal line 510 formed after the self-aligned etching is aligned to prevent the alignment of the two from shifting and affecting the device electrical Sexual performance.
  • step S500 includes:
  • Step S510 forming 2*N masks on the metal layer, each of the masks crossing the second trench 301 in the Y-axis direction, and one mask covering a bit line in the X-axis direction.
  • Fig. 8a is a top view after 2*N masks 600 are formed, and Fig. 8b corresponds to the side cross-sectional view of the section line AA' in Fig. 8a.
  • 2*N masks 600 are formed on the metal layer 500, and each mask 600 crosses the second trench 301 along the Y-axis direction, and one mask 600 covers one bit line 210 along the X-axis direction, that is, 2*N masks.
  • the film 600 corresponds to 2*N bit lines 210 one-to-one.
  • N masks 600 are located on one side of the metal layer 500 along the Y-axis direction and respectively cross the second trenches 301 on the same side along the Y-axis direction, and respectively cover the odd-numbered bit lines 210
  • N masks 600 are located on the other side of the metal layer 500 along the Y-axis direction, and respectively cross another second trench 301 located on the same side along the Y-axis direction, and respectively cover the even-numbered bit lines 210.
  • the masks 600 located on the same side are arranged side by side along the X-axis direction.
  • Step S520 sequentially etch the metal layer and the contact hole layer, reserve the metal layer under the mask to form 2*N metal lines, and reserve the contact hole layer under the metal lines to form 2*N metal lines.
  • 2*N contact holes are formed, where N is a positive integer, 2*N bit lines, 2*N contact holes, and 2*N metal lines are in one-to-one correspondence.
  • Fig. 9a is a top view after 2*N metal wires 510 are formed, and Fig. 9b corresponds to a side sectional view of the AA' section line in Fig. 9a.
  • the exposed metal layer 500 is etched to form 2*N independent metal lines 510.
  • the exposed contact hole layer 400 is continuously etched. Etching to form 2*N independent contact holes 410.
  • 2*N bit lines 210, 2*N contact holes 410, and 2*N metal lines 510 are in a one-to-one correspondence.
  • a bit line 210 is drawn out through the contact hole 410 and the metal line 510 above it.
  • a contact hole layer 400 extending along the X-axis direction is formed first, the contact hole layer 400 is integrally formed and electrically connected to a plurality of bit lines 210, and then formed on the contact hole layer 400 and the second dielectric layer 300 Metal layer 500, and a mask is formed on the metal layer 500, the mask straddles the second trench 301 along the Y-axis direction, and then the exposed metal layer 500 and the contact hole layer 400 are sequentially carved under the shielding effect of the mask By etching, the contact hole layer 400 extending along the X-axis direction is cut into a plurality of independent parts, and the unetched metal layer 500 and the contact hole layer 400 form the lead structure of the bit line 210.
  • the alignment steps of the front and back etching in the conventional technique are omitted, and in this application, the boundary between the metal layer 500 and the contact hole layer 400 remaining after the etching is flush. There is no positional deviation between the metal layer 500 and the contact hole layer 400, which greatly improves the electrical performance of the semiconductor device.
  • the bit line extraction structure described above is formed, wherein the contact hole 410 covers the bit line 210 along the X-axis direction, and the metal line 510 covers the contact hole 410.
  • the contact hole 410 and the metal line 510 The contact area is larger than the contact area between the contact hole 410 and the bit line 210.
  • the contact area between the contact hole 410 and the bit line 210 and the metal line 510 is smaller, which can reduce the influence of the contact hole 410 on the integration of the device, and
  • the contact area between the contact hole 410 and the metal line 510 is relatively large, which can reduce the contact resistance of the entire bit line extraction structure, thereby improving the sensing margin of the semiconductor memory and the charging and discharging speed of the storage capacitor.

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Abstract

本申请涉及一种位线引出结构及其制备方法，在衬底上形成沿Y轴方向延伸的位线；形成沿X轴方向覆盖位线的接触孔，X轴方向和Y轴方向垂直；形成覆盖接触孔的金属线，接触孔位于位线和金属线之间并分别与位线和金属线接触；其中，接触孔与金属线的接触面积大于接触孔与位线的接触面积。

Description

位线引出结构及其制备方法
本申请要求于2020年5月28日提交的申请号为202010465006.1、名称为“位线引出结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体领域，尤其涉及一种位线引出结构和位线引出结构的制备方法。
背景技术
半导体存储器是利用晶体管阵列控制存储电容的充放电而实现数据的存取。其中，晶体管的漏区与位线电连接，在衬底上形成位线后，需要在位线上方形成位线引出结构，通过位线引出结构实现位线与外部控制电路的电连接。
然而，随着半导体器件集成度的不断提高，位线尺寸以及位线之间的间距的不断缩小，位线引出结构的面积也会相应减小，使得位线引出结构与相应位线之间的接触电阻变大，导致流经位线的电流过小，从而降低了半导体存储器的感应裕度和存储电容的充放电速度。
发明内容
本申请一方面提供一种位线引出结构，包括：位线,沿Y轴方向延伸；接触孔，沿X轴方向覆盖所述位线，所述X轴方向和所述Y轴方向垂直；金属线，覆盖所述接触孔，所述接触孔位于所述位线和所述金属线之间并分别与所述位线和所述金属线接触；其中，所述接触孔与所述金属线的接触面积大于所述接触孔与所述位线的接触面积。
本申请的另一方面提供一种位线引出结构的制备方法，包括：在衬底上形成第一介质层，所述第一介质层开设有第一沟槽；在所述第一沟槽内形成沿Y轴方向延伸的位线，所述位线的顶面低于所述第一介质层的顶面；在所述位线上和所述第一沟槽外的第一介质层上形成接触孔层；在所述接触孔层上形成金属层；刻蚀所述金属层和所述接触孔层，形成上述的位线引出结构。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例的技术方案，可参考一幅或多幅附图，但用于描述附图的附加细节或示例不应当被认为是对本申请的发明创造、目前所描述的实施例或优选方式中任何一者的范围的限制。
图1为一实施例的位线引出结构的分布俯视图；
图2为一实施例的对应图1中AA’剖面线的侧剖图；
图3为一实施例的位线引出结构的制备方法的步骤流程图；
图4a为一实施例的形成位线后的俯视图；
图4b为一实施例的对应图4a中AA’剖面线的侧剖图；
图5a为一实施例的在第二介质层上开设第二沟槽后的俯视图；
图5b为一实施例的对应图5a中AA’剖面线的侧剖图；
图6a为一实施例的在第一沟槽和第二沟槽内填充接触孔层后的俯视图；
图6b为一实施例的对应图6a中AA’剖面线的侧剖图；
图7a为一实施例的形成金属层后的俯视图；
图7b为一实施例的对应图7a中AA’剖面线的侧剖图；
图8a为一实施例的形成2*N个掩膜后的俯视图；
图8b为一实施例的对应图8a中AA’剖面线的侧剖图；
图9a为一实施例的形成2*N条金属线后的俯视图；
图9b为一实施例的对应图9a中AA’剖面线的侧剖图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。
应当明白，当元件或层被称为“在...上”时，其可以直接地在其它元件或层上或者可以存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本发明教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示 例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
图1为本申请中一实施例中位线引出结构的俯视图，图2为对应图1中AA’剖面线的侧剖图。
结合图1和图2所示，位线引出结构包括位线210、接触孔410和金属线510。
其中，位线210沿Y轴方向延伸。
接触孔410位于位线210上方并沿X轴方向覆盖位线210，X轴方向与Y轴方向相互垂直。接触孔410沿X轴方向覆盖位线210，指的是接触孔410沿X轴方向的宽度大于或等于位线210沿X轴方向的宽度，在沿Y轴方向上的一段位线210被接触孔410覆盖。
金属线510位于接触孔410上并覆盖接触孔410，即接触孔410位于位线210与金属线510之间，接触孔410的底面与位线210接触，接触孔410的顶面与金属线510接触。其中，接触孔410与金属线510的接触面积大于接触孔410与位线210的接触面积，接触孔410与金属线510的接触面沿X轴方向的宽度大于接触孔410与位线210的接触面沿X轴方向的宽度。
上述位线引出结构，位线210形成于半导体器件的内部，通过在位线210上方 形成接触孔410和金属线510，可以通过金属线510和接触孔410将外部电信号传输至位线210，并通过位线210对半导体器件进行控制。在本申请中，接触孔410沿X轴方向覆盖位线210，而金属线510覆盖接触孔410，接触孔410与金属线510的接触面积大于接触孔410与位线210的接触面积，通过调整接触孔410与位线210和金属线510的接触面积，接触孔410和位线210的接触面积较小，可以减小接触孔410对器件集成度的影响，而接触孔410与金属线510的接触面积较大，可以减小整个位线引出结构的接触电阻，从而提高半导体存储器的感应裕度和存储电容的充放电速度。
在一实施例中，如图2所示，接触孔410的横截面为T型结构，即接触孔410在图2所示的Z轴方向的截面为T型结构，其中，X轴、Y轴和Z轴两两垂直。在本实施例中，接触孔410呈T型结构，接触孔410顶面沿X轴方向的宽度大于底面沿X轴方向的宽度，从而实现接触孔410与金属线510的接触面积大于接触孔410与位线210的接触面积。
更具体的，位线210形成于衬底100上，其中，衬底100上形成有第一介质层200，第一介质层200开设有沿Y轴方向延伸的第一沟槽201，位线210具体填充于第一沟槽201内且位线210的顶面低于第一介质层200的顶面，即位线210的厚度小于第一沟槽201的深度。接触孔410的一部分填充于第一沟槽201内，且位于第一沟槽201外的接触孔410沿X轴方向延伸至位线210两侧的第一介质层200上，此时，位于第一沟槽201内的接触孔410和位于第一沟槽201外的接触孔410共同形成具有T型结构的接触孔410。进一步的，接触孔410上方的金属线510沿X轴方向的宽度等于接触孔410沿X轴方向的宽度，且接触孔410和金属线510沿Y轴方向延伸的侧面相互对齐。
在一实施例中，结合图1和图2所示，位线引出结构包括2*N条位线210，各 位线210沿X轴方向并列分布，2*N条位线210上分别形成2*N个接触孔410，2*N个接触孔410上分别形成2*N条金属线510，各金属线510沿Y轴方向延伸；其中，N为正整数，2*N条位线210、2*N个接触孔410、2*N条金属线510均一一对应。在本实施例中，衬底100上形成有2*N沿X轴方向并列分布的位线210，每条位线210上方均形成有与之对应的接触孔410和金属线510，即每条位线210对应一个独立的位线引出结构，从而可以分别对各条位线210独立控制。更进一步的，2*N条位线210在X轴方向上对齐排列，即2*N条位线210沿Y轴方向的长度相同，各位线210的端点沿X轴方向对齐。
更具体的，如图1所示，N条金属线510和N个接触孔410位于位线210的沿Y轴方向的一侧，另外N条金属线510和另外N个接触孔410位于位线210的沿Y轴方向的另一侧；其中，位于同一侧的金属线510沿X轴方向并列分布。在本实施例中，2*N个接触孔410和2*N条金属线510形成的2*N个引出结构共分为两组引出结构，第一组引出结构包括N个接触孔410和与该N个接触孔410接触的N条金属线510，第二组引出结构包括另外N个接触孔410和与该N个接触孔410接触的另外N条金属线510，其中，第一组引出结构靠近位线210一端端点，第二组引出结构靠近位线210另一端端点，通过将金属线510和接触孔410分散设置于位线210两侧，可以适当提高金属线510或接触孔410的宽度，从而减小位线引出结构的接触电阻。
更进一步的，位于位线210的其中一侧的接触孔410覆盖第奇数条位线210，位于位线210的另一侧的接触孔410覆盖第偶数条位线210。在本实施例中，2*N条位线210沿X轴方向依次排布，第一组引出结构设于第奇数条位线210上，第二组引出结构设于第偶数条位线210上，由此可以增大相邻接触孔410之间的间距，继而可以增大接触孔410和金属线510的宽度，提高接触面积，减小接触电阻。
在一实施例中，接触孔410和金属线510具有不同的导电率，即接触孔410的金属线510的材料不同。具体的，接触孔410的材料可以为包含铜、铝、镍、钨、银、金等中一种或多种的金属合金，金属线510可以为钨线、铝线、铜线、银线、金线等的一种。
如图3所示为本申请一实施例中的位线引出结构的制备方法。
在一实施例中，位线引出结构的制备方法包括：
步骤S100：在衬底上形成第一介质层，所述第一介质层开设有沿Y轴方向延伸的第一沟槽。
步骤S200：在所述第一沟槽内形成沿Y轴方向延伸的位线，所述位线的顶面低于所述第一介质层的顶面。
结合图4a和图4b，其中，图4a为形成位线210后的俯视图，图4b对应图4a中AA’剖面线的侧剖图。
其中，在衬底100上形成第一介质层200，第一介质层200开设有第一沟槽201。在一具体的实施例中，先通过沉积工艺沉积第一介质层200，然后刻蚀第一介质层200，形成上述第一沟槽201。
其中，在第一沟槽201内形成沿Y轴方向延伸的位线210，位线210的顶面低于第一介质层200的顶面，即位线210的厚度小于第一沟槽201的深度。
在一具体的实施例中，如图4a所示，第一介质层200上开设有2*N个分别沿Y轴方向延伸的第一沟槽201，各沟槽沿X轴方向并列分布，在2*N个第一沟槽201形成2*N条沿Y轴方向延伸的位线210，各位线210沿X轴方向并列分布。进一步的，上述各位线210在X轴方向上对齐排列，即2*N条位线210沿Y轴方向的长度相同，各位线210的端点沿X轴方向对齐。
在一具体的实施例中，形成位线210的过程包括：
步骤S210：在所述第一沟槽内和所述第一沟槽外的第一介质层上沉积位线材料层。
具体的，通过沉积工艺覆盖一层位线材料层，位线材料层具有一定的厚度并覆盖第一沟槽201以及第一介质层200。
步骤S220：对所述位线材料层的顶面进行平坦化处理并去除第一介质层上的位线材料层，保留第一沟槽内的位线材料层。
在沉积位线材料层后，位线材料层具有凹凸不平的上表面，接着，通过化学机械研磨工艺，对位线材料层的上表面进行研磨，使位线材料层的上表面平坦化，刻蚀位线材料层以暴露出第一介质层200，保留第一沟槽201内的位线材料层。
步骤S230：回刻所述第一沟槽内的位线材料层，去除第一沟槽顶部的部分位线材料层，保留第一沟槽底部的部分位线材料层，形成所述位线。
具体的，具体通过刻蚀工艺刻蚀第一沟槽201内的位线材料层，削减位线材料层的厚度，使位线材料层的厚度小于第一沟槽201的深度，停止刻蚀后，所保留的位线材料层形成位线210。其中，对位线材料层的回刻深度可以根据具体需要灵活选择。
在形成上述位线210之后，继续执行：
步骤S300：在所述位线上和所述第一沟槽外的第一介质层上形成接触孔层。
在一实施例中，可以在位线210上和第一沟槽201外的第一介质层200上直接形成接触孔层400。
在另一实施例中，步骤S300也可以包括以下子步骤：
步骤S311：在所述第一介质层和所述第一沟槽上形成第二介质层。
通过沉积工艺，在第一介质层200和第一沟槽201上沉积第二介质层300，并对第二介质层300的顶面进行研磨，使第二介质层300的顶面平坦化。
步骤S312：刻蚀所述第二介质层，形成沿X轴方向延伸的第二沟槽，所述第二沟槽穿透所述第二介质层并暴露出所述位线和所述第一介质层。
如图5a和图5b所示，其中，图5a为在第二介质层300上开设第二沟槽301后的俯视图，图5b对应图5a中AA’剖面线的侧剖图。刻蚀第二介质层300，在第二介质层300上形成沿X轴方向延伸的第二沟槽301，第二沟槽301沿Z轴方向穿透第二介质层300并暴露出第二沟槽301底部的位线210和第一介质层200。需要说明的是，在该实施例中，第二介质层300和第一介质层200的刻蚀选择比不同，因此，在刻蚀第二介质层300形成第二沟槽301期间，基本不会刻蚀第一介质层200。
在一实施例中，如图5a所示，在第二介质层300上开设有两个分别沿X轴方向延伸的第二沟槽301，其中一个第二沟槽301位于位线210沿Y轴方向延伸的一侧，其中另一个第二沟槽301位于位线210沿Y轴方向延伸的另一侧，即两个第二沟槽301沿Y轴方向并列分布。更进一步的，两个第二沟槽301分别靠近位线210沿Y轴方向的两侧端点。
步骤S313：在所述第一沟槽和第二沟槽内形成接触孔层。
如图6a和图6b所示，其中，图6a为在第一沟槽201和第二沟槽301内填充接触孔层400后的俯视图，图6b对应图6a中AA’剖面线的侧剖图。通过沉积工艺沉积一层较厚的接触孔材料，接触孔材料填充所暴露的第一沟槽201和第二沟槽301内并高于第二介质层300，再通过研磨工艺对接触孔材料进行平坦化处理，去除第二介质层300上方的接触孔材料，仅保留第一沟槽201和第二沟槽301内的接触孔材料，由此形成所需的接触孔层400。
上述实施例通过步骤S311～步骤S313形成接触孔层400，在其他的实施例中，还可以通过以下子步骤S321～步骤S323形成所需的接触孔层400：
步骤S321：在所述第一介质层200和所述第一沟槽201上沉积接触孔材料。
步骤S322：刻蚀所述接触孔材料，去除两侧的接触孔材料，形成沿X轴方向延伸的接触孔层400。
步骤S323：沉积第二介质材料，并对第二介质材料进行平坦化处理，去除所述接触孔层400上方的第二介质材料层并暴露出所述接触孔层400，保留所述接触孔层400两侧的第二介质材料，形成第二介质层300。
通过上述步骤，形成接触孔层400后，继续执行：
步骤S400：在所述接触孔层上形成金属层。
如图7a和7b所示，其中，图7a为形成金属层500后的俯视图，图7b对应图7a中AA’剖面线的侧剖图。通过沉积工艺，在接触孔层400上形成金属层500。在一实施例中，接触孔层400形成于第二沟槽301内，金属层500形成于接触孔层400和第二介质层300上。
步骤S500：刻蚀所述金属层和所述接触孔层，形成上述位线引出结构。
在接触孔层400上形成金属层500之后，对金属层500和接触孔层400进行刻蚀，刻蚀金属层500形成金属线510，刻蚀接触孔层400形成接触孔410，由此形成上述位线引出结构，其中，位线引出结构中的位线210、接触孔410和金属线510的位置关系已在上文介绍，在此不再赘述。
在一实施例中，刻蚀所述金属层500和所述接触孔层400，具体包括：在金属层500上形成掩膜，在掩膜的保护下，向下刻蚀暴露的金属层500，形成金属线510，并在金属线510的保护下，继续向下刻蚀暴露的接触孔层400，形成接触孔410。即上述对接触孔层400的刻蚀属于自对准刻蚀，经自对准刻蚀后所形成的接触孔410和金属线510的边界对齐，避免两者对位出现偏移而影响器件电性性能。
在一具体的实施例中，衬底100上形成有2*N条位线210，接触孔层400形成 于第二沟槽301内并沿X轴方向延伸，此时，步骤S500包括：
步骤S510：在所述金属层上形成2*N个掩膜，各所述掩膜沿Y轴方向跨过所述第二沟槽301且一个掩膜沿X轴方向覆盖一条位线。
如图8a和图8b所示，其中，图8a为形成2*N个掩膜600后的俯视图，图8b对应图8a中AA’剖面线的侧剖图。在金属层500上形成2*N个掩膜600，各掩膜600沿Y轴方向跨过第二沟槽301且一个掩膜600沿X轴方向覆盖一条位线210，即2*N个掩膜600与2*N条位线210一一对应。进一步的，第二介质层300内开设有两个第二沟槽301，在两个第二沟槽301内分别对应形成两个沿X轴方向延伸的接触孔层400时，上述2*N个掩膜600中，其中N个掩膜600位于金属层500沿Y轴方向的一侧并分别沿Y轴方向跨过位于同侧的第二沟槽301，且分别覆盖第奇数条位线210，另外N个掩膜600位于金属层500沿Y轴方向的另一侧并分别沿Y轴方向跨过位于同侧的另一第二沟槽301，且分别覆盖第偶数条位线210。进一步的，位于同一侧的掩膜600沿X轴方向并列分布。
步骤S520：依次刻蚀所述金属层和所述接触孔层，保留所述掩膜下方的所述金属层以形成2*N个金属线、保留所述金属线下方的所述接触孔层以形成2*N个接触孔，其中，N为正整数，2*N条所述位线、2*N个所述接触孔、2*N条所述金属线均一一对应。
如图9a和图9b所示，其中，图9a为形成2*N条金属线510后的俯视图，图9b对应图9a中AA’剖面线的侧剖图。在2*N个掩膜的保护下，对暴露的金属层500进行刻蚀，形成2*N条独立的金属线510，在金属线510的保护下，继续对暴露的接触孔层400进行刻蚀，形成2*N个独立接触孔410，此时，2*N条所述位线210、2*N个所述接触孔410、2*N条所述金属线510均一一对应，每一条位线210通过其上方的接触孔410和金属线510引出。
在本实施例中，先形成沿X轴方向延伸的接触孔层400，接触孔层400一体成型且与多个位线210电连接，接着在接触孔层400上和第二介质层300上形成金属层500，并在金属层500上形成掩膜，掩膜沿Y轴方向跨过第二沟槽301，然后在掩膜的遮挡作用下依次对暴露的金属层500和接触孔层400进行刻蚀，将沿X轴方向延伸的接触孔层400切割成多个独立的部分，未被刻蚀的金属层500和接触孔层400便形成位线210的引出结构。由于上述对于接触孔层400采用自对准刻蚀，省略了传统技术中前后刻蚀的对准步骤，且本申请中，刻蚀后所保留的金属层500和接触孔层400的边界齐平，金属层500和接触孔层400不存在位置偏移，大大改善了半导体器件的电性性能。
通过上述位线引出结构制备方法，形成上文介绍的位线引出结构，其中，接触孔410沿X轴方向覆盖位线210，而金属线510覆盖接触孔410，接触孔410与金属线510的接触面积大于接触孔410与位线210的接触面积。上述位线引出结构，通过调整接触孔410与位线210和金属线510的接触面积，接触孔410和位线210的接触面积较小，可以减小接触孔410对器件集成度的影响，而接触孔410与金属线510的接触面积较大，可以减小整个位线引出结构的接触电阻，从而提高半导体存储器的感应裕度和存储电容的充放电速度。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种位线引出结构，包括：
    位线,沿Y轴方向延伸；
    接触孔，沿X轴方向覆盖所述位线，所述X轴方向和所述Y轴方向垂直；
    金属线，覆盖所述接触孔，所述接触孔位于所述位线和所述金属线之间并分别与所述位线和所述金属线接触；
    其中，所述接触孔与所述金属线的接触面积大于所述接触孔与所述位线的接触面积。
  2. 根据权利要求1所述的位线引出结构，其中，所述接触孔的横截面为T型结构。
  3. 根据权利要求2所述的位线引出结构，其中，所述位线引出结构包括2*N条所述位线、2*N个所述接触孔和2*N条所述金属线，各所述位线沿所述X轴方向并列分布，各所述金属线沿所述Y轴方向延伸；其中，N为正整数，2*N条所述位线、2*N个所述接触孔、2*N条所述金属线均一一对应。
  4. 根据权利要求3所述的位线引出结构，其中，各所述位线在X轴方向上对齐排列。
  5. 根据权利要求3所述的位线引出结构，其中，N条所述金属线和N个所述接触孔位于所述位线的沿所述Y轴方向的一侧，另外N条所述金属线和另外N个接触孔位于所述位线的沿所述Y轴方向的另一侧；其中，位于同一侧的金属线沿所述X轴方向并列分布。
  6. 根据权利要求5所述的位线引出结构，其中，位于所述位线的其中一侧的所述接触孔覆盖第奇数条所述位线，位于所述位线的另一侧的所述接触孔覆盖第偶数条所述位线。
  7. 根据权利要求1所述的位线引出结构，其中，所述接触孔与所述金属线具有不同的导电率。
  8. 一种位线引出结构的制备方法，包括：
    在衬底上形成第一介质层，所述第一介质层开设有沿Y轴方向延伸的第一沟槽；
    在所述第一沟槽内形成沿Y轴方向延伸的位线，所述位线的顶面低于所述第一介质层的顶面；
    在所述位线上和所述第一沟槽外的第一介质层上形成接触孔层；
    在所述接触孔层上形成金属层；
    刻蚀所述金属层和所述接触孔层，形成权利要求1至7任一项所述的位线引出结构。
  9. 根据权利要求8所述的制备方法，其中，所述在所述第一沟槽内形成位线，所述位线的顶面低于所述第一介质层的顶面，包括：
    在所述第一沟槽内和所述第一沟槽外的第一介质层上沉积位线材料层；
    对所述位线材料层的顶面进行平坦化处理并去除第一介质层上的位线材料层，保留第一沟槽内的位线材料层；
    回刻所述第一沟槽内的位线材料层，去除第一沟槽顶部的部分位线材料层，保留第一沟槽底部的部分位线材料层，形成所述位线。
  10. 根据权利要求8所述的制备方法，其中，所述第一介质层上开设有2*N个所述第一沟槽，在2*N个所述第一沟槽形成2*N条所述位线，各所述位线沿X轴方向并列分布；
    所述在所述位线上和所述第一沟槽外的第一介质层上形成接触孔层，包括：
    在所述第一介质层和所述第一沟槽上形成第二介质层；
    刻蚀所述第二介质层，形成沿X轴方向延伸的第二沟槽，所述第二沟槽穿透所述第二介质层并暴露出所述位线和所述第一介质层；
    在所述第一沟槽和第二沟槽内形成接触孔层；
    所述刻蚀所述金属层和所述接触孔层，包括：
    在所述金属层上形成2*N个掩膜，各所述掩膜沿Y轴方向跨过所述第二沟槽且一个掩膜沿X轴方向覆盖一条位线；
    依次刻蚀所述金属层和所述接触孔层，保留于所述掩膜下方的所述金属层形成2*N个金属线、保留于所述金属线下方的所述接触孔层形成2*N个接触孔，其中，N为正整数，2*N条所述位线、2*N个所述接触孔、2*N条所述金属线均一一对应。
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