WO2021237847A1 - Goa电路及显示面板 - Google Patents

Goa电路及显示面板 Download PDF

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Publication number
WO2021237847A1
WO2021237847A1 PCT/CN2020/097877 CN2020097877W WO2021237847A1 WO 2021237847 A1 WO2021237847 A1 WO 2021237847A1 CN 2020097877 W CN2020097877 W CN 2020097877W WO 2021237847 A1 WO2021237847 A1 WO 2021237847A1
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WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
signal
node
level
Prior art date
Application number
PCT/CN2020/097877
Other languages
English (en)
French (fr)
Inventor
陶健
Original Assignee
武汉华星光电技术有限公司
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Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/970,649 priority Critical patent/US11682330B2/en
Publication of WO2021237847A1 publication Critical patent/WO2021237847A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes

Definitions

  • This application relates to the field of display technology, in particular to a GOA circuit and a display panel.
  • GOA Gate Driver On Array
  • the GOA circuit of the high-resolution display panel has poor stage transfer stability.
  • the purpose of the embodiments of the present application is to provide a GOA circuit and a display panel, which can solve the technical problem of poor grade transfer stability of the GOA circuit of the existing high-resolution display panel.
  • an embodiment of the present application provides a GOA circuit, including: multi-level cascaded GOA units, each level of GOA unit includes a pull-up control module, a pull-up module, a pull-down module, a pull-down maintenance module, and a reset module ;
  • the pull-up control module is connected to the upper-level scan signal, the first scan control signal, and the low-level signal, and is electrically connected to the first node; the pull-up control module is configured to respond to the upper-level scan signal , The low-level signal and the first scan control signal, output the first scan control signal to the first node;
  • the pull-up module is connected to the high-level signal and the clock signal of the current level, and is electrically connected to the scan signal output terminal of the current level and the first node; the pull-up module is used for The current-level clock signal and the potential of the first node output a current-level scan signal at the scan signal output terminal;
  • the pull-down module is connected to the next-level clock signal, the previous-level clock signal, the second scan control signal, the next-level scan signal, the low-level signal, and the high-level signal, and is electrically connected to the first Two nodes and the first node; the pull-down module is used to perform according to the next-stage clock signal, the upper-stage clock signal, the second scan control signal, the next-stage scan signal, the A low-level signal and the high-level signal, pull down the potential of the first node and pull up the potential of the second node;
  • the pull-down maintenance module accesses a pull-down maintenance control signal and the low-level signal, and is electrically connected to the first node, the second node, and the scan signal output terminal of the current stage; the pull-down maintenance module is used for Maintaining the potential of the first node and the potential of the scan signal output terminal of the current stage according to the pull-down maintenance control signal, the low-level signal, and the potential of the second node;
  • the reset module is connected to the first function control signal, the second function control signal, and the high-level signal, and is electrically connected to the scan signal output terminal of the current stage; the reset module is used for The first function control signal, the second function control signal, and the high-level signal reset the potential of the scanning signal output terminal;
  • the reset module includes a twelfth transistor and a thirteenth transistor
  • the gate of the twelfth transistor is electrically connected to the fourth node, the source of the twelfth transistor is electrically connected to the first function control signal, and the drain of the twelfth transistor is electrically connected to At the scanning signal output terminal of the current level;
  • the gate of the thirteenth transistor is electrically connected to the high-level signal, the source of the thirteenth transistor is electrically connected based on the second function control signal, and the drain of the thirteenth transistor Electrically connected to the fourth node;
  • the pull-down maintenance control signal is the same signal as the first function control signal or the second function control signal.
  • the pull-up control module includes a third transistor and a first capacitor
  • the gate of the third transistor is electrically connected to the previous scan signal, the source of the third transistor is electrically connected to the first scan control signal, and the drain of the third transistor is electrically connected Connected to the first node;
  • One end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the low-level signal.
  • the pull-up module includes a sixth transistor and an eighth transistor
  • the gate of the sixth transistor is electrically connected to the high-level signal
  • the source of the sixth transistor is electrically connected to the first node
  • the drain of the sixth transistor is electrically connected to the first node.
  • the gate of the eighth transistor is electrically connected to the third node, the source of the eighth transistor is electrically connected to the clock signal of the current stage, and the drain of the eighth transistor is electrically connected to the third node. Describe the scan signal output terminal of this level.
  • the potential of the third node is greater than the potential of the first node.
  • the pull-down module includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, and a ninth transistor;
  • the gate of the first transistor is electrically connected to the first scan control signal, and the source of the first transistor is electrically connected to the next-stage clock signal;
  • the gate of the second transistor is electrically connected to the second scan control signal, and the source of the second transistor is electrically connected to the upper-level clock signal;
  • the drain of the first transistor, the drain of the second transistor, and the gate of the fifth transistor are electrically connected, and the source of the fifth transistor is electrically connected to the high-level signal, so The drain of the fifth transistor is electrically connected to the second node;
  • the gate of the fourth transistor is electrically connected to the next-level scan signal, the source of the fourth transistor is electrically connected to the second scan control signal, and the drain of the fourth transistor is electrically connected Connected to the first node;
  • the gate of the ninth transistor is electrically connected to the first node, the source of the ninth transistor is electrically connected to the low-level signal, and the drain of the ninth transistor is electrically connected to the The second node.
  • the pull-down maintenance module includes a seventh transistor, a tenth transistor, an eleventh transistor, and a second capacitor;
  • the gate of the seventh transistor is electrically connected to the second node, the source of the seventh transistor is electrically connected to the low-level signal, and the drain of the seventh transistor is electrically connected to the The first node;
  • the gate of the tenth transistor is electrically connected to the first function control signal or the second function control signal, the source of the tenth transistor is electrically connected to the low-level signal, and the tenth transistor The drain of is electrically connected to the second node;
  • the gate of the eleventh transistor is electrically connected to the second node, the source of the tenth transistor is electrically connected to the low-level signal, and the drain wire of the tenth transistor is connected to the Describe the scan signal output terminal of this level.
  • the potential of the fourth node is greater than the potential of the second function control signal.
  • an embodiment of the present application provides a GOA circuit, including: multi-level cascaded GOA units, each level of GOA unit includes a pull-up control module, a pull-up module, a pull-down module, a pull-down maintenance module, and a reset module ;
  • the pull-up control module is connected to the upper-level scan signal, the first scan control signal, and the low-level signal, and is electrically connected to the first node; the pull-up control module is configured to respond to the upper-level scan signal , The low-level signal and the first scan control signal, output the first scan control signal to the first node;
  • the pull-up module is connected to the high-level signal and the clock signal of the current level, and is electrically connected to the scan signal output terminal of the current level and the first node; the pull-up module is used for The current-level clock signal and the potential of the first node output a current-level scan signal at the scan signal output terminal;
  • the pull-down module is connected to the next-level clock signal, the previous-level clock signal, the second scan control signal, the next-level scan signal, the low-level signal, and the high-level signal, and is electrically connected to the first Two nodes and the first node; the pull-down module is used to perform according to the next-stage clock signal, the upper-stage clock signal, the second scan control signal, the next-stage scan signal, the A low-level signal and the high-level signal, pull down the potential of the first node and pull up the potential of the second node;
  • the pull-down maintenance module accesses a pull-down maintenance control signal and the low-level signal, and is electrically connected to the first node, the second node, and the scan signal output terminal of the current stage; the pull-down maintenance module is used for Maintaining the potential of the first node and the potential of the scan signal output terminal of the current stage according to the pull-down maintenance control signal, the low-level signal, and the potential of the second node;
  • the reset module is connected to the first function control signal, the second function control signal, and the high-level signal, and is electrically connected to the scan signal output terminal of the current stage; the reset module is used for The first function control signal, the second function control signal, and the high-level signal reset the potential of the scanning signal output terminal.
  • the pull-up control module includes a third transistor and a first capacitor
  • the gate of the third transistor is electrically connected to the previous scan signal, the source of the third transistor is electrically connected to the first scan control signal, and the drain of the third transistor is electrically connected Connected to the first node;
  • One end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the low-level signal.
  • the pull-up module includes a sixth transistor and an eighth transistor
  • the gate of the sixth transistor is electrically connected to the high-level signal
  • the source of the sixth transistor is electrically connected to the first node
  • the drain of the sixth transistor is electrically connected to the first node.
  • the gate of the eighth transistor is electrically connected to the third node, the source of the eighth transistor is electrically connected to the clock signal of the current stage, and the drain of the eighth transistor is electrically connected to the third node. Describe the scan signal output terminal of this level.
  • the potential of the third node is greater than the potential of the first node.
  • the pull-down module includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, and a ninth transistor;
  • the gate of the first transistor is electrically connected to the first scan control signal, and the source of the first transistor is electrically connected to the next-stage clock signal;
  • the gate of the second transistor is electrically connected to the second scan control signal, and the source of the second transistor is electrically connected to the upper-level clock signal;
  • the drain of the first transistor, the drain of the second transistor, and the gate of the fifth transistor are electrically connected, and the source of the fifth transistor is electrically connected to the high-level signal, so The drain of the fifth transistor is electrically connected to the second node;
  • the gate of the fourth transistor is electrically connected to the next-level scan signal, the source of the fourth transistor is electrically connected to the second scan control signal, and the drain of the fourth transistor is electrically connected Connected to the first node;
  • the gate of the ninth transistor is electrically connected to the first node, the source of the ninth transistor is electrically connected to the low-level signal, and the drain of the ninth transistor is electrically connected to the The second node.
  • the pull-down maintenance module includes a seventh transistor, a tenth transistor, an eleventh transistor, and a second capacitor;
  • the gate of the seventh transistor is electrically connected to the second node, the source of the seventh transistor is electrically connected to the low-level signal, and the drain of the seventh transistor is electrically connected to the The first node;
  • the gate of the tenth transistor is electrically connected to the first function control signal or the second function control signal, the source of the tenth transistor is electrically connected to the low-level signal, and the tenth transistor The drain of is electrically connected to the second node;
  • the gate of the eleventh transistor is electrically connected to the second node, the source of the tenth transistor is electrically connected to the low-level signal, and the drain wire of the tenth transistor is connected to the Describe the scan signal output terminal of this level.
  • the reset module includes a twelfth transistor and a thirteenth transistor
  • the gate of the twelfth transistor is electrically connected to the fourth node, the source of the twelfth transistor is electrically connected to the first function control signal, and the drain of the twelfth transistor is electrically connected to At the scanning signal output terminal of the current level;
  • the gate of the thirteenth transistor is electrically connected to the high-level signal, the source of the thirteenth transistor is electrically connected based on the second function control signal, and the drain of the thirteenth transistor Electrically connected to the fourth node.
  • the potential of the fourth node is greater than the potential of the second function control signal.
  • the pull-down maintenance control signal is the same signal as the first function control signal or the second function control signal.
  • an embodiment of the present application also provides a display panel, including a GOA circuit, the GOA circuit includes: multi-level cascaded GOA units, each level of GOA unit includes a pull-up control module, a pull-up module, and a pull-down module. Module, pull-down maintenance module and reset module;
  • the pull-up control module is connected to the upper-level scan signal, the first scan control signal, and the low-level signal, and is electrically connected to the first node; the pull-up control module is configured to respond to the upper-level scan signal , The low-level signal and the first scan control signal, output the first scan control signal to the first node;
  • the pull-up module is connected to the high-level signal and the clock signal of the current level, and is electrically connected to the scan signal output terminal of the current level and the first node; the pull-up module is used for The current-level clock signal and the potential of the first node output a current-level scan signal at the scan signal output terminal;
  • the pull-down module is connected to the next-level clock signal, the previous-level clock signal, the second scan control signal, the next-level scan signal, the low-level signal, and the high-level signal, and is electrically connected to the first Two nodes and the first node; the pull-down module is used to perform according to the next-stage clock signal, the upper-stage clock signal, the second scan control signal, the next-stage scan signal, the A low-level signal and the high-level signal, pull down the potential of the first node and pull up the potential of the second node;
  • the pull-down maintenance module accesses a pull-down maintenance control signal and the low-level signal, and is electrically connected to the first node, the second node, and the scan signal output terminal of the current stage; the pull-down maintenance module is used for Maintaining the potential of the first node and the potential of the scan signal output terminal of the current stage according to the pull-down maintenance control signal, the low-level signal, and the potential of the second node;
  • the reset module is connected to the first function control signal, the second function control signal, and the high-level signal, and is electrically connected to the scan signal output terminal of the current stage; the reset module is used for The first function control signal, the second function control signal, and the high-level signal reset the potential of the scanning signal output terminal.
  • the pull-up control module includes a third transistor and a first capacitor
  • the gate of the third transistor is electrically connected to the previous scan signal, the source of the third transistor is electrically connected to the first scan control signal, and the drain of the third transistor is electrically connected Connected to the first node;
  • One end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the low-level signal.
  • the pull-up module includes a sixth transistor and an eighth transistor
  • the gate of the sixth transistor is electrically connected to the high-level signal
  • the source of the sixth transistor is electrically connected to the first node
  • the drain of the sixth transistor is electrically connected to the first node.
  • the gate of the eighth transistor is electrically connected to the third node, the source of the eighth transistor is electrically connected to the clock signal of the current stage, and the drain of the eighth transistor is electrically connected to the third node. Describe the scan signal output terminal of this level.
  • the eighth transistor when the eighth transistor is turned on, the potential of the third node is greater than the potential of the first node.
  • a reset module is provided in each level of GOA unit, so that before the end of a frame, each level of GOA unit outputs a high potential, and all display areas are gated.
  • the pole is turned on, the charge of all pixels in the display area is discharged; after that, each level of GOA unit outputs a low potential, and all gates in the display area are set to low potential; that is, the embodiment of the present application can improve And the normal black-sweeping ability; and can improve the stability of the stage transmission of the GOA circuit of the high-resolution display panel.
  • FIG. 1 is a schematic diagram of the structure of a GOA circuit provided by an embodiment of the application
  • Fig. 2 is a schematic circuit diagram of any GOA unit in Fig. 1;
  • Fig. 3 is a signal timing diagram of the GOA unit shown in Fig. 2;
  • FIG. 4 is a schematic diagram of the reset sequence of the GOA circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor other than the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application are N-type transistors or P-type transistors, where the N-type transistor is turned on when the gate is high and turned off when the gate is low; and the P-type transistor is low-voltage on the gate. It is usually turned on and turned off when the gate is high.
  • the GOA circuit provided by the embodiment of the present application can be used to realize forward scanning or reverse scanning.
  • forward scanning refers to the GOA circuit starting from the first-level GOA unit to the last and GOA unit in turn;
  • reverse scanning refers to the GOA unit starting from the last-level GOA unit to the first-level GOA unit in turn .
  • FIG. 1 is a schematic structural diagram of a GOA circuit provided by an embodiment of the application.
  • the GOA circuit 10 provided by the embodiment of the present application includes a multi-stage cascaded GOA unit 20.
  • Each GOA unit 20 is used to output a scan signal.
  • the upper-level scanning signal accessed by the first-level GOA unit 20 is the preset start signal STV; subsequently, the second-level GOA unit 20 and the third-level GOA unit 20 ,..., the last level of GOA unit 20 is sequentially transmitted and started.
  • FIG. 2 is a schematic diagram of a circuit of any GOA unit in FIG. 1.
  • the GOA unit includes a pull-up control module 101, a pull-up module 102, a pull-down module 103, a pull-down maintenance module 104, and a reset module 105.
  • the pull-up control module 101 is connected to the upper-level scan signal Gate N-1, the first scan control signal U2D, and the low-level signal VGL, and is electrically connected to the first node Q1.
  • the pull-up control module 101 is configured to output the first scan control signal U2D to the first node Q1 according to the previous scan signal Gate N-1, the low level signal VGL and the first scan control signal U2D.
  • the pull-up module 102 is connected to the high-level signal VGH and the clock signal CKN of the current level, and is electrically connected to the scan signal output terminal of the current level and the first node Q1.
  • the pull-up module 102 is configured to output the current level scan signal Gate N at the scan signal output terminal according to the high level signal VGH, the current level clock signal CKN, and the potential of the first node Q1.
  • the pull-down module 103 is connected to the next-stage clock signal CKN+1, the previous-stage clock signal CKN-1, the second scan control signal D2U, the next-stage scan signal Gate N+1, the low-level signal VGL, and the high-level
  • the flat signal VGH is electrically connected to the second node Q2 and the first node Q1.
  • the pull-down module 103 is configured to respond to the next-stage clock signal CKN+1, the previous-stage clock signal CKN-1, the second scan control signal D2U, the next-stage scan signal Gate N+1, the low-level signal VGL, and the high-level
  • the signal VGH pulls down the potential of the first node Q1 and pulls up the potential of the second node Q2.
  • the pull-down maintenance module 104 accesses the pull-down maintenance control signal and the low-level signal VGL, and is electrically connected to the first node Q1, the second node Q2, and the scan signal output terminal of the current stage.
  • the pull-down sustaining module 104 is configured to maintain the potential of the first node Q1 and the potential of the scan signal output terminal of the current stage according to the pull-down sustaining control signal, the low-level signal VGL, and the potential of the second node Q2.
  • the reset module 105 is connected to the first function control signal GAS1, the second function control signal GAS2, and the high-level signal VGH, and is electrically connected to the scanning signal output terminal of the current stage.
  • the reset module 105 is configured to reset the potential of the scan signal output terminal according to the first function control signal GAS1, the second function control signal GAS2, and the high-level signal VGH.
  • the specific circuit structures of the pull-up control module 101, the pull-up module 102, the pull-down module 103, and the pull-down maintenance module 104 in the embodiment of the present application do not only include the circuit structure described below. Based on the functional description of the above modules in the technical solution of the present application, the skilled person can obtain a variety of circuit structures that can achieve the same function.
  • the pull-up control module 101 includes a third transistor T3 and a first capacitor C1.
  • the gate of the third transistor T3 is electrically connected to the previous scan signal Gate N-1
  • the source of the third transistor T3 is electrically connected to the first scan control signal U2D
  • the drain of the third transistor T3 is electrically connected to The first node Q1.
  • One end of the first capacitor C1 is electrically connected to the first node Q1, and the other end of the first capacitor C1 is electrically connected to the low-level signal VGL.
  • the pull-up module 102 includes a sixth transistor T6 and an eighth transistor T8.
  • the gate of the sixth transistor T6 is electrically connected to the high-level signal VGH
  • the source of the sixth transistor T6 is electrically connected to the first node Q1
  • the drain of the sixth transistor T6 is electrically connected to the third node Q3.
  • the gate of the eighth transistor T8 is electrically connected to the third node Q3, the source of the eighth transistor T8 is electrically connected to the clock signal CKN of the current stage, and the drain of the eighth transistor T8 is electrically connected to the scan signal output terminal of the current stage .
  • the pull-down module 103 includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, and a ninth transistor T9.
  • the gate of the first transistor T1 is electrically connected to the first scan control signal U2D, and the source of the first transistor T1 is electrically connected to the next-stage clock signal CKN+1.
  • the gate of the second transistor T2 is electrically connected to the second scan control signal D2U, and the source of the second transistor T2 is electrically connected to the upper-level clock signal CKN-1.
  • the drain of the first transistor T1, the drain of the second transistor T2, and the gate of the fifth transistor T5 are electrically connected, the source of the fifth transistor T5 is electrically connected to the high-level signal VGH, and the drain of the fifth transistor T5 The pole is electrically connected to the second node Q2.
  • the gate of the fourth transistor T4 is electrically connected to the next scan signal Gate N+1, the source of the fourth transistor T4 is electrically connected to the second scan control signal D2U, and the drain of the fourth transistor T4 is electrically connected to The first node Q1.
  • the gate of the ninth transistor T9 is electrically connected to the first node Q1, the source of the ninth transistor T9 is electrically connected to the low-level signal VGL, and the drain of the ninth transistor T9 is electrically connected to the second node Q2.
  • the pull-down sustaining module 104 includes a seventh transistor T7, a tenth transistor T10, an eleventh transistor T11, and a second capacitor C2.
  • the gate of the seventh transistor T7 is electrically connected to the second node Q2
  • the source of the seventh transistor T7 is electrically connected to the low-level signal VGL
  • the drain of the seventh transistor T7 is electrically connected to the first node Q1.
  • the gate of the tenth transistor T10 is electrically connected to the first function control signal GAS1 or the second function control signal GAS2, the source of the tenth transistor T10 is electrically connected to the low level signal VGL, and the drain of the tenth transistor T10 is electrically connected Connected to the second node Q2.
  • the gate of the eleventh transistor T11 is electrically connected to the second node Q2, the source of the tenth transistor T10 is electrically connected to the low-level signal VGL, and the drain wire of the tenth transistor T10 is connected to the scan signal output terminal of this stage .
  • the reset module 105 includes a twelfth transistor T12 and a thirteenth transistor T13.
  • the gate of the twelfth transistor T12 is electrically connected to the fourth node Q4, the source of the twelfth transistor T12 is electrically connected to the first function control signal GAS1, and the drain of the twelfth transistor T12 is electrically connected to this stage Scan signal output terminal.
  • the gate of the thirteenth transistor T13 is electrically connected to the high-level signal VGH, the source of the thirteenth transistor T13 is electrically connected to the second function control signal GAS2, and the drain of the thirteenth transistor T13 is electrically connected to the Four-node Q4.
  • FIG. 3 is a signal timing diagram of the GOA unit shown in FIG. 2.
  • the first scan control signal U2D and the second scan control signal D2U are signals with opposite phases, and the potential of the first scan control signal U2D is high, and the potential of the second scan control signal D2U is low.
  • the pull-down sustain control signal is the same signal as the first function control signal GAS1 or the second function control signal GAS2. That is, the embodiment of the present application multiplexes the first function control signal GAS1 or the second function control signal GAS2 as the pull-down maintenance control signal, thereby reducing signal settings and providing more wiring space for the display panel.
  • the potential of the previous scan signal Gate N-1 is low, the third transistor T3 is turned off, and the potential of the first node Q1 maintains the potential at time t1.
  • the potential of the clock signal CKN of this stage changes from low to high. Due to the coupling effect of the parasitic capacitance of the eighth transistor T8, the potential of the third node Q3 jumps instantaneously, so that the potential of the third node Q3 reaches a higher level. High potential.
  • the eighth transistor T8 is turned on, and the scanning signal Gate NG(n) of the current stage and the transmission signal ST(n) of the current stage are also turned to a high potential output terminal.
  • the potential of the current scan signal output by the output terminal is high. At this time, the potential of the second node Q2 is still low. That is, when the eighth transistor T8 is turned on, the potential of the third node Q3 is greater than the potential of the first node Q1.
  • next-stage scan signal Gate N+1 the potential of the next-stage scan signal Gate N+1 is high, the fourth transistor T4 is turned on, and the second scan control signal D2U is output to the first node Q1 through the fourth transistor T4, thereby pulling down the first node Q1 The potential.
  • next-stage clock signal CKN+1 is at a high potential, so that the fifth transistor T5 is turned on, and the high-level signal VGH is output to the second node Q2 through the fifth transistor T5, so that the potential of the second node Q2 is high.
  • the seventh transistor T7 and the eleventh transistor T11 are both turned on, and the low-level signal VGL is output to the first node Q1 and the scan signal output terminal of the current stage through the seventh transistor T7 and the eleventh transistor T11, respectively.
  • the potential of the first node Q1 and the potential of the scan signal Gate N of the current stage are both low.
  • a reset module 105 is provided in each level of GOA unit, so that before the end of a frame, each level of GOA unit outputs a high potential to turn on the gates of all display areas, and display The charge of all pixels in the area is discharged; after that, each level of GOA unit outputs a low potential, and all gates in the display area are set to a low potential.
  • FIG. 4 is a schematic diagram of the reset sequence of the GOA circuit provided by an embodiment of the application.
  • the potential of the second scan control signal D2U is high, and at this time the thirteenth transistor T13 is turned on, and the second scan control signal D2U passes
  • the twelfth transistor T12 is output to the fourth node Q4 to precharge the fourth node Q4; then, at the time t2, the potentials of the second function control signal GAS2 and the first function control signal GAS1 are both high (the second function control The potential of the signal GAS2 can also be low at t2, which can be adjusted according to actual needs).
  • the fourth node Q4 Since the fourth node Q4 is subject to the bootstrap effect, its potential will be pulled to approximately twice the amplitude of the first function control signal, and the output waveform is also better. That is, when the twelfth transistor T12 is turned on, the potential of the fourth node Q4 is greater than the potential of the second function control signal GAS2. Finally, at time t3, the potential of the first function control signal GAS1 is low, and the potential of the second function control signal GAS2 is high, so that the current level scan signal Gate N output from the current level scan signal output terminal is pulled low and reset.
  • FIG. 5 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • the display panel includes a display area 100 and a GOA circuit 200 integratedly arranged on the edge of the display area 100; wherein the structure and principle of the GOA circuit 200 are similar to the GOA circuit 10 described above, and will not be repeated here.

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Abstract

GOA电路(10)及显示面板，通过在每一级GOA单元(20)中均设置一重置模块(105)，从而可以在一帧结束前，每一级GOA单元(20)均输出高电位，将所有显示区栅极打开，显示区所有像素的电荷被放完；之后每一级GOA单元(20)均输出低电位，将显示区所有栅极置为低电位。

Description

GOA电路及显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种GOA电路及显示面板。
 背景技术
Gate Driver On Array，简称GOA，也就是利用现有薄膜晶体管液晶显示器阵列制程将行扫描驱动信号电路制作在阵列基板上，实现对扫描线逐行扫描的驱动方式的一项技术。
随着显示面板的分辨率越来越高，扫描行数也越来越多，其发生级传错误的概率也增大，同时在客户操作过程中有可能会出现异常掉电的情况，如果没有下电扫黑的和重置的功能，往往会造成电荷残留引起异常显示。因此，高分辨率显示面板的GOA电路的级传稳定性较差。
 技术问题
本申请实施例的目的在于提供一种GOA电路及显示面板，能够解决现有的高分辨率显示面板的GOA电路的级传稳定性较差的技术问题。
 技术解决方案
第一方面，本申请实施例提供一种GOA电路，包括：多级级联的GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下拉模块、下拉维持模块以及重置模块；
所述上拉控制模块接入上一级扫描信号、第一扫描控制信号以及低电平信号，并电性连接于第一节点；所述上拉控制模块用于根据所述上一级扫描信号、所述低电平信号以及所述第一扫描控制信号，将所述第一扫描控制信号输出至所述第一节点；
所述上拉模块接入高电平信号以及本级时钟信号，并电性连接于本级扫描信号输出端以及所述第一节点；所述上拉模块用于根据所述高电平信号、所述本级时钟信号以及所述第一节点的电位，在所述扫描信号输出端输出本级扫描信号；
所述下拉模块接入下一级时钟信号、上一级时钟信号、第二扫描控制信号、下一级扫描信号、所述低电平信号以及所述高电平信号，并电性连接于第二节点以及所述第一节点；所述下拉模块用于根据所述下一级时钟信号、所述上一级时钟信号、所述第二扫描控制信号、所述下一级扫描信号、所述低电平信号以及所述高电平信号，下拉所述第一节点的电位以及拉高所述第二节点的电位；
所述下拉维持模块接入下拉维持控制信号以及所述低电平信号，并电性连接于所述第一节点、第二节点以及所述本级扫描信号输出端；所述下拉维持模块用于根据所述下拉维持控制信号、所述低电平信号以及所述第二节点的电位，维持所述第一节点的电位以及所述本级扫描信号输出端的电位；
所述重置模块接入第一功能控制信号、第二功能控制信号以及所述高电平信号，并电性连接于所述本级扫描信号输出端；所述重置模块用于根据所述第一功能控制信号、所述第二功能控制信号以及所述高电平信号，重置所述扫描信号输出端的电位；
所述重置模块包括第十二晶体管以及第十三晶体管；
所述第十二晶体管的栅极电性连接于第四节点，所述第十二晶体管的源极电性连接于所述第一功能控制信号，所述第十二晶体管的漏极电性连接于所述本级扫描信号输出端；
所述第十三晶体管的栅极电性连接于所述高电平信号，所述第十三晶体管的源极电性连基于所述第二功能控制信号，所述第十三晶体管的漏极电性连接于所述第四节点；
所述下拉维持控制信号与所述第一功能控制信号或所述第二功能控制信号为同一信号。
在本申请实施例所述的GOA电路中，所述上拉控制模块包括第三晶体管以及第一电容；
所述第三晶体管的栅极电性连接于所述上一级扫描信号，所述第三晶体管的源极电性连接于所述第一扫描控制信号，所述第三晶体管的漏极电性连接于所述第一节点；
所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述低电平信号。
在本申请实施例所述的GOA电路中，所述上拉模块包括第六晶体管以及第八晶体管；
所述第六晶体管的栅极电性连接于所述高电平信号，所述第六晶体管的源极电性连接于所述第一节点，所述第六晶体管的漏极电性连接于第三节点；
所述第八晶体管的栅极电性连接于所述第三节点，所述第八晶体管的源极电性连接于所述本级时钟信号，所述第八晶体管的漏极电性连接于所述本级扫描信号输出端。
在本申请实施例所述的GOA电路中，当所述第八晶体管打开时，所述第三节点的电位大于所述第一节点的电位。
在本申请实施例所述的GOA电路中，所述下拉模块包括第一晶体管、第二晶体管、第四晶体管、第五晶体管以及第九晶体管；
所述第一晶体管的栅极电性连接于所述第一扫描控制信号，所述第一晶体管的源极电性连接于所述下一级时钟信号；
所述第二晶体管的栅极电性连接于所述第二扫描控制信号，所述第二晶体管的源极电性连接于所述上一级时钟信号；
所述第一晶体管的漏极、所述第二晶体管的漏极以及所述第五晶体管的栅极电性连接，所述第五晶体管的源极电性连接于所述高电平信号，所述第五晶体管的漏极电性连接于所述第二节点；
所述第四晶体管的栅极电性连接于所述下一级扫描信号，所述第四晶体管的源极电性连接于所述第二扫描控制信号，所述第四晶体管的漏极电性连接于所述第一节点；
所述第九晶体管的栅极电性连接于所述第一节点，所述第九晶体管的源极电性连接于所述低电平信号，所述第九晶体管的漏极电性连接于所述第二节点。
在本申请实施例所述的GOA电路中，所述下拉维持模块包括第七晶体管、第十晶体管、第十一晶体管以及第二电容；
所述第七晶体管的栅极电性连接于所述第二节点，所述第七晶体管的源极电性连接于所述低电平信号，所述第七晶体管的漏极电性连接于所述第一节点；
所述第十晶体管的栅极电性连接于所述第一功能控制信号或者第二功能控制信号，所述第十晶体管的源极电性连接于所述低电平信号，所述第十晶体管的漏极电性连接于所述第二节点；
所述第十一晶体管的栅极电性连接于所述第二节点，所述第十晶体管的源极电性连接于所述低电平信号，所述第十晶体管的漏极电线连接于所述本级扫描信号输出端。
在本申请实施例所述的GOA电路中，当所述第十二晶体管打开时，所述第四节点的电位大于所述第二功能控制信号的电位。
第二方面，本申请实施例提供一种GOA电路，包括：多级级联的GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下拉模块、下拉维持模块以及重置模块；
所述上拉控制模块接入上一级扫描信号、第一扫描控制信号以及低电平信号，并电性连接于第一节点；所述上拉控制模块用于根据所述上一级扫描信号、所述低电平信号以及所述第一扫描控制信号，将所述第一扫描控制信号输出至所述第一节点；
所述上拉模块接入高电平信号以及本级时钟信号，并电性连接于本级扫描信号输出端以及所述第一节点；所述上拉模块用于根据所述高电平信号、所述本级时钟信号以及所述第一节点的电位，在所述扫描信号输出端输出本级扫描信号；
所述下拉模块接入下一级时钟信号、上一级时钟信号、第二扫描控制信号、下一级扫描信号、所述低电平信号以及所述高电平信号，并电性连接于第二节点以及所述第一节点；所述下拉模块用于根据所述下一级时钟信号、所述上一级时钟信号、所述第二扫描控制信号、所述下一级扫描信号、所述低电平信号以及所述高电平信号，下拉所述第一节点的电位以及拉高所述第二节点的电位；
所述下拉维持模块接入下拉维持控制信号以及所述低电平信号，并电性连接于所述第一节点、第二节点以及所述本级扫描信号输出端；所述下拉维持模块用于根据所述下拉维持控制信号、所述低电平信号以及所述第二节点的电位，维持所述第一节点的电位以及所述本级扫描信号输出端的电位；
所述重置模块接入第一功能控制信号、第二功能控制信号以及所述高电平信号，并电性连接于所述本级扫描信号输出端；所述重置模块用于根据所述第一功能控制信号、所述第二功能控制信号以及所述高电平信号，重置所述扫描信号输出端的电位。
在本申请实施例所述的GOA电路中，所述上拉控制模块包括第三晶体管以及第一电容；
所述第三晶体管的栅极电性连接于所述上一级扫描信号，所述第三晶体管的源极电性连接于所述第一扫描控制信号，所述第三晶体管的漏极电性连接于所述第一节点；
所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述低电平信号。
在本申请实施例所述的GOA电路中，所述上拉模块包括第六晶体管以及第八晶体管；
所述第六晶体管的栅极电性连接于所述高电平信号，所述第六晶体管的源极电性连接于所述第一节点，所述第六晶体管的漏极电性连接于第三节点；
所述第八晶体管的栅极电性连接于所述第三节点，所述第八晶体管的源极电性连接于所述本级时钟信号，所述第八晶体管的漏极电性连接于所述本级扫描信号输出端。
在本申请实施例所述的GOA电路中，当所述第八晶体管打开时，所述第三节点的电位大于所述第一节点的电位。
在本申请实施例所述的GOA电路中，所述下拉模块包括第一晶体管、第二晶体管、第四晶体管、第五晶体管以及第九晶体管；
所述第一晶体管的栅极电性连接于所述第一扫描控制信号，所述第一晶体管的源极电性连接于所述下一级时钟信号；
所述第二晶体管的栅极电性连接于所述第二扫描控制信号，所述第二晶体管的源极电性连接于所述上一级时钟信号；
所述第一晶体管的漏极、所述第二晶体管的漏极以及所述第五晶体管的栅极电性连接，所述第五晶体管的源极电性连接于所述高电平信号，所述第五晶体管的漏极电性连接于所述第二节点；
所述第四晶体管的栅极电性连接于所述下一级扫描信号，所述第四晶体管的源极电性连接于所述第二扫描控制信号，所述第四晶体管的漏极电性连接于所述第一节点；
所述第九晶体管的栅极电性连接于所述第一节点，所述第九晶体管的源极电性连接于所述低电平信号，所述第九晶体管的漏极电性连接于所述第二节点。
在本申请实施例所述的GOA电路中，所述下拉维持模块包括第七晶体管、第十晶体管、第十一晶体管以及第二电容；
所述第七晶体管的栅极电性连接于所述第二节点，所述第七晶体管的源极电性连接于所述低电平信号，所述第七晶体管的漏极电性连接于所述第一节点；
所述第十晶体管的栅极电性连接于所述第一功能控制信号或者第二功能控制信号，所述第十晶体管的源极电性连接于所述低电平信号，所述第十晶体管的漏极电性连接于所述第二节点；
所述第十一晶体管的栅极电性连接于所述第二节点，所述第十晶体管的源极电性连接于所述低电平信号，所述第十晶体管的漏极电线连接于所述本级扫描信号输出端。
在本申请实施例所述的GOA电路中，所述重置模块包括第十二晶体管以及第十三晶体管；
所述第十二晶体管的栅极电性连接于第四节点，所述第十二晶体管的源极电性连接于所述第一功能控制信号，所述第十二晶体管的漏极电性连接于所述本级扫描信号输出端；
所述第十三晶体管的栅极电性连接于所述高电平信号，所述第十三晶体管的源极电性连基于所述第二功能控制信号，所述第十三晶体管的漏极电性连接于所述第四节点。
在本申请实施例所述的GOA电路中，当所述第十二晶体管打开时，所述第四节点的电位大于所述第二功能控制信号的电位。
在本申请实施例所述的GOA电路中，所述下拉维持控制信号与所述第一功能控制信号或所述第二功能控制信号为同一信号。
第三方面，本申请实施例还提供一种显示面板，包括GOA电路，所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下拉模块、下拉维持模块以及重置模块；
所述上拉控制模块接入上一级扫描信号、第一扫描控制信号以及低电平信号，并电性连接于第一节点；所述上拉控制模块用于根据所述上一级扫描信号、所述低电平信号以及所述第一扫描控制信号，将所述第一扫描控制信号输出至所述第一节点；
所述上拉模块接入高电平信号以及本级时钟信号，并电性连接于本级扫描信号输出端以及所述第一节点；所述上拉模块用于根据所述高电平信号、所述本级时钟信号以及所述第一节点的电位，在所述扫描信号输出端输出本级扫描信号；
所述下拉模块接入下一级时钟信号、上一级时钟信号、第二扫描控制信号、下一级扫描信号、所述低电平信号以及所述高电平信号，并电性连接于第二节点以及所述第一节点；所述下拉模块用于根据所述下一级时钟信号、所述上一级时钟信号、所述第二扫描控制信号、所述下一级扫描信号、所述低电平信号以及所述高电平信号，下拉所述第一节点的电位以及拉高所述第二节点的电位；
所述下拉维持模块接入下拉维持控制信号以及所述低电平信号，并电性连接于所述第一节点、第二节点以及所述本级扫描信号输出端；所述下拉维持模块用于根据所述下拉维持控制信号、所述低电平信号以及所述第二节点的电位，维持所述第一节点的电位以及所述本级扫描信号输出端的电位；
所述重置模块接入第一功能控制信号、第二功能控制信号以及所述高电平信号，并电性连接于所述本级扫描信号输出端；所述重置模块用于根据所述第一功能控制信号、所述第二功能控制信号以及所述高电平信号，重置所述扫描信号输出端的电位。
在本申请实施例所述的显示面板中，所述上拉控制模块包括第三晶体管以及第一电容；
所述第三晶体管的栅极电性连接于所述上一级扫描信号，所述第三晶体管的源极电性连接于所述第一扫描控制信号，所述第三晶体管的漏极电性连接于所述第一节点；
所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述低电平信号。
在本申请实施例所述的显示面板中，所述上拉模块包括第六晶体管以及第八晶体管；
所述第六晶体管的栅极电性连接于所述高电平信号，所述第六晶体管的源极电性连接于所述第一节点，所述第六晶体管的漏极电性连接于第三节点；
所述第八晶体管的栅极电性连接于所述第三节点，所述第八晶体管的源极电性连接于所述本级时钟信号，所述第八晶体管的漏极电性连接于所述本级扫描信号输出端。
在本申请实施例所述的显示面板中，当所述第八晶体管打开时，所述第三节点的电位大于所述第一节点的电位。
 有益效果
本申请实施例提供的GOA电路及显示面板，通过在每一级GOA单元中均设置一重置模块，从而可以在一帧结束前，每一级GOA单元均输出高电位，将所有显示区栅极打开，显示区所有像素的电荷被放完；之后每一级GOA单元均输出低电位，将显示区区所有栅极置为低电位；也即，本申请实施例可以提高提高异常下电扫黑和正常扫黑能力；并且可以提高高分辨率显示面板的GOA电路的级传稳定性。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的GOA电路的结构示意图；
图2为图1中任一GOA单元的电路示意图；
图3为图2所示GOA单元的信号时序图；
图4为本申请实施例提供的GOA电路的重置时序示意图；以及
图5为本申请实施例提供的显示面板的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管为N 型晶体管或P型晶体管，其中，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止；P 型晶体管为在栅极为低电平时导通，在栅极为高电平时截止。
需要说明的是，本申请实施例提供的GOA电路可用于实现正向扫描或者反向扫描。其中，正向扫描指的是，该GOA电路从第一级GOA单元至最后以及GOA单元依次启动；反向扫描指的是，该GOA单元从最后一级GOA单元至第一级GOA单元依次启动。
下面本申请实施例将以正向扫描为例进行说明。请参阅图1，图1为本申请实施例提供的GOA电路的结构示意图。如图1所示，本申请实施例提供的GOA电路10包括多级级联的GOA单元20。每一级GOA单元20均用于输出一扫描信。其中，当该GOA电路10工作时，第一级GOA单元20接入的上一级扫描信号为预先设定好的起始信号STV；随后，第二级GOA单元20、第三级GOA单元20，……，最后一级GOA单元20依次级传启动。
请参阅图2，图2为图1中任一GOA单元的电路示意图。如图2所示，该GOA单元包括上拉控制模块101、上拉模块102、下拉模块103、下拉维持模块104以及重置模块105。
其中，上拉控制模块101接入上一级扫描信号Gate N-1、第一扫描控制信号U2D以及低电平信号VGL，并电性连接于第一节点Q1。上拉控制模块101用于根据上一级扫描信号Gate N-1、低电平信号VGL以及第一扫描控制信号U2D，将第一扫描控制信号U2D输出至第一节点Q1。
其中，上拉模块102接入高电平信号VGH以及本级时钟信号CKN，并电性连接于本级扫描信号输出端以及第一节点Q1。上拉模块102用于根据高电平信号VGH、本级时钟信号CKN以及第一节点Q1的电位，在扫描信号输出端输出本级扫描信号Gate N。
其中，下拉模块103接入下一级时钟信号CKN+1、上一级时钟信号CKN-1、第二扫描控制信号D2U、下一级扫描信号Gate N+1、低电平信号VGL以及高电平信号VGH，并电性连接于第二节点Q2以及第一节点Q1。下拉模块103用于根据下一级时钟信号CKN+1、上一级时钟信号CKN-1、第二扫描控制信号D2U、下一级扫描信号Gate N+1、低电平信号VGL以及高电平信号VGH，下拉第一节点Q1的电位以及拉高第二节点Q2的电位。
其中，下拉维持模块104接入下拉维持控制信号以及低电平信号VGL，并电性连接于第一节点Q1、第二节点Q2以及本级扫描信号输出端。下拉维持模块104用于根据下拉维持控制信号、低电平信号VGL以及第二节点Q2的电位，维持第一节点Q1的电位以及本级扫描信号输出端的电位。
其中，重置模块105接入第一功能控制信号GAS1、第二功能控制信号GAS2以及高电平信号VGH，并电性连接于本级扫描信号输出端。重置模块105用于根据第一功能控制信号GAS1、第二功能控制信号GAS2以及高电平信号VGH，重置扫描信号输出端的电位。
需要说明的是，本申请实施例中的上拉控制模块101、上拉模块102、下拉模块103以及下拉维持模块104的具体电路结构并不仅仅只包括以下所描述的一种电路结构，本领域技术人员基于本申请技术方案中对以上模块的功能描述，可以得到多种可以实现相同功能的电路结构。
在一些实施例中，上拉控制模块101包括第三晶体管T3以及第一电容C1。第三晶体管T3的栅极电性连接于上一级扫描信号Gate N-1，第三晶体管T3的源极电性连接于第一扫描控制信号U2D，第三晶体管T3的漏极电性连接于第一节点Q1。第一电容C1的一端电性连接于第一节点Q1，第一电容C1的另一端电性连接于低电平信号VGL。
在一些实施例中，上拉模块102包括第六晶体管T6以及第八晶体管T8。第六晶体管T6的栅极电性连接于高电平信号VGH，第六晶体管T6的源极电性连接于第一节点Q1，第六晶体管T6的漏极电性连接于第三节点Q3。第八晶体管T8的栅极电性连接于第三节点Q3，第八晶体管T8的源极电性连接于本级时钟信号CKN，第八晶体管T8的漏极电性连接于本级扫描信号输出端。
在一些实施例中，下拉模块103包括第一晶体管T1、第二晶体管T2、第四晶体管T4、第五晶体管T5以及第九晶体管T9。第一晶体管T1的栅极电性连接于第一扫描控制信号U2D，第一晶体管T1的源极电性连接于下一级时钟信号CKN+1。第二晶体管T2的栅极电性连接于第二扫描控制信号D2U，第二晶体管T2的源极电性连接于上一级时钟信号CKN-1。第一晶体管T1的漏极、第二晶体管T2的漏极以及第五晶体管T5的栅极电性连接，第五晶体管T5的源极电性连接于高电平信号VGH，第五晶体管T5的漏极电性连接于第二节点Q2。第四晶体管T4的栅极电性连接于下一级扫描信号Gate N+1，第四晶体管T4的源极电性连接于第二扫描控制信号D2U，第四晶体管T4的漏极电性连接于第一节点Q1。第九晶体管T9的栅极电性连接于第一节点Q1，第九晶体管T9的源极电性连接于低电平信号VGL，第九晶体管T9的漏极电性连接于第二节点Q2。
在一些实施例中，下拉维持模块104包括第七晶体管T7、第十晶体管T10、第十一晶体管T11以及第二电容C2。第七晶体管T7的栅极电性连接于第二节点Q2，第七晶体管T7的源极电性连接于低电平信号VGL，第七晶体管T7的漏极电性连接于第一节点Q1。第十晶体管T10的栅极电性连接于第一功能控制信号GAS1或者第二功能控制信号GAS2，第十晶体管T10的源极电性连接于低电平信号VGL，第十晶体管T10的漏极电性连接于第二节点Q2。第十一晶体管T11的栅极电性连接于第二节点Q2，第十晶体管T10的源极电性连接于低电平信号VGL，第十晶体管T10的漏极电线连接于本级扫描信号输出端。
在一些实施例中，重置模块105包括第十二晶体管T12以及第十三晶体管T13。第十二晶体管T12的栅极电性连接于第四节点Q4，第十二晶体管T12的源极电性连接于第一功能控制信号GAS1，第十二晶体管T12的漏极电性连接于本级扫描信号输出端。第十三晶体管T13的栅极电性连接于高电平信号VGH，第十三晶体管T13的源极电性连基于第二功能控制信号GAS2，第十三晶体管T13的漏极电性连接于第四节点Q4。
下面将结合图2、图3对本申请实施例提供的GOA电路的工作原理进行说明。其中，图3为图2所示GOA单元的信号时序图。
在本申请实施例中，第一扫描控制信号U2D与第二扫描控制信号D2U为相位相反的信号，且第一扫描控制信号U2D的电位为高，第二扫描控制信号D2U的电位为低。
在本申请实施例中，下拉维持控制信号与第一功能控制信号GAS1或第二功能控制信号GAS2为同一信号。也即，本申请实施例通过将第一功能控制信号GAS1或第二功能控制信号GAS2复用为下拉维持控制信号，从而可以减少信号设置，进而为显示面板提供更多的布线空间。
请参阅图2、图3。首先，在t10时刻，上一级扫描信号Gate N-1为高电位时，第三晶体管T3导通，第一扫描控制信号U2D通过第三晶体管T3输出至第一节点Q1，使得第一节点Q1此时的电位为高。由于第六晶体管T6处于常开状态，使得第三节点Q3此时的电位也为高。并且，第一节点Q1与第二节点Q2的电位通过第一电容C1进行存储。与此同时，当上一级扫信号为高电位时，第一晶体管T1也导通，由于此时下一级时钟信号CKN+1为低电位，使得第五晶体管T5关闭，进而使得第二节点Q2的电位为低。
随后，在t20时刻，上一级扫描信号Gate N-1的电位为低，第三晶体管T3关闭，第一节点Q1的电位维持t1时刻的电位。同时，本级时钟信号CKN的电位由低转高，由于第八晶体管T8自身的寄生电容的耦合作用，使得第三节点Q3的电位瞬间发生跳变，进而使得第三节点Q3的电位达到一更高的电位。此时，第八晶体管T8打开，本级扫描信号Gate NG（n）和本级级传信号ST（n）也转为高电位输出端输出的本级扫信号的电位为高。此时，第二节点Q2的电位依然为低。也即，当第八晶体管T8打开时，第三节点Q3的电位大于第一节点Q1的电位。
最后，在t30时刻，下一级扫描信号Gate N+1的电位为高，第四晶体管T4打开，第二扫描控制信号D2U通过第四晶体管T4输出至第一节点Q1，进而下拉第一节点Q1的电位。与此同时，下一级时钟信号CKN+1为高电位，使得第五晶体管T5打开，高电平信号VGH通过第五晶体管T5输出至第二节点Q2，使得第二节点Q2的电位为高。进一步的，此时，第七晶体管T7以及第十一晶体管T11均打开，低电平信号VGL分别经第七晶体管T7以及第十一晶体管T11输出至第一节点Q1和本级扫描信号输出端，从而使得第一节点Q1电位以及本级扫描信号Gate N的电位均为低。
特别的，本申请实施例通过在每一级GOA单元中均设置一重置模块105，从而可以在一帧结束前，每一级GOA单元均输出高电位，将所有显示区栅极打开，显示区所有像素的电荷被放完；之后每一级GOA单元均输出低电位，将显示区区所有栅极置为低电位。
具体的，下面将结合图2、图4进行说明。其中，图4为本申请实施例提供的GOA电路的重置时序示意图。结合图2、图4所示，在一帧结束前，首先，在t1时刻，第二扫描控制信号D2U的电位为高，且此时第十三晶体管T13导通，第二扫描控制信号D2U通过第十二晶体管T12输出至第四节点Q4，对第四节点Q4进行进行预充；接着，在t2时刻第二功能控制信号GAS2和第一功能控制信号GAS1的电位同时为高（第二功能控制信号GAS2的电位在t2时刻亦可为低，可根据实际需求进行调整）。由于第四节点Q4点受到自举效应，所以其电位会被拉到大约2倍第功能控制信号的幅值，进而输出波形也较好。也即，当第十二晶体管T12打开时，第四节点Q4的电位大于第二功能控制信号GAS2的电位。最后，在t3时刻，第一功能控制信号GAS1的电位为低，第二功能控制信号GAS2的电位为高，这样本级扫描信号输出端输出的本级扫描信号Gate N被拉低重置。
请参阅图5，图5为本申请实施例提供的显示面板的结构示意图。如图5所示，该显示面板包括显示区域100以及集成设置在显示区域100边缘上的GOA电路200；其中，该GOA电路200与上述的GOA电路10的结构和原理类似，这里不再赘述。
以上仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种GOA电路，其包括：多级级联的GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下拉模块、下拉维持模块以及重置模块；
    所述上拉控制模块接入上一级扫描信号、第一扫描控制信号以及低电平信号，并电性连接于第一节点；所述上拉控制模块用于根据所述上一级扫描信号、所述低电平信号以及所述第一扫描控制信号，将所述第一扫描控制信号输出至所述第一节点；
    所述上拉模块接入高电平信号以及本级时钟信号，并电性连接于本级扫描信号输出端以及所述第一节点；所述上拉模块用于根据所述高电平信号、所述本级时钟信号以及所述第一节点的电位，在所述扫描信号输出端输出本级扫描信号；
    所述下拉模块接入下一级时钟信号、上一级时钟信号、第二扫描控制信号、下一级扫描信号、所述低电平信号以及所述高电平信号，并电性连接于第二节点以及所述第一节点；所述下拉模块用于根据所述下一级时钟信号、所述上一级时钟信号、所述第二扫描控制信号、所述下一级扫描信号、所述低电平信号以及所述高电平信号，下拉所述第一节点的电位以及拉高所述第二节点的电位；
    所述下拉维持模块接入下拉维持控制信号以及所述低电平信号，并电性连接于所述第一节点、第二节点以及所述本级扫描信号输出端；所述下拉维持模块用于根据所述下拉维持控制信号、所述低电平信号以及所述第二节点的电位，维持所述第一节点的电位以及所述本级扫描信号输出端的电位；
    所述重置模块接入第一功能控制信号、第二功能控制信号以及所述高电平信号，并电性连接于所述本级扫描信号输出端；所述重置模块用于根据所述第一功能控制信号、所述第二功能控制信号以及所述高电平信号，重置所述扫描信号输出端的电位；
    所述重置模块包括第十二晶体管以及第十三晶体管；
    所述第十二晶体管的栅极电性连接于第四节点，所述第十二晶体管的源极电性连接于所述第一功能控制信号，所述第十二晶体管的漏极电性连接于所述本级扫描信号输出端；
    所述第十三晶体管的栅极电性连接于所述高电平信号，所述第十三晶体管的源极电性连基于所述第二功能控制信号，所述第十三晶体管的漏极电性连接于所述第四节点；
    所述下拉维持控制信号与所述第一功能控制信号或所述第二功能控制信号为同一信号。
  2. 根据权利要求1所述的GOA电路，其中，所述上拉控制模块包括第三晶体管以及第一电容；
    所述第三晶体管的栅极电性连接于所述上一级扫描信号，所述第三晶体管的源极电性连接于所述第一扫描控制信号，所述第三晶体管的漏极电性连接于所述第一节点；
    所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述低电平信号。
  3. 根据权利要求1所述的GOA电路，其中，所述上拉模块包括第六晶体管以及第八晶体管；
    所述第六晶体管的栅极电性连接于所述高电平信号，所述第六晶体管的源极电性连接于所述第一节点，所述第六晶体管的漏极电性连接于第三节点；
    所述第八晶体管的栅极电性连接于所述第三节点，所述第八晶体管的源极电性连接于所述本级时钟信号，所述第八晶体管的漏极电性连接于所述本级扫描信号输出端。
  4. 根据权利要求3所述的GOA电路，其中，当所述第八晶体管打开时，所述第三节点的电位大于所述第一节点的电位。
  5. 根据权利要求1所述的GOA电路，其中，所述下拉模块包括第一晶体管、第二晶体管、第四晶体管、第五晶体管以及第九晶体管；
    所述第一晶体管的栅极电性连接于所述第一扫描控制信号，所述第一晶体管的源极电性连接于所述下一级时钟信号；
    所述第二晶体管的栅极电性连接于所述第二扫描控制信号，所述第二晶体管的源极电性连接于所述上一级时钟信号；
    所述第一晶体管的漏极、所述第二晶体管的漏极以及所述第五晶体管的栅极电性连接，所述第五晶体管的源极电性连接于所述高电平信号，所述第五晶体管的漏极电性连接于所述第二节点；
    所述第四晶体管的栅极电性连接于所述下一级扫描信号，所述第四晶体管的源极电性连接于所述第二扫描控制信号，所述第四晶体管的漏极电性连接于所述第一节点；
    所述第九晶体管的栅极电性连接于所述第一节点，所述第九晶体管的源极电性连接于所述低电平信号，所述第九晶体管的漏极电性连接于所述第二节点。
  6. 根据权利要求1所述的GOA电路，其中，所述下拉维持模块包括第七晶体管、第十晶体管、第十一晶体管以及第二电容；
    所述第七晶体管的栅极电性连接于所述第二节点，所述第七晶体管的源极电性连接于所述低电平信号，所述第七晶体管的漏极电性连接于所述第一节点；
    所述第十晶体管的栅极电性连接于所述第一功能控制信号或者第二功能控制信号，所述第十晶体管的源极电性连接于所述低电平信号，所述第十晶体管的漏极电性连接于所述第二节点；
    所述第十一晶体管的栅极电性连接于所述第二节点，所述第十晶体管的源极电性连接于所述低电平信号，所述第十晶体管的漏极电线连接于所述本级扫描信号输出端。
  7. 根据权利要求1所述的GOA电路，其中，当所述第十二晶体管打开时，所述第四节点的电位大于所述第二功能控制信号的电位。
  8. 一种GOA电路，其包括：多级级联的GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下拉模块、下拉维持模块以及重置模块；
    所述上拉控制模块接入上一级扫描信号、第一扫描控制信号以及低电平信号，并电性连接于第一节点；所述上拉控制模块用于根据所述上一级扫描信号、所述低电平信号以及所述第一扫描控制信号，将所述第一扫描控制信号输出至所述第一节点；
    所述上拉模块接入高电平信号以及本级时钟信号，并电性连接于本级扫描信号输出端以及所述第一节点；所述上拉模块用于根据所述高电平信号、所述本级时钟信号以及所述第一节点的电位，在所述扫描信号输出端输出本级扫描信号；
    所述下拉模块接入下一级时钟信号、上一级时钟信号、第二扫描控制信号、下一级扫描信号、所述低电平信号以及所述高电平信号，并电性连接于第二节点以及所述第一节点；所述下拉模块用于根据所述下一级时钟信号、所述上一级时钟信号、所述第二扫描控制信号、所述下一级扫描信号、所述低电平信号以及所述高电平信号，下拉所述第一节点的电位以及拉高所述第二节点的电位；
    所述下拉维持模块接入下拉维持控制信号以及所述低电平信号，并电性连接于所述第一节点、第二节点以及所述本级扫描信号输出端；所述下拉维持模块用于根据所述下拉维持控制信号、所述低电平信号以及所述第二节点的电位，维持所述第一节点的电位以及所述本级扫描信号输出端的电位；
    所述重置模块接入第一功能控制信号、第二功能控制信号以及所述高电平信号，并电性连接于所述本级扫描信号输出端；所述重置模块用于根据所述第一功能控制信号、所述第二功能控制信号以及所述高电平信号，重置所述扫描信号输出端的电位。
  9. 根据权利要求8所述的GOA电路，其中，所述上拉控制模块包括第三晶体管以及第一电容；
    所述第三晶体管的栅极电性连接于所述上一级扫描信号，所述第三晶体管的源极电性连接于所述第一扫描控制信号，所述第三晶体管的漏极电性连接于所述第一节点；
    所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述低电平信号。
  10. 根据权利要求8所述的GOA电路，其中，所述上拉模块包括第六晶体管以及第八晶体管；
    所述第六晶体管的栅极电性连接于所述高电平信号，所述第六晶体管的源极电性连接于所述第一节点，所述第六晶体管的漏极电性连接于第三节点；
    所述第八晶体管的栅极电性连接于所述第三节点，所述第八晶体管的源极电性连接于所述本级时钟信号，所述第八晶体管的漏极电性连接于所述本级扫描信号输出端。
  11. 根据权利要求10所述的GOA电路，其中，当所述第八晶体管打开时，所述第三节点的电位大于所述第一节点的电位。
  12. 根据权利要求8所述的GOA电路，其中，所述下拉模块包括第一晶体管、第二晶体管、第四晶体管、第五晶体管以及第九晶体管；
    所述第一晶体管的栅极电性连接于所述第一扫描控制信号，所述第一晶体管的源极电性连接于所述下一级时钟信号；
    所述第二晶体管的栅极电性连接于所述第二扫描控制信号，所述第二晶体管的源极电性连接于所述上一级时钟信号；
    所述第一晶体管的漏极、所述第二晶体管的漏极以及所述第五晶体管的栅极电性连接，所述第五晶体管的源极电性连接于所述高电平信号，所述第五晶体管的漏极电性连接于所述第二节点；
    所述第四晶体管的栅极电性连接于所述下一级扫描信号，所述第四晶体管的源极电性连接于所述第二扫描控制信号，所述第四晶体管的漏极电性连接于所述第一节点；
    所述第九晶体管的栅极电性连接于所述第一节点，所述第九晶体管的源极电性连接于所述低电平信号，所述第九晶体管的漏极电性连接于所述第二节点。
  13. 根据权利要求8所述的GOA电路，其中，所述下拉维持模块包括第七晶体管、第十晶体管、第十一晶体管以及第二电容；
    所述第七晶体管的栅极电性连接于所述第二节点，所述第七晶体管的源极电性连接于所述低电平信号，所述第七晶体管的漏极电性连接于所述第一节点；
    所述第十晶体管的栅极电性连接于所述第一功能控制信号或者第二功能控制信号，所述第十晶体管的源极电性连接于所述低电平信号，所述第十晶体管的漏极电性连接于所述第二节点；
    所述第十一晶体管的栅极电性连接于所述第二节点，所述第十晶体管的源极电性连接于所述低电平信号，所述第十晶体管的漏极电线连接于所述本级扫描信号输出端。
  14. 根据权利要求8所述的GOA电路，其中，所述重置模块包括第十二晶体管以及第十三晶体管；
    所述第十二晶体管的栅极电性连接于第四节点，所述第十二晶体管的源极电性连接于所述第一功能控制信号，所述第十二晶体管的漏极电性连接于所述本级扫描信号输出端；
    所述第十三晶体管的栅极电性连接于所述高电平信号，所述第十三晶体管的源极电性连基于所述第二功能控制信号，所述第十三晶体管的漏极电性连接于所述第四节点。
  15. 根据权利要求14所述的GOA电路，其中，当所述第十二晶体管打开时，所述第四节点的电位大于所述第二功能控制信号的电位。
  16. 根据权利要求8所述的GOA电路，其中，所述下拉维持控制信号与所述第一功能控制信号或所述第二功能控制信号为同一信号。
  17. 一种显示面板，其包括GOA电路，所述GOA电路包括：多级级联的GOA单元，每一级GOA单元均包括上拉控制模块、上拉模块、下拉模块、下拉维持模块以及重置模块；
    所述上拉控制模块接入上一级扫描信号、第一扫描控制信号以及低电平信号，并电性连接于第一节点；所述上拉控制模块用于根据所述上一级扫描信号、所述低电平信号以及所述第一扫描控制信号，将所述第一扫描控制信号输出至所述第一节点；
    所述上拉模块接入高电平信号以及本级时钟信号，并电性连接于本级扫描信号输出端以及所述第一节点；所述上拉模块用于根据所述高电平信号、所述本级时钟信号以及所述第一节点的电位，在所述扫描信号输出端输出本级扫描信号；
    所述下拉模块接入下一级时钟信号、上一级时钟信号、第二扫描控制信号、下一级扫描信号、所述低电平信号以及所述高电平信号，并电性连接于第二节点以及所述第一节点；所述下拉模块用于根据所述下一级时钟信号、所述上一级时钟信号、所述第二扫描控制信号、所述下一级扫描信号、所述低电平信号以及所述高电平信号，下拉所述第一节点的电位以及拉高所述第二节点的电位；
    所述下拉维持模块接入下拉维持控制信号以及所述低电平信号，并电性连接于所述第一节点、第二节点以及所述本级扫描信号输出端；所述下拉维持模块用于根据所述下拉维持控制信号、所述低电平信号以及所述第二节点的电位，维持所述第一节点的电位以及所述本级扫描信号输出端的电位；
    所述重置模块接入第一功能控制信号、第二功能控制信号以及所述高电平信号，并电性连接于所述本级扫描信号输出端；所述重置模块用于根据所述第一功能控制信号、所述第二功能控制信号以及所述高电平信号，重置所述扫描信号输出端的电位。
  18. 根据权利要求17所述的显示面板，其中，所述上拉控制模块包括第三晶体管以及第一电容；
    所述第三晶体管的栅极电性连接于所述上一级扫描信号，所述第三晶体管的源极电性连接于所述第一扫描控制信号，所述第三晶体管的漏极电性连接于所述第一节点；
    所述第一电容的一端电性连接于所述第一节点，所述第一电容的另一端电性连接于所述低电平信号。
  19. 根据权利要求17所述的显示面板，其中，所述上拉模块包括第六晶体管以及第八晶体管；
    所述第六晶体管的栅极电性连接于所述高电平信号，所述第六晶体管的源极电性连接于所述第一节点，所述第六晶体管的漏极电性连接于第三节点；
    所述第八晶体管的栅极电性连接于所述第三节点，所述第八晶体管的源极电性连接于所述本级时钟信号，所述第八晶体管的漏极电性连接于所述本级扫描信号输出端。
  20. 根据权利要求19所述的显示面板，其中，当所述第八晶体管打开时，所述第三节点的电位大于所述第一节点的电位。
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