WO2021235721A1 - 세라믹 회로 기판의 제조방법 - Google Patents

세라믹 회로 기판의 제조방법 Download PDF

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Publication number
WO2021235721A1
WO2021235721A1 PCT/KR2021/005346 KR2021005346W WO2021235721A1 WO 2021235721 A1 WO2021235721 A1 WO 2021235721A1 KR 2021005346 W KR2021005346 W KR 2021005346W WO 2021235721 A1 WO2021235721 A1 WO 2021235721A1
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Prior art keywords
layer
copper
warpage
paste
circuit board
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PCT/KR2021/005346
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English (en)
French (fr)
Korean (ko)
Inventor
김민수
배일석
박진수
Original Assignee
주식회사 코멧네트워크
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Priority to CN202180035176.9A priority Critical patent/CN115606322A/zh
Publication of WO2021235721A1 publication Critical patent/WO2021235721A1/ko

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
    • H05K3/1283—After-treatment of the printed patterns, e.g. sintering or curing methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern

Definitions

  • the present invention relates to a method of manufacturing a ceramic circuit board, and more particularly, to a method of manufacturing a ceramic circuit board used as a substrate for a power semiconductor.
  • Power semiconductors which are widely used in mobiles, home appliances, and automobiles, play a role in converting, processing, and controlling power.
  • substrates on which they are mounted include Al 2 O 3 , AlN, Zirconia Toughened Alumina (ZTA), Si 3 N 4 , etc.
  • a substrate made of a ceramic material is used. Ceramics such as Al 2 O 3 , AlN, ZTA, and Si 3 N 4 have high insulation, mechanical strength, and relatively high heat dissipation performance, so they are suitable as substrates for high-power power semiconductors.
  • the ceramic circuit board should have a conductive pattern formed on the ceramic substrate. As the conductive pattern, an Al or Cu pattern is mainly used.
  • DBC Direct Bonded Copper
  • AMB Active Metal Brazing Copper
  • DPC Direct Plating Copper
  • DBC technology is a method of manufacturing a ceramic circuit board by bonding copper foil to one or both sides of a ceramic through a high-temperature oxidation process and then patterning the copper foil.
  • a copper-oxygen process eutectic is used to bond the substrate and the copper foil. Bonding is performed in a nitrogen atmosphere containing about 30 ppm oxygen at a temperature of 1083° C. or less, which is the melting point of copper.
  • the DBC method uses an etching process to form a bonded copper foil in a uniform pattern. After etching, Ni, Ag and Au are plated on the surface of the Cu pattern.
  • DBC technology has the advantage of good mechanical strength and adhesion.
  • a pattern that can be formed through etching is limited, and pores exist on the junction surface where copper oxide is not generated, thereby reducing stability to thermal cycles.
  • AMB technology joins ceramic and copper foil by sandwiching an active metal alloy whose melting point is lowered by adding Cu, Ag, etc. to a high-melting-point metal (Ti, Zr, Hf, etc.) that is active against oxygen between the ceramic and copper foil interface.
  • the Cu pattern after bonding is formed by etching copper foil like DBC.
  • DPC technology is a method of manufacturing a ceramic circuit board using a thin film process, an etching process, and a plating process. After depositing a seed layer with Ti, TiW, or the like, photoresist (PR) is applied, patterning is performed, and then a Cu layer is formed through Cu plating. The thickness of the Cu layer is limited to about 150 ⁇ m.
  • Patent Document 1 Korean Patent No. 0477866
  • Patent Document 2 Korea Patent Publication No. 2014-0127228
  • Patent Document 3 Korean Patent No. 1393760
  • Patent Document 4 Korea Patent Publication No. 2014-0095083
  • An object of the present invention is to provide a method of manufacturing a ceramic circuit board capable of forming a three-dimensional pattern on a ceramic substrate to be able to cope with various types of semiconductor devices mounted on the substrate.
  • Another object of the present invention is to provide a method of manufacturing a ceramic circuit board capable of improving durability against thermal cycles.
  • Another object of the present invention is to provide a method of manufacturing a ceramic circuit board capable of improving electrical conductivity and thermal conductivity of a copper pattern.
  • Another object of the present invention is to provide a method of manufacturing a ceramic circuit board capable of improving the surface roughness of a pattern while minimizing a difference between a pattern width on a side in contact with a ceramic substrate and a pattern width on an upper portion of the pattern.
  • Another object of the present invention is to provide a method of manufacturing a ceramic circuit board that minimizes bending of the ceramic substrate in the process of forming a copper pattern.
  • the present invention provides a method for manufacturing a ceramic circuit board in which a copper pattern is formed by printing a copper paste layer on a ceramic substrate, the ceramic substrate having a first surface and a second surface parallel to the first surface and preparing; forming a plurality of copper layers on a first surface of the ceramic substrate, wherein the forming of the plurality of copper layers includes printing a bonding paste on the first surface of the ceramic substrate and drying the bonding paste layer forming a first copper layer by pressing and sintering the dried bonding paste layer; printing a lamination paste on the first copper layer and drying to form a lamination paste layer; There is provided a method of manufacturing a ceramic circuit board comprising the step of forming a second copper layer by pressing and sintering the laminated paste layer.
  • the forming of the plurality of copper layers does not include a glass frit on the second copper layer, and includes copper oxide (Cu 2 O) particles and fine copper particles having an average particle diameter of 1 to 5 ⁇ m. It provides a method of manufacturing a ceramic circuit board, characterized in that it further comprises the step of forming a third copper layer by drying and sintering after printing the surface layer paste having a shrinkage ratio of 10% to 15% containing 60% by weight.
  • the method further includes forming a plurality of anti-warpage layers on the second surface of the ceramic substrate, wherein in the forming of the plurality of anti-warpage layers, the thickness of the plurality of anti-warpage layers is determined by the volume of the copper layers. It provides a method of manufacturing a ceramic circuit board, characterized in that the ratio of the sum of the sum and the sum of the volumes of the anti-warpage layers is adjusted to be 0.9 to 1.1.
  • the forming of the plurality of anti-warpage layers includes printing a bonding paste on the second surface, drying and sintering to form a first anti-warpage layer, and applying a lamination paste on the first anti-warpage layer. and drying and sintering after printing to form a second anti-warpage layer, wherein the thickness of the first anti-warpage layer and the thickness of the second anti-warpage layer are the thicknesses of the first copper layer and the second copper layer. It provides a method of manufacturing a ceramic circuit board, characterized in that the ratio of the sum of the volumes and the sum of the volumes of the first anti-warping layer and the second anti-warping layer is adjusted to be 0.9 to 1.1.
  • the thickness of the first anti-warpage layer is adjusted so that the ratio of the volume of the first copper layer to the volume of the first anti-warpage layer is 0.9 to 1.1
  • the thickness of the second anti-warpage layer is the second copper It provides a method of manufacturing a ceramic circuit board, characterized in that the ratio of the volume of the layer to the volume of the second anti-warpage layer is adjusted to be 0.9 to 1.1.
  • the thickness of the anti-warping layer and the thickness of the third anti-warpage layer are the sum of the volumes of the first copper layer, the second copper layer and the third copper layer and the first anti-warpage layer, the second anti-warpage layer and It provides a method of manufacturing a ceramic circuit board, characterized in that the ratio of the sum of the volumes of the third anti-warpage layer is adjusted to be 0.9 to 1.1.
  • the thickness of the first anti-warpage layer is adjusted so that the volume ratio of the first copper layer and the first anti-warpage layer is 0.9 to 1.1
  • the thickness of the second anti-warpage layer is the second copper layer and the The volume ratio of the second anti-warpage layer is adjusted to 0.9 to 1.1
  • the thickness of the third anti-warpage layer is adjusted so that the volume ratio of the third copper layer and the third anti-warpage layer is 0.9 to 1.1
  • the step of printing a lamination paste on the third copper layer, drying and sintering to form a fourth copper layer, and printing the surface layer paste on the fourth copper layer, drying and sintering to form a fifth copper layer It provides a method of manufacturing a ceramic circuit board, characterized in that it further comprises the step of forming.
  • the bonding paste provides a method of manufacturing a ceramic circuit board, characterized in that the shrinkage rate is 3% or less, including glass frit, inorganic particles, copper oxide particles, and copper particles.
  • the lamination paste does not include a glass frit, and provides a method of manufacturing a ceramic circuit board, characterized in that the shrinkage ratio including inorganic particles and copper particles is 3% to 9%.
  • the inorganic particles Al 2 O 3 , CaO, ZrO 2 Provides a method of manufacturing a ceramic circuit board, characterized in that it comprises at least one powder selected from the powder.
  • the method of manufacturing a ceramic circuit board according to the present invention has an advantage in that a three-dimensional pattern can be formed on the ceramic substrate so as to correspond to various types of semiconductor devices mounted on the substrate.
  • the ceramic circuit board according to the present invention has an advantage in that durability against thermal cycles is improved.
  • the ceramic circuit board according to the present invention has improved electrical conductivity and thermal conductivity of the copper pattern.
  • the method of manufacturing a ceramic circuit board according to some embodiments of the present invention has the advantage of improving the surface roughness of the pattern while minimizing the difference between the pattern width on the side in contact with the ceramic substrate and the pattern width on the top of the pattern.
  • the method of manufacturing a ceramic circuit board according to some embodiments of the present invention has an advantage in that the bending of the ceramic substrate can be minimized in the process of forming the copper pattern layer.
  • FIG. 1 is a conceptual diagram of a ceramic circuit board according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of a method of manufacturing a ceramic circuit board according to an embodiment of the present invention.
  • FIG. 3 is a flow chart of the steps of forming a first copper layer.
  • FIG. 4 is a conceptual diagram of a ceramic circuit board according to another embodiment of the present invention.
  • 5 to 8 are conceptual views of a ceramic circuit board according to still other embodiments of the present invention.
  • a ceramic circuit board 100 according to an embodiment of the present invention has a first surface (top surface in FIG. 1 ) and a second surface (bottom surface in FIG. 1 ) parallel to the first surface.
  • the ceramic substrate 10 includes a conductive pattern 20 including a plurality of copper layers formed on the first surface of the ceramic substrate 10 and a plurality of anti-warpage layers 30 formed on the second surface of the ceramic substrate.
  • the ceramic substrate 10 is, for example, Al 2 O 3 , AlN, ZTA, Si 3 N 4 , etc.
  • the substrate may be made of a ceramic material.
  • the conductive pattern 20 includes a first copper layer 21 , a second copper layer 22 , and a third copper layer 23 sequentially formed on the first surface.
  • the first copper layer 21 includes a glass component
  • the second copper layer 22 and the third copper layer 23 do not include a glass component.
  • the anti-warpage layers 30 include a first anti-warpage layer 31 , a second anti-warpage layer 32 and a third anti-warpage layer 33 sequentially formed on the second surface.
  • the warpage prevention layers 30 serve to prevent the ceramic substrate 10 from being bent during a sintering process to form the conductive pattern 20 .
  • the first copper layer 21 and the first anti-warpage layer 31 are made of the same material
  • the second copper layer 22 and the second anti-warpage layer 32 are made of the same material
  • the third copper layer (23) may be made of the same material as the third anti-warpage layer (33).
  • the thickness of the plurality of anti-warpage layers 30 is adjusted such that a ratio of the sum of the volumes of the copper layers 21 , 22 , and 23 to the sum of the volumes of the anti-warpage layers 30 is 0.9 to 1.1.
  • the volume ratio of the layers corresponding to each other may be adjusted to be 0.9 to 1.1. That is, in the embodiment shown in FIG. 1 , the volume ratio of the first copper layer 21 and the first anti-warpage layer 31 is 0.9 to 1.1, and the second copper layer 22 and the second anti-warpage layer 32 .
  • the volume ratio of the third copper layer 23 and the third anti-warpage layer 33 may also be 0.9 to 1.1.
  • FIG. 2 is a flowchart of a method of manufacturing a ceramic circuit board according to an embodiment of the present invention.
  • a method of manufacturing the ceramic circuit board 100 shown in FIG. 1 will be described with reference to FIG. 2 .
  • the method of manufacturing a ceramic circuit board 100 includes a step ( S1 ) of preparing the ceramic substrate 10 , and a first surface of the ceramic substrate 10 .
  • step S1 of preparing the ceramic substrate 10 will be described.
  • the ceramic substrate 10 is made of Al 2 O 3 , AlN, Zirconia Toughened Alumina (ZTA), Si 3 N 4 , or the like.
  • the substrate may be made of a ceramic material.
  • the ceramic substrate 10 has a first surface and a second surface parallel to the first surface.
  • step S2 of forming the first copper layer 21 will be described.
  • the first copper layer 21 is formed on the first surface of the ceramic substrate 10 .
  • the first copper layer 21 may be formed directly on the first surface of the ceramic substrate 10 .
  • the step of forming the first copper layer 21 includes printing the bonding paste ( S21 ), drying the bonding paste layer ( S22 ), and pressing the dried bonding paste layer. (S23) and sintering the bonding paste layer (S24).
  • the bonding paste can be printed by a screen printing method.
  • the bonding paste includes glass frit, inorganic particles, copper oxide particles, copper particles, a solvent and a binder.
  • the glass frit is a sintering aid that helps sinter the copper (Cu) particles, and serves to bond the first copper layer 21 and the ceramic substrate 10 .
  • the inorganic particles may include at least one powder selected from Al 2 O 3 , CaO, and ZrO 2 powders. Inorganic particles are used to lower the shrinkage of the bonding paste.
  • the shrinkage rate of the paste is measured by printing the paste in the form of a disk, drying and sintering, and comparing the diameter of the disk after drying and sintering.
  • the shrinkage rate of the bonding paste is preferably 3% or less.
  • Copper oxide (CuO, Cu 2 O) particles are added to supplement bonding properties with the ceramic substrate 10 .
  • copper oxide reacts with alumina to form CuAlO 2 , CuAl 2 O 4 , thereby improving bonding properties.
  • the bonding paste layer is dried to remove the solvent.
  • the dried bonding paste layer is compressed to reduce the height difference between the bonding paste layers.
  • the boundary of the bonding paste layer has a higher viscosity than the center of the paste because the flow rate of the paste decreases. Therefore, the boundary of the dried bonding paste layer after printing is thicker than the central portion.
  • the heat treatment profile for sintering the bonding paste layer includes a bake out step of supplying a small amount of water vapor or oxygen to a nitrogen atmosphere in order to remove the binder, a step of liquid phase sintering of copper (Cu) particles, and a step of cooling.
  • the liquid phase sintering of copper (Cu) particles is preferably performed in a nitrogen atmosphere in order to prevent oxidation of copper (Cu). In this case, a small amount of oxygen may be supplied so that the glass frit is easily wetted on the copper (Cu) particles.
  • the bake-out step may be performed at about 300 to 500°C, and the liquid-phase sintering may be performed at about 700 to 900°C.
  • the total sintering time is about 50 to 90 minutes, and may be performed in a continuous heat treatment furnace such as a muffle type heat treatment furnace or a batch type heat treatment furnace such as a box oven.
  • the first anti-warpage layer 31 is formed on the second surface of the ceramic substrate 10 .
  • the first anti-warpage layer 31 may be formed directly on the second surface of the ceramic substrate 10 .
  • the first anti-warpage layer 31, like the first copper layer 21, is formed through the steps of printing the bonding paste, drying the bonding paste layer, pressing the dried bonding paste layer, and sintering the bonding paste layer. formed through steps.
  • the first anti-warpage layer 31 may be formed to cover the entire second surface of the ceramic substrate 10 .
  • the first anti-warpage layer 31 is formed together with the first copper layer 21 . After each bonding paste is printed on the first and second surfaces of the ceramic substrate 10, the bonding paste layers on both sides are dried at once, pressed and sintered at once to form the first anti-warpage layer 31 and the cuprous copper Layer 21 is formed at a time.
  • a second copper layer 22 is formed over the first copper layer 21 .
  • the second copper layer 22 is formed by printing the lamination paste and then drying, pressing and sintering.
  • the second copper layer 22 serves to increase the thickness of the conductive pattern 20 .
  • the lamination paste contains inorganic particles, copper particles, a solvent and a binder.
  • the inorganic particles may include at least one selected from among Al 2 O 3 , CaO, and ZrO 2 particles. Inorganic particles are used to lower the shrinkage of the bonding paste.
  • Lamination paste does not contain glass frit unlike bonding paste. Lamination pastes have a higher shrinkage rate than bonding pastes. It is preferable that the shrinkage ratio of the lamination paste is 3% to 9%.
  • Printing may be performed by a screen printing method. After printing, the lamination paste layer is dried to remove the solvent. Then, the dried lamination paste layer is compressed to reduce the height difference between the bonding paste layers. Next, by heat-treating the ceramic substrate 10 on which the first copper layer 21 and the pressed lamination paste layer are formed, the lamination paste layer is sintered to form the second copper layer 22 . Like the heat treatment of the bonding paste layer, the heat treatment may be performed in a nitrogen atmosphere containing a small amount of oxygen.
  • the step of forming the second copper layer 22 may be performed multiple times, or only the printing, drying, and pressing processes may be performed multiple times.
  • step (S5) of forming the second warpage prevention layer 32 will be described.
  • the second anti-warpage layer 32 is formed over the first anti-warpage layer 31 .
  • the second anti-warpage layer 32 like the second copper layer 22, is formed through the steps of printing the lamination paste, drying the lamination paste layer, pressing the dried lamination paste layer, and sintering the lamination paste layer. formed through steps.
  • the second anti-warpage layer 32 is formed together with the second copper layer 22 .
  • a third copper layer 23 is formed over the second copper layer 22 .
  • the third copper layer 23 is formed by printing the surface layer paste and then drying, pressing and sintering.
  • the third copper layer 23 serves to provide a dense surface for easy plating.
  • the surface layer paste does not contain a glass frit, but contains copper oxide (Cu2O) particles, copper particles, a solvent, and a binder.
  • the copper particles include fine copper particles having an average particle diameter of 1 to 5 ⁇ m.
  • the fine copper particles are contained in an amount of 5 to 60% by weight in the surface layer paste.
  • the fine copper particles serve to increase the density of the third copper layer 23 .
  • Copper oxide (Cu 2 O) particles may form a process liquid phase during the sintering process.
  • the surface layer paste preferably has a shrinkage ratio of 10% to 15%.
  • Printing may be performed by a screen printing method. After printing, the surface paste layer is dried to remove the solvent. And by compressing the dried surface paste layer, the height difference between the surface paste layer is reduced. Next, the third copper layer 23 is formed by heat-treating the ceramic substrate 10 on which the first copper layer 21 , the second copper layer 22 and the pressed surface paste layer are formed to sinter the surface paste layer. do. Like the heat treatment of the bonding paste layer, the heat treatment may be performed in a nitrogen atmosphere containing a small amount of oxygen.
  • step (S7) of forming the third anti-warpage layer 33 will be described.
  • the third anti-warpage layer 33 is formed over the second anti-warpage layer 32 .
  • the third anti-warpage layer 33 is formed by printing the surface paste, drying the surface paste layer, pressing the dried surface paste layer, and sintering the surface paste layer. formed through steps.
  • the third anti-warpage layer 33 is formed together with the third copper layer 23 .
  • the thickness of the first anti-warpage layer, the thickness of the second anti-warpage layer, and the thickness of the third anti-warpage layer are the first copper layer, the second The ratio of the sum of the volumes of the copper layer and the third copper layer to the sum of the volumes of the first, second, and third anti-warpage layers is adjusted to be 0.9 to 1.1.
  • the volume ratio of the layers corresponding to each other may be adjusted to be 0.9 to 1.1. That is, the thickness of the first anti-warpage layer 31 is adjusted so that the volume ratio of the first copper layer 21 and the first anti-warpage layer 31 is 0.9 to 1.1, and the thickness of the second anti-warpage layer 32 is adjusted so that the volume ratio of the second copper layer 22 and the second anti-warpage layer 32 is 0.9 to 1.1, and the thickness of the third anti-warpage layer 33 is the third copper layer 23 and the third warpage
  • the volume ratio of the barrier layer 33 may be adjusted to be 0.9 to 1.1.
  • FIG. 4 is a conceptual diagram of a ceramic circuit board according to another embodiment of the present invention.
  • the ceramic circuit board 200 according to the present embodiment is different from the embodiment shown in FIG. 1 in that the thickness of some conductive patterns 120 is thicker than the thickness of other patterns 20 .
  • the present embodiment has an advantage in that a separate spacer is not required to mount semiconductor devices having different heights.
  • a fourth copper layer 122 and a fifth copper layer 123 are formed on the third copper layer 23 .
  • the fourth copper layer 122 may be formed by printing a lamination paste on the third copper layer 23 and then drying, pressing, and sintering, and the fifth copper layer 123 is formed on the fourth copper layer 122 . After printing the surface layer paste, it can be formed by drying, pressing and sintering.
  • the fourth copper layer 122 may be made of the same material as the second copper layer 22 .
  • the fifth copper layer 123 may be made of the same material as the third copper layer 23 .
  • the fourth anti-warpage layer 132 and the fifth anti-warpage layer 133 are formed on the third anti-warpage layer 33 .
  • the fourth anti-warping layer 132 may be made of the same material as the second copper layer 22
  • the fifth anti-warping layer 133 may be made of the same material as the third copper layer 23 .
  • the thickness of the plurality of anti-warpage layers 130 is adjusted such that a ratio of the sum of the volumes of the copper layers 20 and 120 to the sum of the volumes of the anti-warpage layers 130 is 0.9 to 1.1.
  • the fourth anti-warpage layer 132 is formed together with the fourth copper layer 122 .
  • the fifth anti-warpage layer 133 is formed together with the fifth copper layer 123 .
  • FIG. 5 is a conceptual diagram of a ceramic circuit board according to another embodiment of the present invention.
  • the embodiment shown in FIG. 5 is different from the embodiment shown in FIG. 1 in that there is no third copper layer.
  • the third copper layer may be omitted.
  • the ceramic circuit board 300 of the present embodiment may be manufactured by omitting the process of printing the surface layer paste.
  • FIG. 6 is a conceptual diagram of a ceramic circuit board according to another embodiment of the present invention.
  • the embodiment shown in FIG. 6 is different from the embodiment shown in FIG. 4 in that the fourth anti-warpage layer 132 and the fifth anti-warpage layer 133 are absent.
  • the thickness of the second anti-warping layer 232 and the third anti-warping layer 233 is the second anti-warping layer 32 and the third anti-warpage of the embodiment shown in FIG. 4 . It is also different from the embodiment shown in FIG. 4 in that it is slightly thicker than the thickness of the layer 33 .
  • the second anti-warpage layer 232 and the third anti-warpage layer ( By forming the thickness of 233 to be thicker by the thickness of the fourth anti-warpage layer 132 and the fifth anti-warpage layer 133 , the sum of the volumes of the copper layers 20 and 120 and the volume of the anti-warpage layers 230 . It is adjusted so that the ratio of the sum of is 0.9 to 1.1.
  • FIG. 7 and 8 are conceptual views of a ceramic circuit board according to still other embodiments of the present invention.
  • the embodiment shown in FIG. 7 is shown in FIG. 4 in that the fourth anti-warpage layer 332 and the fifth anti-warpage layer 333 are not formed on the entire surface of the ceramic substrate 10, but form a pattern. There is a difference from the embodiment.
  • the embodiment illustrated in FIG. 8 is different from the embodiment illustrated in FIG. 7 in that a sixth copper layer 222 and a seventh copper layer 223 are formed on a part of the fifth copper layer 123 .
  • a fourth anti-warpage layer 432 and a fifth anti-warpage layer 433 are provided in the embodiment shown in FIG. There is also a difference in that it is slightly thicker than that.
  • compression and sintering are not necessarily performed step by step. After several layers are stacked, pressing can be done at once, and sintering can be done at once. For example, after printing and drying the bonding paste, pressing after printing and drying the lamination paste thereon, printing and drying the surface layer face thereon, pressing again, and sintering may be performed at once. At which stage compression is performed and sintering is performed, it can be appropriately selected according to need.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
PCT/KR2021/005346 2020-05-19 2021-04-28 세라믹 회로 기판의 제조방법 WO2021235721A1 (ko)

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KR102212836B1 (ko) * 2020-05-19 2021-02-05 주식회사 코멧네트워크 세라믹 회로 기판의 제조방법

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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