WO2021232810A1 - 沟槽栅igbt器件及其制备方法 - Google Patents

沟槽栅igbt器件及其制备方法 Download PDF

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WO2021232810A1
WO2021232810A1 PCT/CN2020/140599 CN2020140599W WO2021232810A1 WO 2021232810 A1 WO2021232810 A1 WO 2021232810A1 CN 2020140599 W CN2020140599 W CN 2020140599W WO 2021232810 A1 WO2021232810 A1 WO 2021232810A1
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emitter
emission
area
layer
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French (fr)
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方冬
肖魁
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无锡华润上华科技有限公司
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0804—Emitter regions of bipolar transistors
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
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    • H01L29/66234—Bipolar junction transistors [BJT]
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention relates to the field of semiconductors, in particular to a trench gate IGBT device and a method for preparing the trench gate IGBT device.
  • trench gates are usually formed to improve chip integration and channel current density.
  • the trench gate is formed by opening a trench in the body region and filling the trench with a gate structure. After forming the trench gate, it is necessary to form two emitter regions of different conductivity types in the body region and form an emitter layer electrically connected to each emitter region on the body region.
  • the emitter layer needs to use conductive plugs to achieve electrical connection with the N-type emitter region and the P-type emitter region, and the conductive plugs need to occupy a certain device space, which limits the further increase of the trench gate density.
  • a trench gate IGBT device includes:
  • the drift zone has the first conductivity type
  • the first emitter region has the first conductivity type and is formed on the body region.
  • a plurality of trenches arranged side by side along a first direction are formed in the first emitter region, and each of the trenches sequentially penetrates the first The emission region and the body region extend to the drift region;
  • the second emission region has a second conductivity type, is formed in a partial area of the first emission region and penetrates the first emission region to be in contact with the body region, the first emission region and the second emission region
  • the two emission regions are distributed along the second direction.
  • the first emission region and the second emission region located between two adjacent trenches are in contact with the side surfaces of the trenches adjacent on both sides. The two directions are different from the first direction;
  • a gate conductive layer and a dielectric structure the dielectric structure includes a first dielectric layer and a second dielectric layer, the first dielectric layer is formed on the inner wall of the trench, and the gate conductive layer is formed on the first dielectric layer And fill in the trench, and the second dielectric layer is formed on the gate conductive layer; and
  • the emitter layer is formed on the first emitter region and the second emitter region, and the emitter layer is in contact with the first emitter region and the second emitter region and passes through the second dielectric layer.
  • the gate conductive layer is isolated.
  • a method for preparing a trench gate IGBT device includes:
  • drift region having the first conductivity type, wherein a plurality of trenches distributed side by side along the first direction are opened in the drift region;
  • the depth of the body region is smaller than the depth of the trench
  • a first emission region having a first conductivity type is formed on the surface layer of the body region and a second emission region having a second conductivity type is formed in a partial area of the first emission region.
  • the second emission area penetrates the first emission area and is in contact with the body area, and the first emission area and the second emission area are distributed along the second direction and are located in all areas between two adjacent trenches. Both the first emission area and the second emission area are in contact with the side surfaces of the trenches adjacent on both sides, and the second direction is different from the first direction; and
  • An emitter layer directly in contact with the first emission area and the second emission area is formed on the first emission area and the second emission area, and the emitter layer is connected to the first emission area and the second emission area through the second dielectric layer.
  • the gate conductive layer is isolated.
  • Fig. 1 is a schematic structural diagram of an exemplary trench gate IGBT device
  • Fig. 2a is a schematic structural diagram of a trench gate IGBT device without an emitter layer formed in an embodiment
  • FIG. 2b is a schematic diagram of the contact mode of the emitter layer with the first emitter region and the second emitter region in an embodiment
  • FIG. 3 is a schematic structural diagram of a trench gate IGBT device without an emitter layer in another embodiment
  • FIG. 4 is a schematic structural diagram of a trench gate IGBT device without an emitter layer formed in another embodiment
  • FIG. 5 is a schematic diagram of the distribution of the gate layer according to an embodiment
  • FIG. 6 is a flow chart of steps of a method for manufacturing a trench gate IGBT device according to an embodiment
  • FIG. 7a to 7f are structural schematic diagrams corresponding to the relevant steps of the trench gate IGBT device manufacturing method according to an embodiment.
  • Drift zone 100; body zone: 110; emission zone layer: 120; buffer zone: 130; collector zone: 140; first emission zone: 121; second emission zone: 122; gate conductive layer: 210; dielectric structure: 220; first dielectric layer: 221; second dielectric layer: 222; trench gate: 200; collector layer: 300; emitter layer: 400; active area: AA; peripheral area: W.
  • Figure 1 shows an exemplary trench gate IGBT device.
  • the body region 110' is located on the drift region 100', the drift region 100' is N-type, the body region 110' is P-type, and the P-type emitter region 122' and The N-type emitting area 121' is stacked on the body area 110'.
  • the trench gate 200' penetrates the N-type emitter region 121' and the body region 110' and extends into the drift region 100'.
  • the emitter layer 400' is formed above the N-type emitter region 121', and a conductive plug 410 that penetrates the N-type emitter region 121' and extends into the P-type emitter region 122' is formed between adjacent trench gates 200' '.
  • the emitter layer 400' is electrically connected to the P-type emitter region 122' and the N-type emitter region 121' through the conductive plug 410'.
  • the conductive plug 410' needs to be formed between the trench gates 200', the conductive plug 410' needs to occupy a certain space, which limits the further reduction of the spacing between the trench gates 200', which is not conducive to Improve trench gate density.
  • the trench gate IGBT device in this application includes a drift region 100, a body region 110, a first emitter region 121 and a second emitter region 122, a trench, a gate conductive layer 210, and a dielectric structure 220 , Emitter layer 400.
  • the drift region 100 has the first conductivity type. Specifically, the drift region 100 may be a wafer epitaxial layer of the first conductivity type. One surface defining the drift region 100 is the front side, and the side opposite to the front side of the drift region 100 is the back side.
  • the body region 110 has the second conductivity type and is formed on the front surface of the drift region 100.
  • the surface layer of the drift region 100 can be doped with the second conductivity type, so that the surface layer of the drift region 100 is converted from the first conductivity type to the second conductivity type, so that the surface layer of the drift region 100 is converted to have the second conductivity type. ⁇ 110 ⁇ The body area 110.
  • the first emission region 121 has the first conductivity type and is formed on the body region 110.
  • a plurality of trenches distributed side by side along the first direction are opened in the first emitter region 121, and each trench sequentially penetrates the first emitter region 121 and the body region 110 downwards and extends into the drift region 100.
  • the first direction is the X-axis direction shown in Figure 2a.
  • the second emitter region 122 has the second conductivity type and the doping concentration of the second emitter region 122 is higher than that of the body region 110.
  • the second emitter region 122 is formed in a part of the first emitter region 121 and penetrates the first emitter downward.
  • the area 121 is in contact with the body area 110.
  • the first emission area 121 and the second emission area 122 located between two adjacent trenches are distributed along the second direction.
  • the first emission area 121 and the second emission area located between the two adjacent trenches are connected to both sides
  • the side surfaces of adjacent trenches are in contact, that is, each trench has a side surface extending in the second direction, the first emission region 121 is sandwiched between the adjacent trenches, and the first emission region 121 is connected to the trenches on both sides, respectively.
  • the second emitter region 122 is also sandwiched between adjacent trenches, and the second emitter region 122 is in contact with the trenches on both sides, respectively.
  • the second direction is the Y-axis direction shown in FIG. 2a.
  • the second direction is different from the first direction, that is, the angle between the first direction and the second direction is greater than 0° and less than 180°.
  • the first direction and the second direction are perpendicular to each other.
  • the first emission area 121 and the second emission area 122 constitute the emission area layer 120.
  • the planes where the drift region 100, the body region 110, and the emission region layer 120 are located are all XY planes, and the drift region 100, the body region 110, and the emission region layer 120 are sequentially stacked along the Z axis direction.
  • the first emission area 121 and the second emission area 122 are distributed on the XY plane.
  • a first dielectric layer 221 is formed on the inner wall of the trench.
  • a gate conductive layer 210 is formed on the first dielectric layer 221 and filled in the trench.
  • a second dielectric layer 222 is formed on the gate conductive layer 210.
  • the layer 221 and the second dielectric layer 222 are connected to each other to form a dielectric structure 220 surrounding the gate conductive layer 210. It should be noted that all the dielectric layers formed on the inner wall of the trench are defined as the first dielectric layer 221.
  • the first dielectric layer 221 may include only one dielectric material or multiple dielectric materials, for example, located at different locations. The dielectric material of the first dielectric layer 221 at the position may be the same or different.
  • the second dielectric layer 222 may contain only one dielectric material or multiple dielectric materials, for example, those located at different positions.
  • the dielectric material of the second dielectric layer 222 may be the same or different.
  • the first dielectric layer 221 may specifically be silicon oxide, or may be other materials with a high dielectric constant.
  • the gate conductive layer 210 may be polysilicon, or other materials with good conductivity, such as metal.
  • the material of the second dielectric layer 222 may be the same as or different from the material of the first dielectric layer 221. Specifically, silicon nitride, silicon oxide, etc. may be used.
  • the emitter layer 400 is formed on the first emitter region 121 and the second emitter region 122, that is, the emitter layer 400 is formed on the emitter region layer 120, and the bottom surface of the emitter layer 400 is directly connected to the first emitter region 121 and the second emitter region.
  • the region 122 is in contact without forming a conductive plug, and the emitter layer 400 is electrically isolated from the gate conductive layer 210 by the second dielectric layer 222.
  • the above-mentioned first conductivity type is opposite to the second conductivity type.
  • the second conductivity type is P type
  • the first conductivity type is N type
  • the second conductivity type is P type.
  • the above-mentioned IGBT device further includes a gate layer (not shown in the figure), a collector region 140, and a collector layer 300 electrically connected to the collector region 140.
  • the gate layer is electrically connected to the gate conductive layer 210 in the trench gate 200 to control the switching of the device.
  • the collector region 140 has the second conductivity type, and the collector region 140 is usually formed on the back surface of the drift region 100.
  • a buffer zone 130 is further formed between the collector region 140 and the drift zone 100.
  • the buffer zone 130 has the first conductivity type and the doping concentration of the buffer zone 130 is higher than the doping concentration of the drift zone 100. .
  • the first emitter region 121, the second emitter region 122, the body region 110, the trench gate 200 and the drift region 100 form a MOS tube structure, and the body region 110, the drift region 100, the buffer zone 130 and the collector region 140 form a triode structure.
  • the trench gate 200 can control the on-off of the MOS structure, thereby controlling the on-off of the IGBT.
  • the trench penetrates the first emitter region 121, the body region 110 and extends into the drift region 100.
  • a first dielectric layer 221 is formed on the inner wall of the trench, and the trench is filled with the first dielectric layer.
  • the gate conductive layer 210 on the layer 221, the first dielectric layer 221 sandwiched between the gate conductive layer 210 and the inner wall of the trench is the gate dielectric layer, and the gate conductive layer 210 and the gate dielectric layer form the trench gate 200.
  • the gate 200 controls the on and off of the IGBT device.
  • the second emission area is located in the first emission area and penetrates the first emission area to contact the body area, that is, the first emission area 121 and
  • the second emitter region 122 is distributed in a plane parallel to the top surface of the body region 110.
  • the 121 is in contact with the second emitter region 122, and there is no need to provide a conductive plug, which saves the space occupied by the conductive plug, thereby increasing the density of the trench gate 200 and effectively reducing the device area.
  • the gate conductive layer 210 and the emitter layer 400 can be isolated by the second dielectric layer 222.
  • the first emission area 121 and the second emission area 122 are distributed along the side surface of the trench in the second direction. Compared with the distribution of the first emission area 121 and the second emission area 122 along the first direction, it can be reduced.
  • the spacing between the trenches can further increase the density of the trench gate 200, thereby increasing the channel current density.
  • the emitter layer 400 is directly connected to the first emitter region 121 and the second emitter region.
  • 122 contacts can improve the electrical output capacity of the device, reduce power loss, and is more conducive to heat dissipation of the device.
  • the top surface of the first emission area 121 is flush with the top surface of the second emission area 122
  • the bottom surface of the first emission area 121 is flush with the bottom surface of the second emission area 122
  • the first emission area 121 is flush with the bottom surface of the second emission area 122.
  • the thickness of the second emission region 122 is the same or different.
  • the first emitter region 121 and the second emitter region 122 are both formed by doping the surface layer of the body region 110, and the thickness of the first emitter region 121 and the second emitter region 122 are the same, that is, The implantation depth of the first emission region 121 and the second emission region 122 are the same, which can minimize the phenomenon that the first emission region 121 diffuses below the second emission region 122 or the second emission region 122 diffuses below the first emission region 121 , Making the structure more stable.
  • the implantation depth of the first emitter region 121 and the second emitter region 122 can also be different, and the implantation depth of the two emitter regions can be flexibly adjusted only by adjusting the doping conditions, so as to ensure the second emitter region 122 Just contact the body area 110.
  • the implantation depth of the first emission region 121 and the second emission region 122 is greater than the thickness of the second dielectric layer 222, that is, the first emission region 121 and the second emission region 122 are both connected to the area below the second dielectric layer 222.
  • the gate dielectric layer is in contact to ensure that a complete current path can be formed between the first emitter region 121, the body region 110 and the drift region 100.
  • the gate conductive layer 210 does not fill the trench, that is, the top trench is not filled with the gate conductive layer 210, the top surface of the gate conductive layer 210 is lower than the top surface of the emitter layer 120, and the second dielectric The layer 222 is filled in the trench above the gate conductive layer 210. Further, the second dielectric layer 222 just fills the trench, and the top surface of the second dielectric layer 222 is flush with the top surface of the trench. Furthermore, the top surface of the second dielectric layer 222, the top surface of the first emission region 121, and the top surface of the second emission region 122 are flush. In this embodiment, the top surfaces of the second dielectric layer 222, the first emission region 121, and the second emission region 122 are flush, which can ensure that the surface of the emitter layer 400 is flat.
  • the size of the first emission area 121 and the second emission area 122 can be flexibly set as required. Specifically, the coverage area of the first emitter region 121 on the body region 110 is larger than the coverage area of the second emitter region 122 on the body region 110, thereby increasing the contact area between the first emitter region 121 and the trench gate 200, thereby Improve the density of conductive channels.
  • the second direction is the Y-axis direction
  • a plurality of second emission regions 122 are formed in the first emission region 121 formed between adjacent trenches, that is, in the second direction, on the same side surface as the trench
  • the total number of contacting first emission regions 121 and second emission regions 122 is greater than or equal to three, and the first emission regions 121 and second emission regions 122 are alternately distributed in the second direction, thereby improving the power transmission of the emitter layer 400 Uniformity.
  • the first direction is the X-axis direction
  • the second direction is the Y-axis direction.
  • the IGBT device has a plurality of trenches arranged side by side along the first direction to form a plurality of When the trench gates 200 are arranged side by side in one direction, the first emission area 121 and the second emission area 122 that are distributed along the second direction are arranged between adjacent trenches.
  • the first direction is the X-axis direction
  • the second direction is the Y-axis direction. It is also possible to provide the first direction that is connected and distributed along the second direction between some of the adjacent grooves.
  • the first direction is the X-axis direction
  • the second direction is the Y-axis direction.
  • a plurality of grooves are spaced along the X-axis direction.
  • the grooves have side surfaces extending along the Y-axis direction.
  • the distribution of the first emission area 121 and the second emission area 122 is the same, that is, the first emission area 121 and the second emission area 122 are arranged alternately in the Y-axis direction, and are located on the same straight line in the X-axis direction.
  • the types of the regions are the same.
  • the emitter regions on both sides of the trench are both the first emitter region 121 or the second emitter region 122.
  • the types of emitters on both sides of the trench are the same, that is, the types of emitters arranged side by side in the X-axis direction are the same, which can reduce the difficulty of the process, for example, by When forming the first emitter region 121 or the second emitter region 122 by the doping process, a mask layer needs to be formed on the emitter region layer 120. Since the types of emitter regions in the X-axis direction are the same, the opening of the mask layer is a one-dimensional stripe. Compared with the different types of emission regions in the Y-axis direction and the X-axis direction, a two-dimensional grid-shaped mask needs to be used for the distribution. The mask alignment process required in this embodiment requires lower requirements.
  • the first direction is the X-axis direction
  • the second direction is the Y-axis direction.
  • the second emission regions 122 are provided in the first emission regions 121 on both sides of the trench, and the first emission regions 122 are provided on both sides of the trench.
  • the arrangement of zones is different.
  • the same trench is defined to have opposite first and second side surfaces.
  • the first emitter region 121 contacting the first side surface is opposite to the first side surface.
  • the second emitter region 122 contacting with two side surfaces, and the second emitter region 122 contacting with the first side surface is opposite to the first emitter region 121 contacting with the second side surface.
  • the first emission areas 121 and the second emission areas 122 are alternately distributed in the second direction, and the first emission areas 121 and the second emission areas 122 are also alternately distributed in the first direction.
  • the first emission area 121 and the second emission area 122 are evenly distributed on the emission area layer 120, so that the current transmission is more uniform, thereby improving the stability of the device.
  • the above-mentioned groove is elongated, the opening of the groove has a long side and a short side, the long side of the groove extends along the Y-axis direction, and the short side of the groove extends along the X-axis direction.
  • a stripe-type trench is provided to form a stripe-type trench gate 200, which can increase the density of the trench gate 200.
  • the above-mentioned IGBT device further includes a gate layer electrically connected to the gate conductive layer 210.
  • the trench gate IGBT device has an active area AA and a peripheral area W surrounding the active area AA.
  • the emitter layer 120 is formed in the active area AA.
  • the trench is An elongated trench extending along the Y-axis direction, and the trench opening along the Y-axis direction extends from the active area AA to the peripheral area W, the emitter layer 400 covers the active area AA, and the gate layer is located in the peripheral area W and It is electrically connected to the gate conductive layer 210 located in the trench in the peripheral region W.
  • the gate layer can be drawn in the peripheral area W, and the emitter layer 400 covers the active area AA, so that the gate layer and the emitter layer 400 can be distributed through a simple process In different regions.
  • the first emitter area 121 and the second emitter area 122 are distributed in the XY plane.
  • the emitter layer 400 is directly formed on the emitter region 121 and the second emitter region 122, so that the emitter layer 400 can directly contact the first emitter region 121 and the second emitter region 122, and there is no need to provide conductive plugs, which saves the traditional
  • the space occupied by the conductive plugs can increase the density of the trench gate 200. Since the second dielectric layer 222 is formed on the gate conductive layer 210, the gate conductive layer 210 and the emitter layer 400 can be isolated by the second dielectric layer 222.
  • the distribution of the first emission area 121 and the second emission area 122 along the second direction in the present application can be The spacing between adjacent trenches is reduced, thereby increasing the trench gate 200 density.
  • the present application also relates to a method for preparing a trench gate IGBT device, which is used for preparing the above-mentioned trench gate IGBT device.
  • Fig. 6 shows a step flow chart of a method for manufacturing a trench gate IGBT device.
  • the manufacturing method includes:
  • Step S100 forming a drift zone having a first conductivity type, and a plurality of trenches distributed side by side along a first direction are opened in the drift zone.
  • a drift region 100 is formed on a semiconductor substrate.
  • the drift region 100 has a first conductivity type.
  • the drift region 100 is provided with a plurality of trenches distributed side by side along the first direction.
  • the first direction is the X-axis direction
  • the opening of the groove has long sides and short sides
  • the long side of the groove extends along the Y-axis direction
  • the short side of the groove extends along the X-axis direction
  • multiple grooves are spaced and parallel along the X-axis direction set up.
  • Step S200 forming a first dielectric layer on the inner wall of the trench and filling the gate conductive layer, and forming a second dielectric layer on the gate conductive layer.
  • a first dielectric layer 221 is formed on the inner wall of the trench.
  • the first dielectric layer 221 may be deposited on the inner wall of the trench by a deposition process, and the deposition process may be a chemical vapor deposition process or an atomic layer deposition process.
  • an oxide layer can also be grown on the inner wall of the trench as the first dielectric layer 221 by a thermal oxidation process.
  • a gate conductive layer 210 is filled in the trench.
  • the gate conductive layer 210 is filled in the trench by a deposition process.
  • a second dielectric layer 222 is formed on the gate conductive layer 210.
  • an oxide layer can be grown on the gate conductive layer 210 as the second dielectric layer 222 through a thermal oxidation process.
  • a second dielectric layer 222 may be deposited, and the second dielectric layer 222 may be selectively removed, leaving only the second dielectric layer 222 on the gate conductive layer 210.
  • the gate conductive layer 210 fills the trench, and the second dielectric layer 222 is located above the trench.
  • the gate conductive layer 210 is etched back to reduce the height of the gate conductive layer 210, and then a second layer is deposited in the trench above the gate conductive layer 210. Dielectric layer 222, and make the top surface of the second dielectric layer 222 flush with the top surface of the trench.
  • Step S300 forming a body region with the second conductivity type on the surface layer of the drift region through an ion implantation process, and the depth of the body region is smaller than the depth of the trench.
  • the surface layer of the drift region 100 is implanted with doped ions of the second conductivity type through an ion implantation process, and the implantation depth is less than the depth of the bottom of the trench, so that the surface layer of the drift region 100 is transformed into a second conductivity type.
  • the body region 110 forms a body region 110 on the drift region 100.
  • the depth of the body region 110 is less than the depth of the bottom of the trench. At this time, the trench penetrates the body region 110 and extends into the drift region 100.
  • Step S400 forming a first emission region with a first conductivity type on the surface layer of the body region and a second emission region with a second conductivity type in a partial area of the first emission region through an ion implantation process,
  • the second emission area penetrates the first emission area and is in contact with the body area, and the first emission area and the second emission area are distributed along the second direction and are located between two adjacent trenches. Both the first emission region and the second emission region between are in contact with the side surfaces of the trenches adjacent to both sides.
  • the second direction is the Y-axis direction.
  • Doping ions of the first conductivity type and doping ions of the second conductivity type are respectively implanted into different regions of the surface layer of the body region 110, so as to form first conductivity types of the first conductivity type on the surface layers of different regions of the body region 110.
  • the emission area 121 and the second emission area 122 having the second conductivity type that is, the first emission area 121 and the second emission area 122 both extend from the upper surface of the body area 110 to the inside of the body area 110, and the first emission area 121 and The second emission regions 122 are distributed along the second direction.
  • the first emission regions 121 and the second emission regions 122 located between two adjacent trenches are in contact with the side surfaces of the trenches adjacent on both sides.
  • the first mask layer can be formed first, the surface area of the body region 110 where the first emitter region 121 is to be formed is exposed through the opening of the first mask layer, and the surface layer of the body region 110 is implanted with the first conductivity type dopant Ion, the surface layer of the body region 110 of the exposed area is transformed into the first emission region 121; the first mask layer is removed, and a second mask layer is formed, the second mask layer covers the first emission region 121, and the second mask layer
  • the opening of the film exposes the surface layer region of the body region 110 where the second emitter region 122 is to be formed. Doping ions with the second conductivity type into the surface layer of the body region 110 transforms the surface layer of the body region 110 in another exposed region As a second launch area 122.
  • a backside process is performed. As shown in FIG. In one embodiment, a buffer zone 130 of the first conductivity type is formed between the drift zone 100 and the collector zone 140, and the doping concentration of the buffer zone 130 is higher than that of the drift zone 100. Miscellaneous concentration.
  • Step S500 forming an emitter layer directly in contact with the first emitter region and the second emitter region on the first emitter region and the second emitter region, and the emitter layer passes through the second emitter layer.
  • the dielectric layer is isolated from the gate conductive layer.
  • the emitter layer 400 is deposited on the first emitter region 121 and the second emitter region 122 by a deposition process, the emitter layer 400 is in direct contact with the first emitter region 121 and the second emitter region 122, and the first emitter layer The emitter layer 400 is isolated from the gate conductive structure by the second dielectric layer 222. It can be understood that a collector layer 300 is also deposited on the collector region 140 on the back.
  • the first emitter region 121 and the second emitter region 122 are formed on the surface layer of the body region 110. At this time, it is only necessary to deposit the emitter layer 400 directly on the first emitter region 121 and the second emitter region 122.
  • the emitter layer 400 can be directly contacted with the first emitter region 121 and the second emitter region 122, and there is no need to provide conductive plugs, which saves the space occupied by the conventional conductive plugs, thereby increasing the density of the trench gate 200. Since the second dielectric layer 222 is formed on the gate conductive layer 210, the gate conductive layer 210 and the emitter layer 400 can be isolated by the second dielectric layer 222.
  • the distribution of the first emission area 121 and the second emission area 122 along the second direction in the present application can be The distance between adjacent trenches is reduced, so that the density of the trench gate 200 can be further increased.

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Abstract

一种沟槽栅IGBT器件，包括：依次叠设的漂移区(100)、体区(110)、第一发射区(121)和第二发射区(122)；沟槽沿第一方向分布并穿透第一发射区(121)、体区(110)并向下延伸至漂移区(100)内；第一介质层(221)形成于沟槽内壁上，栅导电层(210)形成于第一介质层(221)上并填于沟槽内，第二介质层(222)形成于栅导电层(210)上；第一发射区(121)和第二发射区(122)沿第二方向衔接分布，位于相邻两沟槽之间的第一发射区(121)和第二发射区(122)均与两侧相邻的沟槽的侧面接触。

Description

沟槽栅IGBT器件及其制备方法
相关申请的交叉引用
本申请要求于2020年05月19日提交中国专利局、申请号为2020104252789、发明名称为“沟槽栅IGBT器件及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体领域，尤其涉及一种沟槽栅IGBT器件及沟槽栅IGBT器件制备方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
在制备IGBT时，通常形成沟槽栅以提高芯片的集成度和沟道电流密度。其中，沟槽栅为在体区内开设沟槽并在沟槽内填入栅极结构所形成。在形成沟槽栅后，需要在体区内形成两个不同导电类型的发射区并在体区上形成与各发射区电连接的发射极层。发射极层需借助导电栓塞以实现与N型发射区和P型发射区的电连接，而导电栓塞需要占据一定的器件空间，由此限制了沟槽栅密度的进一步提升。
发明内容
针对上述问题，提出一种新的沟槽栅IGBT器件及其制备方法。
一种沟槽栅IGBT器件，包括：
漂移区，具有第一导电类型；
体区，具有第二导电类型，形成于所述漂移区上；
第一发射区，具有第一导电类型，形成于所述体区上，所述第一发射区内开设沿第一方向并排分布的多个沟槽，各所述沟槽依次贯穿所述第一发射区和所述体区并延伸至所述漂移区；
第二发射区，具有第二导电类型，形成于所述第一发射区的部分区域中并穿透所述第一发射区以与所述体区接触，所述第一发射区和所述第二发射 区沿第二方向衔接分布，位于相邻两沟槽之间的所述第一发射区和所述第二发射区均与两侧相邻的所述沟槽的侧面接触，所述第二方向不同于所述第一方向；
栅导电层和介质结构，所述介质结构包括第一介质层和第二介质层，所述第一介质层形成于所述沟槽内壁上，所述栅导电层形成于所述第一介质层上并填于所述沟槽内，所述第二介质层形成于所述栅导电层上；及
发射极层，形成于所述第一发射区和所述第二发射区上，所述发射极层与所述第一发射区和所述第二发射区接触并通过所述第二介质层与所述栅导电层隔离。
一种沟槽栅IGBT器件制备方法，包括：
形成具有第一导电类型的漂移区，所述漂移区内开设有沿第一方向并排分布的多个沟槽；
在所述沟槽的内壁上形成第一介质层并填入栅导电层，在所述栅导电层上形成第二介质层；
通过离子注入工艺，在所述漂移区的表层形成具有第二导电类型的体区，所述体区的深度小于所述沟槽的深度；
通过离子注入工艺，在所述体区的表层形成具有第一导电类型的第一发射区并在所述第一发射区的部分区域中形成具有第二导电类型的第二发射区，所述第二发射区穿透所述第一发射区并与所述体区接触，且所述第一发射区和所述第二发射区沿第二方向衔接分布，位于相邻两沟槽之间的所述第一发射区和所述第二发射区均与两侧相邻的所述沟槽的侧面接触，所述第二方向不同于所述第一方向；及
在所述第一发射区和所述第二发射区上形成与所述第一发射区和所述第二发射区直接接触的发射极层，所述发射极层通过所述第二介质层与所述栅导电层隔离。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
图1为一示例性的沟槽栅IGBT器件的结构示意图；
图2a为一实施例中未形成发射极层的沟槽栅IGBT器件的结构示意图；
图2b为一实施例的发射极层与第一发射区、第二发射区的接触方式示意图； 图3为再一实施例中未形成发射极层的沟槽栅IGBT器件的结构示意图；
图4为另一实施例中未形成发射极层的沟槽栅IGBT器件的结构示意图；
图5为一实施例栅极层的分布示意图；
图6为一实施例的沟槽栅IGBT器件制备方法的步骤流程图；
图7a～图7f为一实施例的对应沟槽栅IGBT器件制备方法相关步骤对应的结构示意图。
元件标号说明：
漂移区：100；体区：110；发射区层：120；缓冲区：130；集电区：140；第一发射区：121；第二发射区：122；栅导电层：210；介质结构：220；第一介质层：221；第二介质层：222；沟槽栅：200；集电极层：300；发射极层：400；有源区：AA；外围区域：W。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
如图1所示为一示例性的沟槽栅IGBT器件，体区110＇位于漂移区100＇上，漂移区100＇为N型，体区110＇为P型，P型发射区122＇和N型发射区121＇叠设于体区110＇上。沟槽栅200＇穿透N型发射区121＇和体区110＇并延伸至漂移区100＇内。发射极层400＇形成于N型发射区121＇上方，在相邻沟槽栅200＇之间还形成有穿透N型发射区121＇并延伸至P型发射区122＇中的导电栓塞410＇。发射极层400＇通过导电栓塞410＇实现与P型发射区122＇和N型发射区121＇的电连接。在传统技术中，由于在沟槽栅200＇之间需形成导电栓塞410＇，导电栓塞410＇需占据一定的空间，由此限制了进一步减小沟槽栅200＇之间的间距，不利于提高沟槽栅密度。
基于此，本申请提出一种新的沟槽栅IGBT器件。结合图2a和图2b所示，本申请中的沟槽栅IGBT器件包括漂移区100、体区110、第一发射区121和第二发射区122、沟槽、栅导电层210、介质结构220、发射极层400。
其中，漂移区100具有第一导电类型，具体的，漂移区100具体可以是第一导电类型的晶片外延层。定义漂移区100的一个表面为正面，与漂移区100正面相对的一面为背面。
体区110具有第二导电类型并形成于漂移区100的正面上。具体的，可以对漂移区100的表层进行第二导电类型掺杂，使漂移区100的表层由第一导电类型转变为第二导电类型，从而使漂移区100的表层转变为具有第二导电类型的体区110。
第一发射区121具有第一导电类型且形成于体区110上。
第一发射区121内开设有沿第一方向并排分布的多个沟槽，各沟槽依次向下贯穿第一发射区121和体区110并延伸至漂移区100内，在一实施例中，第一方向为图2a中所示的X轴方向。
第二发射区122具有第二导电类型且第二发射区122的掺杂浓度高于体区110，第二发射区122形成于第一发射区121的部分区域中并向下穿透第一发射区121以与体区110接触。位于相邻两沟槽之间的第一发射区121和第二发射区122沿第二方向衔接分布，位于相邻两沟槽之间的第一发射区121和第二发射区均与两侧相邻的沟槽的侧面接触，也即，各沟槽具有沿第二方向延伸的侧面，第一发射区121夹设于相邻沟槽之间，且第一发射区121分别与两侧沟槽接触，第二发射区122也夹设于相邻沟槽之间，且第二发射区122分别与两侧沟槽接触。在一实施例中，第二方向为图2a中所示的Y轴方向。在其他实施例中，第二方向不同于第一方向，即第一方向与第二方向之间的夹角大于0°小于180°。可选的，第一方向与第二方向相互垂直。此时，第一发射区121和第二发射区122组成发射区层120。如图2a所示，漂移区100、体区110、发射区层120所在的平面均为XY平面，漂移区100、体区110、发射区层120沿Z轴方向依次叠设。第一发射区121和第二发射区122分布于该XY平面。
在沟槽的内壁上形成有第一介质层221，栅导电层210形成于第一介质层221上并填于沟槽内，在栅导电层210上形成有第二介质层222，第一介质层221和第二介质层222相互连接组成包围栅导电层210的介质结构220。需要说明的是，将形成于沟槽内壁上的所有介质层均定义为第一介质层221， 第一介质层221可以仅包含一种介质材料，也可以包含多种介质材料，例如，位于不同位置处的第一介质层221的介质材料可以相同，也可以不同。同理，将位于栅导电层210上方的所有介质层定义为第二介质层222，第二介质层222可以仅包含一种介质材料，也可以包含多种介质材料，例如，位于不同位置处的第二介质层222的介质材料可以相同，也可以不同。在一实施例中，第一介质层221具体可以是氧化硅，也可以是其他具有高介电常数的材料。栅导电层210可以是多晶硅，也可以是其他导电性良好的材料如金属。第二介质层222可以与第一介质层221的材料相同，也可以不同，具体可选用氮化硅、氧化硅等。
发射极层400形成于第一发射区121和第二发射区122上，即发射极层400形成于发射区层120上，且发射极层400的底面直接与第一发射区121和第二发射区122接触而不需形成导电栓塞，发射极层400通过第二介质层222与栅导电层210电隔离。
其中，上述第一导电类型与第二导电类型相反，例如，当第一导电类型为N型时，第二导电类型为P型；当第一导电类型为N型时，第二导电类型为P型。
可以理解的，如图2a或图2b所示，上述IGBT器件还包括栅极层(图中未示出)、集电区140、与集电区140电连接的集电极层300。其中，栅极层与沟槽栅200中的栅导电层210电连接以控制器件的开关。其中，集电区140具有第二导电类型，集电区140通常形成于漂移区100的背面。在一实施例中，在集电区140和漂移区100之间，还形成有缓冲区130，缓冲区130具有第一导电类型且缓冲区130的掺杂浓度高于漂移区100的掺杂浓度。第一发射区121、第二发射区122、体区110、沟槽栅200和漂移区100形成MOS管结构，体区110、漂移区100、缓冲区130和集电区140形成三极管结构，通过沟槽栅200可以控制该MOS结构的通断，从而控制IGBT的通断。
上述沟槽栅IGBT器件，沟槽穿透第一发射区121、体区110并延伸至漂移区100内，沟槽内壁上形成有第一介质层221，在沟槽内填入位于第一介质层221上的栅导电层210，夹设于栅导电层210和沟槽内壁之间的第一介质层221为栅介质层，栅导电层210和栅介质层形成沟槽栅200，通过沟槽栅200控制IGBT器件的通断。
同时，通过改变第一发射区121和第二发射区122的分布方式，使第二发射区位于第一发射区内并穿透第一发射区以与体区接触，即第一发射区121 和第二发射区122分布于与体区110顶面平行的平面内，此时，仅需要在第一发射区121和第二发射区122上直接形成发射极层400便可直接与第一发射区121和第二发射区122接触，不需要设置导电栓塞，省去了导电栓塞占据的空间，从而可以提高沟槽栅200的密度，有效减少器件面积。而由于栅导电层210上形成有第二介质层222，通过第二介质层222可以隔离栅导电层210和发射极层400。同时，第一发射区121和第二发射区122在第二方向沿沟槽侧面衔接分布，相比于第一发射区121和第二发射区122沿第一方向分布的分布方式，可以减小沟槽之间的间距，从而可以进一步提高沟槽栅200密度，继而提高沟道电流密度。同时，相比于传统技术中发射极层400通过导电栓塞与第一发射区121和第二发射区122电连接，本申请中，发射极层400直接与第一发射区121和第二发射区122接触，可以提高器件的电输出能力，降低功率损耗，且更有利于器件散热。
在一实施例中，第一发射区121的顶面和第二发射区122的顶面齐平，第一发射区121的底面与第二发射区122的底面齐平，第一发射区121和第二发射区122的厚度相同或不同。在具体的工艺制程中，第一发射区121和第二发射区122均是由对体区110表层进行掺杂所形成，第一发射区121和第二发射区122的厚度相同，也即，第一发射区121和第二发射区122的注入深度相同，由此可以尽量减少第一发射区121扩散至第二发射区122下方或者第二发射区122扩散至第一发射区121下方的现象，使得结构更加稳定。当然，在其他实施例中，第一发射区121和第二发射区122的注入深度也可以不同，只需要调节掺杂条件便可灵活调节两发射区的注入深度，能确保第二发射区122与体区110接触即可。
在一实施例中，第一发射区121和第二发射区122的注入深度大于第二介质层222的厚度，即第一发射区121和第二发射区122均与第二介质层222下方的栅介质层接触，保证第一发射区121、体区110和漂移区100之间能够形成完整的电流通路。
在一实施例中，栅导电层210并未填满沟槽，即顶部沟槽并未填入栅导电层210，栅导电层210的顶面低于发射区层120的顶面，第二介质层222填充于栅导电层210上方的沟槽内。进一步的，第二介质层222刚好填满沟槽，第二介质层222的顶面与沟槽的顶面齐平。更进一步的，第二介质层222的顶面、第一发射区121的顶面以及第二发射区122的顶面齐平。在本实施例中，第二介质层222、第一发射区121和第二发射区122三者顶面齐平， 可以保证发射极层400的表面平整。
在一实施例中，第一发射区121和第二发射区122的尺寸可根据需要灵活设置。具体的，第一发射区121在体区110上的覆盖面积大于第二发射区122在体区110上的覆盖面积，由此增大第一发射区121与沟槽栅200的接触面积，从而提高导电沟道的密度。
在一实施例中，第二方向为Y轴方向，相邻沟槽之间形成的第一发射区121内形成有多个第二发射区122，即在第二方向上，与沟槽同一侧面接触的第一发射区121和第二发射区122的总数量大于或等于三，第一发射区121和第二发射区122在第二方向上交替分布，由此提高发射极层400电能传输的均匀性。
在一实施例中，如图2a所示，第一方向为X轴方向，第二方向为Y轴方向，IGBT器件具有设有多个沿第一方向并排分布的沟槽以形成多个沿第一方向并排分布的沟槽栅200时，在各相邻的沟槽之间均设置沿第二方向衔接分布的第一发射区121和第二发射区122。在另一实施例中，如图3所示，第一方向为X轴方向，第二方向为Y轴方向，也可以在其中部分相邻沟槽之间设置沿第二方向衔接分布的第一发射区121和第二发射区122，在其他相邻沟槽之间仅形成第一发射区121。
在一实施例中，第一方向为X轴方向，第二方向为Y轴方向，多个沟槽沿X轴方向间隔分布，沟槽具有沿Y轴方向延伸的侧面，沟槽两侧的第一发射区121和第二发射区122的分布方式相同，即第一发射区121和第二发射区122在Y轴方向上交替衔接分布，位于X轴方向的同一直线上，沟槽两侧发射区的类型相同，在X轴方向的同一直线上，沟槽两侧的发射区同为第一发射区121或同为第二发射区122。在本实施例中，位于X轴方向的同一直线上，沟槽两侧发射区的类型相同，即在X轴方向上并排分布的发射区的类型相同，可以减低工艺制程的难度，例如，通过掺杂工艺形成第一发射区121或第二发射区122时，需要在发射区层120上形成掩膜层，由于X轴方向上的发射区类型相同，掩膜层的开口呈一维条状分布，相比于Y轴方向上和X轴方向上的发射区类型均不相同时需要使用二维网格状的掩膜，本实施例中所需的掩膜对准工艺要求更低。
在一实施例中，第一方向为X轴方向，第二方向为Y轴方向，沟槽两侧的第一发射区121中均设置第二发射区122，且沟槽两侧的第一发射区的排布方式不同。在一具体的实施例中，参考图4所示，定义同一沟槽具有相对 的第一侧面和第二侧面，在第一方向上，与第一侧面接触的第一发射区121正对于与第二侧面接触的第二发射区122，与第一侧面接触的第二发射区122正对于与第二侧面接触的第一发射区121。换言之，第一发射区121和第二发射区122在第二方向上交替衔接分布，且第一发射区121和第二发射区122在第一方向上也交替分布。在本实施例中，第一发射区121和第二发射区122在发射区层120上分布均匀，使得电流传输更加均匀，从而提高器件的稳定性。
在一实施例中，参考图2a所示，上述沟槽呈长条形，沟槽的开口具有长边和短边，沟槽的长边沿Y轴方向延伸，沟槽的短边沿X轴方向延伸。在本实施例中，设置条型沟槽以形成条型的沟槽栅200，可以增大沟槽栅200的密度。
上述IGBT器件还包括与栅导电层210电连接的栅极层。在一实施例中，如图5所示，沟槽栅IGBT器件具有有源区AA和包围有源区AA的外围区域W，发射区层120均形成于有源区AA内，上述沟槽为沿Y轴方向延伸的长条形沟槽，且沿Y轴方向的沟槽开口自有源区AA延伸至外围区域W，发射极层400覆盖有源区AA，栅极层位于外围区域W且与位于外围区域W中沟槽内的栅导电层210电连接。在本实施例中，使沟槽延伸至外围区域W，可以在外围区域W引出栅极层，发射极层400覆盖有源区AA，从而通过简单的工艺使栅极层和发射极层400分布于不同区域。
上述沟槽栅IGBT器件，通过改变第一发射区121和第二发射区122的分布方式，使第一发射区121和第二发射区122分布于XY平面内，此时，仅需要在第一发射区121和第二发射区122上直接形成发射极层400，便可使发射极层400直接与第一发射区121和第二发射区122接触，不需要设置导电栓塞，省去了传统中导电栓塞占据的空间，从而可以提高沟槽栅200的密度。而由于栅导电层210上形成有第二介质层222，通过第二介质层222可以隔离栅导电层210和发射极层400。同时，相比于第一发射区121和第二发射区122沿第一方向分布的分布方式，本申请中第一发射区121和第二发射区122沿第二方向衔接分布的分布方式，可以减小相邻沟槽之间的间距，从而提高沟槽栅200密度。
本申请还涉及一种沟槽栅IGBT器件制备方法，用于制备上述沟槽栅IGBT器件。
如图6所示为沟槽栅IGBT器件制备方法的步骤流程图，该制备方法包 括：
步骤S100：形成具有第一导电类型的漂移区，所述漂移区内开设有沿第一方向并排分布的多个沟槽。
如图7a所示，在半导体衬底上形成漂移区100，漂移区100具有第一导电类型，漂移区100开设有沿第一方向并排分布的多个沟槽。第一方向为X轴方向，沟槽的开口具有长边和短边，沟槽的长边沿Y轴方向延伸，沟槽的短边沿X轴方向延伸，多个沟槽沿X轴方向间隔且平行设置。
步骤S200：在所述沟槽的内壁上形成第一介质层并填入栅导电层，在所述栅导电层上形成第二介质层。
如图7b所示，首先，在沟槽内壁上形成第一介质层221。在一实施例中，具体可以通过沉积工艺在沟槽内壁上沉积第一介质层221，沉积工艺可以是化学气相沉积工艺或原子层沉积工艺。在另一实施例中，也可以通过热氧化工艺在沟槽内壁上生长氧化层作为第一介质层221。
在形成第一介质层221后，在沟槽内填入栅导电层210。在一实施例中，通过沉积工艺在沟槽内填入栅导电层210。
在填入栅导电层210后，在栅导电层210上形成第二介质层222。在一实施例中，可通过热氧化工艺在栅导电层210上生长出氧化层作为第二介质层222。在另一实施例中，可沉积一层第二介质层222，选择性去掉第二介质层222，仅保留栅导电层210上的第二介质层222。在一实施例中，上述栅导电层210填满沟槽，第二介质层222位于沟槽上方。在另一实施例中，在沟槽内填满栅导电层210后，对栅导电层210进行回刻，降低栅导电层210的高度，然后在栅导电层210上方的沟槽内沉积第二介质层222，并使第二介质层222的顶面与沟槽顶面齐平。
步骤S300：通过离子注入工艺，在所述漂移区的表层形成具有第二导电类型的体区，所述体区的深度小于所述沟槽的深度。
如图7c所示，通过离子注入工艺，对漂移区100的表层注入第二导电类型的掺杂离子，且注入深度小于沟槽底部深度，使漂移区100的表层转变成具有第二导电类型的体区110，形成位于漂移区100上的体区110，体区110深度小于沟槽底部深度，此时，沟槽穿透体区110并延伸至漂移区100内。
步骤S400：通过离子注入工艺，在所述体区的表层形成具有第一导电类型的第一发射区并在所述第一发射区的部分区域中形成具有第二导电类型的第二发射区，所述第二发射区穿透所述第一发射区并与所述体区接触，且所 述第一发射区和所述第二发射区沿第二方向衔接分布，位于相邻两沟槽之间的所述第一发射区和所述第二发射区均与两侧相邻的所述沟槽的侧面接触。
在一实施例中，如图7d所示，第二方向为Y轴方向。对体区110的表层的不同区域分别注入具有第一导电类型的掺杂离子和具有第二导电类型的掺杂离子，以在体区110不同区域的表层分别形成具有第一导电类型的第一发射区121和具有第二导电类型的第二发射区122，即第一发射区121和第二发射区122均由体区110的上表面向体区110内部延伸，且第一发射区121和第二发射区122沿第二方向衔接分布，位于相邻两沟槽之间的第一发射区121和第二发射区122均与两侧相邻的沟槽的侧面接触。
具体的，可以先形成第一掩膜层，通过第一掩膜层的开口暴露出需形成第一发射区121的体区110表层区域，对体区110表层注入具有第一导电类型的掺杂离子，使所暴露区域的体区110表层转变成第一发射区121；去除第一掩膜层，并形成第二掩膜层，第二掩膜层覆盖第一发射区121，且第二掩膜层的开口暴露出需形成第二发射区122的体区110表层区域，对体区110表层掺入具有第二导电类型的掺杂离子，使所暴露的另一区域的体区110表层转变成第二发射区122。
在另一实施例中，也可以先在体区110表层注入具有第一导电类型的掺杂离子，形成第一发射区121，然后对第一发射区121的部分区域注入具有第二导电类型的掺杂离子，使部分第一发射区121转变为具有第二导电类型的第二发射区122。
在一实施例中，在形成第一发射区121和第二发射区122后，执行背面工艺，如图7e所示，在漂移区100背离体区110的一侧表面上形成具有第二导电类型的集电区140，在一实施例中，在漂移区100和集电区140之间还形成有具有第一导电类型的缓冲区130，缓冲区130的掺杂浓度高于漂移区100的掺杂浓度。
步骤S500：在所述第一发射区和所述第二发射区上形成与所述第一发射区和所述第二发射区直接接触的发射极层，所述发射极层通过所述第二介质层与所述栅导电层隔离。
如图7f所示，通过沉积工艺在第一发射区121和第二发射区122上沉积发射极层400，发射极层400与第一发射区121和第二发射区122直接接触，且第一发射极层400通过第二介质层222于栅导电结构隔离。可以理解的，在背面的集电区140上也沉积一层集电极层300。
上述IGBT器件制备方法，在体区110表层形成第一发射区121和第二发射区122，此时，仅需要在第一发射区121和第二发射区122上直接沉积发射极层400，便可使发射极层400直接与第一发射区121和第二发射区122接触，不需要设置导电栓塞，省去了传统中导电栓塞占据的空间，从而可以提高沟槽栅200的密度。而由于栅导电层210上形成有第二介质层222，通过第二介质层222可以隔离栅导电层210和发射极层400。同时，相比于第一发射区121和第二发射区122沿第一方向分布的分布方式，本申请中第一发射区121和第二发射区122沿第二方向衔接分布的分布方式，可以减小相邻沟槽之间的距离，从而可以进一步提高沟槽栅200密度。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种沟槽栅IGBT器件，包括：
    漂移区，具有第一导电类型；
    体区，具有第二导电类型，形成于所述漂移区上；
    第一发射区，具有第一导电类型，形成于所述体区上，所述第一发射区内开设沿第一方向并排分布的多个沟槽，各所述沟槽依次贯穿所述第一发射区和所述体区并延伸至所述漂移区；
    第二发射区，具有第二导电类型，形成于所述第一发射区的部分区域中并穿透所述第一发射区以与所述体区接触，所述第一发射区和所述第二发射区沿第二方向衔接分布，位于相邻两沟槽之间的所述第一发射区和所述第二发射区均与两侧相邻的所述沟槽的侧面接触，所述第二方向不同于所述第一方向；
    栅导电层和介质结构，所述介质结构包括第一介质层和第二介质层，所述第一介质层形成于所述沟槽内壁上，所述栅导电层形成于所述第一介质层上并填于所述沟槽内，所述第二介质层形成于所述栅导电层上；及
    发射极层，形成于所述第一发射区和所述第二发射区上，所述发射极层与所述第一发射区和所述第二发射区接触并通过所述第二介质层与所述栅导电层隔离。
  2. 如权利要求1所述的沟槽栅IGBT器件，其特征在于，所述第一发射区的顶面与所述第二发射区的顶面齐平，所述第一发射区的底面与所述第二发射区的底面齐平。
  3. 如权利要求1所述的沟槽栅IGBT器件，其特征在于，所述第一发射区 的注入深度和第二发射区的注入深度均大于所述第二介质层的厚度。
  4. 如权利要求1所述的沟槽栅IGBT器件，其特征在于，所述第二介质层的顶面与所述沟槽的顶面齐平。
  5. 如权利要求1所述的沟槽栅IGBT器件，其特征在于，所述第二发射区在所述体区上的覆盖面积小于所述第一发射区在所述体区上的覆盖面积。
  6. 如权利要求1所述的沟槽栅IGBT器件，其特征在于，相邻沟槽之间的第一发射区内形成有多个间隔设置的第二发射区，所述第一发射区和所述第二发射区在所述第二方向上交替分布。
  7. 如权利要求1至6任一项所述的沟槽栅IGBT器件，其特征在于，所述沟槽两侧的所述第一发射区中均设置第二发射区，所述沟槽两侧的第一发射区和第二发射区的排布方式相同。
  8. 如权利要求1至6任一项所述的沟槽栅IGBT器件，其特征在于，所述沟槽两侧的所述第一发射区中均设置第二发射区，所述沟槽两侧的第一发射区和第二发射区的排布方式不同。
  9. 如权利要求8所述的沟槽栅IGBT器件，其特征在于，同一沟槽具有相对的第一侧面和第二侧面，在所述第一方向上，与所述第一侧面接触的第一发射区正对于与所述第二侧面接触的第二发射区，与所述第一侧面接触的第二发射区正对于与所述第二侧面接触的第一发射区。
  10. 如权利要求1所述的沟槽栅IGBT器件，其特征在于，还包括：
    栅极层，位于包围有源区的外围区域，与位于所述外围区域中沟槽内的栅导电层电连接；
    其中，所述第一发射区和第二发射区均形成于所述有源区内，各所述沟槽自有源区延伸至所述外围区域，所述发射极层覆盖所述有源区。
  11. 如权利要求1所述的沟槽栅IGBT器件，其特征在于，还包括：
    集电区，具有第二导电类型，形成于所述漂移区的背面；及
    集电极层，形成于所述集电区的背面。
  12. 如权利要求11所述的沟槽栅IGBT器件，其特征在于，还包括缓冲区，所述缓冲区形成于所述集电区和漂移区之间，所述缓冲区具有第一导电类型，所述缓冲区的掺杂浓度高于所述漂移区的掺杂浓度。
  13. 如权利要求1所述的沟槽栅IGBT器件，其特征在于，所述第一介质层设置为仅包含一种介质材料或包含多种介质材料；
    所述第二介质层设置为仅包含一种介质材料或包含多种介质材料。
  14. 一种沟槽栅IGBT器件制备方法，包括：
    形成具有第一导电类型的漂移区，所述漂移区内开设有沿第一方向并排分布的多个沟槽；
    在所述沟槽的内壁上形成第一介质层并填入栅导电层，在所述栅导电层上形成第二介质层；
    通过离子注入工艺，在所述漂移区的表层形成具有第二导电类型的体区，所述体区的深度小于所述沟槽的深度；
    通过离子注入工艺，在所述体区的表层形成具有第一导电类型的第一发射区并在所述第一发射区的部分区域中形成具有第二导电类型的第二发射区，所述第二发射区穿透所述第一发射区并与所述体区接触，且所述第一发射区和所述第二发射区沿第二方向衔接分布，位于相邻两沟槽之间的所述第一发射区和所述第二发射区均与两侧相邻的所述沟槽的侧面接触，所述第二方向不同于所述第一方向；及
    在所述第一发射区和所述第二发射区上形成与所述第一发射区和所述第 二发射区直接接触的发射极层，所述发射极层通过所述第二介质层与所述栅导电层隔离。
  15. 根据权利要求14所述的方法，其特征在于，所述在所述体区的表层形成具有第一导电类型的第一发射区并在所述第一发射区的部分区域中形成具有第二导电类型的第二发射区的步骤之后，所述在所述第一发射区和所述第二发射区上形成与所述第一发射区和所述第二发射区直接接触的发射极层的步骤之前，还包括在所述漂移区背离体区的一侧表面上形成具有第二导电类型的集电区的步骤。
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