WO2021232809A1 - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
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- WO2021232809A1 WO2021232809A1 PCT/CN2020/140510 CN2020140510W WO2021232809A1 WO 2021232809 A1 WO2021232809 A1 WO 2021232809A1 CN 2020140510 W CN2020140510 W CN 2020140510W WO 2021232809 A1 WO2021232809 A1 WO 2021232809A1
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- Prior art keywords
- semiconductor device
- region
- drift region
- gate electrode
- conductivity type
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000002955 isolation Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 2
- 150000004706 metal oxides Chemical class 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 description 12
- 239000012212 insulator Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- INQLNSVYIFCUML-QZTLEVGFSA-N [[(2r,3s,4r,5r)-5-(6-aminopurin-9-yl)-3,4-dihydroxyoxolan-2-yl]methoxy-hydroxyphosphoryl] [(2r,3s,4r,5r)-5-(4-carbamoyl-1,3-thiazol-2-yl)-3,4-dihydroxyoxolan-2-yl]methyl hydrogen phosphate Chemical compound NC(=O)C1=CSC([C@H]2[C@@H]([C@H](O)[C@@H](COP(O)(=O)OP(O)(=O)OC[C@@H]3[C@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=N1 INQLNSVYIFCUML-QZTLEVGFSA-N 0.000 description 1
- 229910052454 barium strontium titanate Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 description 1
- 229910052451 lead zirconate titanate Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Definitions
- the present invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device.
- an exemplary solution is to provide a polysilicon gate that also functions as a field plate above the drift region. , And the polysilicon gate is overlaid on the insulating isolation structure.
- the on-state breakdown voltage needs to be further increased.
- a semiconductor device includes: a substrate having a second conductivity type; a drift region formed on the substrate and having a first conductivity type; and a first doped region formed on the surface of the drift region and having the first conductivity type And the doping concentration is greater than the doping concentration of the drift region; the second doping region is formed outside the drift region and on the substrate, and has the first conductivity type and the doping concentration is greater than the doping concentration of the drift region.
- Impurity concentration an insulating isolation structure formed on the surface of the drift region, between the first doped region and the second doped region; and a gate structure, including a gate electrode and a gate dielectric layer, the gate electrode is formed On the drift region, one end of the gate electrode extends to the insulating isolation structure, and the other end to the second doped region, the gate dielectric layer is formed under the gate electrode, and the gate
- the electrode is formed with a hollow part, the hollow part includes at least one hollow unit, and the hollow part does not completely cut off the gate electrode in the width direction of the conductive channel; wherein, the first conductivity type and the second conductivity type are Opposite conductivity type.
- Figure 1 is a top view of an exemplary polysilicon gate structure
- Figure 2 is a cross-sectional view taken along the line A-A shown in Figure 1;
- FIG. 3 is a top view of a partial structure of a semiconductor device in an embodiment
- Figure 4 is a cross-sectional view taken along the line B-B shown in Figure 3;
- FIG. 5 is a plan view of a hollow portion of a gate electrode in another embodiment
- FIG. 6 is a comparison diagram of on-state breakdown voltage curves obtained by simulation of the semiconductor device of the embodiment of the present application and the old structure semiconductor device of the comparative example.
- first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or section discussed below may be represented as a second element, component, region, layer or section.
- the embodiments of the invention are described here with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention.
- changes from the shown shape due to, for example, manufacturing technology and/or tolerances can be expected. Therefore, the embodiments of the present invention should not be limited to the specific shapes of the regions shown here, but include shape deviations due to, for example, manufacturing.
- an implanted area shown as a rectangle usually has rounded or curved features and/or an implanted concentration gradient at its edges, rather than a binary change from an implanted area to a non-injected area.
- the buried region formed by the implantation can result in some implantation in the region between the buried region and the surface through which the implantation proceeds. Therefore, the regions shown in the figure are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present invention.
- P-type and N-type impurities in order to distinguish the doping concentration, simply P+ type represents the heavy doping concentration of P type, and P type represents middle P-type doping concentration, P-type represents P-type with light doping concentration, N+-type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents light-doping concentration N type.
- the exemplary device structure is formed with a drift region 120 on the substrate 110, the drift region 120 is provided with a shallow trench isolation structure 130, and the drift region 120 and the shallow trench isolation structure 130 are provided There is a polysilicon gate 140, and the gate oxide layer under the polysilicon gate 140 is omitted in FIG. 2.
- the depletion rate of the drift region 120 where the shallow trench isolation structure 130 is not provided under the polysilicon gate 140 is faster than the depletion rate of the drift region 120 at the shallow trench isolation structure 130, which affects the device The on-state breakdown voltage will not be too high.
- FIG. 3 is a top view of a part of the structure of the semiconductor device in an embodiment
- FIG. 4 is a cross-sectional view along the line B-B shown in FIG. 3. 3 and 4 together
- the semiconductor device includes a substrate 210, a drift region 220, a first doped region 222, a second doped region 224, an insulating isolation structure 230, and a gate structure.
- the substrate 210 has the second conductivity type
- the drift region 220, the first doped region 222, and the second doped region 224 have the first conductivity type.
- the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type is P-type and the second conductivity type is P-type. N type.
- the drift region 220 is formed on the substrate 210.
- the first doped region 222 is formed on the surface of the drift region 220, and its doping concentration is greater than the doping concentration of the drift region 220.
- the second doped region 224 is formed outside the drift region 220 and on the substrate 210, and its doping concentration is greater than the doping concentration of the drift region 220.
- the insulating isolation structure 230 is formed between the surface of the drift region 220 and the first doped region 222 and the second doped region 224.
- the gate structure includes a gate electrode 240 and a gate dielectric layer (not shown in FIG. 4).
- the gate electrode 240 is formed on the drift region 220, and one end of the gate electrode 240 extends to the insulating isolation structure 230 and the other end to the second doped region 224; the gate dielectric layer is formed under the gate electrode 240.
- the gate electrode 240 is formed with a hollow part, so that a part of the gate electrode 240 above the drift region 220 is hollowed out.
- the hollow part includes at least one hollow unit 241, and the hollow part does not completely cut off the gate electrode 240 in the width direction of the conductive channel (ie, the Y direction in FIG. 3).
- the length in the) direction is smaller than the length of the gate electrode 240 in the width direction of the conductive channel.
- the above-mentioned semiconductor device forms a hollow portion on the gate electrode 240 above the drift region 220 of the first conductivity type. Therefore, the depletion of the hollow portion formed by the drift region 220 is reduced compared with the case where the hollow portion is not provided, thereby slowing the drift region in the hollow portion.
- the depletion speed of the position can in turn increase the on-state breakdown voltage BVon of the device. Since only the photolithography of the gate photoetching plate needs to be modified to form the hollow part, there is no need to increase the photoetching level, and the on-state breakdown voltage of the device does not need to increase the process cost.
- the first doped region 222 is a drain region
- the second doped region 224 is a source region.
- the doping concentration of the drift region 220 is relatively low, which is equivalent to forming a high resistance region between the source and the drain, which can increase the breakdown voltage and reduce the parasitic capacitance between the source and the drain. Conducive to improving the frequency characteristics of the device.
- the semiconductor device further includes a substrate lead-out area 226 provided on the substrate 210.
- the substrate lead-out region 226 is disposed close to the second doped region 224 and is located on the side of the second doped region 224 away from the drift region 220.
- the substrate lead-out region 226 has the second conductivity type, and the doping concentration of the substrate lead-out region 226 is greater than the doping concentration of the substrate 210.
- the hollow portion is provided above the drift region 220 between the insulating isolation structure 230 and the second doped region 224.
- the depletion rate of the drift region 220 where the shallow trench isolation structure 230 is not provided under the gate electrode 240 is faster than the depletion rate of the drift region 220 where the shallow trench isolation structure 230 is located. Therefore, the inventor believes that the drift region is slowed down.
- the depletion speed of the front end of 220 (where the shallow trench isolation structure 230 is not provided) can significantly increase the on-state breakdown voltage of the device. It can be seen in FIG. 4 that there is no gate electrode 240 in some positions on the front end of the drift region 220, so that the depletion of the front end of the drift region 220 will be weakened, thereby increasing the on-state breakdown voltage of the device.
- the size and shape of the hollow cells of the gate electrode 240 may be the same or different.
- the hollow cells 241 are evenly distributed along the width direction of the conductive channel.
- the cross section of each hollow unit 241 is rectangular.
- the hollow portion includes at least a hollow unit whose cross section is one of a polygon, a circle, and an ellipse.
- the polygon may be a hexagon, a pentagon, a quadrilateral, or the like.
- the hollowed-out units 241 are arranged in a row; in other embodiments, the hollowed-out units can also be arranged in more than two rows.
- each hollowed-out unit 243 is arranged in two rows, and the number of hollowed-out units 243 in each row is different. In other embodiments, the hollow cells may also be distributed irregularly.
- a hollow unit may also be provided on the edge of the gate electrode 240, that is, a part of the edge of the gate electrode 240 is removed.
- the first doped region 222 and the second doped region 224 are N+ regions, and the substrate lead-out region 226 is a P+ region.
- the substrate 210 is a semiconductor substrate, and its material may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), silicon on insulator (SSOI), Silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc. are stacked on the insulator.
- the constituent material of the substrate 210 is monocrystalline silicon.
- the gate electrode 240 is a polysilicon gate. In other embodiments, metal, metal nitride, metal silicide or similar compounds can also be used as the material of the gate electrode 240.
- the gate dielectric layer may include conventional dielectric materials such as oxides, nitrides, and oxynitrides of silicon with a dielectric constant of from about 4 to about 20 (measured in vacuum), or the gate dielectric layer A generally higher dielectric constant dielectric material having a dielectric constant of from about 20 to at least about 100 may be included.
- Such higher dielectric constant dielectric materials may include, but are not limited to: hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs), and lead zirconate titanate (PZTs).
- the insulating isolation structure 230 is a shallow trench isolation structure (STI); in other embodiments, the insulating isolation structure 230 may also be a local oxidation of silicon isolation structure (LOCOS).
- STI shallow trench isolation structure
- LOCOS local oxidation of silicon isolation structure
- the aforementioned semiconductor device is a laterally diffused metal oxide semiconductor (LDMOS) device.
- LDMOS laterally diffused metal oxide semiconductor
- TCAD BVon Curve on-state breakdown voltage curve obtained by the simulation of the semiconductor device of the embodiment of the application and the old structure semiconductor device of the comparative example.
- the curve in the figure is measured when the gate voltage Vg is 5V.
- the abscissa is the on-state breakdown voltage of the device in volts, and the ordinate is the leakage current of the device in amperes. It can be seen that the on-state breakdown voltage of the new structure of the embodiment of the present application has an increase of nearly 10V compared with the old structure.
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Abstract
一种半导体器件,包括:衬底(210);漂移区(220),形成于衬底(210)上;第一掺杂区(222),形成于该漂移区(220)表面;第二掺杂区(224),形成于该漂移区(220)外、该衬底(210)上;绝缘隔离结构(230),形成于该漂移区(220)表面、该第一掺杂区(222)与第二掺杂区(224)之间;栅极结构,包括栅电极(240)和栅介电层,栅电极(240)形成于漂移区(220)上,且栅电极(240)的一端延伸至绝缘隔离结构(230)上、另一端延伸至第二掺杂区(224),栅介电层形成于栅电极(240)下方,栅电极(240)形成有镂空部,镂空部包括至少一个镂空单元(241),镂空部不将栅电极(240)在导电沟道宽度方向上整个截断。
Description
相关申请的交叉引用
本申请要求于2020年05月21日提交中国专利局、申请号为2020104366258、发明名称为“半导体器件”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本发明涉及半导体制造领域,特别是涉及一种半导体器件。
这里的陈述仅提供与本申请有关的背景信息,而不必然地构成现有技术。
对于漂移区中设有绝缘隔离结构(例如浅沟槽隔离结构STI或硅局部氧化隔离结构LOCOS)的半导体器件,一种示例性的方案是漂移区上方设有兼具场板作用的多晶硅栅极,且该多晶硅栅极搭到绝缘隔离结构上。
为了满足市场需求,对于漂移区中设有绝缘隔离结构、且漂移区及该绝缘隔离结构上设有多晶硅栅极的器件,需要进一步提升其开态击穿电压。
发明内容
基于此,有必要提供一种开态击穿电压更高的半导体器件。
一种半导体器件,包括:衬底,具有第二导电类型;漂移区,形成于衬底上,具有第一导电类型;第一掺杂区,形成于所述漂移区表面,具有第一导电类型且掺杂浓度大于所述漂移区的掺杂浓度;第二掺杂区,形成于所述漂移区外、所述衬底上,具有第一导电类型且掺杂浓度大于所述漂移区的掺杂浓度;绝缘隔离结构,形成于所述漂移区表面、所述第一掺杂区与第二掺杂区之间;及栅极结构,包括栅电极和栅介电层,所述栅电极形成于所述漂 移区上,且栅电极的一端延伸至所述绝缘隔离结构上、另一端延伸至所述第二掺杂区,所述栅介电层形成于所述栅电极下方,所述栅电极形成有镂空部,所述镂空部包括至少一个镂空单元,所述镂空部不将所述栅电极在导电沟道宽度方向上整个截断;其中,所述第一导电类型和第二导电类型为相反的导电类型。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
为了更好地描述和说明这里公开的那些发明的实施例和/或示例,可以参考一幅或多幅附图。用于描述附图的附加细节或示例不应当被认为是对所公开的发明、目前描述的实施例和/或示例以及目前理解的这些发明的最佳模式中的任何一者的范围的限制。
图1是一种示例性的多晶硅栅极结构的俯视图;
图2是沿图1所示A-A线的剖视图;
图3是一实施例中半导体器件的部分结构的俯视图;
图4是沿图3所示B-B线的剖视图;
图5是另一实施例中栅电极的镂空部的俯视图;
图6是本申请实施例的半导体器件与对比例的旧结构半导体器件仿真得到的开态击穿电压曲线对比图。
为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
除非另有定义,本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用 的术语只是为了描述具体的实施例的目的,不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
需要说明的是,当元件被称为“固定于”另一个元件,它可以直接在另一个元件上或者也可以存在居中的元件。当一个元件被认为是“连接”另一个元件,它可以是直接连接到另一个元件或者可能同时存在居中元件。本文所使用的术语“竖直的”、“水平的”、“上”、“下”、“左”、“右”以及类似的表述只是为了说明的目的。当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时,其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层,或者可以存在居间的元件或层。相反,当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时,则不存在居间的元件或层。应当明白,尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分,这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此,在不脱离本发明教导之下,下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
当在本说明书中使用术语“包含”和/或“包括”时,其指明存在所述特征、整体、步骤、操作、元件和/或组件,但不排除存在或附加一个或多个其他特征、整体、步骤、操作、元件、组件和/或它们的组合。单数形式的“一”、“一个”和“所述/该”也意图包括复数形式,除非上下文清楚指出另外的方式。
这里参考作为本发明的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例。这样,可以预期由于例如制造技术和/或容差导致的从所示形状的变化。因此,本发明的实施例不应当局限于在此所示的区的特定形状,而是包括由于例如制造导致的形状偏差。例如,显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度,而不是从注入区到非注 入区的二元改变。同样,通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此,图中显示的区实质上是示意性的,它们的形状并不意图显示器件的区的实际形状且并不意图限定本发明的范围。
本文所使用的半导体领域词汇为本领域技术人员常用的技术词汇,例如对于P型和N型杂质,为区分掺杂浓度,简易的将P+型代表重掺杂浓度的P型,P型代表中掺杂浓度的P型,P-型代表轻掺杂浓度的P型,N+型代表重掺杂浓度的N型,N型代表中掺杂浓度的N型,N-型代表轻掺杂浓度的N型。
参见图1和图2,示例性的器件结构在衬底110上形成有漂移区120,漂移区120中设有浅沟槽隔离结构130、且漂移区120及浅沟槽绝缘隔离结构130上设有多晶硅栅极140,图2中省略了位于多晶硅栅极140下方的栅氧化层。对于这种结构,多晶硅栅极140下方未设置浅沟槽隔离结构130处的漂移区120的耗尽速度要比浅沟槽隔离结构130处的漂移区120的耗尽速度快,受此影响器件的开态击穿电压不会太高。
图3是一实施例中半导体器件的部分结构的俯视图,图4是沿图3所示B-B线的剖视图。请一并参见图3和图4,半导体器件包括衬底210、漂移区220、第一掺杂区222、第二掺杂区224、绝缘隔离结构230及栅极结构。其中,衬底210具有第二导电类型,漂移区220、第一掺杂区222、第二掺杂区224具有第一导电类型。在图3和图4所示的实施例中,第一导电类型为N型,第二导电类型为P型;在其他实施例中也可以是第一导电类型为P型,第二导电类型为N型。
漂移区220形成于衬底210上。第一掺杂区222形成于漂移区220表面,其掺杂浓度大于漂移区220的掺杂浓度。第二掺杂区224形成于漂移区220外、衬底210上,其掺杂浓度大于漂移区220的掺杂浓度。绝缘隔离结构230形成于漂移区220表面、第一掺杂区222与第二掺杂区224之间。栅极结构包括栅电极240和栅介电层(图4中未示)。栅电极240形成于漂移区220上,且栅电极240的一端延伸至绝缘隔离结构230上、另一端延伸至第二掺杂区 224;栅介电层形成于栅电极240下方。栅电极240形成有镂空部,从而使得漂移区220上方一部分位置的栅电极240被镂空。镂空部包括至少一个镂空单元241,镂空部不将栅电极240在导电沟道宽度(width)方向(即图3中的Y方向)上整个截断,也即镂空单元241在导电沟道宽度(width)方向上的长度小于栅电极240在导电沟道宽度(width)方向上的长度。
上述半导体器件在第一导电类型的漂移区220上方的栅电极240形成镂空部,因此漂移区220形成镂空部位置的耗尽相对于不设置镂空部的情况会减弱,从而减缓了漂移区在该位置的耗尽速度,进而能够提升器件的开态击穿电压BVon。由于只需要对栅极光刻的光刻版进行修改就可以形成镂空部,因此不需要增加光刻层次,提高器件的开态击穿电压不需要增加工艺成本。
在一个实施例中,第一掺杂区222为漏极区,第二掺杂区224为源极区。漂移区220的掺杂浓度较低,相当于在源极和漏极之间形成一个电阻较高的区域,能够提高击穿电压,并减小了源极和漏极之间的寄生电容,有利于提高器件的频率特性。
在图3和图4所示的实施例中,半导体器件还包括设于衬底210上的衬底引出区226。衬底引出区226靠近第二掺杂区224设置、且位于第二掺杂区224远离漂移区220的一侧。衬底引出区226具有第二导电类型,且衬底引出区226的掺杂浓度大于衬底210的掺杂浓度。
在图4所示的实施例中,镂空部设于绝缘隔离结构230与第二掺杂区224之间的漂移区220上方。如前述,栅电极240下方未设置浅沟槽隔离结构230处的漂移区220的耗尽速度要比浅沟槽隔离结构230处的漂移区220的耗尽速度快,因此发明人认为减缓漂移区220前端(未设置浅沟槽隔离结构230的位置)的耗尽速度能够较为显著地提高器件的开态击穿电压。可以看到图4中在漂移区220前端上有部分位置是没有栅电极240的,这样漂移区220前端耗尽会减弱,从而提升了器件的开态击穿电压。
栅电极240各镂空单元的大小和形状可以相同也可以不同。在图3所示的实施例中,各镂空单元241沿导电沟道宽度方向均匀分布。在图3所示实 施例中,各镂空单元241的横截面为矩形。在其他实施例中,镂空部至少包括横截面为多边形、圆形、椭圆形中的一种的镂空单元,多边形可以是六边形、五边形、四边形等。
在图3所示的实施例中,各镂空单元241排成一列;在其他实施例中,镂空单元也可以设置两列以上。在图5所示的实施例中,各镂空单元243排成两列,且每列的镂空单元243数量不相同。在其他实施例中,镂空单元也可以无规律地分布。
在一个实施例中,在栅电极240的边缘也可以设置镂空单元,即栅电极240的边缘被去除掉一部分。
在图4所示的实施例中,第一掺杂区222和第二掺杂区224为N+区,衬底引出区226为P+区。
在一个实施例中,衬底210为半导体衬底,其材料可以采用未掺杂的单晶硅、掺杂有杂质的单晶硅、绝缘体上硅(SOI)、绝缘体上层叠硅(SSOI)、绝缘体上层叠锗化硅(S-SiGeOI)、绝缘体上锗化硅(SiGeOI)以及绝缘体上锗(GeOI)等。在图4所示的实施例中,衬底210的构成材料选用单晶硅。
在一个实施例中,栅电极240为多晶硅栅极,在其他实施例中也可使用金属、金属氮化物、金属硅化物或类似化合物作为栅电极240的材料。
在一个实施例中,栅介电层可以包括传统的电介质材料诸如具有电介质常数从大约4到大约20(真空中测量)的硅的氧化物、氮化物和氮氧化物,或者,栅介电层可以包括具有电介质常数从大约20到至少大约100的通常较高电介质常数电介质材料。这种较高电介质常数电介质材料可以包括但不限于:氧化铪、硅酸铪、氧化钛、钛酸锶钡(BSTs)和锆钛酸铅(PZTs)。
在一个实施例中,绝缘隔离结构230为浅沟槽隔离结构(STI);在其他实施例中,绝缘隔离结构230也可以为硅局部氧化隔离结构(LOCOS)。
在一个实施例中,上述半导体器件为横向扩散金属氧化物半导体(LDMOS)器件。
图6是本申请实施例的半导体器件与对比例的旧结构半导体器件仿真得 到的开态击穿电压曲线(TCAD BVon Curve)对比图,图中曲线是在栅极电压Vg为5V时测得,横坐标为器件开态击穿电压,单位为伏特,纵坐标为器件漏电流,单位为安培。可以看到本申请实施例的新结构相比旧结构开态击穿电压有近10V的提升。
以上所述实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例中的各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。
Claims (15)
- 一种半导体器件,包括:衬底,具有第二导电类型;漂移区,形成于衬底上,具有第一导电类型;第一掺杂区,形成于所述漂移区表面,具有第一导电类型且掺杂浓度大于所述漂移区的掺杂浓度;第二掺杂区,形成于所述漂移区外、所述衬底上,具有第一导电类型且掺杂浓度大于所述漂移区的掺杂浓度;绝缘隔离结构,形成于所述漂移区表面、所述第一掺杂区与第二掺杂区之间;及栅极结构,包括栅电极和栅介电层,所述栅电极形成于所述漂移区上,且栅电极的一端延伸至所述绝缘隔离结构上、另一端延伸至所述第二掺杂区,所述栅介电层形成于所述栅电极下方,所述栅电极形成有镂空部,所述镂空部包括至少一个镂空单元,所述镂空部不将所述栅电极在导电沟道宽度方向上整个截断;其中,所述第一导电类型和第二导电类型为相反的导电类型。
- 根据权利要求1所述的半导体器件,其特征在于,各所述镂空单元沿导电沟道宽度方向分布。
- 根据权利要求2所述的半导体器件,其特征在于,各所述镂空单元在导电沟道宽度方向上均匀分布。
- 根据权利要求3所述的半导体器件,其特征在于,所述镂空部包括在导电沟道宽度方向上均匀分布的一列镂空单元。
- 根据权利要求1所述的半导体器件,其特征在于,所述镂空部至少包括横截面为多边形、圆形、椭圆形中的一种的镂空单元。
- 根据权利要求1所述的半导体器件,其特征在于,各所述镂空单元的横截面为矩形。
- 根据权利要求1所述的半导体器件,其特征在于,还包括设于所述衬底上的衬底引出区,所述衬底引出区靠近所述第二掺杂区设置、且位于所述第二掺杂区远离所述漂移区的一侧,具有第二导电类型且掺杂浓度大于所述衬底的掺杂浓度。
- 根据权利要求1所述的半导体器件,其特征在于,所述绝缘隔离结构为浅沟槽隔离结构。
- 根据权利要求1所述的半导体器件,其特征在于,所述绝缘隔离结构为硅局部氧化隔离结构。
- 根据权利要求1所述的半导体器件,其特征在于,所述栅电极为多晶硅栅极,所述栅介电层为栅氧化层。
- 根据权利要求1中任一项所述的半导体器件,其特征在于,所述镂空部设于所述绝缘隔离结构与所述第二掺杂区之间的漂移区上方。
- 根据权利要求1所述的半导体器件,其特征在于,所述第一导电类型为N型,所述第二导电类型为P型。
- 根据权利要求7所述的半导体器件,其特征在于,所述第一掺杂区为漏极区,所述第二掺杂区为源极区。
- 根据权利要求13所述的半导体器件,其特征在于,所述漏极区和源极区为N+区,所述衬底引出区为P+区。
- 根据权利要求1所述的半导体器件,其特征在于,所述半导体器件为横向扩散金属氧化物半导体器件。
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