WO2021218372A1 - 一种驱动电路、驱动ic以及驱动系统 - Google Patents

一种驱动电路、驱动ic以及驱动系统 Download PDF

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Publication number
WO2021218372A1
WO2021218372A1 PCT/CN2021/078961 CN2021078961W WO2021218372A1 WO 2021218372 A1 WO2021218372 A1 WO 2021218372A1 CN 2021078961 W CN2021078961 W CN 2021078961W WO 2021218372 A1 WO2021218372 A1 WO 2021218372A1
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Prior art keywords
hhmt
hemt
circuit
signal output
output port
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PCT/CN2021/078961
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English (en)
French (fr)
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黎子兰
张树昕
陈勘
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广东致能科技有限公司
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Priority to US17/594,844 priority Critical patent/US11870434B2/en
Priority to EP21783127.0A priority patent/EP3940746A4/en
Priority to KR1020227031850A priority patent/KR20220140621A/ko
Priority to JP2022554421A priority patent/JP7450060B2/ja
Publication of WO2021218372A1 publication Critical patent/WO2021218372A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption

Definitions

  • This application relates to the technical field of electronic circuits, and in particular to a driving circuit, a driving IC, and a driving system.
  • BJT Bipolar Junction Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the drive circuit In power electronic products, for the use of fully-controlled semiconductor high-voltage power devices, the drive circuit is an indispensable key part.
  • the current drive circuit is generally large in size and cannot be effectively integrated.
  • the current drive circuit has the problems of large volume and low integration.
  • the purpose of the present application is to provide a driving circuit, a driving IC, and a driving system to solve the problem of large volume and low integration of the driving circuit in the prior art.
  • the present application provides a drive circuit
  • the drive circuit includes a control module and a drive signal output module
  • the control module is electrically connected to the drive signal output module
  • the drive signal output module is connected to the drive signal output module.
  • the device is electrically connected; among them,
  • the driving signal output module includes at least two transistors, and at least two of the transistors are epitaxially grown on the same substrate;
  • the control module is used to control the off state of at least two of the transistors to control the working state of the device to be driven.
  • the present application provides a driver IC.
  • the driver IC includes at least two transistors, and at least two of the transistors are epitaxially grown on the same substrate.
  • the present application provides a drive system, the drive system includes a device to be driven and the above-mentioned drive circuit, the drive circuit is electrically connected to the device to be driven, wherein the drive circuit is used to control the The working state of the device to be driven, and the device to be driven includes a nitride device.
  • FIG. 1 is a schematic diagram of a module of the driving circuit provided by this application.
  • FIG. 2 is a schematic diagram of a structure of the driving signal output module provided by this application.
  • Figures 3 to 8 are schematic diagrams of corresponding structures when processing the substrate provided by this application.
  • FIG. 9 is a schematic cross-sectional view of the driving signal output module provided by this application.
  • FIG. 10 is a schematic diagram of the FOM value of the power device provided by this application.
  • FIG. 11 is a schematic diagram of circuit symbols of the power devices HEMT and HHMT provided by this application.
  • FIG. 12 is a schematic circuit diagram of a single-phase half-bridge circuit provided by this application.
  • FIG. 13 is a schematic diagram of another circuit of the single-phase half-bridge circuit provided by this application.
  • FIG. 14 is a schematic circuit diagram of a single-phase circuit provided by this application.
  • FIG. 15 is a schematic circuit diagram of a two-phase circuit provided by this application.
  • FIG. 16 is a schematic diagram of a three-phase circuit provided by this application.
  • FIG. 17 is a schematic circuit diagram of a dual-output half-bridge driving circuit provided by this application.
  • FIG. 18 is a schematic diagram of a module of the control module provided by this application.
  • FIG. 19 is a schematic circuit diagram of a driving circuit provided by this application.
  • FIG. 20 is a schematic diagram of a module of the driving circuit provided by this application.
  • 100-control module 200-drive signal output module.
  • orientation or positional relationship indicated by the terms “upper”, “lower”, “inner”, “outer”, etc. are based on the orientation or positional relationship shown in the drawings, or the The orientation or positional relationship usually placed when the application product is used is only for the convenience of describing the application and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, therefore It cannot be understood as a restriction on this application.
  • the drive circuit In power electronic products, for the use of fully-controlled semiconductor high-voltage power devices, the drive circuit is an indispensable key part.
  • the current drive circuit is generally large in size and cannot be effectively integrated.
  • the present application provides a driving circuit, which realizes the integration of devices by growing at least two transistors on the same substrate, thereby realizing the miniaturization of the driving circuit.
  • the drive circuit includes a control module 100 and a drive signal output module 200, the control module 100 is electrically connected to the drive signal output module 200, and the drive signal output module 200 is electrically connected to the drive signal output module 200.
  • the device to be driven is electrically connected; wherein the driving signal output module 200 includes at least two transistors, and the at least two transistors are epitaxially grown on the same substrate.
  • the control module 100 is used to control the off state of the at least two transistors to control The working status of the device to be driven.
  • the miniaturization of the driving signal output module 200 can be realized, and thus the miniaturization of the entire driving circuit can be realized.
  • control module 100 will send a corresponding control signal, and then by controlling the driving signal output module 200, the effect of controlling the device to be driven is achieved.
  • the device to be driven provided in this application can be a power tube, and the number of devices to be driven is not limited in this application, and it can be one, two or three. It is understandable that the output terminal of the driving signal output module 200 is electrically connected to the grid of the power tube, thereby providing a driving signal for the operation of the power tube.
  • the driving signal output module 200 provided in the present application will be exemplarily described below:
  • this application does not limit the types of transistors used.
  • all of them may be N-type transistors, or all of them may be P-type transistors, or some of them may be N-type transistors, and some of them may be P-type transistors.
  • Transistor In addition, the transistors provided in this application are all normally-off transistors.
  • the transistor can be a triode, a MOS (Metal Oxide Semiconductor Field Effect Transistor, a metal oxide half field effect transistor) or a HEMT (High Electron Mobility Transistor). ), HHMT (High Hole Mobility Transistor).
  • MOS Metal Oxide Semiconductor Field Effect Transistor, a metal oxide half field effect transistor
  • HEMT High Electron Mobility Transistor
  • HHMT High Hole Mobility Transistor
  • the at least two transistors include at least one N-type MOS transistor and at least one P-type MOS tube, the at least one N-type MOS tube and the at least one P-type MOS tube are both epitaxially grown through the same substrate; as another possible implementation in this application, the at least two transistors include at least One N-type transistor and at least one P-type transistor, and the at least one N-type transistor and at least one P-type transistor are epitaxially grown on the same substrate; as another possible implementation in this application, the at least two The transistor includes at least one HEMT and at least one HHMT, and the at least one HEMT and at least one HHMT are epitaxially grown on the same substrate.
  • the driving signal output module 200 includes at least one HEMT and at least one HHMT as an example for description. Since HEMT and HHMT are of different conductivity types, the driving signal output module 200 may be considered as a complementary module.
  • the substrate when at least one HEMT and at least one HHMT are epitaxially grown on the same substrate, the substrate may include a vertical interface, and the HEMT and the HHMT are located on both sides of the vertical interface.
  • the integration of HEMT and HHMT can be realized, miniaturization can be realized, and the growth process is simple, and the production efficiency is high.
  • the growth of HEMT and HHMT can be realized by using the difference in crystal orientation of the vertical interface on the substrate.
  • the substrate For example, please refer to FIG. 2.
  • At least one HEMT and at least one HHMT share the same channel layer and barrier layer, and the channel layer is arranged outside the vertical interface.
  • the AlN nucleation layer and the buffer layer shown in FIG. 2 can be used as Vertical interface.
  • the barrier layer is arranged on the outside of the channel layer, the interface between the channel layer and the barrier layer includes a first polarity surface and a second polarity surface, the first polarity surface and the second polarity surface are respectively located at the vertical interface
  • the first polar surface is used to provide two-dimensional electron gas
  • the second polar surface is used to provide two-dimensional hole gas
  • the HHMT device is formed on the left side of the vertical interface, and on the right side of the vertical interface Form a HEMT device.
  • the HEMT and the HHMT do not need to share the same channel layer and barrier layer, which is not limited in this application.
  • the substrate needs to be processed first to obtain the required substrate structure.
  • the (111) plane in the vertical direction can be obtained on the (110) plane by anisotropic etching.
  • the substrate can be sapphire, 4H-SiC and other substrates with hexagonal symmetry on the (0001) plane.
  • Substrates such as sapphire and 4H-SiC are commonly used for GaN materials. Growth surface, which can obtain higher GaN crystal quality.
  • common planes perpendicular to the (0001) plane include m plane (1-100), a plane (11-20), and so on. Therefore, the (0001) plane in the vertical direction can be obtained on the substrate having these surfaces and become the growth plane of the GaN-based epitaxial layer.
  • substrates are only examples. In practical applications, other substrates can also be used, such as Al2O3, SiC, etc., as long as a surface with hexagonal symmetry can be obtained on the surface perpendicular to the substrate- Such as Si (111) surface, Al2O3 (0001) surface, 4H-SiC (0001) surface, etc., can realize the same structure of the device.
  • the wafer can be taken out after the AlN is grown, and through anisotropic etching, only the AlN nucleation layer on the vertical plane is retained and the AlN in other places is removed.
  • the AlN on the vertical plane is weakly bombarded by the ions while the AlN on the other planes is bombarded more strongly, so that only the AlN on the vertical plane can be retained.
  • Vertical interface on the substrate since the silicon (111) surface is more likely to cause the nucleation of AlN compared to amorphous SiO2 or SiN and other insulating materials, under a suitable growth process, AlN can also be nucleated only on the vertical (111) silicon surface. And growth, but the process window is smaller.
  • GaN can nucleate and grow on the Al2O3 (0001) plane, which can avoid the above problems.
  • the processing of the substrate can be to first etch a long structure with a (111) plane on the substrate, for example, in An insulating layer is formed on the upper surface of the substrate.
  • the insulating layer may be a SiO2 layer formed by thermal oxidation or vapor deposition.
  • the thickness of the insulating layer is about 0.5 micrometers.
  • the insulating layer is lithographically performed using a mask to form insulating layers arranged at intervals. Then the substrate is etched. Due to the barrier of the insulating layer, the substrate below the insulating layer will not be etched away, and the area without the insulating layer will be etched out of grooves, thereby forming a vertical multiplicity. There are two grooves, and the grooves are arranged at intervals. Wherein, the sidewall of the groove has a hexagonal symmetrical lattice structure, such as the (111) plane of Si.
  • a sacrificial layer is deposited on the surface of the substrate.
  • the surface of the insulating layer, the surface of the bottom of the groove, and the surface of the sidewall of the groove are all covered with the sacrificial layer.
  • the material of the sacrificial layer may be silicon nitride.
  • dry etching is performed to remove the sacrificial layer on the surface of the insulating layer and the bottom surface of the groove, while leaving the sacrificial layer on the sidewall surface of the groove.
  • an insulating layer can be formed on the bottom surface of the trench again, and the material of the insulating layer can still be SiO2.
  • an insulating layer is formed on the surface of the substrate and the surface of the bottom of the groove, which can avoid the incompatibility between gallium atoms and the silicon substrate during the subsequent growth of nitride semiconductors, and avoid the phenomenon of melt-back.
  • the insulating layer on the bottom surface of the groove can also effectively block the leakage current between the nitride semiconductor and the silicon substrate, and reduce the parasitic capacitance caused by the silicon substrate.
  • the sacrificial layer on the side surface of the groove is removed by using the etching selection ratio of the sacrificial layer and the insulating layer.
  • the upper surface of the substrate and the bottom surface of the groove are both covered with an insulating layer.
  • the thickness of the insulating layer on the upper surface of the substrate and the bottom surface of the groove is the same.
  • the side wall of the groove is exposed.
  • an oxidation process can be used again to form a thin insulating layer on the sidewall of the groove, wherein the thickness of the insulating layer on the sidewall of the groove needs to be smaller than the upper surface of the substrate and the bottom surface of the groove The thickness of the insulating layer. This is to satisfy that when the insulating layer on the sidewall is subsequently removed, there is still a certain thickness of insulating layer on the bottom of the substrate and the bottom surface of the groove to protect the substrate.
  • These insulating layers can avoid the incompatibility between gallium atoms and the silicon substrate during the subsequent growth of nitride semiconductors, and avoid the phenomenon of melt-back, which is indispensable for the production of nitride semiconductor devices on the silicon substrate.
  • part of the insulating layer on the sidewall of the groove is removed. It should be noted that when the part of the insulating layer on the sidewall is removed, the insulating layer on the upper surface of the substrate will be removed at the same time, but due to the insulation on the upper surface of the substrate The thickness of the layer is much greater than the thickness of the insulating layer on the sidewall of the groove, so the insulating layer on the upper surface of the substrate will only be etched to a certain thickness, but it will not be completely removed.
  • the nucleation layer may also be GaN. At this time, it is easier to achieve nucleation only on the exposed substrate surface through process adjustment.
  • the AlN nucleation layer can be used as the core to fabricate the drive signal output module described in this application.
  • the first nitride semiconductor layer can be epitaxially grown along the nucleation layer side. It is understandable that due to the existence of the groove, the groove is filled with the first nitride semiconductor layer after growth. It can be understood that, before the first nitride semiconductor layer is grown, a buffer layer may be deposited first, or the buffer layer may not be formed.
  • At least one P-type doped region and/or N-type doped region may be formed in the first nitride semiconductor layer, thereby depleting the gate Two-dimensional carrier gas near the electrode.
  • the first nitride semiconductor layer forms at least one P-type doped region, which at least partially overlaps the gate electrode in the projection direction of the ⁇ 0001> crystal orientation, and is electrically coupled with the two-dimensional carrier gas, thereby substantially depleting the Two-dimensional carrier gas of the first conductivity type to realize the transistor as a normally-off type.
  • the insulating layer on the surface of the substrate and a part of the substrate under the insulating layer can be taken out. At this time, a groove structure is still formed on the substrate. Then, a second nitride semiconductor layer is epitaxially grown. Among them, the first nitride semiconductor layer is the channel layer, and the second nitride semiconductor layer is the barrier layer. Finally, the electrodes are fabricated to complete the fabrication of the driving signal output module described in this application.
  • the crystal orientations on both sides of the vertical interface are (000-1) and (0001) respectively, and the opposite direction of (0001) is (000-1).
  • the channel The layer and the barrier layer will form 2DHG (two-dimensional hole gas)
  • the channel layer and the barrier layer will form 2DEG (two-dimensional electron gas).
  • the HEMT device can be formed by forming the source, drain, and gate on the 2DEG side
  • the HHMT device can be formed by forming the source, drain, and gate on the 2DHG side.
  • the source and drain should form a good ohmic contact with 2DEG or 2DHG, that is, the smaller the contact resistance, the better.
  • the leakage current to the channel should be minimized: Schottky contact between the gate and the barrier layer can be formed, or an insulating layer can be formed under the gate electrode to reduce the leakage current, that is, the gate is formed before the gate electrode is formed. Insulation.
  • the source and drain can usually be made of the same material, but because the ohmic contact metal of HEMT and HHMT are usually different, the source and drain material of HEMT and the source and drain of HHMT are usually different. Very often different. Since the requirements for the work function are usually different, the gate material of the HEMT and the gate of the HHMT are usually also different.
  • the fin structure formed in this way has a vertical channel structure, and by increasing the height of the channel, the effective conduction area can be significantly increased, the conduction resistance is reduced, and the production cost is reduced.
  • the above-mentioned SiO2 insulating layer may also be unnecessary. This is mainly because Ga atoms are compatible with Al2O3 or SiC, and there is no reflow phenomenon. Under suitable process conditions, it is easier to nucleate and grow on Al2O3 (0001) or SiC (0001) with hexagonal symmetry. Therefore, this substrate with a vertical growth surface naturally has the ability to grow in selected areas. Of course, if amorphous insulating layers such as SiO2 and SiN are still used, the process window for this selective growth is larger and more controllable.
  • Fig. 9 is a schematic cross-sectional view of a situation where one HHMT and HEMT are prepared on the left and right sides of the vertical interface provided by this application.
  • HHMT and/or HEMT can be grown on the same substrate to realize device integration.
  • the material for making the at least one HEMT and the at least one HHMT may be a group III nitride.
  • the working state of low-voltage power devices is mainly divided into three states, the off state, the instantaneous switching state of the switch, and the on state.
  • the loss of the low-voltage power device itself and the operating frequency seriously affect the power consumption and volume of the entire power electronic product.
  • the loss of the low-voltage power device itself is divided into the loss in the turn-on state and the loss in the instant switching state of the switch; the turn-on loss is mainly related to the current and the on-resistance value Ron.
  • the turn-on loss is mainly related to the current and the on-resistance value Ron.
  • the switching loss is mainly related to the operating frequency and the parasitic capacitance Cp of the device. In high-frequency operation, the parasitic capacitance Cp is mainly reduced by reducing the effective area of the bare band inside the device.
  • the product value of Ron and Cp is usually used as an important performance index to measure low-voltage power devices, and the product value of Ron and Cp is usually referred to as low-voltage power.
  • the FOM value (figure of merit) of the device If the low-voltage power device can work in a high-frequency and high-current state when its own loss is very low, then the entire power electronic circuit system can achieve high-frequency operation. At high frequencies, passive large-volume components such as inductors and transformers in the circuit can be doubled in size, thereby achieving low power consumption and miniaturization of the product.
  • this application shows a schematic diagram of the FOM value of the power device. It can be seen from the figure that, compared to the conventional Si material transistor, the ROM value of the transistor device using Group III nitride in this application is smaller. Moreover, by growing HHMT and/or HEMT on the same substrate, the parasitic capacitance, inductance, etc. can be further reduced, the operating frequency of the device can be increased, and the loss can be reduced. In other words, through the improvement of materials and the method of growing HHMT and/or HEMT on the same substrate, the present application jointly achieves the effect of reducing device loss.
  • the driving signal output module 200 provided in the present application can be manufactured.
  • the drive circuit generally includes isolated drive IC devices and non-isolated drive IC devices.
  • the isolated drive IC devices mainly include isolated single-channel output devices and isolated half-bridge output devices.
  • Non-isolated drive IC devices mainly include single-channel output devices and dual-channel output devices. Output devices, multiple output devices and half-bridge output devices, etc.
  • the driving signal output module 200 may include a single-phase half-bridge circuit, a two-phase half-bridge circuit, and a three-phase half-bridge circuit.
  • FIG. 11 illustrates the circuit symbols of the High Electron Mobility Transistor (HEMT) and the High Hole Mobility Transistor (HHMT).
  • the HEMT includes a first source electrode 101, a first drain electrode 103, a first gate electrode 102, and a first body electrode 104. Between the first source electrode 101 and the first drain electrode 103 is a two-dimensional electron gas (Two-Dimensional Electron Gas).
  • Electron Gas, 2DEG Electron Gas, 2DEG
  • the HHMT includes a second source electrode 201, a second drain electrode 203, a second gate electrode 202, and a second body electrode 204, wherein between the second source electrode 201 and the second drain electrode 203 is a two-dimensional hole gas (Two- Dimensional Hole Gas, 2DHG) channel 205, hollow spheres represent holes.
  • the first gate electrode 102 and the second gate electrode 202 control the on and off of the HEMT and HHMT conductive channels, respectively.
  • the driving signal output module 200 when the driving signal output module 200 includes a single-phase half-bridge circuit, the driving signal output module 200 includes a first HHMT and a first HEMT, the drains of the first HHMT and the first HEMT are both connected to the output port, and The output port is used to electrically connect with the device to be driven;
  • the driving signal output module 200 includes a dual-phase half-bridge circuit
  • the driving signal output module 200 includes a first HHMT, a first HEMT, a second HHMT, and a second HEMT.
  • the first HHMT, the second HHMT, the first HEMT, and the second HEMT The drains of the HEMT are all connected to the output port;
  • the driving signal output module 200 includes a three-phase half-bridge circuit
  • the driving signal output module 200 includes a first HHMT, a first HEMT, a second HHMT, a second HEMT, a third HHMT, and a third HEMT.
  • the drains of the HEMT, the second HHMT, the second HEMT, the third HHMT, and the third HEMT are all connected to the output port.
  • the output port includes a first output port and a second output port, and both the first output port and the second output port are electrically connected to the same device to be driven.
  • the driving signal output module 200 when the driving signal output module 200 includes a single-phase half-bridge circuit, the driving signal output module 200 further includes a first additional circuit and a second additional circuit.
  • the drain of the first HHMT passes through the first additional circuit and the first additional circuit.
  • the output port is electrically connected
  • the drain of the first HEMT is electrically connected to the second output port through the second additional circuit
  • the first additional circuit and the second additional circuit respectively regulate the conduction time of the first HHMT and the first HEMT.
  • the first additional circuit and the second additional circuit may include devices such as diodes and capacitors, so as to adjust the on-time of the HHMT.
  • the resistance values of the first additional circuit and the second additional circuit are different.
  • the turn-on and turn-off time of the device can be controlled. For example, when the resistance value of the first additional circuit is 100 ⁇ , the device conduction time requires 100ms; and when the resistance value of the first accessory circuit is 200 ⁇ , the device conduction time requires 200ms. At the same time, on this basis, more additional circuits can be set, and the additional circuit is connected in parallel with the first additional circuit, and the resistance value of the additional circuit is also different, so that the conduction time of different devices can be controlled when they are turned on. Can vary.
  • the first additional circuit and the second additional circuit described in the present application may be a resistor, or may be a circuit composed of multiple resistors in series or in parallel.
  • the additional circuit may also be other energy-consuming or non-energy-consuming devices, which are not limited in this application.
  • the driving signal output module 200 When the driving signal output module 200 includes a two-phase half-bridge circuit, the driving signal output module 200 further includes a third additional circuit and a fourth additional circuit.
  • the drain of the first HHMT is electrically connected to the first output port through the first additional circuit
  • the drain of the second HHMT is electrically connected to the first output port through the third additional circuit
  • the drain of the first HEMT is electrically connected to the second output port through the second additional circuit
  • the drain of the second HEMT is electrically connected to the second output port through the fourth additional circuit.
  • the second output port is electrically connected, wherein the resistance values of the third additional circuit and the fourth additional circuit are different.
  • the third additional circuit and the fourth additional circuit respectively regulate the conduction time of the second HHMT and the second HEMT.
  • the driving signal output module 200 When the driving signal output module 200 includes a three-phase half-bridge circuit, the driving signal output module 200 further includes a fifth additional circuit and a sixth additional circuit.
  • the drain of the first HHMT is electrically connected to the first output port through the first additional circuit
  • the drain of the second HHMT is electrically connected to the first output port through the third additional circuit
  • the drain of the third HHMT is electrically connected to the first output port through the fifth additional circuit
  • the drain of the first HEMT is electrically connected to the first output port through the second additional circuit.
  • the second output port is electrically connected, the drain of the second HEMT is electrically connected to the second output port through the fourth additional circuit, and the drain of the third HEMT is electrically connected to the second output port through the sixth additional circuit, wherein the fifth additional circuit The resistance of the circuit is different from that of the sixth additional circuit.
  • the fifth additional circuit and the sixth additional circuit respectively regulate the conduction time of the third HHMT and the third HEMT.
  • the driving signal output module 200 may include a single-phase circuit, a two-phase circuit, and a three-phase circuit.
  • the driving signal output module 200 when the driving signal output module 200 includes a single-phase circuit, the driving signal output module 200 includes a first HHMT, a first HEMT, and a fourth HHMT.
  • the first HHMT and the fourth HHMT are connected in parallel, and the first HHMT and the fourth HHMT
  • the drains of the fourth HHMT and the first HEMT are all connected to the output port.
  • the first HHMT and the fourth HHMT it is also possible to control the turn-on and turn-off time of the device to be driven.
  • the first HHMT can be controlled to be turned on to achieve pre-start, and then the first HHMT and the fourth HHMT are controlled to be turned on at the same time, thereby shortening the turn-on time of the device to be driven.
  • the drive current can also be increased, which is particularly advantageous for HHMTs with relatively low drive currents.
  • the driving signal output module 200 when the driving signal output module 200 includes a two-phase circuit, the driving signal output module 200 includes a first HHMT, a first HEMT, a second HHMT, a second HEMT, a fourth HHMT, and a fifth HHMT.
  • the second HHMT, the fourth HHMT, and the fifth HHMT are connected in parallel, and the drains of the first HHMT, the first HEMT, the second HHMT, the second HEMT, the fourth HHMT, and the fifth HHMT are all connected to the output port;
  • the driving signal output module 200 when the driving signal output module 200 includes a three-phase circuit, the driving signal output module 200 includes a first HHMT, a first HEMT, a second HHMT, a second HEMT, a third HHMT, a third HEMT, and a fourth HHMT.
  • the fifth HHMT and the sixth HHMT, the first HHMT, the second HHMT, the third HHMT, the fourth HHMT, the fifth HHMT, and the sixth HHMT are connected in parallel, and the first HHMT, the first HEMT, the second HHMT, the second HEMT, The drains of the third HHMT, the third HEMT, the fourth HHMT, the fifth HHMT, and the sixth HHMT are all connected to the output port.
  • the drive signal output module 200 includes a dual-output half-bridge drive circuit, where:
  • the driving signal output module 200 includes a first HHMT, a first HEMT, a second HHMT, and a second HEMT.
  • the drains of the first HHMT and the first HEMT are all connected to the first output port, and the drains of the second HHMT and the second HHMT Connected to the second output port; wherein, the first output port is used to connect to a device to be driven, and the second output port is used to connect to another device to be driven.
  • the drive signal output module 200 includes a dual output half-bridge drive circuit
  • two devices to be driven can form an upper and lower half bridge, and the purpose of controlling the upper and lower half bridges can be controlled by the drive signal output module 200.
  • the number of input ports can also be greater to drive more devices to be driven, which is not limited in this application.
  • the drive signal output module 200 includes multiple devices, for example, in the above implementation, when the drive signal output module 200 includes a three-phase half-bridge circuit, three HHMT devices and three HEMT devices are required, which can be used in This is achieved by fabricating 3 HHMT devices on one side of the vertical interface of the substrate and 3 HEMT devices on the other side.
  • a non-isolated gate drive circuit such as a low-end gate drive and a half-bridge gate drive circuit, etc.
  • an isolated drive circuit can be fabricated, such as an isolated gate drive circuit.
  • Gate drive circuit includes isolation devices, such as capacitors and other isolation devices.
  • the control module 100 includes a drive signal input module, a control signal input module, a power supply module, a protection module, and a main control module, wherein the power supply module is electrically connected to the drive signal output module 200 ;
  • the driving signal input module, the control signal input module, and the protection module are all electrically connected to the main control module, and the main control module is electrically connected to the driving signal output module 200;
  • the main control module is used to input the module according to the driving signal, the control signal input module and the protection The signal of the module controls the off state of the drive signal output module 200.
  • the main control module can be a circuit composed of an AND gate, a non-inverter, and an inverter.
  • the control signal input module (not shown in the figure) and the drive signal input module are electrically connected.
  • the drive signal input module can be electrically connected to the controller and other devices and used to receive corresponding control signals
  • the control signal input module can be a controller or other device, which is electrically connected to the AND gate and used to control the AND gate to start or stop.
  • the protection module provided by the present application includes an over-temperature protection module and a low-voltage protection module, and both the over-temperature protection module and the low-voltage protection module are electrically connected to the AND gate and input signals to the AND gate.
  • the AND gate controls the drive signal output module 200 to work.
  • the drive circuit provided by the present application can also realize the integration of the control module 100 and the drive signal output module 200, and since the drive signal output module 200 has been integrated once, when the control module 100 and the drive signal output module 200 are integrated , Its integrated volume is smaller.
  • the present application also provides a driver IC.
  • the driver IC includes at least two transistors, and the at least two transistors are epitaxially grown on the same substrate.
  • the driver IC provided by the present application can realize the integration of devices based on a unified substrate, thereby enabling miniaturization.
  • the present application also provides a driving system that includes a device to be driven and the above-mentioned driving circuit, the driving circuit is electrically connected to the device to be driven, wherein the driving circuit is used to control the operation of the device to be driven State, and the device to be driven includes a nitride device.
  • the driving circuit and the device to be driven are integrated on the same chip.
  • the driving circuit and the device to be driven are integrated on the same chip.
  • the present application provides a drive circuit, a drive IC, and a drive system.
  • the drive circuit includes a control module and a drive signal output module, the control module is electrically connected to the drive signal output module, and the drive signal output module is used to communicate with The device to be driven is electrically connected; wherein the drive signal output module includes at least two transistors, and the at least two transistors are epitaxially grown on the same substrate; the control module is used to control the off state of the at least two transistors to control the to-be-driven The working status of the device. Since the transistors in the driving signal output module provided by the present application are grown on the same substrate, they are integrated, the driving circuit can be made smaller, and the goals of miniaturization and improved integration are achieved.
  • the functional modules in this application may be integrated together to form an independent part, or each module may exist alone, or two or more modules may be integrated to form an independent part.
  • the present application provides a driving circuit, a driving IC, and a driving system.
  • the driving circuit is small in size and high in integration.

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Abstract

本申请提供了一种驱动电路、驱动IC以及驱动系统，涉及电子电路技术领域。该驱动电路包括控制模块与驱动信号输出模块，控制模块与驱动信号输出模块电连接，且驱动信号输出模块用于与待驱动器件电连接；其中，驱动信号输出模块包括至少两个晶体管，且至少两个晶体管通过同一衬底外延生长而成；控制模块用于控制至少两个晶体管的关断状态，以控制待驱动器件的工作状态。本申请提供的驱动电路、驱动IC以及驱动系统具有实现了小型化及提高了集成度的优点。

Description

一种驱动电路、驱动IC以及驱动系统
相关申请的交叉引用
本申请要求于2020年4月29日提交中国专利局的申请号为202010358117.2、名称为“一种驱动电路、驱动IC以及驱动系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子电路技术领域，具体而言，涉及一种驱动电路、驱动IC以及驱动系统。
背景技术
作为全控型半导体高压功率器件的种类，有BJT(Bipolar Junction Transistor)、IGBT(Insulated Gate Bipolar Transistor)等功率半导体器件，以及现在的MOSFET(Metal Oxide Semiconductor Field Effect Transistor)器件等，目前正在向Ⅲ族氮化物材料形成的第三代半导体功率器件GaN FET(Gallium Nitride)等快速演进。
在电力电子产品中，对于全控型半导体高压功率器件的使用来说，驱动电路是其必不可少的关键部分，然而，目前的驱动电路一般体积较大，无法有效的实现集成化。
综上所述，目前的驱动电路存在体积较大、集成度较低的问题。
发明内容
本申请的目的在于提供一种驱动电路、驱动IC以及驱动系统，以解决现有技术中驱动电路体积较大、集成度较低的问题。
为了实现上述目的，本申请采用的技术方案如下：
第一方面，本申请提供了一种驱动电路，所述驱动电路包括控制模块与驱动信号输出模块，所述控制模块与所述驱动信号输出模块电连接，且所述驱动信号输出模块与待驱动器件电连接；其中，
所述驱动信号输出模块包括至少两个晶体管，且至少两个所述晶体管通过同一衬底外延生长而成；
所述控制模块用于控制至少两个所述晶体管的关断状态，以控制所述待驱动器件的工作状态。
第二方面，本申请提供了一种驱动IC，所述驱动IC包括至少两个晶体管，且至少两个所述晶体管通过同一衬底外延生长而成。
第三方面，本申请提供一种驱动系统，所述驱动系统包括待驱动器件与上述的驱动电路，所述驱动电路与所述待驱动器件电连接，其中，所述驱动电路用于控制所述待驱动器件的工作状态，且所述待驱动器件包括氮化物器件。
为使本申请的上述目的、特征和优点能更明显易懂，下面参照附图对本申请的可选的实施方式进行详细说明。
附图说明
为了更清楚地说明本申请的技术方案，下面将对所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本申请的某些实现方式，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它相关的附图。
图1为本申请提供的驱动电路的一种模块示意图。
图2为本申请提供的驱动信号输出模块的一种结构示意图。
图3-图8为本申请提供的对衬底进行处理时对应的结构示意图。
图9为本申请提供的驱动信号输出模块的剖面示意图。
图10为本申请提供的功率器件的FOM值的示意图。
图11为本申请提供的功率器件HEMT与HHMT的电路符号示意图。
图12为本申请提供的单相半桥电路的一种电路示意图。
图13为本申请提供的单相半桥电路的另一种电路示意图。
图14为本申请提供的单相电路的一种电路示意图。
图15为本申请提供的双相电路的一种电路示意图。
图16为本申请提供的三相电路的一种电路示意图。
图17为本申请提供的双路输出半桥驱动电路的一种电路示意图。
图18为本申请提供的控制模块的一种模块示意图。
图19为本申请提供的驱动电路的一种电路示意图。
图20为本申请提供的驱动电路的一种模块示意图。
图中：100-控制模块；200-驱动信号输出模块。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合本申请中的附图，对本申请中的技术方案进行清楚、完整地描述，显然，所描述的实现方式是本申请一部分方式，而不是全部的方式。通常在此处附图中描述和示出的本申请中的组件可以以各种不同的配置来布置和设计。
因此，以下对在附图中提供的本申请的实施方式的详细描述并非旨在限制要求保护的本申请的范围，而是仅仅表示本申请的选定实施方式。基于本申请中的实施方式，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。同时，在本申请的描述中，术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
在本申请的描述中，需要说明的是，术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，或者是该申请产品使用时惯常摆放的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
在本申请的描述中，还需要说明的是，除非另有明确的规定和限定，术语“设置”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
下面结合附图，对本申请的可选的实施方式作详细说明。在不冲突的情况下，下述的实施方式中的特征可以相互组合。
在电力电子产品中，对于全控型半导体高压功率器件的使用来说，驱动电路是其必不可少的关键部分，然而，目前的驱动电路一般体积较大，无法有效的实现集成化。
有鉴于此，本申请提供了一种驱动电路，通过在同一衬底上生长至少两个晶体管的方式，实现器件的集成，进而实现驱动电路的小型化。
下面对本申请提供的驱动电路进行示例性说明：
作为一种可选的实现方式，请参阅图1及图20，该驱动电路包括控制模块100与驱动信号输出模块200，控制模块100与驱动信号输出模块200电连接，且驱动信号输出模块 200与待驱动器件电连接；其中，驱动信号输出模块200包括至少两个晶体管，且至少两个晶体管通过同一衬底外延生长而成，控制模块100用于控制至少两个晶体管的关断状态，以控制待驱动器件的工作状态。
通过在同一衬底上外延生长驱动信号输出模块200的方式，能够实现驱动信号输出模块200的小型化，进而实现整个驱动电路的小型化。
可以理解地，当需要控制待驱动器件开始或停止工作时，控制模块100会发送相应的控制信号，进而通过控制驱动信号输出模块200的方式，达到控制待驱动器件的效果。
需要说明的是，本申请提供的待驱动器件可以为功率管，并且，本申请对待驱动器件的数量也并不做限定，其可以为1个，也可以为2个或者3个。可以理解地，驱动信号输出模块200的输出端与功率管的栅极电连接，进而提供功率管工作的驱动信号。
下面对本申请提供的驱动信号输出模块200进行示例性说明：
其中，本申请并不对使用的晶体管的类型进行限定，例如，在该至少两个晶体管中，可以全部为N型晶体管，也可以全部为P型晶体管，或者部分为N型晶体管，部分为P型晶体管。并且，本申请提供的晶体管均为常关型晶体管。
同时，本申请也并不对晶体管的种类进行限定，例如，晶体管可以为三极管、MOS管(Metal Oxide Semiconductor Field Effect Transistor，金氧半场效晶体管)或者HEMT(High Electron Mobility Transistor，高电子迁移率晶体管)、HHMT(高空穴迁移率晶体管)。
例如，当驱动信号输出模块200中部分为N型晶体管，部分为P型晶体管时，作为本申请中的一种可能的实现方式，该至少两个晶体管中包括至少一个N型MOS管与至少一个P型MOS管，该至少一个N型MOS管与至少一个P型MOS管均通过同一衬底外延生长而成；作为本申请中的另一种可能的实现方式，该至少两个晶体管中包括至少一个N型三极管与至少一个P型三极管，且该至少一个N型三极管与至少一个P型三极管通过同一衬底外延生长而成；作为本申请中的另一种可能的实现方式，该至少两个晶体管中包括至少一个HEMT与至少一个HHMT，且该至少一个HEMT与至少一个HHMT通过同一衬底外延生长而成。
下面以驱动信号输出模块200中包括至少一个HEMT与至少一个HHMT为例进行说明，其中，由于HEMT与HHMT为不同的导电类型，因此该驱动信号输出模块200可被认为是互补型模块。
可选的，本申请中，同一衬底上外延生长至少一个HEMT与至少一个HHMT时，衬底上可以包括垂直界面，HEMT与HHMT分别位于垂直界面的两侧。通过将HEMT与HHMT分别设置于垂直界面两侧的方式，可以实现HEMT与HHMT的集成，实现小型化，且生长工艺简单，制作效率高。
作为一种可选的实现方式，可以利用衬底上的垂直界面的晶向的不同来实现HEMT与HHMT的生长。例如，请参阅图2，至少一个HEMT与至少一个HHMT共用同一沟道层与势垒层，沟道层设置于垂直界面的外侧，其中，图2所示的AlN成核层与缓冲层可作为垂直界面。势垒层设置于沟道层的外侧，沟道层与势垒层之间的界面包括第一极性面与第二极性面，第一极性面与第二极性面分别位于垂直界面的两侧，其中，第一极性面用于提供二维电子气，第二极性面用于提供二维空穴气，进而在垂直界面的左侧形成HHMT器件，在垂直界面的右侧形成HEMT器件。可选地，HEMT与HHMT也可无需共用同一沟道层与势垒层，本申请对此并不进行限定。
下面以一可选的具体制备工艺进行说明。
首先，为了实现在垂直界面的两侧分别制作HEMT与HHMT，需要先对衬底进行处理，以获取所需的衬底结构。以硅衬底为例，可以在(110)面上通过各向异性腐蚀的等方式获取垂直方向上的(111)面。
其中，本申请对于衬底的材料不做限定，例如，衬底可以选用蓝宝石、4H-SiC等(0001)面具有六角对称性的衬底，蓝宝石、4H-SiC等衬底是GaN材料的常用生长面，由此可以获得较高的GaN晶体质量。并且，常见的与(0001)面垂直的面有m面(1-100)、a面(11-20)等。因此，在具有这些表面的衬底上可获得垂直方向上的(0001)面并成为GaN基外延层的生长面。
需要说明的是，上述衬底仅为举例，在实际应用中，也可采用其它衬底，例如采用Al2O3、SiC等衬底，只要可在垂直于衬底的表面获得具有六角对称性的面-如Si(111)面、Al2O3(0001)面、4H-SiC(0001)面等，都可以实现同样结构的器件。
还需要说明的是，对于硅衬底，由于Ga原子的回熔(melt-back)效应，必须采用AlN等成核层。但是由于AlN选区生长能力较弱，所以在绝缘材料上也可能有一定的生长，这对器件有不利的影响。因此可以在生长完AlN后取出晶圆，通过具有各向异性的刻蚀，仅保留垂直面上的AlN成核层而把其他地方的AlN去除。例如在具有垂直取向的离子轰击的干法刻蚀过程中，垂直面上的AlN受到的离子轰击较弱而其他面上的AlN受到的轰击较强，这样可以仅保留垂直面上的AlN，形成衬底上的垂直界面。当然，由于硅(111)面相对于非晶的SiO2或SiN等绝缘材料更容易导致AlN的成核，所以在合适的生长工艺下，AlN也可以实现仅在垂直的(111)硅面上成核与生长，只是工艺窗口较小。
在其他材料如Al2O3中，GaN就可在Al2O3(0001)面上成核生长，可以避免上述问题。
其中，以硅衬底为例，请参阅图3，在生长AlN成核层之前，对衬底的处理可以为首先在衬底上刻蚀形成有(111)面的长条结构，例如，在衬底的上表面形成绝缘层，可选地， 绝缘层可以为热氧化或气相沉积形成的SiO2层。并且，作为一种可选的实现方式，该绝缘层的厚度约为0.5微米。
如图4所示，利用掩膜对绝缘层进行光刻，进而形成间隔设置的绝缘层。然后对衬底进行刻蚀，由于绝缘层的阻挡，因此位于绝缘层下方的衬底不会被刻蚀掉，而没有绝缘层的区域，会被刻蚀出凹槽，进而形成了垂直的多个凹槽，且该凹槽间隔设置。其中，凹槽的侧壁具有六角对称的晶格结构，例如Si的(111)面。
然后，请参阅图5，在衬底的表面沉积形成牺牲层，此时，绝缘层的表面，凹槽底部的表面以及凹槽侧壁的表面均覆盖有牺牲层。可选地，牺牲层的材料可以为氮化硅。接着，如图6所示，进行干法刻蚀，去除绝缘层表面上与凹槽底部表面上的牺牲层，而保留凹槽侧壁表面的牺牲层。
接着，通过氧化工艺，在沟槽的底面上可再次形成绝缘层，该绝缘层的材料仍可以为SiO2。其中，在衬底表面与凹槽底部的表面制作绝缘层，可以避免在后续生长氮化物半导体时镓原子与硅衬底的不兼容，避免出现回熔(melt-back)现象。同时，在凹槽底部表面的绝缘层还可以有效阻绝氮化物半导体与硅衬底之间的漏电流，并降低硅衬底所带来的寄生电容。
然后，通过选择性湿法腐蚀，利用牺牲层和绝缘层的刻蚀选择比，去除凹槽侧表面的牺牲层。
可以理解地，此时衬底的上表面以及凹槽底部表面均覆盖有绝缘层，作为一种实现方式，衬底的上表面以及凹槽底部表面的绝缘层的厚度相同。并且，凹槽侧壁裸露。
在实现上述操作后，可再次通过氧化工艺，在凹槽的侧壁上形成薄的绝缘层，其中，凹槽的侧壁上的绝缘层的厚度需小于衬底的上表面以及凹槽底部表面的绝缘层的厚度。以满足在后续去除侧壁的绝缘层时，在衬底底部与凹槽底部表面仍有一定厚度的绝缘层保护衬底。这些绝缘层可以避免在后续生长氮化物半导体时镓原子与硅衬底的不兼容，避免出现回熔(melt-back)现象，对于硅衬底上制作氮化物半导体器件是必不可少的。
然后通过曝光显影工艺，去除凹槽侧壁上的部分绝缘层，需要说明的是，在去除侧壁部分绝缘层时，会同时去除衬底上表面的绝缘层，但由于衬底上表面的绝缘层的厚度远大于凹槽侧壁上绝缘层的厚度，因此衬底上表面的绝缘层仅会被刻蚀一定的厚度，但并不会完全去除。
可以理解的，请参阅图7，此时除了凹槽侧壁上部分区域未被绝缘层覆盖，其它位置均被绝缘层所覆盖。因此，如图8所示，在硅衬底上沉积AlN成核层时，仅会在侧壁部分区域上形成AlN成核层，且单晶AlN晶体的生长方向是<0001>，表面是(0001)面。
需要说明的是，如果采用其他衬底例如Al2O3，则成核层也可以是GaN。此时通过工 艺调节可以较容易实现仅在暴露的衬底表面成核。
在形成成核层后，即可以AlN成核层为核心，制作本申请所述的的驱动信号输出模块。
作为一种实现方式，可以沿成核层侧向外延生长第一氮化物半导体层，可以理解地，由于凹槽的存在，生长后为凹槽内填充有第一氮化物半导体层。可以理解的是，在生长所述第一氮化物半导体层之前，还可以先沉积形成缓冲层，也可以不形成缓冲层。
为了实现本申请中提供的HEMT与HHMT器件为常关型器件，本申请中，在第一氮化物半导体层可形成至少一个P型掺杂区域和/或N型掺杂区域，进而耗尽栅电极附近的二维载流子气。例如，第一氮化物半导体层形成至少一个P型掺杂区域，其与栅电极在<0001>晶向投影方向上至少部分重叠，并与二维载流子气电耦合，从而基本耗尽该第一导电类型二维载流子气，以实现晶体管为常关型。
在上述结构的基础上，可再取出衬底表面的绝缘层以及该绝缘层下的部分衬底，此时衬底上仍会形成有凹槽结构。然后再外延生长第二氮化物半导体层。其中，第一氮化物半导体层即为沟道层，第二氮化物半导体层即为势垒层。最后再制作电极，完成本申请所述的驱动信号输出模块的制作。
可以理解地，在垂直界面的两侧的晶向分别为(000-1)与(0001)，且(0001)的反方向为(000-1)，在(000-1)晶向上，沟道层与势垒层会形成2DHG(二维空穴气)，在(0001)晶向上，沟道层与势垒层会形成2DEG(二维电子气)。其中，通过在2DEG侧形成源极、漏极、栅极可构成HEMT器件；通过在2DHG侧形成源极、漏极、栅极可构成HHMT器件。其中，源极与漏极与2DEG或2DHG要形成好的欧姆接触，也就是接触电阻越小越好。栅极则要尽量减少到沟道的漏电流：可以使栅极和势垒层形成肖特基接触，也可以在栅电极下形成绝缘层来降低漏电流，也就是在形成栅电极前形成栅绝缘层。
对于HEMT和HHMT两种器件，其源极和漏极通常都可以采用同一种材料，但是由于HEMT的欧姆接触金属和HHMT的欧姆接触金属通常不同，所以HEMT的源漏极材料和HHMT的源漏极通常不同。由于对功函数的要求通常不同，HEMT的栅极材料和HHMT的栅极通常也不同。
本申请中HHMT与HEMT源漏栅的对应排布方式仅是用于示意，也可以有很多其他的相对位置关系。
这样形成的鳍式结构具有垂直的沟道结构，通过增加沟道的高度可以显著的增加有效导通面积，降低导通电阻，从而降低生产成本。
需要说明的是，如果采用Al2O3或SiC衬底，也可以不需要上述SiO2绝缘层。这主要是因为Ga原子与Al2O3或SiC是兼容的，没有回熔现象。在合适的工艺条件下，在具六角对称性的Al2O3(0001)或SiC(0001)上更容易成核与生长，因此，这种具有垂直的 生长面的衬底自然的具有选区生长的能力。当然，如果仍然采用非晶的绝缘层如SiO2、SiN，这种选择性生长的工艺窗口更大更可控。
图9为本申请提供的在垂直界面左右侧分别制备有一个HHMT与HEMT的的情况的横切面示意图。当然，也可以仅制作HHMT或HEMT，或在垂直界面的两侧制作多个HHMT与HEMT。
通过上述制备工艺，能够在同一衬底上生长HHMT和/或HEMT，实现器件的集成。
需要说明的是，制作该至少一个HEMT与至少一个HHMT的材料可以为三族氮化物。
其中，低压功率器件的工作状态主要分为三种状态，关断状态，开关瞬间切换状态以及开通状态，低压功率器件本身的损耗以及工作频率严重影响整个电力电子产品的功耗和体积。
低压功率器件自身的损耗分为开通状态时的损耗和开关瞬间切换状态时的损耗；开通损耗主要与电流和导通电阻值Ron相关，在大电流开通下，主要通过增加器件内部导通区域的有效面积来降低导通电阻值Ron。开关损耗主要与工作频率和器件的寄生电容Cp相关，在高频工作时，主要通过减小器件内部裸带的有效面积来降低寄生电容值Cp。
由于降低上述两种状态下自身的损耗的主要手段是相互矛盾的，所以通常用Ron和Cp的乘积值作为衡量低压功率器件的一个重要性能指标，通常把Ron和Cp的乘积值简称为低压功率器件的FOM值(figure of merit)。若低压功率器件在本身损耗很低时就可以工作在高频大电流状态，那么整个电力电子电路系统就可以实现高频工作。在高频时电路中的电感，变压器等无源大体积元器件就可以成倍的缩减体积，进而实现产品的低功耗和体积小型化。
如图10所示，本申请示出了功率器件的FOM值的示意图，由图可知，相对于传统的Si材料晶体管，本申请采用三族氮化物的晶体管器件的ROM值更小。并且，通过在同一衬底上生长HHMT和/或HEMT，可以进一步降低寄生电容、电感等，提高器件的工作频率并降低损耗。换言之，本申请通过材料的改进以及在同一衬底上生长HHMT和/或HEMT的方式，共同实现了降低器件损耗的效果。
并且，在上述制备工艺的基础上，可制作本申请提供的驱动信号输出模块200。其中，驱动电路一般包括隔离驱动IC器件和非隔离驱动IC器件，其中隔离驱动IC器件主要包括隔离单路输出器件和隔离半桥输出器件，非隔离驱动IC器件主要包括单路输出器件，双路输出器件，多路输出器件以及半桥输出器件等。
本申请以非隔离驱动IC器件为例进行说明，作为一种可能的实现方式，驱动信号输出模块200可以包括单相半桥电路、两相半桥电路以及三相半桥电路。需要说明的是，图11示意的是高电子迁移率晶体管(High Electron Mobility Transistor，HEMT)及高空穴迁移率 晶体管(High Hole Mobility Transistor，HHMT)的电路符号。HEMT包括第一源电极101、第一漏电极103、第一栅电极102和第一体电极104，其中在第一源电极101和第一漏电极103之间是二维电子气(Two-Dimensional Electron Gas，2DEG)沟道105，实心圆球代表电子。HHMT包括第二源电极201、第二漏电极203、第二栅电极202和第二体电极204，其中在第二源电极201和第二漏电极203之间是二维空穴气(Two-Dimensional Hole Gas，2DHG)沟道205，空心圆球代表空穴。第一栅电极102和第二栅电极202分别控制HEMT和HHMT导电沟道的导通和关断。
请参阅图12，当驱动信号输出模块200包括单相半桥电路时，驱动信号输出模块200包括第一HHMT与第一HEMT，第一HHMT与第一HEMT的漏极均与输出端口连接，且输出端口用于与待驱动器件电连接；
当驱动信号输出模块200包括双相半桥电路时，驱动信号输出模块200包括第一HHMT、第一HEMT、第二HHMT以及第二HEMT，第一HHMT、第二HHMT、第一HEMT、第二HEMT的漏极均与输出端口连接；
当驱动信号输出模块200包括三相半桥电路时，驱动信号输出模块200包括第一HHMT、第一HEMT、第二HHMT、第二HEMT、第三HHMT以及第三HEMT，第一HHMT、第一HEMT、第二HHMT、第二HEMT、第三HHMT以及第三HEMT的漏极均与输出端口连接。
可选地，输出端口包括第一输出端口与第二输出端口，第一输出端口与第二输出端口均与同一待驱动器件电连接。
请参阅图13，当驱动信号输出模块200包括单相半桥电路时，驱动信号输出模块200还包括第一附加电路与第二附加电路，第一HHMT的漏极通过第一附加电路与第一输出端口电连接，第一HEMT的漏极通过第二附加电路与第二输出端口电连接，第一附加电路与第二附加电路分别调控第一HHMT与第一HEMT的导通时间。作为一种实现方式，第一附加电路与第二附加电路可包括二极管、电容等器件，进而对HHMT的导通时间进行调控。作为另一种实现方式，第一附加电路与第二附加电路的阻值不同。通过设置阻值不同的附加电路，能够控制器件导通与关断时间。例如，在第一附加电路阻值为100Ω时，器件导通时间需要100ms；而当第一附件电路的阻值为200Ω时，器件导通时间需要200ms。同时，在此基础上，还可设置更多的附加电路，且附加电路与第一附加电路并联，附加电路的阻值也并不相同，进而能够实现控制不同器件导通时，其导通时间可以变化。
其中，本申请所述的第一附加电路与第二附加电路可以为一电阻，也可以为多个电阻串联或并联组成的电路。或者，附加电路也可以为其它耗能或非耗能器件，本申请不做限定。
当驱动信号输出模块200包括双相半桥电路时，驱动信号输出模块200还包括第三附加电路与第四附加电路，第一HHMT的漏极通过第一附加电路与第一输出端口电连接，第二HHMT的漏极通过第三附加电路与第一输出端口电连接，第一HEMT的漏极通过第二附加电路与第二输出端口电连接，第二HEMT的漏极通过第四附加电路与第二输出端口电连接，其中，第三附加电路与第四附加电路的阻值不同，同理地，第三附加电路与第四附加电路分别调控第二HHMT与第二HEMT的导通时间。
当驱动信号输出模块200包括三相半桥电路时，驱动信号输出模块200还包括第五附加电路与第六附加电路，第一HHMT的漏极通过第一附加电路与第一输出端口电连接，第二HHMT的漏极通过第三附加电路与第一输出端口电连接，第三HHMT的漏极通过第五附加电路与第一输出端口电连接，第一HEMT的漏极通过第二附加电路与第二输出端口电连接，第二HEMT的漏极通过第四附加电路与第二输出端口电连接，第三HEMT的漏极通过第六附加电路与第二输出端口电连接，其中，第五附加电路与第六附加电路的阻值不同。同理地，第五附加电路与第六附加电路分别调控第三HHMT与第三HEMT的导通时间。
作为本申请的另一种可能的实现方式，驱动信号输出模块200可以包括单相电路、两相电路以及三相电路。
请参阅图14，当驱动信号输出模块200包括单相电路时，驱动信号输出模块200包括第一HHMT、第一HEMT以及第四HHMT，第一HHMT与第四HHMT并联，且第一HHMT、第四HHMT、第一HEMT的漏极均与输出端口连接。
通过设置第一HHMT与第四HHMT，同样能够实现控制待驱动器件导通与关断的时间。例如，在控制待驱动器件导通时，可以先控制第一HHMT导通，实现预启动，然后再控制第一HHMT与第四HHMT同时导通，进而缩短待驱动器件的导通时间。通过设置并联的器件，也可以增大驱动电流，这对于驱动电流相对较低的HHMT尤为有利。
请参阅图15，当驱动信号输出模块200包括双相电路时，驱动信号输出模块200包括第一HHMT、第一HEMT、第二HHMT、第二HEMT、第四HHMT以及第五HHMT，第一HHMT、第二HHMT、第四HHMT以及第五HHMT并联，且第一HHMT、第一HEMT、第二HHMT、第二HEMT、第四HHMT以及第五HHMT的漏极均与输出端口连接；
请参阅图16，当驱动信号输出模块200包括三相电路时，驱动信号输出模块200包括第一HHMT、第一HEMT、第二HHMT、第二HEMT、第三HHMT、第三HEMT、第四HHMT、第五HHMT以及第六HHMT，第一HHMT、第二HHMT、第三HHMT、第四HHMT、第五HHMT以及第六HHMT并联，第一HHMT、第一HEMT、第二HHMT、第二HEMT、第三HHMT、第三HEMT、第四HHMT、第五HHMT以及第六HHMT的漏极均与输出端口连接。
作为本申请的另一种可能的实现方式，请参阅图17，驱动信号输出模块200包括双路输出半桥驱动电路，其中，
驱动信号输出模块200包括第一HHMT、第一HEMT、第二HHMT以及第二HEMT，第一HHMT、第一HEMT的漏极均与第一输出端口连接，第二HHMT、第二HHMT的漏极与第二输出端口连接；其中，第一输出端口用于与一待驱动器件连接，第二输出端口用于与另一待驱动器件连接。
可选地，在驱动信号输出模块200包括双路输出半桥驱动电路时，两个待驱动器件可以组成上下半桥，进而能够通过驱动信号输出模块200控制上下半桥工作的目的。当然，输入端口的数量也可以更多，进而驱动更多的待驱动器件，本申请对此并不做任何限定。
可以理解地，当驱动信号输出模块200包括多个器件，例如上述实现方式中，当驱动信号输出模块200包括三相半桥电路时，需要3个HHMT器件与3个HEMT器件，其可以通过在衬底的垂直界面的一侧制作3个HHMT器件，另一侧制作3个HEMT器件的方式实现。
可选地，在利用驱动信号输出模块200构建驱动电路时，可以制作非隔离栅极驱动电路，例如低端栅极驱动与半桥栅极驱动电路等，也可以制作隔离型驱动电路，例如隔离栅极驱动电路。其中，隔离栅极驱动电路中包括隔离器件，例如电容等隔离器件。
作为一种可选的实现方式，请参阅图18，控制模块100包括驱动信号输入模块、控制信号输入模块、电源模块、保护模块以及主控模块，其中，电源模块与驱动信号输出模块200电连接；驱动信号输入模块、控制信号输入模块、保护模块均与主控模块电连接，主控模块与驱动信号输出模块200电连接；主控模块用于依据驱动信号输入模块、控制信号输入模块以及保护模块的信号控制驱动信号输出模块200的关断状态。
以图19为例进行说明，主控模块可以为与门、同相器以及反相器组成的电路，该与门的输出端可以分别与HEMT与HHMT电连接，与门的输入端分别与保护模块、控制信号输入模块(图未示)以及驱动信号输入模块电连接。其中，驱动信号输入模块可以与控制器等装置电连接，并用于接收相应的控制信号，控制信号输入模块可以为控制器等装置，其与与门电连接，并用于控制与门开始工作或停止工作。并且，本申请提供的保护模块包括过温保护模块与低压保护模块，且过温保护模块与低压保护模块均与与门电连接，并向与门输入信号。
换言之，当控制信号输入模块、驱动信号输入模块、过温保护模块与低压保护模块均输出高电平时(表示驱动电路未出现过温或低压的情况)，与门控制驱动信号输出模块200工作。
同时，本申请提供的驱动电路还可实现控制模块100与驱动信号输出模块200的集成， 且由于驱动信号输出模块200已经进行了一次集成，因此当控制模块100与驱动信号输出模块200进行集成时，其集成后的体积更小。
基于上述内容，本申请还提供了一种驱动IC，驱动IC包括至少两个晶体管，且至少两个晶体管通过同一衬底外延生长而成。本申请提供的驱动IC，能够实现器件基于统一衬底进行集成，进而能够实现小型化。
并且，基于上述内容，本申请还提供了一种驱动系统，该驱动系统包括待驱动器件与上述的驱动电路，驱动电路与待驱动器件电连接，其中，驱动电路用于控制待驱动器件的工作状态，且待驱动器件包括氮化物器件。
并且，该驱动电路与待驱动器件集成于同一芯片，通过将驱动电路与待驱动器件集成于同一芯片，能够实现整个驱动系统的小型化。
综上所述，本申请提供了一种驱动电路、驱动IC以及驱动系统，该驱动电路包括控制模块与驱动信号输出模块，控制模块与驱动信号输出模块电连接，且驱动信号输出模块用于与待驱动器件电连接；其中，驱动信号输出模块包括至少两个晶体管，且至少两个晶体管通过同一衬底外延生长而成；控制模块用于控制至少两个晶体管的关断状态，以控制待驱动器件的工作状态。由于本申请提供的驱动信号输出模块中的晶体管通过同一衬底生长而成，因此其实现了集成，能够将驱动电路做得更小，实现了小型化以及提升了集成度的目的。
另外，在本申请中的各功能模块可以集成在一起形成一个独立的部分，也可以是各个模块单独存在，也可以两个或两个以上模块集成形成一个独立的部分。
以上所述仅为本申请的优选实施方式而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。
对于本领域技术人员而言，显然本申请不限于上述示范性实施方式的细节，而且在不背离本申请的精神或基本特征的情况下，能够以其它的具体形式实现本申请。因此，无论从哪一点来看，均应将实施方式看作是示范性的，而且是非限制性的，本申请的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本申请内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
工业实用性
本申请提供一种驱动电路、驱动IC以及驱动系统，该驱动电路体积小、集成度高。

Claims (16)

  1. 一种驱动电路，其特征在于，所述驱动电路包括控制模块与驱动信号输出模块，所述控制模块与所述驱动信号输出模块电连接，且所述驱动信号输出模块与待驱动器件电连接；其中，
    所述驱动信号输出模块包括至少两个晶体管，且至少两个所述晶体管通过同一衬底外延生长而成；
    所述控制模块用于控制至少两个所述晶体管的关断状态，以控制所述待驱动器件的工作状态。
  2. 如权利要求1所述的驱动电路，其特征在于，至少两个所述晶体管中包括至少一个P型晶体管与至少一个N型晶体管。
  3. 如权利要求2所述的驱动电路，其特征在于，至少两个所述晶体管中包括至少一个HEMT与至少一个HHMT，所述衬底包括垂直界面，所述HEMT与所述HHMT分别位于所述垂直界面的两侧。
  4. 如权利要求3所述的驱动电路，其特征在于，至少一个所述HEMT与至少一个所述HHMT都包含沟道层与势垒层，所述沟道层设置于所述垂直界面的外侧，所述势垒层设置于所述沟道层的外侧，所述沟道层与所述势垒层之间的界面包括第一极性面与第二极性面，所述第一极性面与所述第二极性面分别位于所述垂直界面的两侧，其中，
    所述第一极性面提供二维电子气，所述第二极性面提供二维空穴气。
  5. 如权利要求3所述的驱动电路，其特征在于，所述驱动信号输出模块包括单相半桥电路、两相半桥电路以及三相半桥电路，其中，
    当所述驱动信号输出模块包括单相半桥电路时，所述驱动信号输出模块包括第一HHMT与第一HEMT，所述第一HHMT与所述第一HEMT的漏极均与输出端口连接，且所述输出端口与所述待驱动器件电连接；
    当所述驱动信号输出模块包括双相半桥电路时，所述驱动信号输出模块包括第一HHMT、第一HEMT、第二HHMT以及第二HEMT，所述第一HHMT、所述第二HHMT、所述第一HEMT、所述第二HEMT的漏极均与输出端口连接；
    当所述驱动信号输出模块包括三相半桥电路时，所述驱动信号输出模块包括第一HHMT、第一HEMT、第二HHMT、第二HEMT、第三HHMT以及第三HEMT，所述第一HHMT、所述第一HEMT、所述第二HHMT、所述第二HEMT、所述第三HHMT以及所述第三HEMT的漏极均与输出端口连接。
  6. 如权利要求5所述的驱动电路，其特征在于，所述输出端口包括第一输出端口与第二输出端口，所述第一输出端口与所述第二输出端口均与同一待驱动器件电连接；
    当所述驱动信号输出模块包括单相半桥电路时，所述驱动信号输出模块还包括第一附加电路与第二附加电路，所述第一HHMT的漏极通过所述第一附加电路与所述第一输出端口电连接，所述第一HEMT的漏极通过所述第二附加电路与所述第二输出端口电连接，以通过所述第一附加电路与所述第二附加电路分别调控所述第一HHMT与所述第一HEMT的导通时间；
    当所述驱动信号输出模块包括双相半桥电路时，所述驱动信号输出模块还包括第三附加电路与第四附加电路，所述第一HHMT的漏极通过所述第一附加电路与所述第一输出端口电连接，所述第二HHMT的漏极通过所述第三附加电路与所述第一输出端口电连接，所述第一HEMT的漏极通过所述第二附加电路与所述第二输出端口电连接，所述第二HEMT的漏极通过所述第四附加电路与所述第二输出端口电连接，以通过所述第三附加电路与所述第四附加电路分别调控所述第二HHMT与所述第二HEMT的导通时间；
    当所述驱动信号输出模块包括三相半桥电路时，所述驱动信号输出模块还包括第五附加电路与第六附加电路，所述第一HHMT的漏极通过所述第一附加电路与所述第一输出端口电连接，所述第二HHMT的漏极通过所述第三附加电路与所述第一输出端口电连接，所述第三HHMT的漏极通过所述第五附加电路与所述第一输出端口电连接，所述第一HEMT的漏极通过所述第二附加电路与所述第二输出端口电连接，所述第二HEMT的漏极通过所述第四附加电路与所述第二输出端口电连接，所述第三HEMT的漏极通过所述第六附加电路与所述第二输出端口电连接，以通过所述第五附加电路与所述第六附加电路分别调控所述第三HHMT与所述第三HEMT的导通时间。
  7. 如权利要求6所述的驱动电路，其特征在于，所述第一附加电路与所述第二附加电路的阻值不同，所述第三附加电路与所述第四附加电路的阻值不同，所述第五附加电路与所述第六附加电路的阻值不同。
  8. 如权利要求3所述的驱动电路，其特征在于，所述驱动信号输出模块包括单相电路、两相电路以及三相电路，其中，
    当所述驱动信号输出模块包括单相电路时，所述驱动信号输出模块包括第一HHMT、第一HEMT以及第四HHMT，所述第一HHMT与所述第四HHMT并联，且所述第一HHMT、所述第四HHMT、所述第一HHMT的漏极均与输出端口连接；
    当所述驱动信号输出模块包括双相电路时，所述驱动信号输出模块包括第一HHMT、第一HEMT、第二HHMT、第二HEMT、第四HHMT以及第五HHMT，所述 第一HHMT、所述第二HHMT、所述第四HHMT以及所述第五HHMT并联，且所述第一HHMT、所述第一HEMT、所述第二HHMT、所述第二HEMT、所述第四HHMT以及所述第五HHMT的漏极均与输出端口连接；
    当所述驱动信号输出模块包括三相电路时，所述驱动信号输出模块包括第一HHMT、第一HEMT、第二HHMT、第二HEMT、第三HHMT、第三HEMT、第四HHMT、第五HHMT以及第六HHMT，所述第一HHMT、所述第二HHMT、所述第三HHMT、所述第四HHMT、所述第五HHMT以及所述第六HHMT并联，所述第一HHMT、所述第一HEMT、所述第二HHMT、所述第二HEMT、所述第三HHMT、所述第三HEMT、所述第四HHMT、所述第五HHMT以及所述第六HHMT的漏极均与输出端口连接。
  9. 如权利要求3所述的驱动电路，其特征在于，所述驱动信号输出模块包括双路输出半桥驱动电路，其中，
    所述驱动信号输出模块包括第一HHMT、第一HEMT、第二HHMT以及第二HEMT，所述第一HHMT、所述第一HEMT的漏极均与第一输出端口连接，所述第二HHMT、所述第二HEMT的漏极与第二输出端口连接；其中，所述第一输出端口用于与一待驱动器件连接，所述第二输出端口用于与另一待驱动器件连接。
  10. 如权利要求3所述的驱动电路，其特征在于，制作至少一个所述HEMT与至少一个所述HHMT的材料包括三族氮化物。
  11. 如权利要求1～10中任一项所述的驱动电路，其特征在于，至少两个所述晶体管均为常关型晶体管。
  12. 如权利要求1～11中任一项所述的驱动电路，其特征在于，至少两个所述晶体管中包括至少一个N型三极管与至少一个P型三极管；或
    至少两个所述晶体管中包括至少一个N型MOS管与至少一个P型MOS管。
  13. 如权利要求1～12中任一项所述的驱动电路，其特征在于，所述控制模块包括驱动信号输入模块、控制信号输入模块、电源模块、保护模块以及主控模块，其中，
    所述电源模块与所述驱动信号输出模块电连接；所述驱动信号输入模块、所述控制信号输入模块、所述保护模块均与所述主控模块电连接，所述主控模块与所述驱动信号输出模块电连接；
    所述主控模块用于依据所述驱动信号输入模块、所述控制信号输入模块以及所述保护模块的信号控制所述驱动信号输出模块的关断状态。
  14. 一种驱动IC，其特征在于，所述驱动IC包括至少两个晶体管，且至少两个所述晶体管通过同一衬底外延生长而成。
  15. 一种驱动系统，其特征在于，所述驱动系统包括待驱动器件与如权利要求1-12 中任一项所述的驱动电路，所述驱动电路与所述待驱动器件电连接，其中，
    所述驱动电路用于控制所述待驱动器件的工作状态，且所述待驱动器件包括氮化物器件。
  16. 如权利要求15所述的驱动系统，其特征在于，所述驱动电路与所述待驱动器件集成于同一芯片。
PCT/CN2021/078961 2020-04-29 2021-03-03 一种驱动电路、驱动ic以及驱动系统 WO2021218372A1 (zh)

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