WO2022037028A1 - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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WO2022037028A1
WO2022037028A1 PCT/CN2021/075970 CN2021075970W WO2022037028A1 WO 2022037028 A1 WO2022037028 A1 WO 2022037028A1 CN 2021075970 W CN2021075970 W CN 2021075970W WO 2022037028 A1 WO2022037028 A1 WO 2022037028A1
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electrode
channel
heterojunction
doped region
layer
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PCT/CN2021/075970
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English (en)
French (fr)
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黎子兰
张树昕
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广东致能科技有限公司
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Priority to EP21857133.9A priority Critical patent/EP4199116A4/en
Priority to US18/042,185 priority patent/US20230335631A1/en
Publication of WO2022037028A1 publication Critical patent/WO2022037028A1/zh

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Definitions

  • the present invention relates to a semiconductor device, in particular to a nitride semiconductor device.
  • Group III nitride semiconductors are important semiconductor materials, mainly including AlN, GaN, InN and compounds of these materials such as AlGaN, InGaN, AlInGaN, and the like. Due to the advantages of direct band gap, wide band gap, and high breakdown electric field strength, group III nitride semiconductors represented by GaN have broad application prospects in the fields of light-emitting devices, power electronics, and radio frequency devices.
  • Polar semiconductors Different from conventional non-polar semiconductor materials such as Si, group III nitride semiconductors are polar, that is, polar semiconductor materials. Polar semiconductors have many unique properties. Of particular importance is the presence of fixed polarization charges at the surface of polar semiconductors or at the interface of two different polar semiconductors. The existence of these fixed polarized charges can attract mobile electron or hole carriers to form a two-dimensional electron gas 2DEG or a two-dimensional hole gas 2DHG. The generation of these two-dimensional electron gas 2DEG or two-dimensional hole gas 2DHG does not require an additional electric field, nor does it depend on doping effects in the semiconductor, and is generated spontaneously.
  • the 2D electron gas or 2D hole gas at the polar semiconductor interface can have a high surface charge density.
  • the ion scattering and other effects of the two-dimensional electron gas or two-dimensional hole gas are also greatly reduced, so it has a high mobility.
  • the high surface charge density and mobility enable the spontaneously generated two-dimensional electron or hole gas at the interface to have good conduction capability and high response speed.
  • this two-dimensional electron gas or two-dimensional hole gas can be used to fabricate high-mobility transistors with high performance in high-energy, high-voltage or high-frequency applications.
  • the existing structure has many defects, which seriously restrict its application range.
  • the present invention proposes a semiconductor device, including:
  • FIG. 1A is a schematic cross-sectional structure diagram of a single-channel HEMT according to an embodiment of the present invention
  • FIG. 1B is a schematic diagram of an on-state electric field structure of a device with a body electrode and a complementary channel according to an embodiment of the present invention
  • 1C is a schematic diagram of an electric field structure with a body electrode and a complementary channel off-state electric field of a device with a complementary channel according to an embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional structure diagram of a dual-channel HEMT according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a cross-sectional structure of a single-channel HHMT according to an embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional structure diagram of a dual-channel HHMT according to an embodiment of the present invention.
  • 5A-5Z are schematic flowcharts of a method for preparing a dual-channel HEMT according to an embodiment of the present invention.
  • the present invention proposes a semiconductor device.
  • the semiconductor device may be formed on a foreign substrate.
  • using the nucleation layer as an intermediary can not only avoid using an expensive homogenous substrate, but also increase the distance between the vertical heterojunction and the heterosubstrate, thereby improving the voltage withstand capability of the semiconductor device.
  • the foreign substrate may be removed to further improve the performance of the semiconductor device.
  • the foreign substrate is a substrate other than GaN intrinsic semiconductor, including but not limited to silicon Si substrate, sapphire (Al 2 O 3 ), and silicon carbide SiC substrate.
  • the carriers involved are electrons or holes. Involving the doping type is N-type or P-type, and the conductive multiton is also electron or hole. Therefore, in the description, in the case where the carrier is the same as or opposite to the doped multi-carrier, it is understood by those skilled in the art that the carrier type is the same or opposite to the doping type.
  • the description of the electrical contact in this application includes both the direct or indirect electrical connection relationship and the electrical interaction relationship.
  • the P-type doping generally refers to doping the nitride semiconductor with elements such as Mg and Zn
  • the N-type doping refers to doping the nitride semiconductor with elements such as Si, O, Se, and Ge.
  • the semiconductor device proposed by the present invention can be a Schottky diode, HEMT, HHMT or other semiconductor devices.
  • HEMT HEMT
  • HHMT HHMT
  • FIG. 1A is a schematic cross-sectional structure diagram of a single-channel HEMT according to an embodiment of the present invention.
  • the HEMT 100 includes a first channel layer 103 and a first barrier layer 104A.
  • a first heterojunction with a vertical interface is formed between the first channel layer 103 and the first barrier layer 104A, and a vertical 2DEG 105A is formed within the first heterojunction.
  • the first channel layer 103 includes a first channel region 132 , a first gate doped region 134 and a second channel region 135 .
  • the first channel region 132 is an N-type doped region based on a nitride semiconductor (eg, GaN). It is usually low doped or un (intentionally) doped, with a doping concentration of ⁇ 1E17/cm 3 .
  • the low doping or non-doping of the first channel region 132 can reduce the phenomenon of decreasing the channel carrier mobility caused by the overall doping of the device.
  • the first gate doped region 134 is disposed over the first channel region 132 .
  • the first gate doped region 134 is a P-type doped region based on a nitride semiconductor (eg, GaN).
  • the multi-subtype in the first gate doped region 134 is opposite to the device carrier type.
  • the doping concentration of the first gate doping region enables the first gate doping region 134 to deplete the two-dimensional carriers (ie, 2DEG) in the HEMT 100 to achieve a normally off device in a non-operating state (no voltage is applied). condition.
  • the doping concentration of the first gate doping region 134 is 1E18-1E20/cm 3 .
  • the different doping concentrations of the first gate doped regions 134 allow the HEMTs 100 to have different threshold voltages. Therefore, the doping concentration of the first gate doping region 134 also has the effect of modulating the threshold voltage of the device.
  • the second channel region 135 is disposed over the first gate doping region 134 .
  • the second channel region 135 is an N-type doped region based on a nitride semiconductor (eg, GaN).
  • the second channel region 135 is generally low-doped or not (intentionally) doped to reduce the phenomenon of channel carrier mobility degradation caused by doping.
  • the first channel region 132, the first gate doping region 134, and the second channel region 135 are all components of the first channel layer 103, and each region is made of nitride semiconductors with the same or similar forbidden band widths. foundation formed. Therefore, the forbidden band width of the first channel layer 103 as the entire channel layer is uniform.
  • the first channel layer 103 further includes other regions formed on the basis of nitride semiconductors with the same or similar forbidden band widths. Further, since each region has the same or similar forbidden band width, the electrical characteristics of the transition portion between the regions are relatively stable, and have no adverse effect on the overall performance of the device.
  • the first channel layer 103 is defined by trenches. Before forming the first channel layer 103, a trench is formed. The height and width of the trench are the same or close to the desired height and width of the first channel layer. Then, the first channel layer 103 is formed by epitaxial growth in the trench. The first channel layer 103 formed in this way can have a larger aspect ratio, and the conditions of epitaxial growth and the morphology of the channel layer are also easier to control.
  • the first barrier layer 104A is disposed on the right side of the first channel layer 103 .
  • a first heterojunction having a vertical interface is formed between the first channel layer 103 and the first barrier layer 104A, and a vertical 2DEG 105A is formed within the first heterojunction.
  • the carriers of 2DEG 105A are electrons.
  • the doping type of the first channel region 132 and the second channel region 135 is N-type, electrons can also be supplied. Therefore, it can be considered that the doping type of the first channel region 132 and the second channel region 135 is the same as the two-dimensional carrier type.
  • the doping type of the first gate doping region 134 is opposite to the two-dimensional carrier type.
  • the surface of the channel layer and the barrier layer grown on the Si(111) plane is the ⁇ 0001> plane, that is, the direction from the Si substrate to the channel layer and the barrier layer is ⁇ 0001> crystal orientation.
  • 2DEG is obtained near the interface between the channel layer and the barrier layer in the channel layer.
  • the direction of the crystal orientation is opposite, that is, the ⁇ 000-1> direction, then 2DHG is obtained in the channel layer near the interface between the channel layer and the barrier layer.
  • the first channel layer 103 and the first barrier layer 104A may be formed over the substrate and the nucleation layer (not shown). After this, the substrate and nucleation layer can be removed. In this way, the structure of the final device does not include the substrate and the nucleation layer, so as to help eliminate the influence of the foreign substrate (eg Si).
  • the substrate and nucleation layer can be removed. In this way, the structure of the final device does not include the substrate and the nucleation layer, so as to help eliminate the influence of the foreign substrate (eg Si).
  • the HEMT 100 further includes: a first electrode 107 and a second electrode 108 .
  • the first electrode 107 is disposed under the first gate doped region 134 and is in electrical contact with the 2DEG 105A within the first heterojunction.
  • the second electrode 108 is disposed over the first gate doped region 134 and is also in electrical contact with the 2DEG 105A within the first heterojunction.
  • the first electrode 107 and the second electrode 108 may become the drain and source electrodes of the HEMT 100 .
  • the first electrode 107 and the second electrode 108 are in ohmic contact with the channel layer and/or the barrier layer 104A.
  • the electrical contact here includes both the direct or indirect electrical connection relationship and the electrical interaction relationship.
  • the HEMT 100 also includes a third electrode 109.
  • the third electrode 109 is in electrical contact with the 2DEG 105A within the first heterojunction at the first gate doped region 134.
  • the third electrode 109 is provided between the first electrode 107 and the second electrode 108, which can be used as a gate electrode to control the current intensity between the first electrode 107 and the second electrode 108 to form a HEMT structure.
  • the voltage applied to the third electrode 109 can modulate the number of electrons (holes) in the first gate doped region 134 .
  • the carriers (electrons) in the 2DEG 105A are no longer in a depleted state, and a conductive channel is re-formed between the first electrode 107 and the second electrode 108 .
  • the length of the horizontal extension of the third electrode 109 is not less than the length of 2DEG 105A, so as to realize the control of the current path between the first electrode 107 and the second electrode 108 .
  • the third electrode 109 is located between the first electrode 107 and the second electrode 108, and is closer to the second electrode 108 that is the source. Such an arrangement increases the distance between the drain and the gate, which can effectively improve the voltage resistance of the semiconductor device 100 .
  • the first channel layer 103 further includes a first electric field modulation doped region 133 .
  • the first electric field modulation doping region 133 is located near the third electrode and is electrically connected to the first gate doping region 134 . As shown in the figure, the first electric field modulation doping region 133 is disposed between the first gate doping region 134 and the first electrode 107 , and is closer to the first gate doping region 134 .
  • the first electric field modulation doped region 133 is also a P-type doped region based on a nitride semiconductor (eg, GaN). The doping concentration is less than the first gate doping region 134, typically ⁇ 2E19/cm 3 .
  • the first gate doping region 134 needs to completely deplete the electrons in the 2DEG 105A, its doping concentration is relatively high.
  • the first electrode 107 drain
  • the local electric field strength at the contact position between the first gate doped region 134 and the channel region 132 is uneven, which affects the voltage withstand performance of the device.
  • Disposing the first electric field modulation doped region 133 therebetween as a buffer can avoid the above problems.
  • the first electric field modulation doping region 133 is both P-type doped, the doping concentration is lower than that of the first gate doping region 134 to prevent the electric field modulation doping region 134 from seriously depleting the channel carrier concentration Thereby increasing the on-resistance of the device.
  • the electric field modulation doped region 133 adjusts the electric field distribution of the device, reduces the local electric field strength near the gate doped region 134, and avoids the breakdown phenomenon caused by excessive local high electric field. Meanwhile, forming the first electric field modulation doping region 133 on the channel region 132 first and then forming the first gate doping region 134 is also easy to handle in terms of process.
  • the first channel layer 103 further includes a first ohmic contact doped region 131 .
  • the first ohmic contact doped region 131 is disposed between the first channel region 132 and the first electrode 107 .
  • the first ohmic contact doped region 131 is used to form an ohmic contact with the first electrode 107 .
  • the doping type of the first ohmic contact doped region 131 is N-type, and its concentration is 1E16-2E19/cm 3 .
  • the first ohmic contact doped region 131 increases the carrier concentration, which can reduce the ohmic contact resistance with the first electrode 107 .
  • the first channel layer 103 further includes a second ohmic contact doped region 136 .
  • the second ohmic contact doped region 136 is disposed between the second channel region 135 and the second electrode 108 .
  • the second ohmic contact doped region 136 is used to form an ohmic contact with the second electrode 108 .
  • the doping type of the second ohmic contact doped region 136 is N-type, and its concentration is 1E16-2E19/cm 3 .
  • the second ohmic contact doped region 136 increases the carrier concentration, which can reduce the ohmic contact resistance with the second electrode 108 .
  • the HEMT 100 further includes a second barrier layer 104B formed on the left side of the first channel layer 103, wherein a vertical interface is formed between the first channel layer 103 and the second barrier layer 104B A second heterojunction within which vertical 2DHG 105B is formed.
  • the second barrier layer 104B may be composed of the same nitride semiconductor material as the first barrier layer 104A.
  • 2DEG 105A and 2DHG 105B form complementary channels.
  • the 2DEG 105A is at a high potential near the first electrode 107, and the 2DEG of the first gate doped region 134 and the first electrode 107 is depleted, exposing the background positive charges.
  • An electric field with a certain direction is formed inside the HEMT 100 , so that the electric field inside the HEMT 100 is unevenly distributed, thereby affecting the performance of the device.
  • 2DHG 105B is not connected to other electrodes. The uneven distribution of the internal electric field of HEMT100 will change the distribution of 2DHG, which will make the internal electric field distribution of HEMT100 more uniform and the device work more stable.
  • the 2DHG 105B can be formed on one side of all or part of the first channel layer 103, so that the internal electric field can be adjusted in these regions.
  • 2DHG can form the first channel layer 103 corresponding to the region between the first electrode (drain) and the third electrode (gate) (eg, the first ohmic contact doped region 131, the first channel region 132, electric field modulation doping region 133 and first gate doping region 134), so as to improve the withstand voltage performance of the device.
  • a fourth electrode 106 is further included, which is disposed close to the first gate doped region 134 and is electrically connected to the first gate doped region 134 .
  • the fourth electrode 106 may be in electrical contact with the first gate doped region 134 directly or indirectly. Alternatively, as shown, it is in electrical contact with the 2DHG 105B within the second heterojunction at the location of the first gate doped region 134.
  • the fourth electrode 106 may be individually controlled as a body electrode or electrically connected to the second electrode 108 . As an example, the fourth electrode 106 can be selectively connected to a voltage of 0V.
  • the electrodes 109 are connected to an external voltage to turn on the device.
  • the charges originally introduced by the external voltage cannot be fully released, and some residual charges may be formed in the first gate doping region 134 .
  • These residual charges will neutralize the polytrons in the first gate doped region 134 to a certain extent. Therefore, when operating again, the threshold voltage of the HEMT100 will drift.
  • the fourth electrode 106 is added, when the HEMT 100 is turned off, the residual charges will be conducted to the outside of the device through the fourth electrode (body electrode). In this way, the potential of the first gate doped region 134 is relatively fixed, and the threshold voltage of the HEMT 100 is also more stable.
  • FIGS. 1B-1C The effect of the complementary channel and the fourth electrode on adjusting and balancing the electric field in the device will be described in detail below with reference to FIGS. 1B-1C.
  • the device structure is simplified for the convenience of description, and those skilled in the art should know that the technical effect is applicable to the used device including the structure.
  • 1B is a schematic diagram of an on-state electric field structure of a device with a body electrode and a complementary channel according to an embodiment of the present invention.
  • FIG. 1C is a schematic diagram of an electric field structure in a complementary channel off state of a device with a body electrode and a complementary channel according to an embodiment of the present invention.
  • the structures that are the same or similar to those in FIG. 1A will not be repeated here.
  • Figure IB further includes a background positive charge 155A corresponding to 2DEG 105A and a background negative charge 155B corresponding to 2DHG 105B.
  • FIG. 1B when the device is turned on, the electric field distribution in the device is uniform, and the fourth electrode 106 has no influence.
  • FIG. 1C the electric field distribution in the off state of the device is shown in FIG. 1C .
  • the fourth electrode 106 When the 2DHG 105B and the fourth electrode 106 (body electrode) coexist, the fourth electrode 106 is located on the left side of the 2DHG 105B and is electrically connected to the 2DHG 105B.
  • the 2DHG 105B When the device is in the off state, the 2DHG 105B is contacted through the fourth electrode 106.
  • the 2DHG 105B Since the voltage of the fourth electrode 106 is much lower than the voltage of the first electrode 107, the 2DHG 105B is fully or partially depleted, exposing the negative background charge.
  • the negative background charge on the left side and the positive background charge on the right side form a stable internal electric field, and the distribution is more uniform, which also makes the device work more stable.
  • HEMT 100 further includes a first nucleation layer.
  • the first channel layer 103 is epitaxially grown from the first nucleation layer.
  • the first channel layer 103 is over the first nucleation layer.
  • the first nucleation layer is doped and thus has good electrical conductivity.
  • the first nucleation layer is epitaxially grown from a first vertical interface of the substrate.
  • insulating layer 112 is included between electrode 107 and electrode 109 flanking barrier layer 104A.
  • the insulating layer 112 extends horizontally and laterally, and its material may be an insulating material such as SiO 2 .
  • the shielding layer 112 may serve as a gate insulating layer partially filled between the barrier layer 104A and the electrode 109 .
  • an insulating layer 113 is included under the side electrodes 106 of the barrier layer 104B.
  • the insulating layer 113 extends horizontally and laterally, and its material may be an insulating material such as SiO 2 .
  • the shielding layer 112 and the insulating layer 113 isolate the side surfaces of the barrier layer 104A and the barrier layer 104B from the outside world, which can prevent the outside world from affecting the performance of the device.
  • a passivation layer (not shown) may be included over the semiconductor device shown in FIG. 1 to protect underlying semiconductor structures.
  • the semiconductor device may further include a first conductor interconnection layer, a second conductor interconnection layer and a third conductor interconnection layer, which are respectively electrically connected to the first electrode 107 , the second electrode 108 and the third electrode 109 .
  • the fourth electrode may be electrically connected on the outside with a fourth conductor interconnect layer over the semiconductor device.
  • Each of the four electrodes corresponds to a corresponding conductor interconnection layer, and the access positions in the vertical direction are different, and the process is simpler.
  • HEMT 100 further includes a heterogeneous substrate.
  • the substrate is a silicon Si substrate.
  • the lattice of the vertical surface of the substrate has hexagonal symmetry to enable subsequent epitaxial growth of nitride semiconductor crystals.
  • the vertical interface of the exposed substrate can be a Si(111) plane.
  • the substrate can also be a sapphire Al 2 O 3 substrate, a SiC substrate, or a GaN intrinsic substrate.
  • the nucleation layer may be AlN.
  • the nucleation layer may further include a buffer layer (not shown).
  • the buffer layer may have a single-layer or multi-layer structure, including one or more of AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN.
  • the above description is merely illustrative of the structure of the HEMT.
  • the devices involved in the present application also have various other structures or improvements, changes, or modifications in these structures to provide different characteristics or functions. These structures and their improvements, changes or modifications are under the technical concept of the present invention, and can also be applied to the solutions of the present invention.
  • the semiconductor device involved in the present invention not only has a 2DEG with a vertical structure, but also the channel layer is no longer composed of a single material, but is divided into multiple regions and formed by different doping.
  • the doping type of the gate doped region is opposite to the type of carriers, which can deplete the carriers, so that the device can realize the normally-off function in the normal state when no voltage is applied to the gate electrode.
  • Traditional devices do not have a similar structure, so the device itself is in a normally-on state, which will greatly increase power consumption in practical applications.
  • the semiconductor device involved in the present invention does not include structures such as a substrate and a nucleation layer.
  • the formation process is completed on a foreign substrate, such as Si, and the cost of the preparation process is low.
  • the substrate and the nucleation layer are removed, which avoids the disadvantages of low pressure resistance of the foreign substrate, and has better pressure resistance and carrier mobility than traditional devices.
  • FIG. 2 is a schematic cross-sectional structure diagram of a dual-channel HEMT according to an embodiment of the present invention.
  • the HEMT 200 shown in FIG. 2 can also be considered to be a combination of two semiconductor devices HEMT 100 shown in FIG. 1 , and the parts with the structure similar to the foregoing will not be repeated here.
  • the left side of the HEMT 200 includes a first channel layer 203A, which includes a first ohmic contact doped region 231A, a first channel region 232A, a first electric field modulation doped region 233A, a A gate doped region 234A, a second channel region 235A and a second ohmic contact doped region 236A.
  • the right side of the HEMT 200 includes a second channel layer 203B, which includes a third ohmic contact doped region 231B, a third channel region 232B, a second electric field modulation doped region 233B, and a second gate doped region stacked from bottom to top 234B, the fourth channel region 235B, and the fourth ohmic contact doped region 236B.
  • the right side of the first channel layer 203A of the HEMT 200 further includes a first barrier layer 204A, and the left side of the second channel layer 203B further includes a third barrier layer 204C. Since the first channel layer 203A and the first and second barrier layers 204A and 204C have different energy band gaps, first and third heterojunctions having vertical interfaces are formed in the HEMT 200, and within the two heterojunctions Vertical two-dimensional electron gases 2DEG 205A and 2DEG 205C are formed.
  • An electrode 208A and an electrode 208B are respectively provided on the ohmic contact doped region 236A and the ohmic contact doped region 236B, respectively forming ohmic contact with the ohmic contact doped region 236A and the ohmic contact doped region 236B, and also with the 2DEG 205A and 2DEG respectively 205C electrical connection.
  • 2DEG 205A and 2DEG 205C in the two channel layers are formed at the right and left positions of the channel layer, respectively, because during the formation process, the vertical interface of the substrate where the two-part structure is grown is an isomorphic structure relatively set. Such a structure can achieve a higher level of integration.
  • the left side of the first channel layer 203A of the HEMT 200 further includes a second barrier layer 204B, and the right side of the second channel layer 203B further includes a fourth barrier layer 204D. Since the channel and barrier layers 204B and 204D have different energy band gaps, second and fourth heterojunctions with vertical interfaces are formed within the HEMT 200 . Vertical two-dimensional hole gases 2DHG 205B and 2DHG 205D are formed within the two heterojunctions.
  • a position on the left side of the second barrier layer 204B of the HEMT 200 adjacent to the gate doped region 234A further includes a fourth electrode 206A; which is in electrical contact with the 2DHG 205B within the heterojunction at the first gate doped region 234A .
  • the second barrier layer 204D of the HEMT 200 further includes a fourth electrode 206B at a position close to the gate doped region 234B; it is in electrical contact with the 2DHG 205C in the heterojunction at the first gate doped region 234B.
  • the fourth electrodes 206A and 206B may be individually controlled as body electrodes or may be electrically connected to the second electrodes 208A and 208B.
  • the fourth electrodes 206A and 206B are connected to 0V.
  • the electrode 209 is shared as a gate electrode, and the electrode 207 is shared as a drain electrode.
  • the first channel layer and the second channel layer may have respective gate and drain electrodes, respectively.
  • the HEMT200 not only has the advantages of the HEMT100 described above, but on this basis, the HEMT200 includes two conductive channels, namely 2DEG 205A and 205C.
  • the increased conduction channel can increase the on-current, resulting in higher power; and the double conduction channel has better withstand voltage and heat resistance than the single conduction channel.
  • electrodes of the same property of the dual-conductivity channel structure can be shared without the need to form two electrodes separately, which saves space, and can also significantly save manufacturing costs and man-hours.
  • similar structures can also form a high hole mobility transistor HHMT with 2DHG.
  • 3 is a schematic cross-sectional structure diagram of a single-channel HHMT according to an embodiment of the present invention. Among them, parts with similar structures to those in FIG. 1 will not be repeated here.
  • the overall structure of HHMT 300 is similar to HEMT100, but since the vertical interface of the substrate during the formation process is the (000-1) plane, which is different from HEMT100, the conductive channel in HHMT300 is 2DHG 305A. Accordingly, HHMT 300 further includes 2DEG 305B. Since the conductive channel is 2DHG105A, its carriers also have electrons to become holes. Therefore, the doping type of the ohmic contact doped region 331 , the channel region 332 , the channel region 335 and the ohmic contact doped region 336 in the HHMT 300 is P-type. The doping type of the electric field modulation doping region 333 and the gate doping region 334 is N-type.
  • the HHMT does not have a substrate and a nucleation layer, which have no effect on the conductive channel, and the performance of the device can be further improved.
  • FIG. 4 is a schematic structural diagram of a dual-channel HHMT according to another embodiment of the present invention.
  • the HHMT 400 shown in FIG. 4 can also be considered to be a combination of two semiconductor devices HHMT 300 shown in FIG. 3 , and the parts similar to the aforementioned structures will not be repeated here.
  • the left side of the HHMT 400 includes a first channel layer 403A, which includes a first ohmic contact doped region 431A, a first channel region 432A, a first electric field modulation doped region 433A, The first gate doped region 434A, the second channel region 435A, and the second ohmic contact doped region 436A.
  • the right side of the HHMT 400 includes a second channel layer, which includes a third ohmic contact doped region 431B, a third channel region 432B, a second electric field modulation doped region 433B, and a second gate doped region 434B stacked from bottom to top , a fourth channel region 435B, and a fourth ohmic contact doped region 436B.
  • the right side of the first channel layer 403A of the HHMT 400 further includes a first barrier layer 404A, and the left side of the second channel layer 403B further includes a third barrier layer 404C. Since the channel and barrier layers 404A and 404C have different energy band gaps, first and third heterojunctions with vertical interfaces are formed within the HHMT 200 . Vertical two-dimensional electron gases 2DHG 405A and 2DHG 405C are formed within the two heterojunctions.
  • An electrode 408A and an electrode 408B are respectively provided on the ohmic contact doped region 436A and the ohmic contact doped region 436B, respectively forming ohmic contact with the ohmic contact doped region 436A and the ohmic contact doped region 436B, and also with the 2DHG 405A and 2DHG respectively 405C electrical connection.
  • the left side of the first channel layer 403A of the HEMT 400 further includes a second barrier layer 404B, and the right side of the second channel layer 403B further includes a fourth barrier layer 404D. Since the channel and barrier layers 404B and 404D have different energy band gaps, second and fourth heterojunctions with vertical interfaces are formed within the HEMT 400 . Vertical two-dimensional electron gases 2DEG 405B and 2DEG 405D are formed within the two heterojunctions.
  • a location on the left side of the second barrier layer 404B of the HHMT 400 adjacent to the gate doped region 434A further includes an electrode 406A; which is in electrical contact with the 2DHG 405B within the heterojunction at the first gate doped region 434A.
  • the second barrier layer 404D of the HHMT 400 further includes a first electrode 406B at a position close to the gate doped region 434B; it is in electrical contact with the 2DHG 405C in the heterojunction at the first gate doped region 434B.
  • Electrodes 406A and 406B may be individually controlled as body electrodes or electrically connected to electrodes 408A and 408B. Optionally, electrodes 406A and 406B are connected to a voltage of 0V.
  • the electrode 409 is shared as a gate electrode, and the electrode 407 is shared as a drain electrode.
  • the first channel layer and the second channel layer may have respective gate and drain electrodes, respectively.
  • HEMT 400 includes two conductive channels, namely 2DHG 405A and 405C.
  • the increased conduction channel can increase the on-current, resulting in higher power; and the double conduction channel has better withstand voltage and heat resistance than the single conduction channel.
  • electrodes of the same property of the dual-conductivity channel structure can be shared without the need to form two electrodes separately, which saves space, and can also significantly save manufacturing costs and man-hours.
  • the present invention also includes a method of manufacturing the semiconductor device.
  • the manufacturing method of the semiconductor device of the present invention is described below by taking a manufacturing process of a dual-channel HEMT as an example.
  • FIGS. 5A-5Z are schematic flowcharts of a method for preparing a dual-channel HEMT according to an embodiment of the present invention.
  • a semiconductor device is fabricated on a silicon substrate.
  • other substrates such as intrinsic GaN, Al 2 O 3 (sapphire), SiC, etc., can also achieve similar structures.
  • the preparation method 500 of the HEMT includes: in step 5001 , as shown in FIG. 5A , a Si substrate 501 is provided.
  • a plurality of first trenches are formed on the substrate, as shown in FIG. 5B.
  • the substrate 501 is etched by a photolithography technique, and a plurality of rectangular first trenches 521 are formed on the substrate 501 to expose the vertical interfaces 541 and 542 of the substrate 501; wherein, the vertical substrate interface 541 in the first trench 521 is exposed.
  • 542 are the (111) plane (ie, the crystal ⁇ 0001> plane) of the Si substrate.
  • the number of the first trenches provided on the same substrate depends on the requirements of specific integration, voltage resistance, etc., and only three trenches are used as an example for description here.
  • the method involved in the present invention can pre-configure the shape and size of the trench according to actual requirements. For example, when a semiconductor device with a relatively high withstand voltage is formed, the depth of the trench is also deep.
  • the HHMT shown in FIG. 3 or FIG. 4 can be formed, and details are not described herein again.
  • a protective layer is formed on the substrate and the surface of the first trench on the substrate, as shown in FIG. 5C.
  • a SiN protective layer 531 is grown on the substrate 501 using a technique such as LPCVD to cover the surfaces of the substrate 501 and the plurality of trenches 521 .
  • step 5004 the protective layer extending horizontally on the bottom surface of the first trench and the upper surface of the substrate is removed, and the protective layer on the sidewalls of the first trench is retained, as shown in FIG. 5D .
  • the protective layer 531 formed by SiN on the vertical interfaces 541 and 542 remains, and the Si substrate 501 on the bottom surface of the trench 521 is exposed.
  • the protective layer 531 covers the substrate vertical interfaces 541 and 542 of the substrate trench 521 .
  • a first spacer layer is formed over the substrate and the first trench, as shown in Figure 5E.
  • the spacer layer 511 is covered on the bottom surface of the first trench 521 .
  • SiO 2 may be formed using oxidation techniques to form the first spacer layer 511 on the substrate 501 . Since the vertical interfaces 541 and 542 of the substrate 501 are covered with the protective layer 531 , the spacer layer 511 is substantially not grown on the vertical interfaces 541 and 542 of the substrate 501 .
  • the protective layer on the sidewalls of the trenches is removed, as shown in FIG. 5F.
  • the spacer layer 511 over the substrate 501 covers the mask, and the protective layer 531 on the sidewall of the first trench 521 is partially etched by selective etching technology, photolithography technology or other technology.
  • the etching may include removing portions of the sidewalls of the first trenches 521 .
  • vertical interfaces 541 and 542 of substrate 501 are exposed.
  • a first nucleation layer and a second nucleation layer are formed at the vertical interface, as shown in FIG. 5G.
  • First and second nucleation layers 502A and 502B are grown on exposed vertical surfaces 541 and 542 of substrate 501 .
  • Nucleation layers 502A and 502B include AlN.
  • one or more buffer materials of AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN may be further grown.
  • the nucleation layer grows vertically along with the horizontal extension (not shown). Through the control of process parameters, the growth of the nucleation layer can be made along the horizontal direction as much as possible. Although there is growth in the vertical direction, it does not affect the device structure.
  • a nitride semiconductor nucleation layer (AlN or a composite structure of AlN/AlGaN/GaN) is deposited, and polycrystalline or amorphous AlN or AlGaN may be present on SiO2 due to the low selectivity of Al growth.
  • the wafer can be taken out, and the polycrystalline or amorphous AlN or AlGaN can be removed by vertical etching.
  • a second spacer layer is formed over the entire surface of the device, as shown in Figure 5H.
  • a second spacer layer 519 of SiO 2 is formed by a deposition process.
  • the second spacer layer 519 fills the trenches 521 and forms a certain height of the second spacer layer 519 of SiO 2 on the substrate.
  • the height of the second spacer layer 519 may be increased accordingly.
  • the second spacer layer is patterned to form a plurality of second trenches, exposing portions of the nucleation layer, as shown in FIG. 5I.
  • Vertical second trenches 525 and 524 are etched on the second spacer layer 519 by a vertical etching technique. Basically, the second trenches 525 and 524 define the height of the second layer of the semiconductor device, ie the overall height of the device after the device is formed. And limit the height of the nucleation layer to the first layer.
  • the upper surfaces of nucleation layers 502A and 502B are exposed.
  • nucleation layers 502A and 502B are formed on the (111) side of the Si substrate, and thus, the nucleation layers 502A and 502B have hexagonal symmetry. After exposing the upper surfaces of nucleation layers 502A and 502B, other structures formed within trenches 523 and 524 also have hexagonal symmetry.
  • first ohmic contact doped regions are grown within the plurality of second trenches, as shown in Figure 5J.
  • a nitride semiconductor and a doping medium are deposited on the nucleation layers 502A and 502B by chemical vapor doping to form first ohmic contact doped regions 531A and 531B.
  • the doping type is N-type.
  • the doping type is P-type. Since the carriers in 2DEG are electrons, and N-type doping is also conducted by electrons, it can be considered that the doping type is the same as the two-dimensional carrier type.
  • the horizontal growth state is not easy to control, so it is difficult for the semiconductor structure to maintain complete vertical growth, and multiple growth planes may appear.
  • the structure involved in the present invention can maintain continuous growth on the same side, thereby improving the electrical characteristics of the device.
  • a first channel region is formed on the first ohmic contact doped region, as shown in FIG. 5K.
  • a first channel region 532A and a third channel region 532B are formed by depositing a nitride semiconductor and a doping medium on the first ohmic contact doped regions 5331A and 531B by chemical vapor doping.
  • the doping of the first channel region 532A and the third channel region 532B is low doping or non-(intentional) doping, and the doping type is N-type.
  • an electric field modulated doped region is formed on the first channel region, as shown in Figure 5L.
  • a nitride semiconductor and a doped dielectric are deposited on the first channel region 532A and the third channel region 532B by chemical vapor doping to form the electric field modulation doped regions 533A and 533B.
  • the doping type of the electric field modulation doping regions 533A and 533B is P-type.
  • a gate stack doped region is formed on the electric field modulation doped region, as shown in FIG. 5M.
  • a nitride semiconductor and a doping medium are passed through chemical vapor doping to form gate doping regions 534A and 534B.
  • the doping type of the gate doping regions 534A and 534B is P-type, and the doping concentration is higher than that of the electric field modulation doping regions 533A and 533B.
  • a second channel region is formed on the gate doped region, as shown in Figure 5N.
  • chemical vapor phase doping of the nitride semiconductor and the doping medium forms a second channel region 535A and a fourth channel region 535B.
  • the doping of the second channel region 535A and the fourth channel region 535B is low doping or non-(intentional) doping, and the doping type is N-type.
  • a second ohmic contact doped region is formed on the second channel region and the fourth channel region, as shown in FIG. 5O.
  • the nitride semiconductor and the doping medium are doped by chemical vapor doping to form the second ohmic contact doped regions 536A and 536B.
  • the doping type of the second ohmic contact doped regions 536A and 536B is N-type.
  • the remaining second spacer layer is removed, as shown in Figure 5P.
  • the remaining second spacer layer 519 is removed by an etching technique. After removal, the upper surface of the spacer layer 511 is exposed, and the first channel layer and the second channel layer are all exposed except for the contact positions with the nucleation layer. The upper surface of the nucleation layer is not exposed to the positions where the first channel layer and the second channel layer are in contact and the sidewalls that are not in contact with the substrate.
  • a barrier layer is deposited, as shown in Figure 5Q.
  • a barrier layer 504 is deposited on the device, and the barrier layer covers the surface of the device. forming a barrier layer 504 in which a first heterojunction and a second heterojunction with vertical interfaces are formed between the first channel layer and the barrier layer, within the first heterojunction and the second heterojunction Vertical 2DEG505A and 2DHG505B formed within the junction.
  • a third heterojunction and a fourth heterojunction with vertical interfaces are formed between the second channel layer and the barrier layer, and verticals are formed in the third heterojunction and the fourth heterojunction 2DEG505C and 505D.
  • a relatively thin undoped channel layer may be deposited prior to deposition of the barrier layer, which may be the same material as the original channel layer base nitride semiconductor. In this way, better contact between the barrier layer and the channel layer can be ensured, and the electrical characteristics are more stable.
  • an insulating layer is deposited, as shown in Figure 5R.
  • the insulating layer 518 is deposited on the surface of the device, and the insulating layer 518 will cover the barrier layer 504, and finally the device is made more flat.
  • the insulating layer is patterned to form a third trench between the first channel layer and the second channel layer, as shown in FIG. 5S.
  • the insulating layer 518 between the first channel layer and the second channel layer is etched to form the third trench 525 , while the remaining insulating layer forms the shielding layer 512 .
  • the etching depth here needs to be slightly lower than the contact surface between the gate doped region and the electric field modulation doped region, so as to ensure good contact between the electrode and the gate doped region in the subsequent process of forming the electrode.
  • a third electrode is deposited, as shown in Figure 5T.
  • the third electrode 509 is at the bottom of the trench 525, between the first gate doped region and the second gate doped region, and is in electrical contact with the 2DEGs 505A and 505B in the first heterojunction, and is deposited on the barrier layer by electrode deposition.
  • a third electrode 509 is formed between the positions. In order to ensure that the third electrode 509 is in electrical contact with the first gate doping region and the second gate doping region.
  • the height of the electrode 509 is slightly higher than the upper surfaces of the first gate doped region and the second gate doped region.
  • the electrode 509 is arranged as the gate at a position closer to the upper position, and the electrode 509 is as the gate as far away from the drain as possible, so as to improve the overall voltage resistance of the device.
  • the electrodes 509 may be two electrodes that control the first channel layer and the second channel layer, respectively. The technical process of the solution in this embodiment is simpler.
  • a third spacer layer is deposited, and then the upper surfaces of the first channel layer and the second channel layer are exposed, as shown in FIG. 5U.
  • a third spacer layer 514 is re-formed over the entire device.
  • a third spacer layer 514 is formed by depositing SiO 2 on the semiconductor device through a deposition process to fill the portion above the electrode 507 and cover the channel layer and the barrier layer.
  • a part of the barrier layer 504 is removed by a photolithography process to expose the upper surfaces of the first channel layer and the second channel layer.
  • the originally integrated barrier layer 504 is divided into a first barrier layer 504A, a second barrier layer 504B, a third barrier layer 504C, and a fourth barrier layer 504D.
  • a second electrode is deposited, as shown in Figure 5V.
  • Second electrodes 508A and 508B are formed by an electrode deposition method on the upper surfaces of the first channel layer and the second channel layer at positions close to the 2DEGs 505A and 505B.
  • the second electrodes 508A and 508B form ohmic contacts with the second ohmic contact doped regions and are electrically connected to the 2DEGs 505A and 505C.
  • the second electrodes 508A and 508B are not electrically connected to the 2DHGs 505B and 505D.
  • the second electrodes 508A and 508B act as device sources.
  • the second electrodes 508A and 508B are connected to a low level, eg, 0V.
  • the second electrodes 508A and 508B may also be the same electrode.
  • the insulating layers adjacent to the second barrier layer and the fourth barrier layer are patterned, as shown in FIG. 5W.
  • the insulating layers adjacent to the second barrier layer and the fourth barrier layer are patterned, as shown in FIG. 5W.
  • the etching depth here needs to be slightly lower than the contact surface between the gate doped region and the electric field modulation doped region, so as to ensure good contact between the electrode and the gate doped region in the subsequent process of forming the electrode.
  • a fourth electrode is deposited, as shown in Figure 5X.
  • the fourth electrode 506 is at the bottom of the trench 526, between the first gate doped region and the second gate doped region, and is in electrical contact with the 2DHG 505B and 505D in the first heterojunction, and is deposited on the barrier layer by electrode deposition.
  • a fourth electrode 506 is formed between the positions. In order to ensure sufficient electrical contact between the fourth electrode 506 and the first gate doping region and the second gate doping region.
  • the height of the electrode 506 is slightly higher than the upper surfaces of the first gate doped region and the second gate doped region. In some embodiments, electrode 506 is disposed at the same height as electrode 509 as a body electrode.
  • the electrodes 506 may be two electrodes that control the first channel layer and the second channel layer, respectively.
  • the technical process of the solution in this embodiment is simpler.
  • a fourth electrode directly in ohmic contact with the 2DHG can also be formed, and the fourth electrode is electrically connected to the gate doped region through the 2DHG.
  • the entire semiconductor device is turned over and the substrate and nucleation layers are removed, as shown in Figure 5Y.
  • the substrate 501 faces upward.
  • the substrate 501 is first thinned, and then the entire substrate 501 and the nucleation layers 502A and 502B are removed from the semiconductor device by wet etching.
  • the upper surfaces of the first channel layer and the second channel layer are exposed.
  • a first electrode is formed, as shown in Figure 5Z.
  • a metal electrode ie, the first electrode 507
  • the first electrode 507 is electrically connected to both the vertical 2DEGs 505A and 505C in the first and third heterojunctions, but not to the 2DHGs 505B and 505D.
  • subsequent steps include forming a first conductor interconnect layer, a second conductor interconnect layer, and a third conductor interconnect layer, which are electrically connected to the first electrode, the second electrode, and the third electrode, respectively. These steps are well known to those skilled in the art and will not be repeated here.
  • the channel layer of the HEMT formed by the above method can have a high aspect ratio.
  • the device is normally closed in a non-energized state.
  • more semiconductor structures may be included in the same trench, resulting in a more integrated solution.

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Abstract

本发明涉及一种半导体器件，包括：第一沟道层，其包括第一沟道区、第一栅掺杂区、和第二沟道区，其中所述第二沟道区在所述第一沟道区之上，所述第一栅掺杂区在所述第一沟道区和所述第二沟道区之间；第一势垒层，其中在第一沟道层与第一势垒层之间形成具有垂直界面的第一异质结，在所述第一异质结内形成垂直的2DEG或2DHG；第一电极，其在所述第一栅掺杂区下方与所述第一异质结内的2DEG或2DHG电接触；第二电极，其在所述第一栅掺杂区上方与所述第一异质结内的2DEG或2DHG电接触；以及第三电极，其在所述第一栅掺杂区与所述第一异质结内的2DEG或2DHG电接触。本发明进一步包括一种半导体器件的制造方法。

Description

一种半导体器件及其制造方法 技术领域
本发明涉及一种半导体器件，特别地涉及一种氮化物半导体器件。
背景技术
III族氮化物半导体是重要的半导体材料，主要包括AlN、GaN、InN及这些材料的化合物如AlGaN、InGaN、AlInGaN等。由于具有直接带隙、宽禁带、高击穿电场强度等优点，以GaN为代表的III族氮化物半导体在发光器件、电力电子、射频器件等领域具有广阔的应用前景。
与传统的Si等非极性半导体材料不同，III族氮化物半导体具有极性，即是极性半导体材料。极性半导体具有许多独特的特性。尤为重要的是，在极性半导体的表面或两种不同的极性半导体界面处存在固定极化电荷。这些固定极化电荷的存在可吸引可移动的电子或空穴载流子，从而形成二维电子气2DEG或二维空穴气2DHG。这些二维电子气2DEG或二维空穴气2DHG的产生不需要附加电场，也不依赖于半导体内的掺杂效应，是自发产生的。极性半导体界面处的二维电子气或二维空穴气可以具有较高的面电荷密度。同时，由于不需要掺杂，二维电子气或二维空穴气受到的离子散射等作用也大大减少，因此具有较高的迁移率。较高的面电荷密度和迁移率使得这种界面处自发产生的二维电子或空穴气体具有良好的导通能力和很高的响应速度。
结合氮化物半导体本身固有的高击穿电场强度等优点，这种二维电子气或二维空穴气可被用于制作高迁移率晶体管,在高能量、高电压或高频率的应用中性能显著优于传统的Si或GaAs器件。然而，现有的结构却存在较多缺陷，严重制约了其应用范围。
发明内容
针对现有技术中存在的技术问题，本发明提出了一种半导体器件，包括：
附图说明
下面，将结合附图对本发明的优选实施方式进行进一步详细的说明，其中：
图1A是根据本发明一个实施例的单通道HEMT截面结构示意图；
图1B是根据本发明一个实施例的具有体电极和互补沟道器件导通状态电场结构示意图；
图1C是根据本发明一个实施例的具有体电极和互补沟道器件互补沟道截止状态电场结构示意图；
图2是根据本发明一个实施例的双通道HEMT截面结构示意图；
图3是根据本发明一个实施例的单通道HHMT截面结构示意图；
图4是根据本发明一个实施例的双通道HHMT截面结构示意图；
图5A-图5Z为根据本发明一个实施例的双通道HEMT的制备方法流程示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
在以下的详细描述中，可以参看作为本申请一部分用来说明本申请的特定 实施例的各个说明书附图。在附图中，相似的附图标记在不同图式中描述大体上类似的组件。本申请的各个特定实施例在以下进行了足够详细的描述，使得具备本领域相关知识和技术的普通技术人员能够实施本申请的技术方案。应当理解，还可以利用其它实施例或者对本申请的实施例进行结构、逻辑或者电性的改变。
本发明提出了一种半导体器件。在一些实施例中，该半导体器件可以在异质衬底上形成。例如通过成核层作为中介，不但可以避免使用昂贵的同质衬底，同时可以将垂直的异质结与异质衬底之间的距离增加，从而提高半导体器件的耐压能力。进一步地，在一些实施例中，异质衬底可以被除去，以进一步提高半导体器件的性能。异质衬底为GaN本征半导体之外的衬底，包括但不限于硅Si衬底、蓝宝石(Al 2O 3)、碳化硅SiC衬底。
本申请中，所涉及载流子为电子或空穴。涉及掺杂类型为N型或P型，导电多子也为电子或空穴。因此，在描述上将载流子与掺杂多子相同或相反的情况，描述为载流子类型与掺杂类型相同或相反是本领域技术人员能够理解的。另外，本申请中有关电接触的描述，既包括直接或间接的电连接关系，也包括电学相互作用关系。
本申请中所述P型掺杂一般是在氮化物半导体中掺杂Mg、Zn等元素，所述N型掺杂是在氮化物半导体中掺杂Si、O、Se、Ge等元素。
本发明所提出的半导体器件可以是肖特基二极管、HEMT、HHMT或者其他半导体器件。以下以HEMT为例进行说明。本领域技术人员应当理解，对于肖特基二极管也可以采用类似的方式实现。
图1A是根据本发明一个实施例的单通道HEMT的截面结构示意图。如图所示，HEMT100包括：第一沟道层103和第一势垒层104A。在第一沟道层103与第一势垒层104A之间形成具有垂直界面的第一异质结，在所述第一异质结内形成垂直的2DEG 105A。
在一些实施例中，第一沟道层103包括：第一沟道区132、第一栅掺杂区134和第二沟道区135。第一沟道区132，其是一种以氮化物半导体(例如GaN)为基的N型掺杂区。其通常为低掺杂或非(故意)掺杂，掺杂浓度为<1E17/cm 3。第一沟道区132的低掺杂或非掺杂可以降低器件整体掺杂引起的沟道载流子迁移率降低现象。
第一栅掺杂区134设置在第一沟道区132上方。第一栅掺杂区134是一种以氮化物半导体(例如GaN)为基的P型掺杂区。第一栅掺杂区134内多子类型与器件载流子类型相反。第一栅掺杂区的掺杂浓度使得第一栅掺杂区134可以耗尽HEMT 100中的二维载流子(即2DEG)，实现器件在非工作状态(不施加电压)下的常关状态。一般的，第一栅掺杂区134的掺杂浓度为1E18-1E20/cm 3。在一些实施例中，第一栅掺杂区134的不同掺杂浓度使得HEMT100具有不同的阈值电压。所以，第一栅掺杂区134的掺杂浓度同样具有调制器件阈值电压的作用。
第二沟道区135设置在第一栅掺杂区134上方。第二沟道区135是一种以氮化物半导体(例如GaN)为基的N型掺杂区。第二沟道区135通常为低掺杂或非(故意)掺杂，以降低掺杂引起的沟道载流子迁移率降低现象。
第一沟道区132、第一栅掺杂区134、第二沟道区135都是第一沟道层103的组成部分，并且各个区都是以相同或禁带宽度相近的氮化物半导体为基础形成的。因此，第一沟道层103作为沟道层整体的禁带宽度是统一的。在一些实施例中，第一沟道层103还包括其他以相同或禁带宽度相近的氮化物半导体为基础形成的区域。进一步地，由于各个区具有相同或相近的禁带宽度，各个区之间的过渡部分电学特性相对稳定，对器件整体性能并无不良影响。
在一些实施例中，第一沟道层103是由沟槽限定。在形成第一沟道层103之前，先形成一个沟槽。该沟槽的高度和宽度等量度与希望的第一沟道层的高度和宽度等量度相同或接近。然后，在该沟槽中外延生长形成第一沟道层103。 以这样方式形成的第一沟道层103可以具有更大的高宽比，而且外延生长的条件和沟道层的形态也更容易控制。
如图所示，第一势垒层104A设置在第一沟道层103右侧。在第一沟道层103与第一势垒层104A之间形成具有垂直界面的第一异质结，在所述第一异质结内形成了垂直的2DEG 105A。这里，2DEG 105A的载流子为电子。而第一沟道区132和第二沟道区135的掺杂类型为N型，也可以提供电子。因此，可以认为第一沟道区132和第二沟道区135的掺杂类型与二维载流子类型相同。同理，第一栅掺杂区134的掺杂类型与二维载流子类型相反。
在通常的生长条件下，在Si(111)面生长的沟道层和势垒层其表面是<0001>面，也就是从Si衬底到沟道层和势垒层的方向是<0001>晶向。在这样的晶向下，沟道层内靠近沟道层和势垒层界面处得到的即为2DEG。如果晶向的方向相反，也就是<000-1>方向，那么在沟道层内靠近沟道层和势垒层界面处得到的即为2DHG。
在一些实施例中，第一沟道层103和第一势垒层104A可以形成于衬底和成核层(未示出)上方。在此之后，衬底和成核层可以被移除。这样，最终器件的结构中并不包含衬底和成核层，以有利于消除异质衬底(例如Si)带来的影响。
如图所示，在本实施例中，HEMT100进一步包括：第一电极107和第二电极108。第一电极107设置在第一栅掺杂区134下方并与第一异质结内的2DEG 105A电接触。第二电极108设置在第一栅掺杂区134上方并也与第一异质结内的2DEG 105A电接触。第一电极107和第二电极108可以成为HEMT100的漏极和源极。在本实施例中，第一电极107与第二电极108与沟道层和/或势垒层104A为欧姆接触。如本领域技术人员所理解的，这里的电接触既包括直接或间接的电连接关系，也包括电学相互作用关系。
如图所示，HEMT 100还包括第三电极109。第三电极109在第一栅掺杂 区134与所述第一异质结内的2DEG 105A电接触。第三电极109提供在第一电极107和第二电极108之间，其可以作为栅电极，控制在第一电极107与第二电极108之间的电流强度，形成HEMT结构。举例而言，施加在第三电极109的电压可以调制第一栅掺杂区134中的多子(空穴)。在此作用下，2DEG 105A中的载流子(电子)不再处于被耗尽状态，第一电极107和第二电极108之间重新形成导电沟道。在一些实施例中，第三电极109水平延伸的长度不低于2DEG 105A长度，以实现对第一电极107和第二电极108之间电流通路的控制。优选地，第一电极107接作漏极接入高电压情况下，第三电极109位于第一电极107和第二电极108之间，更靠近作为源极的第二电极108。这样的设置增大了漏极和栅极之间的距离，能有效提升半导体器件100的耐压性。
在一些实施例中，第一沟道层103进一步包括第一电场调制掺杂区133。第一电场调制掺杂区133位于第三电极附近，并且与第一栅掺杂区134电连接。如图所示，第一电场调制掺杂区133设置在第一栅掺杂区134和第一电极107之间，更靠近第一栅掺杂区134。第一电场调制掺杂区133也是一种以氮化物半导体(例如GaN)为基的P型掺杂区。掺杂浓度小于第一栅掺杂区134，通常为<2E19/cm 3。
因为第一栅掺杂区134需要将2DEG105A内的电子全部耗尽，所以其掺杂浓度相对较高。当第一电极107(漏极)接入高电压时，第一栅掺杂区134与沟道区132二者接触位置的局部电场强度不均匀，影响器件的耐压性能。在两者之间设置第一电场调制掺杂区133作为缓冲可以避免上述问题。第一电场调制掺杂区133虽然同为P型掺杂，但相较第一栅掺杂区134，掺杂浓更低，以避免电场调制掺杂区134严重耗尽沟道载流子浓度从而增加器件的导通电阻。由此，电场调制掺杂区133调节器件电场分布，降低栅掺杂区134附近的局部电场强度，避免出现过局部高电场导致的击穿现象。同时，在沟道区132上先形成第一电场调制掺杂区133再形成第一栅掺杂区134在工艺上也易于处 理。
在一些实施例中，第一沟道层103进一步包括第一欧姆接触掺杂区131。第一欧姆接触掺杂区131设置在第一沟道区132和第一电极107之间。第一欧姆接触掺杂区131用于与第一电极107形成欧姆接触。第一欧姆接触掺杂区131的掺杂类型为N型，其浓度为1E16-2E19/cm 3。第一欧姆接触掺杂区131增加了载流子浓度，可以降低与第一电极107的欧姆接触电阻。
在一些实施例中，第一沟道层103进一步包括第二欧姆接触掺杂区136。第二欧姆接触掺杂区136设置在第二沟道区135和第二电极108之间。第二欧姆接触掺杂区136用于与第二电极108形成欧姆接触。第二欧姆接触掺杂区136的掺杂类型为N型，其浓度为1E16-2E19/cm 3。第二欧姆接触掺杂区136增加了载流子浓度，可以降低与第二电极108的欧姆接触电阻。
在一些实施例中，HEMT100进一步包括第二势垒层104B，其形成在第一沟道层103左侧，其中在第一沟道层103与第二势垒层104B之间形成具有垂直界面的第二异质结，在所述第二异质结内形成垂直的2DHG 105B。第二势垒层104B可以与第一势垒层104A相同氮化物半导体材料组成。
2DEG 105A和2DHG 105B形成互补性沟道。例如，当HEMT100处于关闭状态时，2DEG 105A靠近第一电极107处于高电位，第一栅掺杂区134与第一电极107的2DEG被耗尽，露出本底的正电荷。在HEMT100内部形成具有一定方向的电场，使得HEMT100内部电场分布不均，进而影响器件性能。2DHG 105B并不与其他电极相连，HEMT100的内部电场分布不均将使得2DHG的分布改变，从而使得HEMT100内部电场分布更均匀，器件工作更稳定。本领域技术人员应当理解，2DHG 105B可以形成在第一沟道层103的全部或部分区域的一侧，从而在这些区域中都可以发挥调节内部电场的作用。特别地，2DHG可以形成第一沟道层103对应于第一电极(漏极)和第三电极(栅极)之间的区域(例如：第一欧姆接触掺杂区131、第一沟道区132、电场调 制掺杂区133和第一栅掺杂区134)，以提高器件的耐压性能。
在一些实施例中，进一步包括第四电极106，其设置在靠近第一栅掺杂区134的位置，并与第一栅掺杂区134电连接。在没有第二异质结以及2DHG 105B的情况下，第四电极106可以直接或间接与第一栅掺杂区134电接触。或者，如图所示，其在第一栅掺杂区134的位置与第二异质结内的2DHG 105B电接触。第四电极106可以作为体电极单独控制或者与第二电极108电连接。如所举例的，第四电极106可以选择接入0V电压。
当HEMT100工作时，电极109会接入外部电压以开启器件。当电极109与外部电压连接时，原本接入外部电压而引入的电荷无法全部释放，可能会在第一栅掺杂区134形成部分残余电荷。这些残余电荷会一定程度上中和第一栅掺杂区134内的多子。因此，再次工作时，HEMT100的阈值电压会发生漂移。增加了第四电极106后，在HEMT100关断时，残余电荷会经由第四电极(体电极)传导至器件之外。这样，第一栅掺杂区134的电势相对固定，HEMT100的阈值电压也更稳定。
下面结合图1B-图1C详细描述互补沟道和第四电极对器件内电场的调整平衡作用。其中，为了方便说明对器件结构进行了简化，本领域技术人员应该知晓，所述技术效果适用于所用包含该结构的器件。图1B是根据本发明一个实施例的具有体电极和互补沟道器件导通状态电场结构示意图。图1C是根据本发明一个实施例的具有体电极和互补沟道器件互补沟道截止状态电场结构示意图。其中，与图1A中相同或相似结构在此不再赘述。
图1B进一步包括与2DEG 105A相对应的本底正电荷155A以及与2DHG 105B相对应的本底负电荷155B。如图1B所示，在器件导通时，器件内电场分布均匀，第四电极106基本无影响。本申请所涉及结构中，在器件关闭状态下电场分布，如图1C所示。在2DHG 105B和第四电极106(体电极)同时存在时，第四电极106位于2DHG 105B左侧并与2DHG 105B电连接。当器件处 于关闭状态时，2DHG 105B通过第四电极106接触，由于第四电极106电压远低于第一电极107电压，2DHG 105B被全部或者部分耗尽，露出本底负电荷。左侧本底负电荷与右侧本底正电荷形成稳定的内部电场，分布更均匀，也使得器件工作更稳定。
在一些实施例中，HEMT100进一步包括第一成核层。第一沟道层103从第一成核层外延生长。在一些实施例中，第一沟道层103在第一成核层上方。在一些实施例中，第一成核层是经掺杂的，因此具有良好的导电性。在一些实施例中，所述第一成核层从衬底的第一垂直界面外延生长而形成。
在一些实施例中，在势垒层104A侧面电极107和电极109之间包括绝缘层112。绝缘层112水平横向延伸，其材料可以为SiO 2等绝缘材料。在一些实施例中，屏蔽层112可以作为栅绝缘层，部分填充至势垒层104A和电极109之间。
在一些实施例中，在势垒层104B侧面电极106下方包括绝缘层113。绝缘层113水平横向延伸，其材料可以为SiO 2等绝缘材料。屏蔽层112和绝缘层113将势垒层104A和势垒层104B侧面与外界隔离，能够避免外界对于器件性能产生影响。
在一些实施例中，在图1所示的半导体器件上方可以包括钝化层(未示出)以保护下方的半导体结构。进一步地，半导体器件上方还可以包括第一导体互联层、第二导体互联层和第三导体互联层，其分别与第一电极107、第二电极108和第三电极109电连接。这些都是本领域技术人员所熟知，这里不再赘述。在一些实施例中，第四电极可以在外侧与半导体器件上方的第四导体互联层电连接。四个电极各自对应相应的导体互联层，在垂直方向接入位置各不相同，工艺制程更加简单。
在一些实施例中，HEMT100进一步包括异质衬底。在本实施例中，衬底为硅Si衬底。衬底的垂直表面的晶格具有六角对称性，以使得随后能够外延 生长氮化物半导体晶体。例如，被曝露的衬底的垂直界面可以是Si(111)面。在其他一些实施例中，衬底也可以为蓝宝石Al 2O 3衬底、SiC衬底、或者GaN本征衬底。在一些实施例中，成核层可以为AlN。在本文中，成核层还可以包括缓冲层(未示出)。缓冲层可以具有单层或多层结构，包括AlN、GaN、AlGaN、InGaN、AlInN和AlGaInN中一种或多种。
如本领域技术人员所知，以上的描述仅仅是示例性的说明HEMT的结构。本申请所涉及器件还存在着多种其他的结构或者在这些结构上的改进、变更、或者变型，以提供不同的特性或者功能。这些结构及其改进、变更或变型在本发明的技术构思之下，也可以应用于本发明的方案中。
本发明所涉及半导体器件，相较传统器件而言，其不但具有垂直结构的2DEG，而且其沟道层组成不再是单一材料，而是分成多个区域经过不同掺杂形成的。栅掺杂区的掺杂类型与载流子类型相反，能够耗尽载流子，使得器件在栅电极不施加电压的常态下实现常闭功能。传统器件中不具有类似结构，因此器件本身是常开状态，在实际应用中会大大增加功耗。
本发明所涉及半导体器件，不包括衬底和成核层等结构。但其形成过程中是在异质衬底，例如Si，上完成的，制备工艺成本较低。形成器件后，将衬底和成核层去除，避免了异质衬底耐压性低等缺点，相较传统器件具有更好的耐压性和载流子迁移率。
本发明进一步包括一种双通道HEMT结构。图2是根据本发明一个实施例的双通道HEMT截面结构示意图。图2中所示HEMT200也可以认为是两个如图1所示半导体器件HEMT100组合而成，其中，与前述结构相似的部分，在此不再赘述。
如图所示，HEMT200左侧包括第一沟道层203A，其包括由下至上层叠设置的第一欧姆接触掺杂区231A、第一沟道区232A、第一电场调制掺杂区233A、第一栅掺杂区234A、第二沟道区235A以及第二欧姆接触掺杂区236A。 HEMT200右侧包括第二沟道层203B，其包括由下至上层叠设置的第三欧姆接触掺杂区231B、第三沟道区232B、第二电场调制掺杂区233B、第二栅掺杂区234B、第四沟道区235B以及第四欧姆接触掺杂区236B。
HEMT 200的第一沟道层203A右侧进一步包括第一势垒层204A，第二沟道层203B左侧进一步包括第三势垒层204C。由于第一沟道层203A和第一和第二势垒层204A和204C具有不同的能带带隙，HEMT200内形成具有垂直界面的第一和第三异质结，在两个异质结内形成垂直的二维电子气2DEG 205A和2DEG 205C。
在欧姆接触掺杂区236A和欧姆接触掺杂区236B上分别设置有电极208A和电极208B，分别与欧姆接触掺杂区236A和欧姆接触掺杂区236B形成欧姆接触，也分别与2DEG 205A和2DEG 205C电连接。在HEMT200中，两个沟道层内2DEG 205A和2DEG 205C分别形成在沟道层偏右和偏左的位置，是因为在形成过程中，生长两部分结构的衬底垂直界面是同晶向结构相对设置的。这样的结构可以实现更高的集成度。
HEMT 200第一沟道层203A左侧进一步包括第二势垒层204B，第二沟道层203B右侧进一步包括第四势垒层204D。由于沟道层和势垒层204B和204D具有不同的能带带隙，HEMT 200内形成具有垂直界面的第二和第四异质结。在两个异质结内形成垂直的二维空穴气2DHG 205B和2DHG 205D。
在一些实施例中，HEMT 200第二势垒层204B左侧靠近栅掺杂区234A的位置进一步包括第四电极206A；其在第一栅掺杂区234A与异质结内的2DHG 205B电接触。HEMT 200第二势垒层204D有侧靠近栅掺杂区234B的位置进一步包括第四电极206B；其在第一栅掺杂区234B与异质结内的2DHG 205C电接触。第四电极206A和206B可以作为体电极单独控制或者与第二电极208A和208B电连接。可选地，第四电极206A和206B接入0V电压。
HEMT200中，对于第一沟道层203A和第二沟道层203B，电极209同作 为栅电极是共用的，电极207同作为漏电极是共用的。在一些实施例中，第一沟道层和第二沟道层可以分别具有各自的栅电极和漏电极。
在本实施例中，HEMT200不但具有上述HEMT100的优点，在此基础上HEMT200包括两个导电沟道，即2DEG 205A和205C。增加的导电沟道可以增大导通电流，从而有着更高的功率；并且，双导电通道相较单导电通道的耐压和耐热性能也更优。而且，双导电沟道结构的相同属性电极可以共用，而无需分别形成两个电极，这样节省了空间，也能够显著节省了制造成本和制造工时。
在一些实施例中，类似结构同样可以形成具有2DHG的高空穴迁移率晶体管HHMT。图3是根据本发明一个实施例的单通道HHMT截面结构示意图。其中，与图1中结构类似的部分在此不再赘述。
如图所示，HHMT 300的整体结构与HEMT100类似，但由于形成过程中衬底的垂直界面为(000-1)面，与HEMT100不同，因此HHMT300中导电沟道为2DHG 305A。相应的，HHMT 300进一步包括2DEG 305B。由于导电沟道是2DHG105A，其载流子也有电子变成空穴。因此，HHMT 300中欧姆接触掺杂区331、沟道区332、沟道区335以及欧姆接触掺杂区336的掺杂类型为P型。电场调制掺杂区333和栅掺杂区334的掺杂类型为N型。
本实施例中，HHMT没有衬底和成核层，二者对导电沟道无影响，器件的性能能够得到进一步的提高。
图4是根据本发明另一个实施例的双沟道HHMT的结构示意图。图4中所示HHMT400也可以认为是两个如图3所示半导体器件HHMT300组合而成，其中，与前述结构相似的部分，在此不再赘述。
如图所示，HHMT 400左侧包括第一沟道层403A，其包括由下至上层叠设置的第一欧姆接触掺杂区431A、第一沟道区432A、第一电场调制掺杂区433A、第一栅掺杂区434A、第二沟道区435A以及第二欧姆接触掺杂区436A。 HHMT400右侧包括第二沟道层，其包括由下至上层叠设置的第三欧姆接触掺杂区431B、第三沟道区432B、第二电场调制掺杂区433B、第二栅掺杂区434B、第四沟道区435B以及第四欧姆接触掺杂区436B。
HHMT 400第一沟道层403A右侧进一步包括第一势垒层404A，第二沟道层403B左侧进一步包括第三势垒层404C。由于沟道层和势垒层404A和404C具有不同的能带带隙，HHMT200内形成具有垂直界面的第一和第三异质结。在两个异质结内形成垂直的二维电子气2DHG 405A和2DHG 405C。
在欧姆接触掺杂区436A和欧姆接触掺杂区436B上分别设置有电极408A和电极408B，分别与欧姆接触掺杂区436A和欧姆接触掺杂区436B形成欧姆接触，也分别与2DHG 405A和2DHG 405C电连接。
HEMT 400第一沟道层403A左侧进一步包括第二势垒层404B，第二沟道层403B右侧进一步包括第四势垒层404D。由于沟道层和势垒层404B和404D具有不同的能带带隙，HEMT 400内形成具有垂直界面的第二和第四异质结。在两个异质结内形成垂直的二维电子气2DEG 405B和2DEG 405D。
在一些实施例中，HHMT 400第二势垒层404B左侧靠近栅掺杂区434A的位置进一步包括电极406A；其在第一栅掺杂区434A与异质结内的2DHG 405B电接触。HHMT 400第二势垒层404D有侧靠近栅掺杂区434B的位置进一步包括第电极406B；其在第一栅掺杂区434B与异质结内的2DHG 405C电接触。电极406A和406B可以作为体电极单独控制或者与电极408A和408B电连接。可选地，电极406A和406B接入0V电压。
HEMT400中，对于第一沟道层403A和第二沟道层403B，电极409同作为栅电极是共用的，电极407同作为漏电极是共用的。在一些实施例中，第一沟道层和第二沟道层可以分别具有各自的栅电极和漏电极。
在本实施例中，HEMT400包括两个导电沟道，即2DHG 405A和405C。增加的导电沟道可以增大导通电流，从而有着更高的功率；并且，双导电通道 相较单导电通道的耐压和耐热性能也更优。而且，双导电沟道结构的相同属性电极可以共用，而无需分别形成两个电极，这样节省了空间，也能够显著节省了制造成本和制造工时。
本发明还包括一种半导体器件的制造方法。下面以一种双通道HEMT的制造流程为例，说明本发明的半导体器件的制备方法。
图5A-图5Z为根据本发明一个实施例的双通道HEMT的制备方法流程示意图。在本实施例中，在硅衬底上制作半导体器件。如本领域技术人员所理解，其他衬底如本征GaN、Al 2O 3(蓝宝石)、SiC等，也可以实现类似结构。
如图所示，HEMT的制备方法500包括：在步骤5001，如图5A所示，提供Si衬底501。
在步骤5002，在衬底上形成多个第一沟槽，如图5B所示。例如，通过光刻技术刻蚀衬底501，衬底501上形成多个矩形第一沟槽521，曝露衬底501的垂直界面541和542；其中，第一沟槽521内衬底垂直界面541和542是Si衬底的(111)面(即晶体<0001>面)。本领域中也存在其他方式得到第一沟槽521，这些方法也可以应用于此。
在一些实施例中，同一衬底设置的第一沟槽的个数视具体集成度、耐压性等要求而定，这里仅以3条沟槽为例进行说明。本发明所涉及方法可以根据实际需求预先构造沟槽的形状和尺寸，例如形成耐压比较高的半导体器件时，沟槽深度也较深。
在一些实施例中，当曝露出的垂直界面是<000-1>面时，可以形成如图3或图4所示HHMT，在此不再赘述。
在步骤5003，在衬底及衬底上的第一沟槽表面形成保护层，如图5C所示。在衬底501上使用LPCVD等技术生长SiN保护层531，覆盖衬底501和多个沟槽521的表面。
在步骤5004，去除第一沟槽底面和衬底上表面水平延伸的保护层，保留第 一沟槽侧壁的保护层，如图5D所示。通过具有垂直取向的刻蚀技术，仅保留在垂直界面541和542上的SiN形成的保护层531，曝露沟槽521底面的Si衬底501。保护层531覆盖衬底沟槽521的衬底垂直界面541和542。
在步骤5005，在衬底和第一沟槽上形成第一分隔层，如图5E所示。在第一沟槽521的底面上覆盖分隔层511。在一些实施例中，可以使用氧化技术形成SiO 2，从而在衬底501上形成第一分隔层511。由于衬底501的垂直界面541和542上覆盖有保护层531，衬底501的垂直界面541和542上基本没有生长分隔层511。
在步骤5006，去除沟槽侧壁的保护层，如图5F所示。在衬底501上方的分隔层511覆盖掩膜，通过选择性刻蚀技术、光刻技术或其他技术部分刻蚀第一沟槽521侧壁上的保护层531。例如，刻蚀可以包括去除部分第一沟槽521的侧壁。刻蚀后，衬底501的垂直界面541和542曝露。本领域中还存在其他方法以去除保护层而曝露衬底的垂直界面。这些方法也可以应用于此。
在步骤5007，在垂直界面形成第一成核层和第二成核层，如图5G所示。衬底501曝露的垂直表面541和542上生长第一和第二成核层502A和502B。成核层502A和502B包括AlN。在一些实施例中，在形成AlN后，可以进一步生长AlN、GaN、AlGaN、InGaN、AlInN和AlGaInN中一种或多种缓冲材料。在一些实施例中，成核层在水平延伸生长的同时，也会在垂直方向上生长(未示出)。通过工艺参数的控制，可以使得成核层的生长尽量沿水平方向。尽管存在垂直方向上的生长，但是并不会对器件结构产生影响。
在一些实施例中，沉积氮化物半导体成核层(AlN或AlN/AlGaN/GaN的复合结构),由于Al生长的低选择性，在SiO2上可能存在多晶或非晶的AlN或AlGaN。可以在形成成核层后取出晶圆，通过垂直刻蚀方式去除多晶或非晶的AlN或AlGaN。
在步骤5008，在整个器件的表面形成第二分隔层，如图5H所示。在图5G 所示结构上，通过沉积工艺形成SiO 2第二分隔层519。第二分隔层519填充沟槽521并在衬底上形成一定高度的SiO 2第二分隔层519。在一些实施例中，如果希望形成高宽比较大的半导体器件，第二分隔层519的高度也就会相应增加。
在步骤5009，图形化第二分隔层，形成多个第二沟槽，曝露部分成核层，如图5I所示。通过垂直刻蚀技术，在第二分隔层519上刻蚀垂直的第二沟槽525和524。基本上，第二沟槽525和524定义了半导体器件第二层的高度，即形成器件后器件的整体高度。并将成核层的高度限制在第一层。在沟槽523和524底部，曝露出成核层502A和502B的上表面。
本领域技术人员应当注意，成核层502A和502B形成在Si衬底(111)面，因此，成核层502A和502B具有六角对称性。曝露成核层502A和502B的上表面后，沟槽523和524内形成的其他结构也具有六角对称性。
在步骤5010，在多个第二沟槽内生长第一欧姆接触掺杂区，如图5J所示。通过化学气相掺杂将氮化物半导体和掺杂介质沉积在成核层502A和502B上，形成第一欧姆接触掺杂区531A和531B。对于通过2DEG导电的器件，掺杂类型为N型。对于通过2DHG导电的器件，掺杂类型为P型。由于2DEG中载流子为电子，N型掺杂也是通过电子导电，因此可以认为掺杂类型与二维载流子类型相同。对于传统沉积或外延生长，其水平方向生长状况不易控制，因此半导体结构很难保持完全垂直生长，可能出现多个生长面。本发明所涉及结构能保持同一面的连续生长，提升了器件的电学特性。
在步骤5011，在第一欧姆接触掺杂区上形成第一沟道区，如图5K所示。通过化学气相掺杂将氮化物半导体和掺杂介质沉积在第一欧姆接触掺杂区5331A和531B上，形成第一沟道区532A和第三沟道区532B。第一沟道区532A和第三沟道区532B的掺杂为低掺杂或非(故意)掺杂，掺杂类型为N型。
在步骤5012，在第一沟道区上形成电场调制掺杂区，如图5L所示。通过化学气相掺杂将氮化物半导体和掺杂介质沉积在第一沟道区532A和第三沟道 区532B上，形成电场调制掺杂区533A和533B。电场调制掺杂区533A和533B的掺杂类型为P型。
在步骤5013，在电场调制掺杂区上形成栅堆垛掺杂区，如图5M所示。电场调制掺杂区533A和533B上，通过化学气相掺杂将氮化物半导体和掺杂介质通入，形成栅掺杂区534A和534B。栅掺杂区534A和534B的掺杂类型为P型，掺杂浓度高于电场调制掺杂区533A和533B。
在步骤5014，在栅掺杂区上形成第二沟道区，如图5N所示。栅掺杂区534A和534B上，化学气相掺杂将氮化物半导体和掺杂介质，形成第二沟道区535A和第四沟道区535B。第二沟道区535A和第四沟道区535B的掺杂为低掺杂或非(故意)掺杂，掺杂类型为N型。
在步骤5015，在第二沟道区和第四沟道区上形成第二欧姆接触掺杂区，如图5O所示。第二沟道区535A和第四沟道区535B上，通过化学气相掺杂将氮化物半导体和掺杂介质，形成第二欧姆接触掺杂区536A和536B。第二欧姆接触掺杂区536A和536B的掺杂类型为N型。
在步骤5016，去除剩余第二分隔层，如图5P所示。通过刻蚀技术将剩余的第二分隔层519去除。去除后，分隔层511上表面曝露，第一沟道层和第二沟道层除与成核层接触位置全部曝露。成核层上表面未与第一沟道层和第二沟道层接触位置和未与衬底接触的侧壁曝露。
在步骤5017，沉积势垒层，如图5Q所示。在器件上沉积势垒层504，势垒层覆盖在器件表面。形成势垒层504，其中在第一沟道层与势垒层之间形成具有垂直界面的第一异质结和第二异质结，在所述第一异质结内和第二异质结内形成垂直的2DEG505A和2DHG505B。同样的，在第二沟道层与势垒层之间形成具有垂直界面的第三异质结和第四异质结，在所述第三异质结内和第四异质结内形成垂直的2DEG505C和505D。在一些实施例中，在沉积势垒层之前可以先沉积一层较薄的未掺杂的沟道层，其材料与原沟道层基底氮化物半导 体相同。这样可以保证势垒层和沟道层更良好的接触，电学特性更稳定。
在步骤5018，沉积绝缘层，如图5R所示。沉积绝缘层518在器件表面，绝缘层518会覆盖在势垒层504上，最终使得器件更加平整。
在步骤5019，图形化绝缘层，在第一沟道层和第二沟道层之间形成第三沟槽，如图5S所示。在一些实施例中，刻蚀在第一沟道层和第二沟道层之间的绝缘层518，形成第三沟槽525，同时保留的绝缘层形成屏蔽层512。这里刻蚀的深度需保证略低于栅掺杂区和电场调制掺杂区接触面，以保证在后续形成电极的过程中电极与栅掺杂区的良好接触。
在步骤5020，沉积第三电极，如图5T所示。第三电极509在沟槽525底部，在第一栅掺杂区和第二栅掺杂区之间，并与第一异质结内的2DEG505A和505B电接触，通过电极沉积方法在势垒层之间位置形成第三电极509。为保证第三电极509与第一栅掺杂区和第二栅掺杂区的处分电接触。电极509的高度略高于第一栅掺杂区和第二栅掺杂区上表面。在一些实施例中，电极509作为栅极设置在更靠近上方位置，电极509作为栅极尽量远离漏极，以提升器件整体耐压性。在一些实施例中，电极509可以是分别控制第一沟道层和第二沟道层的两个电极。本实施例中的方案工艺流程更加简单。
在步骤5021，沉积第三分隔层，后曝露第一沟道层和第二沟道层上表面，如图5U所示。在整个器件上重新形成第三分隔层514。通过沉积工艺将SiO 2沉积在半导体器件上，使其填充电极507上方部分并覆盖沟道层与势垒层，形成第三分隔层514。然后通过光刻工艺去除部分势垒层504将第一沟道层和第二沟道层上表面曝露。此时原本为一整体的势垒层504被分隔为第一势垒层504A、第二势垒层504B、第三势垒层504C以及第四势垒层504D。
在步骤5022，沉积第二电极，如图5V所示。在第一沟道层和第二沟道层上表面靠近2DEG505A和505B的位置通过电极沉积方法形成第二电极508A和508B。第二电极508A和508B与第二欧姆接触掺杂区形成欧姆接触，且与 2DEG505A和505C电连接。并且第二电极508A和508B不与2DHG505B和505D电连接。在一些实施例中，第二电极508A和508B作为器件源极。在一些实施例中，第二电极508A和508B接入低电平，例如0V。
在一些实施例中，第二电极508A和508B也可以是同一电极。
在步骤5023，图形化靠近第二势垒层和第四势垒层的绝缘层，如图5W所示。通过垂直刻蚀技术，将刻蚀部分第二势垒层和第四势垒层的绝缘层518，形成沟槽526，同时形成绝缘层513。这里刻蚀的深度需保证略低于栅掺杂区和电场调制掺杂区接触面，以保证在后续形成电极的过程中电极与栅掺杂区的良好接触。
在步骤5024，沉积第四电极，如图5X所示。第四电极506在沟槽526底部，在第一栅掺杂区和第二栅掺杂区之间，并与第一异质结内的2DHG505B和505D电接触，通过电极沉积方法在势垒层之间位置形成第四电极506。为保证第四电极506与第一栅掺杂区和第二栅掺杂区的充分电接触。电极506的高度略高于第一栅掺杂区和第二栅掺杂区上表面。在一些实施例中，电极506作为体电极设置在与电极509同等高度的位置。在一些实施例中，电极506可以是分别控制第一沟道层和第二沟道层的两个电极。本实施例中的方案工艺流程更加简单。也可以形成直接于2DHG欧姆接触的第四电极，并且第四电极通过2DHG与栅掺杂区电连接。
在步骤5025，将整个半导体器件翻转，并去除衬底和成核层，如图5Y所示。如图所示，半导体器件翻转后，衬底501朝向上方。先将衬底501减薄，然后在通过湿法刻蚀，将整个衬底501和成核层502A和502B从半导体器件中除去。曝露出第一沟道层和第二沟道层上表面。
在步骤5026，形成第一电极，如图5Z所示。通过沉积金属，在第一沟道层和第二沟道层上形成金属电极，即第一电极507。第一电极507与第一异质结和第三异质结中垂直的2DEG505A和505C都电连接，但不与2DHG505B 和505D电连接。
在一些实施例中，后续步骤包括形成第一导体互联层、第二导体互联层和第三导体互联层，其分别电连接到第一电极、第二电极和第三电极。这些步骤都是本领域技术人员所熟知的，这里不再赘述。
通过上述方法形成的HEMT，其沟道层可以具有较高的宽高比。同时实现器件在非通电状态下的常闭。
本发明前述结构只是示例性的说明了本发明的技术方案。在一些实施例中，同一沟槽中可以包括更多的半导体结构，从而形成一种集成度更高的方案。例如在形成HHMT时，只需调整衬底垂直界面晶向和沟道层内各区掺杂类型即可。
上述实施例仅供说明本发明之用，而并非是对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明范围的情况下，还可以做出各种变化和变型，因此，所有等同的技术方案也应属于本发明公开的范畴。

Claims (40)

  1. 一种半导体器件，包括：
    第一沟道层，其包括第一沟道区、第一栅掺杂区、和第二沟道区，其中所述第二沟道区在所述第一沟道区之上，所述第一栅掺杂区在所述第一沟道区和所述第二沟道区之间；
    第一势垒层，其中在第一沟道层与第一势垒层之间形成具有垂直界面的第一异质结，在所述第一异质结内形成垂直的2DEG或2DHG；
    第一电极，其在所述第一栅掺杂区下方与所述第一异质结内的2DEG或2DHG电接触；
    第二电极，其在所述第一栅掺杂区上方与所述第一异质结内的2DEG或2DHG电接触；以及
    第三电极，其在所述第一栅掺杂区与所述第一异质结内的2DEG或2DHG电接触。
  2. 如权利要求1所述的半导体器件，其中所述第一栅掺杂区的掺杂类型与所述第一异质结内的二维载流子类型相反。
  3. 如权利要求1所述的半导体器件，其中所述第一栅掺杂区耗尽所述第一异质结内的二维载流子。
  4. 如权利要求1所述的半导体器件，其中所述第一沟道层包括第一电场调制掺杂区，其中所述第一电场调制掺杂区与所述第一栅掺杂区电连接。
  5. 如权利要求4所述的半导体器件，其中所述第一电场调制掺杂区位于所述第三电极附近。
  6. 如权利要求4所述的半导体器件，其中所述第一电场调制掺杂区位于所述第一电极与第三电极之间。
  7. 如权利要求1所述的半导体器件，其中所述第一沟道层的所述第一沟道区为低掺杂或非故意掺杂。
  8. 如权利要求1所述的半导体器件，其中所述第二沟道层的所述第一沟 道区为低掺杂或非故意掺杂。
  9. 如权利要求1所述的半导体器件，其中所述第一沟道层包括与第一电极相邻的第一欧姆接触掺杂区。
  10. 如权利要求1所述的半导体器件，其中所述第一沟道层包括与第二电极相邻的第二欧姆接触掺杂区。
  11. 如权利要求1所述的半导体器件，进一步包括第二势垒层，其中在第一沟道层与第二势垒层之间形成具有垂直界面的第二异质结，在所述第二异质结内形成垂直的2DEG或2DHG。
  12. 如权利要求11所述的半导体器件，进一步包括第四电极，其与所述第一栅掺杂区电接触。
  13. 如权利要求12所述的半导体器件，其中第四电极单独控制或者与所述第一电极电连接。
  14. 如权利要求12所述的半导体器件，其中所述第二势垒层位于所述第四电极的下方。
  15. 如权利要求1所述的半导体器件，进一步包括第一成核层，其中所述第一沟道层从所述第一成核层外延生长。
  16. 如权利要求15所述的半导体器件，其中所述第一沟道层在所述第一成核层上方。
  17. 如权利要求15所述的半导体器件，其中所述第一成核层是经掺杂的。
  18. 如权利要求15所述的半导体器件，其中所述第一成核层从衬底的第一垂直界面外延生长。
  19. 如权利要求1所述的半导体器件，其中所述第一沟道层由沟槽限定。
  20. 如权利要求1所述的半导体器件，其中所述第一电极与所述第一异质结下方的第一外部电压连接；其中所述第二电极与所述第一异质结上方的第二外部电压连接。
  21. 如权利要求1所述的半导体器件，进一步包括：
    第二沟道层，其包括第三沟道区、第二栅掺杂区、和第四沟道区，其中所述第四沟道区在所述第三沟道区之上，所述第二栅掺杂区在所述第三沟道区和所述第四沟道区之间；
    第三势垒层，其中在第二沟道层与第三势垒层之间形成具有垂直界面的第第三异质结，在所述第三异质结内形成垂直的2DEG或2DHG；
    第五电极，其在所述第二栅掺杂区下方与所述第三异质结内的2DEG或2DHG电接触；以及
    第六电极，其在所述第二栅掺杂区上方与所述第三异质结内的2DEG或2DHG电接触；
    其中，所述第三电极在所述第二栅掺杂区与所述第三异质结内的2DEG或2DHG电接触。
  22. 如权利要求21所述的半导体器件，其中所述第一电极与所述第五电极为同一电极。
  23. 如权利要求21所述的半导体器件，其中所述第二电极与所述第六电极为同一电极。
  24. 如权利要求21所述的半导体器件，其中所述第二沟道层包括第二电场调制掺杂区，其中所述第二电场调制掺杂区与所述第二栅掺杂区电连接。
  25. 如权利要求21所述的半导体器件，进一步包括第四势垒层，其中在第二沟道层与第四势垒层之间形成具有垂直界面的第四异质结，在所述第四异质结内形成垂直的2DEG或2DHG。
  26. 如权利要求24所述的半导体器件，进一步包括第七电极，其在所述第二栅掺杂区与所述第四异质结内的2DEG或2DHG电接触。
  27. 如权利要求25所述的半导体器件，其中第七电极单独控制或者与所述第五电极电连接。
  28. 如权利要求21所述的半导体器件，进一步包括第二成核层，其中所述第二沟道层从所述第二成核层外延生长。
  29. 如权利要求27所述的半导体器件，其中所述第二成核层从衬底的第二垂直界面外延生长。
  30. 如权利要求21所述的半导体器件，进一步包括异质衬底。
  31. 一种半导体器件的制造方法，包括：
    在衬底的垂直界面形成第一成核层；
    从第一成核层外延生长第一沟道层的第一沟道区；
    在第一沟道区之上形成第一沟道层的第一栅掺杂区；
    在第一栅掺杂区之上形成第一沟道层的第二沟道区；
    形成第一势垒层，其中在第一沟道层与第一势垒层之间形成具有垂直界面的第一异质结，在所述第一异质结内形成垂直的2DEG或2DHG；以及
    形成第一电极、第二电极和第三电极，其中，第一电极在所述第一栅掺杂区下方与所述第一异质结内的2DEG或2DHG电接触；第二电极在所述第一栅掺杂区上方与所述第一异质结内的2DEG或2DHG电接触；以及第三电极在所述第一栅掺杂区与所述第一异质结内的2DEG或2DHG电接触。
  32. 如权利要求31所述的方法，进一步包括：形成第一沟槽；其中，所述第一沟道区、第一栅掺杂区以及第二沟道区形成于第一沟槽中。
  33. 如权利要求32所述的方法，进一步包括：形成第一电场调制掺杂区，其中第一电场调制掺杂区形成于第一沟槽中。
  34. 如权利要求31所述的方法，进一步包括：形成第二势垒层，其中在第一沟道层与第二势垒层之间形成具有垂直界面的第二异质结，在所述第二异质结内形成垂直的2DEG或2DHG。
  35. 如权利要求34所述的方法，进一步包括：形成第四电极，其在所述第一栅掺杂区与所述第二异质结内的2DEG或2DHG电接触。
  36. 如权利要求34所述的方法，进一步包括：去除衬底。
  37. 如权利要求36所述的方法，其中第一电极从经去除衬底的方向与第一异质结电接触。
  38. 如权利要求36所述的方法，进一步包括：
    形成第二沟道层，其中第二沟道层包括第三沟道区、第二栅掺杂区、和第四沟道区，其中所述第四沟道区在所述第三沟道区之上，所述第二栅掺杂区在所述第三沟道区和所述第四沟道区之间；
    形成第三势垒层，其中第三势垒层在第二沟道层与第三势垒层之间形成具有垂直界面的第第三异质结，在所述第三异质结内形成垂直的2DEG或2DHG；
    形成第五电极，其中第五电极在所述第二栅掺杂区下方与所述第三异质结内的2DEG或2DHG电接触；以及
    形成第六电极，其中第六电极在所述第二栅掺杂区上方与所述第三异质结内的2DEG或2DHG电接触；
    其中，所述第三电极在所述第二栅掺杂区与所述第三异质结内的2DEG或2DHG电接触。
  39. 如权利要求38所述的方法，进一步包括：形成第四势垒层，其中在第二沟道层与第四势垒层之间形成具有垂直界面的第四异质结，在所述第四异质结内形成垂直的2DEG或2DHG。
  40. 如权利要求39所述的方法，进一步包括：形成第七电极，其在所述第二栅掺杂区与所述第四异质结内的2DEG或2DHG电接触。
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