WO2019242101A1 - 氧化镓垂直结构半导体电子器件及其制作方法 - Google Patents

氧化镓垂直结构半导体电子器件及其制作方法 Download PDF

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WO2019242101A1
WO2019242101A1 PCT/CN2018/103270 CN2018103270W WO2019242101A1 WO 2019242101 A1 WO2019242101 A1 WO 2019242101A1 CN 2018103270 W CN2018103270 W CN 2018103270W WO 2019242101 A1 WO2019242101 A1 WO 2019242101A1
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gate
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electronic device
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French (fr)
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张晓东
李军帅
范亚明
张宝顺
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中国科学院苏州纳米技术与纳米仿生研究所
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the invention particularly relates to a gallium oxide vertical structure semiconductor electronic device and a manufacturing method thereof, and belongs to the technical field of semiconductor devices.
  • any solid-state energy conversion system is composed of circuits.
  • Switching power supplies are the cornerstone of energy conversion and are widely implanted in these circuits. If the switching device is implemented in the field of energy conversion to achieve high efficiency and energy saving, the loss of the entire system can be reduced, and at the same time, costs can be saved. Therefore, to implement a zero-loss system, start by making a zero-loss power switch. To realize a zero-loss power switch, the key is to find a suitable semiconductor material so that the resistance of the switch is almost zero when it is turned on.
  • field effect transistors mainly have two structure types: one is a horizontal structure device, and the other is a vertical structure device (Vertical Field Effect Transistor), which mainly includes vertical MOSFETs and vertical current aperture transistors CAVET, Current Aperture, Vertical, Electron, Transistor).
  • the horizontal device has the following disadvantages compared to the vertical device: When the horizontal structure electronic device is in the off state, electrons can reach the drain from the semi-insulating buffer layer, forming a buffer layer leakage phenomenon. The leakage phenomenon of the buffer layer will seriously cause leakage. The pole current has reached the condition of the breakdown judgment at a lower voltage.
  • horizontal structure electronic devices mainly rely on the active area between the gate and the drain to withstand the voltage.
  • a large gate-drain spacing needs to be designed, which increases the chip.
  • the required area is inconsistent with the demand for miniaturization and is not conducive to reducing production costs.
  • High power conversion applications require large currents and high voltages.
  • Chips designed with horizontal structures are neither economical nor difficult to prepare.
  • the high electric field region is located on the edge of the gate near the drain side.
  • the high electric field injects electrons into the traps on the surface, causing the current to collapse. This serious reliability problem further limits the lateral device Application in high voltage field.
  • the main purpose of the present invention is to provide a gallium oxide vertical structure semiconductor electronic device and a manufacturing method thereof to overcome the shortcomings of the prior art.
  • An embodiment of the present invention provides a gallium oxide vertical structure semiconductor electronic device, which includes a buffer layer, a current blocking layer, and a channel layer disposed in this order. A current through hole is also distributed in the current blocking layer.
  • the channel layer A source electrode and a gate electrode are disposed on the buffer layer, the buffer layer is connected to the drain electrode, the drain electrode is disposed opposite to the current blocking layer, the current via is located below the gate electrode, and the channel layer and the buffer layer are connected via The current vias are electrically connected.
  • An embodiment of the present invention also provides a method for manufacturing a gallium oxide vertical structure semiconductor electronic device, which includes:
  • a through hole is processed in the current blocking layer, and the through hole is located below the gate;
  • An epitaxial material for growing a channel layer is grown on the current blocking layer, and a part of the epitaxial material is filled into the through hole, thereby forming a channel layer and a current through hole, and making the channel layer It is electrically connected with the buffer layer through the current through hole to make a gate, a source, and a drain.
  • the source and the gate are disposed on the channel layer.
  • the drain is connected to the buffer layer and is in phase with the current blocking layer.
  • An embodiment of the present invention further provides a gallium oxide vertical structure semiconductor electronic device manufactured by the method for manufacturing a gallium oxide vertical structure semiconductor electronic device.
  • the gallium oxide vertical structure semiconductor electronic device provided by the present invention has a simple structure, can well meet the requirements of high-power switches, and has a series of advantages such as large saturation current and high breakdown voltage.
  • the material characteristics of Ga 2 O 3 are greatly exerted, so that gallium oxide vertical structure semiconductor electronic devices play a greater role in the field of power semiconductor electronic devices.
  • FIG. 1 is a schematic structural diagram of a gallium oxide vertical structure semiconductor electronic device in a typical embodiment of the present invention.
  • An embodiment of the present invention provides a gallium oxide vertical structure semiconductor electronic device, which includes a buffer layer, a current blocking layer, and a channel layer disposed in this order. A current through hole is also distributed in the current blocking layer.
  • the channel layer A source electrode and a gate electrode are disposed on the buffer layer, the buffer layer is connected to the drain electrode, the drain electrode is disposed opposite to the current blocking layer, the current via is located below the gate electrode, and the channel layer and the buffer layer are connected via The current vias are electrically connected.
  • the source, channel layer, current via, and drain are turned on in sequence, and when the device is in an off state, the gate can turn the The channel is depleted.
  • the channel layer is provided integrally with the current through hole.
  • the buffer layer is formed on the first surface of the substrate, the drain is disposed on the second surface of the substrate, and the first surface is disposed opposite to the second surface.
  • the thickness of the substrate is 1 ⁇ m to 1 mm.
  • the material of the substrate includes N-type or P-type Ga 2 O 3 .
  • the material of the channel layer includes N + -type or P + -type Ga 2 O 3 .
  • the material of the buffer layer includes N-type or P-type Ga 2 O 3 .
  • the thickness of the buffer layer is 1 nm-100 ⁇ m.
  • the material of the current blocking layer includes P-type or N-type Ga 2 O 3 .
  • the gallium oxide vertical structure semiconductor electronic device includes two sources, and the gate is distributed between the two sources.
  • a gate insulating layer is also distributed between the gate and the channel layer.
  • An embodiment of the present invention also provides a method for manufacturing a gallium oxide vertical structure semiconductor electronic device, which includes:
  • a through hole is processed in the current blocking layer, and the through hole is located below the gate;
  • An epitaxial material for growing a channel layer is grown on the current blocking layer, and a part of the epitaxial material is filled into the through hole, thereby forming a channel layer and a current through hole, and making the channel layer It is electrically connected with the buffer layer through the current through hole to make a gate, a source and a drain.
  • the source and the gate are arranged on the channel layer.
  • the drain is connected to the buffer layer and is in phase with the current blocking layer Back to settings.
  • the manufacturing method includes: removing at least a part of the region of the current blocking layer by at least one of photolithography, etching, or etching methods to form the through hole.
  • the material of the channel layer includes N + -type or P + -type Ga 2 O 3 .
  • the material of the buffer layer includes N-type or P-type Ga 2 O 3 .
  • the material of the current blocking layer includes P-type or N-type Ga 2 O 3 .
  • the manufacturing method includes manufacturing two sources, and the gate is distributed between the two sources.
  • the manufacturing method includes: providing a gate insulating layer on the channel layer, and then manufacturing a gate on the gate insulating layer.
  • the buffer layer is formed on the first surface of the substrate, the drain is disposed on the second surface of the substrate, and the first surface is disposed opposite to the second surface.
  • the manufacturing method further includes: forming an ohmic contact between the source electrode and the channel layer, and forming an ohmic contact between the drain electrode and the buffer layer or the substrate.
  • An embodiment of the present invention further provides a gallium oxide vertical structure semiconductor electronic device manufactured by the method for manufacturing a gallium oxide vertical structure semiconductor electronic device.
  • the forbidden bandwidth of the Ga 2 O 3 material provided by the embodiment of the present invention is 4.7 to 5.3 eV, and the breakdown field strength is 8 to 10 MV / cm. Therefore, the critical field strength of Ga 2 O 3 is more than 20 to 30 times that of Si. It is also more than twice as much as the third-generation semiconductors GaN and SiC, and the Ga 2 O 3 Barriga's figure of merit is also more than 2 to 4 times that of GaN and SiC and other materials. It is higher in low-frequency devices. Compared with traditional Si and third-generation semiconductor materials, 2 O 3 materials and devices have great advantages in high-power and high-voltage devices, and have the potential to affect the entire power conversion field.
  • Ga 2 O 3 field effect transistors mainly have two types of structures: one is a horizontal structure device, and the other is a vertical field effect transistor (Vertical Field Effect Transistor), which mainly includes vertical MOSFETs and vertical current aperture transistors. CAVET, CurrentAperture Vertical Electron Transistor).
  • VET Vertical Field Effect Transistor
  • CAVET CurrentAperture Vertical Electron Transistor
  • a gallium oxide vertical structure semiconductor electronic device may include: an N-type or P-type Ga 2 O 3 substrate (1 ⁇ m-1 mm) and an N-type or P-type substrate disposed in this order.
  • Ga 2 O 3 buffer layer (1 nm-100 ⁇ m).
  • a P-type or N-type Ga 2 O 3 current blocking layer (1 nm-100 ⁇ m) is provided above the N-type or P-type Ga 2 O 3 buffer layer.
  • N-type Ga is formed with an electrical flow hole 2 O 3 current blocking layer, formed on an N + type or 2 O 3 channel layer of P + type Ga (1nm-100 ⁇ m above the P-type or N-type Ga 2 O 3 current blocking layer ), And two source electrodes and a gate electrode are provided on the N + -type or P + -type Ga 2 O 3 channel layer, the gate electrode is located between the two source electrodes, and the drain electrode is provided on the N-type or P-type
  • the insulation layer can be a high-K dielectric such as aluminum nitride. Material; wherein the current via is located below the gate.
  • a source electrode and a gate electrode are located at the top of the device, a drain electrode is located at the bottom of the device, and a buffer layer (N-type or P-type Ga 2 O 3 ) current blocking layer (P-type or N-type Ga 2 O 3) and the vicinity of the channel layer (N + type or P + type Ga 2 O 3) exists, so that electrons can not pass, so that electrons can only flow through the channel layer by the horizontal electric The holes flow into the buffer layer.
  • the electrons from the source pass through the horizontal channel (N + or P + Ga 2 O 3 ), the control region under the gate, and the current blocking layer (P or N Ga 2 O 3 ) in this order. Aperture, N-type or P-type Ga 2 O 3 buffer layer and N-type or P-type Ga 2 O 3 substrate, and finally reach the drain; in the off state, the gate layer (N + or P + -type Ga 2 O 3 ) is completely depleted.
  • the withstand voltage of the device is mainly borne by a PN junction formed by a reverse-biased N-type or P-type Ga 2 O 3 buffer layer / P-type or N-type Ga 2 O 3 .
  • the N-type or P-type Ga 2 O 3 buffer layer thickness can be controlled to improve the withstand voltage of the device. Because the Ga 2 O 3 material has a strong breakdown field, the thickness of the drift region can be greatly reduced under the same withstand voltage condition, thereby obtaining a smaller on-resistance. Therefore, the device of this structure has a high breakdown voltage and a low on-state. The characteristics of resistance and large current can reduce the thickness of the Ga 2 O 3 substrate or leave only N-type or P-type Ga 2 O 3 buffer layers in the device manufacturing process.
  • an N-type or P-type Ga 2 O 3 film (that is, a buffer layer) can be grown on a N-type or P-type Ga 2 O 3 substrate by a semiconductor thin film epitaxy technology, and then a P-type or N layer is epitaxially grown.
  • Ga 2 O 3 thin film ie, current blocking layer
  • a part of the second epitaxially grown P-type or N-type Ga 2 O 3 thin film is removed by photolithography, etching, or etching to form a film having a certain width.
  • the ohmic contact electrode is prepared to be a source and a drain of the vertical structure electronic device.
  • the N-type implanted ions include: Si, Sn, Ge, etc.
  • the P-type implanted ions include: Mg, B, In, etc.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种氧化镓垂直结构半导体电子器件及其制作方法。所述氧化镓垂直结构半导体电子器件包括依次设置的缓冲层、电流阻挡层和沟道层，所述电流阻挡层内还分布有电流通孔，所述沟道层上设置有源极和栅极，所述缓冲层与漏极连接，所述漏极与电流阻挡层相背对设置，所述电流通孔位于栅极下方，所述沟道层与缓冲层经所述电流通孔电连接。所述氧化镓垂直结构半导体电子器件，能够很好的满足了大功率开关的需求，且拥有大的饱和电流、高击穿电压等一系列优势。

Description

氧化镓垂直结构半导体电子器件及其制作方法 技术领域
本发明特别涉及一种氧化镓垂直结构半导体电子器件及其制作方法，属于半导体器件技术领域。
背景技术
在现代社会中，电力电子技术是实现各种能源与电能转换和利用的核心，也国民经济和国家安全领域的基础和重要支柱，电力电子器件在电力电子技术领域的应用和市场中起着决定性作用，它是弱电控制与强电运行之间的桥梁，是信息技术与先进制造技术，传统和现代产业实现自动化、智能化、节能化、机电一体化的基础支撑。随着高压变频、交流传动机车/动车组、城市轨道交通、电动/混合动力汽车、通讯及新一代数据中心服务器、无线通讯、无人机等无线技术的不断发展，迫切需要更高性能的电力电子器件满足其发展需求。
一般来讲，任何固态能量转换系统都是由电路组成，开关电源作为能量转换的基石，被广泛植入在这些电路中。如果在能量转换领域中把开关器件实现高效节能，能把整个系统的损耗降低，同时还可节省成本。因此，要实现一个零损耗的系统，首先从制作一个零损耗的功率开关开始。而要实现一个零损耗功率开关，关键在于找到一种合适的半导体材料，使得处于开启状态下开关的电阻几乎为零。
当前技术最为成熟的硅(Si)基功率器件已经达到硅材料极限，也更难实现高击穿电压，低导通电阻，大电流，耐高温，小型化的电子器件的需求与发展趋势，新型的超宽带隙半导体(Ga 2O 3)材料与器件相较于传统的半导体材料有很大的优势，特别适用于高压、大功率和高温应用，是电力电子应用最具潜力的材料之一。
目前，场效应晶体管(Field Effect Transistor,FET)主要有两种结构类型的：一是水平式结构器件，二是垂直结构器件(Vertical Field Effect Transistor，主要包括垂直MOSFET和垂直电 流孔径晶体管CAVET,Current Aperture Vertical Electron Transistor)。然而，水平式器件相对于垂直型器件存在如下劣势：水平式结构电子器件在关断状态下，电子可以从半绝缘缓冲层到达漏端，形成缓冲层漏电现象，缓冲层泄漏现象严重会使得漏极电流在较低电压下就已经到达击穿判定的条件。同时，水平式结构电子器件主要依靠栅极与漏极之间的有源区来承受耐压，要获得大的击穿电压，需设计很大的栅极与漏极间距，从而增大了芯片所需的面积，与小型化的需求不符，也不利于降低制作成本。大功率转换应用需要大电流和高电压，采用水平结构设计的芯片既不经济且制备困难。
此外，在水平式器件中高电场区域位于靠近漏极一侧的栅极边缘，由于高电场将电子注入表面存在的陷阱中，从而造成电流的崩塌，这一严重的可靠性问题进一步限制了横向器件在高压领域的应用。
发明内容
本发明的主要目的在于提供一种氧化镓垂直结构半导体电子器件及其制作方法，以克服现有技术的不足。
为实现前述发明目的，本发明采用的技术方案包括：
本发明实施例提供了一种氧化镓垂直结构半导体电子器件，其包括依次设置的缓冲层、电流阻挡层和沟道层，所述电流阻挡层内还分布有电流通孔，所述沟道层上设置有源极和栅极，所述缓冲层与漏极连接，所述漏极与电流阻挡层相背对设置，所述电流通孔位于栅极下方，所述沟道层与缓冲层经所述电流通孔电连接。
本发明实施例还提供了一种氧化镓垂直结构半导体电子器件的制作方法，其包括：
在缓冲层上形成电流阻挡层，
在所述电流阻挡层中加工出通孔，所述通孔位于栅极下方，
在所述电流阻挡层上生长用以形成沟道层的外延材料，并使部分的所述外延材料填充入所述通孔，从而形成沟道层与电流通孔，且使所述沟道层与缓冲层经所述电流通孔电连接，制作栅极、源极和漏极，所述源极和栅极设置在沟道层上，所述漏极与缓冲层连接并与电流阻挡层相背对设置。
本发明实施例还提供了由所述的氧化镓垂直结构半导体电子器件的制作方法制作的氧化镓垂直结构半导体电子器件。
与现有技术相比，本发明提供的氧化镓垂直结构半导体电子器件，结构简单，能够很好的满足了大功率开关的需求，且拥有大的饱和电流、高击穿电压等一系列优势，极大的发挥Ga 2O 3材料特性，使氧化镓垂直结构半导体电子器件在功率半导体电子器件领域发挥更大的作用。
附图说明
图1是本发明一典型实施案例中一种氧化镓垂直结构半导体电子器件的结构示意图。
具体实施方式
鉴于现有技术中的不足，本案发明人经长期研究和大量实践，得以提出本发明的技术方案。如下将对该技术方案、其实施过程及原理等作进一步的解释说明。
本发明实施例提供了一种氧化镓垂直结构半导体电子器件，其包括依次设置的缓冲层、电流阻挡层和沟道层，所述电流阻挡层内还分布有电流通孔，所述沟道层上设置有源极和栅极，所述缓冲层与漏极连接，所述漏极与电流阻挡层相背对设置，所述电流通孔位于栅极下方，所述沟道层与缓冲层经所述电流通孔电连接。
进一步的，在所述器件处于开态时，所述源极、沟道层、电流通孔与漏极依次导通，而在所述器件处于关态时，所述栅极能够将栅下的沟道耗尽。
进一步的，所述沟道层与电流通孔一体设置。
更进一步的，所述缓冲层形成在衬底的第一表面上，所述漏极设置于所述衬底的第二表面上，所述第一表面与第二表面相背对设置。
优选的，所述衬底的厚度为1μm-1mm。
优选的，所述衬底的材质包括N型或P型Ga 2O 3。
进一步的，所述沟道层的材质包括N+型或P+型Ga 2O 3。
进一步的，所述缓冲层的材质包括N型或P型Ga 2O 3。
优选的，所述缓冲层的厚度为1nm-100μm。
进一步的，所述电流阻挡层的材质包括P型或N型Ga 2O 3。
进一步的，所述的氧化镓垂直结构半导体电子器件包括两个源极，所述栅极分布于所述两个源极之间。
进一步的，所述栅极与沟道层之间还分布有栅绝缘层。
本发明实施例还提供了一种氧化镓垂直结构半导体电子器件的制作方法，其包括：
在缓冲层上形成电流阻挡层，
在所述电流阻挡层中加工出通孔，所述通孔位于栅极下方，
在所述电流阻挡层上生长用以形成沟道层的外延材料，并使部分的所述外延材料填充入所述通孔，从而形成沟道层与电流通孔，且使所述沟道层与缓冲层经所述电流通孔电连接，制作栅极、源极和漏极，所述源极和栅极设置在沟道层上，所述漏极与缓冲层连接并与电流阻挡层相背对设置。
进一步的，所述的制作方法包括：至少通过光刻、刻蚀或腐蚀方法中的任意一种除掉所述电流阻挡层的部分区域，从而形成所述通孔。
进一步的，所述沟道层的材质包括N+型或P+型Ga 2O 3。
进一步的，所述缓冲层的材质包括N型或P型Ga 2O 3。
进一步的，所述电流阻挡层的材质包括P型或N型Ga 2O 3。
进一步的，所述的制作方法包括制作两个源极，所述栅极分布于所述两个源极之间。
进一步的，所述的制作方法包括：在所述沟道层上设置栅绝缘层，之后在所述栅绝缘层上制作栅极。
进一步的，所述缓冲层形成在衬底的第一表面上，所述漏极设置于所述衬底的第二表面上，所述第一表面与第二表面相背对设置。
进一步的，所述制作方法还包括：使源极与沟道层形成欧姆接触，使漏极与缓冲层或衬底形成欧姆接触。
本发明实施例还提供了由所述的氧化镓垂直结构半导体电子器件的制作方法制作的氧化镓垂直结构半导体电子器件。
对于半导体功率电子器件，巴利加优值(Baliga’s figure ofmerit，其可作为低损耗性指标，FOM＝BV 2/R on)是一个用于综合评价功率器件的指标，获得许多业内学者的认可，其中击穿场强(BV)和导通电阻(R on)是影响器件性能的两个重要参数。
本发明实施例提供的Ga 2O 3材料的禁带宽带为4.7～5.3eV，击穿场强是8～10MV/cm，因此Ga 2O 3的临界场强是Si的20～30余倍，也是第三代半导体GaN和SiC的2倍多，而Ga 2O 3巴利加优值也是GaN和SiC等材料的2～4倍多；在低频器件方面更高，基于上述的优异表现，Ga 2O 3材料与器件相较于传统的Si以及第三代半导体材料在大功率、高电压器件上的极大优势，拥有影响整个功率转换领域的潜力。
目前Ga 2O 3场效应晶体管(Field Effect Transistor,FET)主要有两种结构类型的：一是水平式结构器件，二是垂直结构器件(Vertical Field Effect Transistor，主要包括垂直MOSFET和垂直电流孔径晶体管CAVET,CurrentAperture Vertical Electron Transistor)。目前研究对象大多为横向结构Ga 2O 3器件，其大多应用在中小功率领域，而更大功率的高压大电流领域，主要为垂直结构器件，为此，本发明实施例提供了一种新型Ga 2O 3垂直结构器件以满足高压/高流应用。
如下将结合附图对该技术方案、其实施过程及原理等作进一步的解释说明。
请参阅图1，在本发明的实施例中，一种氧化镓垂直结构半导体电子器件可以包括：依次设置的N型或P型Ga 2O 3衬底(1μm-1mm)和N型或P型Ga 2O 3缓冲层(1nm-100μm)，所述N型或P型Ga 2O 3缓冲层上方设置有P型或N型Ga 2O 3电流阻挡层(1nm-100μm)，在P型或N型Ga 2O 3电流阻挡层内形成有电流通孔，在所述P型或N型Ga 2O 3电流阻挡层上方形成有N+型或P+型Ga 2O 3沟道层(1nm-100μm)，以及，在N+型或P+型Ga 2O 3沟道层上设置有两个源极和栅极，所述栅极位于两个源极之间，漏极设置于所述N型或P型Ga 2O 3衬底的背面(即下方)；在栅极和N+型或P+型Ga 2O 3沟道层之间还设置有栅绝缘层，绝缘层可以是氮化铝等高K介质材料；其中所述电流通孔位于栅极下方。
具体的，在本发明实施例提供的一种氧化镓垂直结构半导体电子器件中，源极和栅极位于器件的顶部，漏极位于器件的底部，缓冲层(N型或P型Ga 2O 3)与沟道层(N+型或P+型Ga 2O 3)附近存在电流阻挡层(P型或N型Ga 2O 3)，使得电子无法通过，从而电子只能由水平沟道层经电流通孔流入缓冲层内。在开态下，电子从源极出发，依次经过水平沟道(N+型或 P+型Ga 2O 3)、栅极下方控制区、电流阻挡层(P型或N型Ga 2O 3)之间的孔径，N型或P型Ga 2O 3缓冲层和N型或P型Ga 2O 3衬底，最终到达漏极；在关态下，栅极将其下方的沟道层(N+型或P+型Ga 2O 3)完全耗尽，此时器件耐压主要由反偏N型或P型Ga 2O 3缓冲层/P型或N型Ga 2O 3形成的P-N结所承受。因此可以通过控制N型或P型Ga 2O 3缓冲层厚度，提高器件耐压度。由于Ga 2O 3材料击穿场强大，在相同的耐压情况下，漂移区的厚度可以大大降低，进而得到更小的导通电阻，所以此结构的器件具有高击穿电压，低导通电阻，大电流的特性，在器件制备工艺中，可以减薄Ga 2O 3衬底的厚度，或者仅留下N型或P型Ga 2O 3缓冲层。
本实施例可以通过半导体薄膜外延技术在N型或P型Ga 2O 3衬底上生长一定厚度的N型或P型Ga 2O 3薄膜(即缓冲层)，然后外延一层P型或N型Ga 2O 3薄膜(即电流阻挡层)，然后通过光刻、刻蚀或腐蚀等工艺方法去除掉部分第二层外延生长的P型或N型Ga 2O 3薄膜，进行形成具有一定宽度和深度的孔(即电流通孔)，之后再通过外延技术在第二层外延生长的P型或N型Ga 2O 3薄膜和加工形成的孔内生长高浓度N+型或P+型Ga 2O 3薄膜(即沟道层)，之后在刻蚀的孔上方沉积绝缘介质和金属电极(gate)，使其可以控制电流的开与关，在孔对应区域的器件上方的两侧和衬底背面制备欧姆接触电极使其成为此垂直结构电子器件的源极(source)和漏极(drain)。
由于源极和漏极的欧姆接触影响器件性能，所以对此区域进行离子注入以提高器件性能。其中N型注入离子包括：Si，Sn，Ge等，P型注入离子包括：Mg，B，In等。
应当理解，上述实施例仅为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (12)

  1. 一种氧化镓垂直结构半导体电子器件，其特征在于包括依次设置的缓冲层、电流阻挡层和沟道层，所述电流阻挡层内还分布有电流通孔，所述沟道层上设置有源极和栅极，所述缓冲层与漏极连接，所述漏极与电流阻挡层相背对设置，所述电流通孔位于栅极下方，所述沟道层与缓冲层经所述电流通孔电连接。
  2. 根据权利要求1所述的氧化镓垂直结构半导体电子器件，其特征在于：在所述器件处于开态时，所述源极、沟道层、电流通孔与漏极依次导通，而在所述器件处于关态时，所述栅极能够将栅下的沟道耗尽。
  3. 根据权利要求1或2所述的氧化镓垂直结构半导体电子器件，其特征在于：所述沟道层与电流通孔一体设置。
  4. 根据权利要求3所述的氧化镓垂直结构半导体电子器件，其特征在于：所述缓冲层形成在衬底的第一表面上，所述漏极设置于所述衬底的第二表面上，所述第一表面与第二表面相背对设置；优选的，所述衬底的厚度为1μm-1mm；优选的，所述衬底的材质包括N型或P型Ga 2O 3；和/或，所述沟道层的材质包括N+型或P+型Ga 2O 3；和/或，所述缓冲层的材质包括N型或P型Ga 2O 3；优选的，所述缓冲层的厚度为1nm-100μm；和/或，所述电流阻挡层的材质包括P型或N型Ga 2O 3。
  5. 根据权利要求1所述的氧化镓垂直结构半导体电子器件，其特征在于包括两个源极，所述栅极分布于所述两个源极之间。
  6. 根据权利要求1或5所述的氧化镓垂直结构半导体电子器件，其特征在于：所述栅极与沟道层之间还分布有栅绝缘层。
  7. 一种氧化镓垂直结构半导体电子器件的制作方法，其特征在于包括：
    在缓冲层上形成电流阻挡层，
    在所述电流阻挡层中加工出通孔，所述通孔位于栅极下方，
    在所述电流阻挡层上生长用以形成沟道层的外延材料，并使部分的所述外延材料填充入所述通孔，从而形成沟道层与电流通孔，且使所述沟道层与缓冲层经所述电流通孔电连接，制作栅极、源极和漏极，所述源极和栅极设置在沟道层上，所述漏极与缓冲层连接并与电流阻挡层相背对设置。
  8. 根据权利要求7所述的制作方法，其特征在于包括：至少通过光刻、刻蚀或腐蚀方法中的任意一种除掉所述电流阻挡层的部分区域，从而形成所述通孔。
  9. 根据权利要求7或8所述的制作方法，其特征在于：所述沟道层的材质包括N+型或P+型Ga 2O 3；和/或，所述缓冲层的材质包括N型或P型Ga 2O 3；和/或，所述电流阻挡层的材质包括P型或N型Ga 2O 3。
  10. 根据权利要求7所述的制作方法，其特征在于包括制作两个源极，所述栅极分布于所述两个源极之间。
  11. 根据权利要求7所述的制作方法，其特征在于包括：在所述沟道层上设置栅绝缘层，之后在所述栅绝缘层上制作栅极；
    和/或，所述缓冲层形成在衬底的第一表面上，所述漏极设置于所述衬底的第二表面上，所述第一表面与第二表面相背对设置。
    和/或，所述制作方法还包括：使源极与沟道层形成欧姆接触，使漏极与缓冲层或衬底形成欧姆接触。
  12. 由权利要求7-11中任一项所述的氧化镓垂直结构半导体电子器件的制作方法制作的氧化镓垂直结构半导体电子器件。
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