WO2021217830A1 - 阵列基板、显示面板和显示装置 - Google Patents
阵列基板、显示面板和显示装置 Download PDFInfo
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- WO2021217830A1 WO2021217830A1 PCT/CN2020/097321 CN2020097321W WO2021217830A1 WO 2021217830 A1 WO2021217830 A1 WO 2021217830A1 CN 2020097321 W CN2020097321 W CN 2020097321W WO 2021217830 A1 WO2021217830 A1 WO 2021217830A1
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- 239000000758 substrate Substances 0.000 title claims abstract description 286
- 239000010409 thin film Substances 0.000 claims abstract description 149
- 239000004973 liquid crystal related substance Substances 0.000 claims description 43
- 239000003086 colorant Substances 0.000 claims description 16
- 230000008093 supporting effect Effects 0.000 claims description 4
- 230000000903 blocking effect Effects 0.000 claims 1
- 239000004744 fabric Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 886
- 239000010408 film Substances 0.000 description 108
- 238000010586 diagram Methods 0.000 description 54
- 238000004519 manufacturing process Methods 0.000 description 28
- 230000000694 effects Effects 0.000 description 26
- 230000009286 beneficial effect Effects 0.000 description 22
- 239000000463 material Substances 0.000 description 21
- 238000000034 method Methods 0.000 description 17
- 238000005530 etching Methods 0.000 description 13
- 238000000059 patterning Methods 0.000 description 8
- 230000000149 penetrating effect Effects 0.000 description 7
- 239000004020 conductor Substances 0.000 description 6
- 239000007769 metal material Substances 0.000 description 6
- 230000005684 electric field Effects 0.000 description 4
- 238000001125 extrusion Methods 0.000 description 3
- 230000002452 interceptive effect Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 210000002858 crystal cell Anatomy 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000001795 light effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136222—Colour filters incorporated in the active matrix substrate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/13338—Input devices, e.g. touch panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133514—Colour filters
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
Definitions
- the present application relates to the field of display technology, for example, to an array substrate, a display panel, and a display device.
- the display screen is bent to form a curved screen, and when the curved screen is applied to a vehicle display device, the display of the vehicle display device can be increased. Viewing angle to reduce the display difference perceived by the human eye under different viewing angles.
- the liquid crystal display panel has the characteristics of low power consumption, no radiation, and soft display screen, it is widely used in various display devices.
- people's requirements for the color richness of the images displayed by the liquid crystal display panel increase, how to improve the display color gamut of the liquid crystal display panel has become a technical problem to be solved urgently.
- the embodiments of the present application provide an array substrate, a display panel, and a display device, so as to reduce the difficulty of punching and improve the product yield and display effect.
- an array substrate including:
- a thin film transistor located on one side of the base substrate, the thin film transistor including at least a first electrode;
- a pixel electrode located on a side of the thin film transistor away from the base substrate;
- At least two color resist layers located between the thin film transistor and the pixel electrode, and a dielectric layer is provided between any two adjacent color resist layers;
- the pixel electrode is electrically connected to the first electrode of the thin film transistor through a via hole, and the via hole penetrates through the at least two color resist layers and between any two adjacent color resist layers.
- the dielectric layer is electrically connected to the first electrode of the thin film transistor through a via hole, and the via hole penetrates through the at least two color resist layers and between any two adjacent color resist layers.
- an embodiment of the present application further provides a display panel, including:
- a counter substrate arranged opposite to the array substrate
- an embodiment of the present application further provides a display device, including: the above-mentioned display panel.
- FIG. 1 is a schematic diagram of the structure of an array substrate in the related art
- FIG. 2 is a schematic diagram of a top view of a related art array substrate
- 3 is a schematic diagram of microscopic imaging of the structure in the hole of the array substrate in the related art
- FIG. 4 is a schematic diagram of a film structure of an array substrate provided by an embodiment of the present application.
- FIG. 5 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 6 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 7 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 8 is a schematic diagram of a film structure of another array substrate provided by an embodiment of the present application.
- FIG. 9 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- FIG. 10 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 11 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 12 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 13 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 14 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 15 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 16 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- FIG. 17 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 18 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 19 is a schematic diagram of a film structure of another array substrate provided by an embodiment of the present application.
- FIG. 20 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 21 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 22 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 23 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 24 is a schematic diagram of a top view structure of an array substrate provided by an embodiment of the present application.
- FIG. 25 is a schematic top view of another array substrate provided by an embodiment of the present application.
- FIG. 26 is a schematic top view of another array substrate provided by an embodiment of the present application.
- FIG. 27 is a schematic diagram of a film structure of yet another array substrate provided by an embodiment of the present application.
- FIG. 28 is a schematic top view of another array substrate provided by an embodiment of the present application.
- FIG. 29 is a schematic diagram of a film structure of an array substrate corresponding to FIG. 28;
- FIG. 30 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
- FIG. 31 is a schematic structural diagram of a display device provided by an embodiment of the present application.
- the liquid crystal display usually includes a backlight module and a liquid crystal display panel.
- the backlight module can provide a light source for the liquid crystal display panel;
- the liquid crystal display panel includes a color film substrate and a thin film transistor (TFT) array substrate, and is located on the color film substrate
- TFT thin film transistor
- the thin film transistor is transmitted to the corresponding pixel electrode; at this time, the pixel electrode can form an electric field with the common electrode, and the electric field can drive the liquid crystal molecules in the corresponding position in the liquid crystal layer to deflect, so that the light source provided by the backlight module can pass through the corresponding position
- the liquid crystal molecules reach the color filter substrate; and the color filter substrate is provided with a color resist
- the light-shielding layer can shield the positions that do not need to transmit light to prevent unnecessary light leakage; the color resist layer includes color resists of different colors The pattern enables the light source that passes through the liquid crystal molecules at the corresponding position to pass through the color resist pattern of the corresponding color to display a colorful picture.
- the liquid crystal display panel in order to increase the viewing angle of the liquid crystal display panel, the liquid crystal display panel is usually bent to form a curved liquid crystal display panel. Because the light shielding layer and the color resist layer of the curved liquid crystal display panel are arranged on the color film substrate , And the array substrate is provided with corresponding thin film transistors, pixel electrodes and metal traces, and when the liquid crystal display panel is bent to form a curved liquid crystal display panel, the array substrate and the color film substrate of the liquid crystal display panel will be deformed , So that the light-shielding position of the light-shielding layer in the color filter substrate is inaccurately aligned with the position of the array substrate that needs to be shielded, so that the light source provided by the backlight module transmits the liquid crystal display panel, so that when the liquid crystal display panel performs display and light emission, light leakage will occur , Affect the display effect of the display panel.
- FIG. 1 is a schematic diagram of the structure of an array substrate in the related art.
- a thin film transistor array 020, a pixel electrode layer 030, and a light shielding layer 080 are provided on the side of the base substrate 010 of the array substrate 001, and are provided on the thin film transistor array 020 and the pixel electrode.
- the color resist layer 040, the planarization layer 050, and the common electrode 060 are arranged in sequence between 030, and the insulating layer 070 is also arranged between the common electrode 060 and the pixel electrode 030; in this way, the light shielding layer 080 and the color resist layer 040 are both arranged on In the array substrate 001, when the array substrate 001 is bent, the light shielding layer 080 will not be displaced from the position of the array substrate 001 that needs to be shielded due to extrusion deformation, which can prevent light leakage due to extrusion deformation.
- the pixel electrode of the pixel electrode layer 030 is electrically connected to the thin film transistor of the thin film transistor array 020 through the via hole, so that the thin film transistor can transmit the pixel voltage signal to the pixel electrode that is electrically connected thereto, and is connected to the common pixel electrode through the pixel electrode.
- An electric field is generated between the common electrodes of the electrode layer 060 to drive the liquid crystal molecules of the liquid crystal layer in the liquid crystal display panel using the array substrate 001 to twist.
- the via hole must penetrate at least the insulating layer 070, the planarization layer 050, and the color resist layer 040, etc. ⁇ Film layer.
- the light source provided by the backlight module can sequentially pass through the array substrate 001 and the liquid crystal
- the layer and the opposite substrate disposed opposite to the array substrate 001 make the liquid crystal display panel display light
- the color resist pattern of the color resist layer 040 in the array substrate 001 converts the light source provided by the backlight module into light of a corresponding color, thereby Make the liquid crystal display panel display a colorful picture.
- the thickness of the color resist layer is related to the color gamut of the liquid crystal display panel, and when the color resist material is the same, the greater the thickness of the color resist layer, the higher the color gamut, so to improve the color gamut of the display light In order to increase the thickness of the color resist layer.
- the color resist layer 040 is located between the thin film transistor array 020 and the pixel electrode layer 030. If the thickness T0 of the color resist layer 040 is thicker, the film is placed between the pixel electrode and the thin film transistor.
- the via hole of the layer has a deeper depth, thereby increasing the process difficulty of setting the via hole; at the same time, because the thickness T0 of the color resist layer 040 is thick, the via hole is prepared by photolithography, etching, etc.
- over-etching or under-etching is prone to occur; as shown in Figure 2, over-etching will damage the color resist pattern around the via hole H0, thereby affecting the display effect of the display panel; and as shown in Figure 3, Insufficient etching will cause residual color resist material in the via hole H0, thereby affecting the electrical connection between the pixel electrode and the thin film transistor, causing poor contact between the pixel electrode and the thin film transistor, and further affecting the display effect of the display panel.
- An embodiment of the application provides an array substrate, the array substrate includes a base substrate, a thin film transistor located on one side of the base substrate and at least a first electrode, a pixel electrode located on the side of the thin film transistor away from the base substrate, and a thin film transistor located on the side of the thin film transistor. At least two color resistance layers between the transistor and the pixel electrode, wherein a dielectric layer is arranged between any two adjacent color resistance layers, and the pixel electrode is electrically connected to the first electrode of the thin film transistor through a via hole.
- the at least two color resist layers have a relatively thick total thickness, It can meet the display requirements of high color gamut, thereby improving the display effect of the display panel; in addition, the color resistance layer that meets the display requirements of high color gamut is divided into at least two color resistance layers, compared with the same color gamut requirements
- a color resist layer, each color resist layer of the at least two color resist layers has a relatively thin thickness, and a dielectric layer is arranged between the two adjacent color resist layers to penetrate the pixel electrode and the thin film transistor
- FIG. 4 is a schematic diagram of a film structure of an array provided by an embodiment of the present application.
- a thin film transistor 20 is provided on one side of the base substrate 10 of the array substrate 100, and the thin film transistor 20 includes at least a first electrode 23; wherein, the first electrode 23 of the thin film transistor 20 may be the thin film transistor 20.
- the thin film transistor 20 may further include an active layer 21, a gate 22, and a second electrode 24; by applying a gate voltage signal to the gate 22 of the thin film transistor 20, the first electrode 23 and the second electrode 24 of the thin film transistor 20 can be controlled Turn on, so that the corresponding pixel voltage signal can pass through the thin film transistor 20.
- the second electrode 24 of the thin film transistor 20 can be the drain or source of the thin film transistor 20, that is, when the thin film transistor 20 When the first electrode 23 of the thin film transistor 20 is the source of the thin film transistor 20, the second electrode 24 of the thin film transistor 20 is the drain of the thin film transistor; and when the first electrode 23 of the thin film transistor 20 is the drain of the thin film transistor At this time, the second electrode 24 of the thin film transistor 20 is the source of the thin film transistor.
- FIG. 4 is only an exemplary drawing of an embodiment of the present application.
- the thin film transistor 20 is a top-gate thin film transistor, that is, the gate 22 of the thin film transistor 20 is located on the active layer 21 away from the base substrate. 10; and in the embodiments of the present application, the gate of the thin film transistor may also be located on the side of the active layer close to the substrate, that is, the thin film transistor is a bottom gate thin film transistor; or, the thin film transistor is near and far away
- the gate of the thin film transistor is arranged on one side of the base substrate, that is, the thin film transistor is a double gate thin film transistor.
- the array substrate 100 further includes a pixel electrode 30 located on the side of the thin film transistor 20 away from the base substrate 10.
- the pixel electrode 30 is electrically connected to the first electrode of the thin film transistor 20 through a via hole, so as to be connected to the thin film transistor 20.
- a gate signal is applied to the gate 22 of the thin film transistor 20 to control the conduction of the first electrode 23 and the second electrode 24 of the thin film transistor 20, the thin film transistor 20 can transmit the pixel voltage signal to the corresponding pixel electrode 30, so that the pixel electrode The position of 30 can show light.
- each color resist layer (41, 42) can be provided with a color resist pattern of different colors to allow a single color of light to pass through.
- Each color resist pattern of the color resist layer (41, 42) can emit colorful light; when the array substrate 100 is applied to a display panel, there is no need to set colors in the counter substrate disposed opposite to the array substrate 100.
- the barrier layer enables the display panel to realize color display; in this way, when the display panel including the array substrate 100 is bent to form a curved display panel, there is no need to consider the alignment problem between the array substrate 100 and the opposite substrate. It is beneficial to increase the aperture ratio of the display panel, so that the display effect of the display panel can be improved.
- the thickness of the color resistance layer is related to the color gamut of the display light, that is, within a certain range, the greater the thickness of the color resistance layer of the same color resistance material, the higher the color gamut of the display light.
- At least two color resist layers are provided between the thin film transistor 30 and the thin film transistor 20, so that the color resist layer 40 of the array substrate 100 has a relatively thick total thickness (T1+T2), so that the array substrate 100 can be used
- T1+T2 total thickness
- a dielectric layer 60 is also arranged between any adjacent two color resist layers (41 and 42) of the at least two color resist layers 40, so that the color resist layers (41, 42) are arranged at intervals.
- the via hole penetrates at least two color resist layers 40 between the pixel electrode 30 and the thin film transistor 20 and is located in any phase.
- At least two color resist layers 40 including two color resist layers 41 and 42 are taken as an example. After the color resist layer 42 is formed, a hole can be opened at the corresponding position of the color resist layer 42 to expose the first electrode 23 of the thin film transistor 20.
- the depth of the hole of the color resist layer 42 is equivalent to the thickness T2 of the color resist layer 42 ; And then on the side of the color resist layer 42 away from the base substrate 10 is provided with a dielectric layer 60, the dielectric layer 60 will cover the color resist layer 42 and fill the opening positions of the color resist layer 42, so that the dielectric layer 60 away from the color resist layer A relatively flat surface is formed on one side of the dielectric layer 42, that is, the dielectric layer 60 can fill the opening positions of the color resist layer 42 and the depressions caused by patterning, so as to reduce the protrusion and the surface of the dielectric layer 60 away from the base substrate 10.
- the height difference between the recesses forms a relatively flat surface; then, the color resist layer 41 is formed on the side of the dielectric layer 60 away from the color resist layer 42; when the color resist material of the color resist layer 41 and the dielectric layer of the dielectric layer 60 When the material is different, the opening method of the color resist layer 41 is different from that of the dielectric layer 60.
- the color resist layer 41 can be opened by exposure and development, while the opening method of the dielectric layer 60 can be dry.
- Etching method at this time, the corresponding position of the color resist layer 41 can be opened by exposure and development, and the depth of the opening is equivalent to the thickness T1 of the color resist layer 41; then, dry etching is used
- the dielectric layer 60 is opened to expose the first electrode 23 of the thin film transistor 20; when the color resist layer 41 is opened, the dielectric layer 60 between the color resist layer 41 and the color resist layer 42 can protect the dielectric layer.
- each color resist layer (41, 42) has a relatively shallow opening depth, thereby reducing the difficulty of setting the via hole.
- each of the at least two color resist layers 40 disposed between the pixel electrode 30 and the thin film transistor 20 is opened separately, which can make each color resist layer (41, 42) have a shallower opening depth, thereby reducing the difficulty of setting the via; at the same time, it is arranged between two adjacent color resist layers 41 and 42
- the dielectric layer 60 can protect the color resist layer 41 on the side of the dielectric layer close to the base substrate 10, so as to improve the phenomenon that the color resist pattern in the color resist layer is damaged by over-etching or the residual in the hole appears due to insufficient etching, which is beneficial to improve Product yield, reduce production costs, and improve display effects.
- the material of the medium layer located between two adjacent color resist layers may be organic materials or inorganic materials.
- the dielectric layer 60 and the color resist layer 41 can be opened in the same manner, after the color resist layer 42 is formed and the color resist layer 42 is opened, the dielectric layer 60 and the color resist layer 42 can be formed in sequence.
- the color resist layer 42 and the dielectric layer 60 are sequentially opened by the same kind of opening method; since the formed dielectric layer 60 will fill the holes of the color resist layer 42, the dielectric layer 60 and the color resist layer 42 When opening holes, the color resist layer 42 can be protected by the dielectric layer 60 arranged around the holes of the color resist layer 42 to prevent the color resist layer 42 from being damaged by over-etching when the color resist layer 41 and the dielectric layer 60 are opened. .
- FIG. 4 is only an exemplary drawing of an embodiment of the present application, and FIG. 4 only exemplarily shows that the array substrate 100 includes two color resist layers; and in the embodiment of the present application, the array substrate The number of color resist layers can be two, three or more layers.
- the array substrate further includes a planarization layer, which is located between the pixel electrode and the thin film transistor, and the planarization layer can fill the gap caused by the patterning of the thin film transistor and other film layers between the planarization layer and the base substrate.
- the planarization layer can fill the gap caused by the patterning of the thin film transistor and other film layers between the planarization layer and the base substrate.
- the phenomenon of uneven display will occur.
- at least two color resist layers located between the pixel electrode and the thin film transistor may be provided between the planarization layer and the pixel electrode; or, at least two color resist layers located between the pixel electrode and the thin film transistor are provided in the planarization layer.
- the at least two color resist layers may include at least one first color resist layer and at least one second color resist layer, and at least one first color resist layer may be disposed on the planarization layer And the pixel electrode, and at least one second color resist layer can be arranged between the planarization layer and the thin film transistor.
- a planarization layer 50 and at least two color resist layers 40 are provided between the pixel electrode 30 of the array substrate 100 and the thin film transistor 20.
- the at least two color resist layers 40 include a color resist layer 41 and a color resist layer 42, and the color resist layer 41 and the color resist layer 42 are both located between the planarization layer 50 and the thin film transistor 20, that is, the at least two color resist layers 40 is located on the side of the planarization layer 50 close to the base substrate 10.
- the planarization layer 50 can simultaneously fill in the depressions and protrusions caused by the patterning of each color resist layer (41, 42) in the at least two color resist layers 40 and the patterning of each film layer in the thin film transistor 20.
- the via holes that penetrate the pixel electrode 30 and the film layer where the first electrode 23 of the thin film transistor 20 is located it may be: forming a color resist layer 42 and opening the color resist layer 42 to sequentially form a dielectric layer 60 and the color resist layer 41, and separately make holes on the color resist layer 41 and separately make holes on the dielectric layer 60; then form a planarization layer 50 on the side of the color resist layer 41 away from the base substrate 10, and The planarization layer 50 is opened to leak out the first electrode 23 of the thin film transistor 20; correspondingly, if the material of the dielectric layer 60 between the two adjacent color resist layers 41 and 42 is the same as the material of the planarization layer 50 , Or the material of the dielectric layer 60 is different from the material of the planarization layer 50, but when the dielectric layer 60 and the planarization layer 50 can be opened by
- FIG. 5 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- the planarization layer 50 is located between the thin film transistor 20 and the at least two color resist layers 40.
- the planarization layer 50 can fill the thin film between the planarization layer 50 and the base substrate 10.
- at least two color resist layers 40 arranged on the side of the planarization layer away from the base substrate 10 can be arranged on a relatively flat surface, ensuring that the thickness of the color resist layers 41 and 42 at each position tends to be uniform.
- FIG. 6 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- Figure 6 is the same as Figures 4 and 5, please refer to the above description of Figures 4 and 5, which will not be repeated here.
- the planarization layer 50 is disposed between two adjacent color resist layers 41 and 42.
- the color resist layer 41 located between the planarization layer 50 and the pixel electrode 30 is the first color resist layer
- the color resist layer 42 located between the planarization layer 50 and the thin film transistor 20 is the second color resist layer
- the planarization layer 50 can at least fill in the protrusions and depressions caused by the patterning of the thin film transistor 20 and the second color resist layer 42; at the same time, the planarization layer 50 can serve as the adjacent first color resist layer 41 and the second color resist layer.
- the dielectric layer between the resist layers 42 At this time, there is no need to provide an additional dielectric layer between the adjacent first color resist layer 41 and the second color resist layer 42, which is beneficial to simplify the process of the array substrate 100 and reduce the cost of the array substrate 100.
- the planarization layer 50 can be formed.
- the protrusions and depressions caused by the openings make the side of the planarization layer 50 away from the base substrate 10 have a relatively flat surface; then, the first color resist layer 41 is formed on the side of the planarization layer 50 away from the base substrate 10 , And the first color resist layer 41 is opened; then the planarization layer 50 is opened to leak the first electrode 23 of the thin film transistor 20; in this way, the planarization layer 50 is used as the first color resist layer 41 and
- the dielectric layer between the second color resist layers 42 can also make each color resist layer (41, 42) individually open, and the holes provided in each color resist layer have a shallower depth, thereby reducing the difficulty of setting via holes , Which is conducive to improving production yield and reducing production costs.
- FIG. 4, FIG. 5, and FIG. 6 are only exemplary drawings of embodiments of the present application, and the array substrate 100 in FIG. 4, FIG. 5, and FIG. 6 each includes two color resist layers 41 and 42;
- the at least two color resist layers may be two, three or more layers; correspondingly, at least one first color resist layer may be one, two or more layers, and at least one The second color resist layer can be one, two or more layers.
- a common electrode is further provided in the array substrate; the common electrode is located between the planarization layer and the pixel electrode.
- the common electrode may be a whole-surface structure, a strip structure or a block structure.
- the common electrode and the pixel electrode are both arranged in the array substrate.
- the array substrate is applied to the display panel, by applying a common voltage signal to the common electrode and applying a pixel voltage signal to the pixel electrode, the common electrode of the array substrate and the pixel electrode
- the pixel electrode forms an in-plane field, and drives the liquid crystal molecules of the liquid crystal layer in the display panel to twist, so that light can pass through the liquid crystal layer of the display panel, and a display screen with high color gamut is displayed on the display surface of the display panel.
- At least one insulating layer may be provided between the common electrode and the pixel electrode, so that the common electrode and the pixel electrode are insulated from each other, so as to prevent the common voltage signal on the common electrode and the pixel voltage signal on the pixel electrode from interfering with each other and affecting display effect.
- the via hole used to electrically connect the pixel electrode and the first electrode of the thin film transistor penetrates the film layer where the common electrode is located;
- the via hole can be arranged between two adjacent common electrodes. At this time, the via hole penetrates the insulating layer between the two adjacent common electrodes.
- the array substrate is also provided with at least two color resist layers
- the at least two color resist layers are located between the pixel electrode and the thin film transistor, so according to the film layer between the at least two color resist layers and the planarization layer Relationship, the positional relationship between the common electrode and the at least two color resist layers can be determined.
- FIG. 7 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- at least two color resist layers 40 include a color resist layer 41 and a color resist layer 42, and both the color resist layer 41 and the color resist layer 42 are located between the planarization layer 50 and the thin film transistor 20; at this time, The common electrode 80 may be disposed on a side of the planarization layer 50 away from the at least two color resist layers 40; at this time, an insulating layer 70 is disposed between the pixel electrode 30 and the common electrode 80. In this way, the flattening layer 50 is formed after opening holes at corresponding positions of the at least two color resist layers 40.
- the flattening layer 50 will be formed on the side of the at least two color resist layers 40 away from the base substrate 10 and the filling color
- the opening positions of the resist layers 41 and/or 42 are used to fill in the depressions and protrusions caused by patterning, and to protect the color resist patterns of the color resist layers 41 and/or 42 at the opening positions from being over-etched ;
- a common electrode 80 is formed on the side of the planarization layer 50 away from the base substrate 10, and after opening the corresponding position of the film layer where the common electrode 80 is located, on the side of the common electrode 80 away from the base substrate 10
- An insulating layer 70 is formed.
- the insulating layer 70 covers the common electrode 80 so as to prevent the common voltage signal on the common electrode 80 from interfering with the pixel voltage signal on the pixel electrode 30 and affect the display effect. At the same time, the insulating layer 70 will also fill the common electrode. At the opening position of the film layer where the electrode 80 is located, the insulating layer provided at the opening position can insulate the common electrode 80 from the connection line between the pixel electrode 30 and the first electrode 23 of the thin film transistor 20, thereby avoiding the common electrode 80 The common voltage signal on the above and the pixel voltage signal on the pixel electrode 30 interfere with each other, which is beneficial to improve the display effect.
- the common electrode may be located between the planarization layer and the at least two color resist layers; or, the common electrode is located between the pixel electrode and the at least two layers. Between the color resist layers; or, the common electrode is located between two adjacent color resist layers.
- FIG. 8 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- at least two color resist layers 40 include a color resist layer 41 and a color resist layer 42, and both the color resist layer 41 and the color resist layer 42 are located between the planarization layer 50 and the pixel electrode 30; at this time,
- the common electrode 80 may be located between the planarization layer 50 and the color resist layer 42, and the color resist layer 41, the color resist layer 42, and the dielectric layer between the color resist layer 41 and the color resist layer 42 may serve as the pixel electrode 30 and the common color resist layer.
- the insulating layer of the electrode 80 in this way, there is no need to provide an additional insulating layer between the pixel electrode 30 and the common electrode 80, which is beneficial to simplify the process of the array substrate 100 and reduce the cost of the array substrate 100, so that the array substrate 100 is applied to In the case of the display panel, it is beneficial to the thinning of the display panel.
- an insulating layer may also be provided between the pixel electrode 30 and the at least two color resist layers 40 and/or between the at least two color resist layers 40 and the common electrode 80.
- the insulating layer can be used to protect the color resist layer 41, so as not to engrave the insulating layer on the side of the insulating layer away from the base substrate 10.
- the color resist pattern in the color resist layer 41 is damaged, so that the production yield can be improved and the production cost can be reduced.
- FIG. 9 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- the common electrode 80 can also be arranged between the color resist layer 41 and the pixel electrode 30.
- a corresponding insulating layer 70 needs to be arranged between the pixel electrode 30 and the common electrode 80 to make the pixel electrode 30 and the common
- the electrodes 80 are insulated from each other.
- a corresponding dielectric layer can also be arranged between the common electrode 80 and the color resist layer 41 to protect the color resist layer 41; correspondingly, the dielectric layer can fill the opening positions of the color resist layer 41 to make the dielectric layer deviate from One side of the base substrate 10 has a relatively flat surface, so that the common electrode 80 can be formed on a relatively flat surface, which facilitates the film formation of the common electrode 80.
- FIG. 10 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present application.
- the common electrode 80 is located between two adjacent color resist layers 41 and 42, and the dielectric layer 60 disposed between the two color resist layers 41 and 42 can be located on the common electrode 80 away from the substrate.
- the dielectric layer 60 can protect the color resist pattern of the color resist layer 42 on the side close to the base substrate 10 from being damaged and insulated; at the same time, it can be provided between the common electrode 80 and the pixel electrode 30
- the color resist layer 41 and the dielectric layer 60 between the common electrode 80 and the pixel electrode 30 can be used as an insulating layer between the common electrode 80 and the pixel electrode 30 to insulate the common electrode 80 and the pixel electrode 30;
- the additional provision of an insulating layer is conducive to simplifying the manufacturing process of the array substrate 100 and reducing the cost of the array substrate 100, so that when the array substrate 100 is applied to a display panel, it is conducive to the thinning of the display panel.
- the planarization layer 50 and the color resist layer 42 can be sequentially formed, and then only the color resist layer 42 is opened, the planarization layer 50 is temporarily not opened; the common electrode 80 is formed on the side of the color resist layer 42 away from the base substrate 10, and after the common electrode 80 is opened, the common electrode 80 is away from the base substrate A dielectric layer 60 is formed on one side of 10, and the dielectric layer 60 will fill the opening positions of the common electrode 80 and the color resist layer 42, so that the side of the dielectric layer 60 away from the base substrate 10 has a relatively flat surface; The color resist layer 41 is formed on the side of the layer 60 away from the base substrate 10, and the color resist layer 41 is separately opened, and then the dielectric layer 60 and the planarization layer 50 are simultaneously opened; in this way, each color can also be opened.
- the resist layers (41, 42) are individually opened, so that each color resist layer (41, 42) has a shallower opening depth, so as to reduce the difficulty of arranging the color resist layer.
- a corresponding insulating layer may be provided between the pixel electrode 30 and the color resist layer 41 to protect the color resist layer 41 located between the insulating layer and the common electrode 80.
- FIG. 11 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- a common electrode 80 and a dielectric layer 60 are provided between the color resist layer 41 and the color resist layer 42, and the common electrode 80 is located on the side of the dielectric layer 60 away from the base substrate 10; at the same time, the pixel electrode 30
- An insulating layer 70 is also provided between the color resist layer 41 and the color resist layer 41.
- the planarization layer 50 and the color resist layer 42 can be formed in sequence, and then the color resist layer A hole is opened at the corresponding position 42, and the depth of the hole is equivalent to the thickness T2 of the color resist layer 42; then a dielectric layer 60 is formed on the side of the color resist layer 42 away from the base substrate 10, and the dielectric layer 60 will cover the color resist layer 42 And fill the opening positions of the color resist layer 42 so that the side of the dielectric layer 60 away from the base substrate 10 forms a relatively flat surface; then a common electrode 80 is formed on the side of the dielectric layer 60 away from the base substrate 10, so that the common The electrode 80 can be formed on a relatively flat surface, which is conducive to the film formation of the common electrode 80; after the common electrode 80 is formed, the common electrode 80 can be patterned and/or apertured, and the dielectric layer 60 will not be apertured temporarily;
- the insulating layer 70, the dielectric layer 60, and the planarization layer 50 can be opened in the same manner, after the insulating layer 70 is formed, the insulating layer 70, the dielectric layer 60, and the planarization layer 50 can be opened at the same time. Holes; in this way, it is also possible to ensure that each color resist layer (41, 42) has a separate hole, thereby reducing the difficulty of setting the via hole, which is beneficial to improve the product yield and reduce the production cost.
- FIG. 12 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- the common electrode 80 is provided between the color resist layer 41 and the color resist layer 42, and an insulating layer 70 is provided between the color resist layer 41 and the pixel electrode 30; at this time, the common electrode 80 can be used as a color resist layer.
- the dielectric layer between 41 and the color resist layer 42 does not require an additional dielectric layer between the color resist layer 41 and the color resist layer 42, and the insulating layer 70 provided between the color resist layer 41 and the pixel electrode 30 can be filled with color
- the insulation prevents mutual interference between the common voltage signal of the common electrode 80 and the pixel voltage signal of the pixel electrode 30.
- a full-surface common electrode 80 may be formed on the side of the color resist layer 42 away from the base substrate 10, and then the common electrode 80 may be away from it.
- the color resist layer 41 is formed on one side of the base substrate 10, and after the color resist layer 41 is opened, the common electrode 80 is opened, so that the common electrode 80 protects the color resist layer 42 from being damaged;
- the insulating layer 70 on the side of the color resist layer 41 away from the base substrate 10 will fill the holes provided in the color resist layer 42, the common electrode 80, and the color resist layer 42, so that the color resist layer 41, the common electrode 80, and the color resist layer
- the insulating layer around the hole of the resist layer 42 can protect the color resist layer 41 and the color resist layer 42, and at the same time can insulate the common electrode 80 from the connection line of the pixel electrode 30 and the first electrode 23 of the thin film transistor 20 to avoid the common electrode 80.
- the common voltage signal and the pixel voltage signal of the pixel electrode 30 interfere with each other.
- a corresponding dielectric layer may also be provided between the common electrode 80 and the color resist layer 41 and/or the common electrode 80 and the color resist layer 42.
- the at least two color resist layers include at least one first color resist layer and at least one second color resist layer
- at least one first color resist layer is located between the planarization layer and the pixel electrode
- the common electrode may be located between the planarization layer and at least one layer of the first color resist layer; or, the common electrode may be located between the at least one layer of first color resist layer and the pixel electrode; or, the common electrode may be located between two adjacent layers. Between the first color resist layer.
- FIG. 13 is a schematic structural diagram of yet another array substrate provided by an embodiment of the present application.
- the at least two color resist layers 40 include a first color resist layer 41 and a second color resist layer 42, and the planarization layer 50 is located on the adjacent first color resist layer 41 and the second color resist layer.
- the common electrode 80 is located between the first color resist layer 41 and the pixel electrode 30; at this time, an insulating layer 70 is provided between the common electrode 80 and the pixel electrode 30 to prevent the common electrode on the common electrode 80 The signal and the pixel voltage signal on the pixel electrode 30 interfere with each other.
- FIG. 14 is a schematic structural diagram of another array substrate provided by an embodiment of the present application.
- FIG. 14 and FIG. 13 reference may be made to the above description of FIG. 13, which will not be repeated here.
- FIG. 14 and FIG. 13 Only the differences between FIG. 14 and FIG. 13 will be exemplified. As shown in FIG.
- the common electrode 80 is provided between the first color resist layer 41 and the planarization layer 50, and an insulating layer 70 is provided between the first color resist layer 41 and the pixel electrode 30; the insulating layer 70 can be used
- the first color resist layer 41 is protected to prevent the color resist pattern of the first color resist layer 41 from being damaged when the functional film layer located on the insulating layer 70 away from the first color resist layer 41 is etched; at this time, the planarization layer 50 and the common electrode 80 can be used as a dielectric layer between the first color resist layer 41 and the second color resist layer 42 together, and there is no need to provide additional dielectric layers for the first color resist layer 41 and the second color resist layer 42 to simplify the array
- the process of the substrate reduces the production cost; and after opening the first color resist layer 41, the common electrode layer 80, the planarization layer 50, and the second color resist layer 42, an insulating layer 70 is formed so that the insulating layer 70 The material will be filled in the opening position, so that the through holes in the through insulating
- a dielectric layer may be additionally provided between the first color resist layer 41 and the second color resist layer 42.
- the common electrode 80 may be located on the dielectric layer away from the base substrate 10. , Or on the side of the dielectric layer close to the base substrate 10.
- FIG. 15 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- the at least two color resist layers 40 of the array substrate 100 include two first color resist layers 41 (411 and 412) and a second color resist layer 42, and the planarization layer 50 is located adjacent to the first color resist layer.
- the common electrode 80 is located between the two first color resist layers 411 and 412, and the common electrode 80 can serve as the two first color resist layers 411 and 412 There is no need to provide an additional dielectric layer between the two adjacent first color resist layers 411 and 412.
- the planarization layer 50 and the first color resist layer 412 can be formed in sequence; and then the first color resist layer 412 is processed
- the common electrode 80 is formed, and the first color resist layer 411 is formed on the side of the common electrode 80 away from the base substrate 10.
- the common electrode 80 can serve as the first color resist layer 411 and the first color resist layer 412
- the dielectric layer between the first color resist layer 411 and the first color resist layer 412 are isolated from each other; then the color resist layer 411 is opened to leak the common electrode 80, and then the common electrode 80 in the hole is flattened Layer 50 is perforated in sequence.
- first color resist layer 411, the first color resist layer 412, and the second color resist layer 42 are individually opened, which reduces the difficulty of opening the color resist layer, improves the product yield, and reduces the production cost.
- a corresponding dielectric layer can also be provided between the common electrode 80 and the first color resist layer 411 and/or the common electrode 80 and the first color resist layer 411.
- FIGS. 7 to 15 are only exemplary drawings of the embodiments of the present application, which exemplarily show the film layer between the common electrode 80 and the planarization layer 50 and the at least two color resist layers 40 relation.
- the common electrode is located between at least two color resist layers and the pixel electrode as an example to illustrate the technical solutions of the embodiments of the present application.
- a first lap conductive layer is further provided on the side of the planarization layer away from the base substrate; the first lap conductive layer includes a first lap structure.
- the via hole used to penetrate the film layer between the pixel electrode and the first electrode of the thin film transistor may include a first via hole and a second via hole, and the pixel electrode may pass through the first via hole and the first overlap conductive layer
- the first overlapping structure corresponds to electrical connection, and the first overlapping structure can be electrically connected to the first electrode of the thin film transistor through the second via hole.
- the material of the first lap conductive layer may be a metal material or other conductive materials.
- FIG. 16 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- the planarization layer 50 is located between at least two color resist layers 40 and the pixel electrode 30.
- the first bonding conductive layer 91 may be located between the planarization layer 50 and the pixel electrode 30, so that the pixel electrode 30 can pass through the first via H1 and the first bonding structure 911 in the first bonding conductive layer 91
- the first lap structure 911 is electrically connected to the first electrode 23 of the thin film transistor 20 through the second via H2.
- the first via hole H1 penetrates the film layer between the first bonding conductive layer 91 and the pixel electrode 30, and the second via hole H2 penetrates the film layer between the first bonding conductive layer 91 and the thin film transistor.
- the first lap conductive layer 91 is provided on the side of the planarization layer 50 away from the base substrate 10, and the pixel electrode 30 and the pixel electrode 30 are electrically connected to each other through the first lap structure 911 in the first lap conductive layer 91.
- the first electrode 23 of the thin film transistor 20, the first via hole H1 and the second via hole H2 have a relatively shallow depth, which can further reduce the difficulty of setting the via hole, thereby helping to improve the production efficiency and product yield of the array substrate , Reduce the production cost of the array substrate.
- FIG. 17 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- the first bonding conductive layer 91 may be located between the planarization layer 50 and the at least two color resist layers 40.
- the first via hole H1 and the second via hole H2 can also have a shallower depth, thereby reducing the difficulty of setting the via hole.
- FIG. 18 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- the planarization layer 50 is located on the adjacent first color resist layer 41
- the second color resist layer 42 the first lap conductive layer 91 can be located between the planarization layer 50 and the first color resist layer 41; in this way, the first via H1 and the second via H2 can also be It has a shallower depth, thereby reducing the difficulty of setting the via.
- FIGS. 16 to 18 are only exemplary illustrations of the embodiments of the present application, in which the first lap conductive layer 91 is disposed on the surface of the planarization layer 50; and in the embodiment of the present application, the planarization layer and Corresponding functional film layers may also be arranged between the first overlapping conductive layers, provided that the difficulty of setting the vias can be reduced.
- the first bonding conductive layer disposed between the planarization layer and the pixel electrode layer may further include touch traces; in this case, touch electrodes are also provided in the array substrate, and the first bonding conductive layer The touch traces are electrically connected to the touch electrodes to realize the transmission of touch signals.
- the first lap structure and the touch trace located on the first lap conductive layer can be formed of the same material and formed in the same process, which is beneficial to simplify the process steps of the array substrate, improve production efficiency, and reduce production costs. .
- the common electrodes in the array substrate can be multiplexed as touch electrodes.
- the touch electrode when the touch electrode is a self-capacitive touch electrode, the common electrode can be set as a block structure.
- a common voltage signal is applied to the common electrode during the display stage, so that the common electrode and the pixel electrode form an in-plane field.
- the corresponding touch detection signal can be received through the common electrode; and when the touch electrode is a mutual-capacitive touch electrode, the common electrode can be reused as a mutual-capacitive touch electrode in the touch
- the driving electrode in this case, the common electrode may be in a strip shape, a block shape, or a surface shape.
- the array substrate further includes at least one second lap conductive layer; the second lap conductive layer includes a second lap structure, and the second lap conductive layer is located between two adjacent color resist layers , And the second overlapping structures of different second overlapping conductive layers are electrically connected in turn; wherein, when at least two color resist layers are located between the planarization layer and the pixel electrode, they penetrate through the first overlapping conductive layer and the pixel electrode
- the first via hole of the interlayer film may include a first sub via hole and a second sub via hole; the pixel electrode is electrically connected to the second overlapping structure of the second overlapping conductive layer through the first sub via hole, and the second The two overlapping structures are electrically connected to the first overlapping structure of the first overlapping conductive layer through the second sub-vias; and when at least two color resist layers are located between the planarization layer and the thin film transistor, they penetrate through the first overlapping structure
- the second via hole connecting the film layer between the metal and the thin film transistor includes a third sub-via hole and a fourth
- FIG. 19 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- the at least two color resist layers 40 may include two color group layers 41 and 42, and the at least two color resist layers 40 are located between the planarization layer 50 and the pixel electrode.
- the first overlap conductive layer It is located between the planarization layer 50 and at least two color group layers 40, and the second lap conductive layer 92 is located between the two adjacent color resist layers 41 and 42; at this time, the pixel electrode 30 passes through the first sub-layer
- the via hole H11 is electrically connected to the second overlapping structure 921 of the second overlapping conductive layer 92, and the second overlapping structure 921 is connected to the first overlapping structure 911 of the first overlapping conductive layer 91 through the second sub-via H12.
- the first lap structure 911 is electrically connected to the first electrode 23 of the thin film transistor 20 through the second via H2; in this way, a film layer penetrating between the pixel electrode and the second lap conductive layer 92 is respectively provided
- FIG. 20 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- the planarization layer 50 is located between at least two color resist layers 40 and the pixel electrode 30
- the first lap conductive layer 91 is located between the planarization layer 50 and the pixel electrode 30
- the second lap conductive layer is located between the planarization layer 50 and the pixel electrode 30.
- the layer 92 is located between the two adjacent color resist layers 41 and 42; at this time, the pixel electrode 30 can be electrically connected to the first bonding structure 911 of the first bonding conductive layer 91 through the first via H1.
- the first lap structure 911 can be electrically connected to the second lap structure 921 of the second lap conductive layer 92 through the third sub-via H21, and the second lap structure is electrically connected to the thin film transistor 20 through the fourth sub-via H22.
- the first electrode 23 is correspondingly electrically connected; in this way, a third sub-via H21 penetrating the film layer between the first bonding conductive layer 91 and the second bonding conductive layer 92 and a third sub-via H21 penetrating the second bonding conductive layer 92 and
- the fourth sub-via H22 of the film layer between the thin film transistors 20 makes the third sub-via H21 and the fourth sub-via H22 have a relatively shallow depth, which can further reduce the difficulty of setting the via. It is beneficial to improve the production efficiency and product yield of the array substrate 100, and reduce the production cost of the array substrate 100.
- FIG. 19 and FIG. 20 are exemplary drawings of embodiments of the present application.
- at least two color resist layers 40 include two color resist layers 41 and 42.
- a second lap conductive layer 92 is provided between the resist layers 41 and 42; since the at least two color resist layers in the embodiment of the present application can be two, three or more layers, and any adjacent color resist layers A second lap conductive layer can be provided between them. Therefore, the array substrate of the embodiment of the present application may include one, two or more second lap conductive layers.
- a corresponding insulating structure can also be arranged between adjacent functional film layers to avoid mutual interference of the functional film layers.
- the at least two color resist layers may include at least two first color resist layers and at least one second color resist layer, that is, at least two The first color resist layer is located between the planarization layer and the pixel electrode, and at least one second color resist layer is located between the planarization layer and the thin film transistor;
- the array substrate may also include at least one layer of third bonding A conductive layer, and the third lap conductive layer is located between two adjacent first color resist layers;
- the third lap conductive layer may include a third lap structure, and the third lap conductive layer is different from the third lap conductive layer
- the three overlapping structures are electrically connected in sequence; wherein, the first via hole penetrating the film layer between the pixel electrode and the first overlapping structure may include a first sub-via hole and a second sub-via hole, so that the pixel electrode passes through the first sub-via hole.
- the hole is electrically connected with the third overlapping structure;
- the third overlapping structure is electrically connected with the first
- FIG. 21 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- the at least two color resist layers 40 of the array substrate 100 include two first color resist layers 41 (411 and 412) and a second color resist layer 42, and the planarization layer 50 is located adjacent to the first color resist layer.
- the third lap conductive layer 93 is located between the adjacent first color resist layers 411 and 412, and the first lap conductive layer 91 is located in the first color group layer 412 and the planarization layer 50; at this time, the pixel electrode 30 may be electrically connected to the third bonding structure 931 of the third bonding conductive layer 93 through the first sub-via H11, and the third bonding structure 931 may pass through
- the second sub-via H12 is electrically connected to the first lap structure 911 of the first lap conductive layer 91, and the first lap structure 911 is electrically connected to the first electrode 23 of the thin film transistor 20 through the second via H2;
- the first sub-via H11 and the second sub-via H12 provided have a relatively shallow depth, which can reduce the difficulty of setting the via, which is beneficial to improve the production efficiency and product yield of the array substrate, thereby reducing the array The production cost of the substrate.
- FIG. 21 is only an exemplary drawing of an embodiment of the present application.
- at least two color resist layers 40 include two first color resist layers 41 and a second color resist layer 42;
- the at least two color resist layers may include at least two first color resist layers and at least one second color resist layer, that is, the first color resist layers may be two, three or more layers,
- the second color resist layer may be one, two or more layers, and the number of the first color resist layer may be the same as or different from the number of the second color resist layer.
- the at least two color resist layers may include at least one first color resist layer and at least two second color resist layers.
- a first color resist layer is located between the planarization layer and the pixel electrode, and the at least two second color resist layers are located between the planarization layer and the thin film transistor;
- the array substrate may further include at least one fourth layer Overlapping conductive layer, the fourth overlapping conductive layer is located between two adjacent second color resist layers, and the fourth overlapping conductive layer includes a fourth overlapping structure, and the fourth overlapping conductive layer is different from the fourth overlapping conductive layer
- the four overlapping structures are electrically connected in sequence; wherein, the second via hole penetrating the film layer between the first overlapping conductive layer and the film layer where the first electrode of the thin film transistor is located includes a third sub-via hole and a fourth sub-via hole;
- the first lap structure is electrically connected to the fourth lap structure of the fourth lap conductive layer through the third sub-via, and the fourth lap
- FIG. 22 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- the at least two color resist layers 40 of the array substrate 100 include a first color resist layer 41 and two second color resist layers 42 (421 and 422).
- the planarization layer 50 is located adjacent to the first color resist layer.
- the fourth lap conductive layer 94 is located between the adjacent second color resist layers 421 and 422, and the first lap conductive layer 91 is located in the first color group layer 41 and the planarization layer 50; at this time, the pixel electrode 30 may be electrically connected to the first lap structure 911 of the first lap conductive layer 91 through the first via H1, and the first lap structure 911 may pass through the first lap structure 911.
- the three sub-vias H21 are electrically connected to the fourth lap structure 941 of the fourth lap conductive layer 94, and the fourth lap structure 941 can be electrically connected to the first electrode 23 of the thin film transistor 20 through the fourth sub-via H22.
- the third sub-via H21 and the fourth sub-via H22 are set to have a relatively shallow depth, which can reduce the difficulty of setting the via, which is beneficial to improve the production efficiency and product yield of the array substrate, and then Reduce the production cost of the array substrate.
- FIG. 22 is only an exemplary drawing of an embodiment of the present application.
- at least two color resist layers 40 include a first color resist layer 41 and two second color resist layers 42;
- the at least two color resist layers may include at least one first color resist layer and at least two second color resist layers, that is, the first color resist layer may be one, two or more layers,
- the second color resist layer may be two, three or more layers, and the number of the first color resist layer may be the same as or different from the number of the second color resist layer.
- the at least two color resist layers may include at least two first color resist layers and at least two second color resist layers.
- the two first color resist layers are located between the planarization layer and the pixel electrode, and the at least two second color resist layers are located between the planarization layer and the thin film transistor; in this case, the array substrate may also include at least one third layer.
- An overlap conductive layer and at least one fourth overlap conductive layer is located between two adjacent layers of the first color group, the third overlap conductive layer includes a third overlap structure, and The third overlapping structures of different third overlapping conductive layers are electrically connected in sequence; the fourth overlapping conductive layer is located between two adjacent second color resist layers, and the fourth overlapping conductive layer includes a fourth overlapping conductive layer.
- the first via hole penetrating the film layer between the pixel electrode and the first overlapping conductive layer may include a first sub
- the via hole and the second sub via hole, and the second via hole penetrating the film layer between the first lap conductive layer and the film layer where the first electrode of the thin film transistor is located include a third sub via hole and a fourth sub via hole
- the pixel electrode is electrically connected to the third lap structure of the third lap conductive layer through the first sub-via hole
- the third lap structure is electrically connected to the first lap structure of the first lap conductive layer through the second sub-via hole
- the first lap structure is electrically connected to the fourth lap structure of the fourth lap conductive layer through the third sub-via
- the fourth lap structure is electrically connected to the first electrode of the thin film transistor through the fourth sub-via.
- the material of the third lap conductive layer may be a metal material or
- FIG. 23 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- the at least two color resist layers 40 of the array substrate 100 include two first color resist layers 41 (411 and 412) and two second color resist layers 42 (421 and 422).
- the planarization layer 50 Located between the adjacent first color resist layer 412 and the second color group layer 421, the third overlapping conductive layer 93 is located between the adjacent first color resist layers 411 and 412, and the fourth overlapping conductive layer 94 is located Between the adjacent second color resist layers 421 and 422, the first lap conductive layer 91 is located between the first color group layer 412 and the planarization layer 50; at this time, the pixel electrode 30 can pass through the first sub-via H11 Correspondingly and electrically connected to the third overlapping structure 931 of the third overlapping conductive layer 93, the third overlapping structure 931 is electrically connected to the first overlapping structure 911 of the first overlapping conductive layer 91 through the second sub-via H12 , The first lap structure 911 may be electrically connected to the fourth lap structure 941 of the fourth lap conductive layer 94 through the third sub-via H21, and the fourth lap structure 941 may be electrically connected to the fourth lap structure 941 through the fourth sub-via H22
- FIG. 23 is only an exemplary drawing of an embodiment of the present application.
- at least two color resist layers 40 include two first color resist layers 41 and two second color resist layers 42;
- the at least two color resist layers may include at least two first color resist layers and at least two second color resist layers, that is, the first color resist layers may be two, three or more layers,
- the second color resist layer can also be two, three or more layers, and the number of the first color resist layer can be the same as or different from the number of the second color resist layer.
- each color resist layer in the array substrate may include a plurality of color resist patterns of different colors, and the shape of the color resist pattern may be a strip or a block; when the shape of the color resist pattern is a strip, the multiple colors
- the resist patterns are arranged along the first direction and all extend along the second direction, the first direction intersects the second direction; correspondingly, the via hole that penetrates the pixel electrode and the film layer where the first electrode of the thin film transistor is located is on the front side of the base substrate.
- the projection is in the orthographic projection of the color resist pattern on the base substrate; when the shape of the color resist pattern is block, a plurality of color resist patterns are arranged in an array; correspondingly, the film layer that penetrates the pixel electrode and the first electrode of the thin film transistor is located The via hole is located between two adjacent color resist patterns of the same color.
- FIG. 24 is a schematic top view of the structure of an array substrate provided by an embodiment of the present application.
- each color resist layer of the array substrate may include color resist patterns of different colors.
- each color resist layer may include a first color resist pattern 401 with a first color and a second color resist pattern 401 with a second color.
- the two-color resist pattern 402 and the third color resist pattern 403 with a third color, the first color, the second color, and the third color may be red, green, and blue, respectively.
- the first color resist pattern 401, the second color resist pattern 402, and the third color resist pattern 403 all extend along the second direction Y and are arranged along the first direction X; because the color resist layer is located between the pixel electrode and the thin film transistor Therefore, the via hole H that penetrates the film layer between the pixel electrode and the film layer where the first electrode of the thin film transistor is located will penetrate each of the color resist patterns 401, 402, and 403 of the color resist layer; at the same time, because it is located between the pixel electrode and the thin film transistor
- the color resist layer is divided into at least two layers to be arranged.
- the color resist layer can be individually opened by The dielectric layer arranged between two adjacent color resist layers protects the color resist layer on the side of the dielectric layer close to the base substrate, thereby reducing the difficulty of setting the via hole and improving the color damage of the color resist layer due to over-etching. Resist patterns (401, 402, and 403) or insufficient etching will cause residuals in the holes, which is beneficial to improve product yield, reduce production costs, and improve display effects.
- FIG. 25 is a schematic top view of another array substrate provided by an embodiment of the present application.
- the color resist patterns 401, 402, and 403 of the color resist layer of the array substrate are all block structures, and the color resist patterns 401, 402, and 403 of the block structure are along the first direction X and the second direction Y.
- the via hole H that penetrates the film layer between the pixel electrode and the film layer where the first electrode of the thin film transistor is located can be set between two color resist patterns of the same color, for example, two adjacent Via holes are provided between the color resist patterns 401, between two adjacent color resist patterns 402, and between two adjacent color resist patterns 403, so that the via hole H does not penetrate the color resist patterns 401, 402, 403 Therefore, it is possible to prevent the hole from damaging the color resist pattern, or to prevent the pixel electrode and the first electrode of the thin film transistor from being poorly contacted due to the residue of the color resist material, thereby improving the product yield, reducing the production cost, and improving display effect.
- FIGS. 25 and 26 only exemplarily show a part of the color resist pattern of the color resist layer, and the color of the color resist pattern of each color resist layer, for example, may also include a white color resist pattern and a yellow color resist pattern.
- the array substrate of the embodiment of the present application includes at least two layers of color resist patterns, and the color resist patterns of each color resist layer can be the same or different.
- FIG. 26 is a schematic top view of another array substrate provided by an embodiment of the present application.
- the array substrate also includes a light-shielding layer 110; the light-shielding layer 110 includes a light-shielding area and a plurality of first opening areas; the orthographic projection of the first opening area of the light-shielding layer 110 on the base substrate 10 is located in the color resist patterns 401, 402, and 403.
- the through hole H that penetrates the film layer between the pixel electrode and the film layer where the first electrode of the thin film transistor is located in the orthographic projection of the base substrate 10 is located in the light-shielding area of the light-shielding layer 110 on the base substrate 10 in the orthographic projection.
- FIG. 27 is a schematic diagram of another film structure of an array substrate provided by an embodiment of the present application.
- the light shielding layer 110 may be located on the side of the pixel electrode 30 away from the base substrate 10, so that the light shielding layer 110 can shield each film layer at the location of the light-shielding area of the light-shielding layer 110. Under the premise of preventing light leakage, it can also block the reflected light of each film layer at the location of the light-shielding area to ensure the use of the array substrate 100. Light leakage does not occur at positions where light is unnecessary in the display panel, so that the display effect of the display panel can be further improved.
- the light-shielding layer 110 is disposed in the array substrate 100, when the array substrate 100 is bent to deform the array substrate 100, the position of the light-shielding area of the light-shielding layer 110 will not be different from the position in the array substrate 100 that needs to be shielded.
- the misalignment can prevent the phenomenon of squeezing light leakage and metal light leakage caused by bending deformation, which is beneficial to improve the display effect of the curved display panel using the array substrate 100.
- each color resist layer includes a plurality of color resist patterns of different colors;
- the array substrate includes a plurality of sub-pixels of different colors, and each sub-pixel includes a light-transmitting area and a non-light-transmitting area surrounding the light-transmitting area;
- the pattern is at least in the light-transmitting area;
- at least one of the at least two color resist layers includes a first color resist pattern and a second color resist pattern, and the color of the first color resist pattern and the color of the second color resist pattern Different;
- a plurality of sub-pixels of different colors including a first sub-pixel and a second sub-pixel;
- the first color resist pattern is located at least in the light-transmitting area of the first sub-pixel;
- the second color resist pattern is located in the light-transmitting area of the second sub-pixel ,
- the via is located between the light-transmitting
- FIG. 28 is a schematic diagram of a top view of another array substrate provided by an embodiment of the present application
- FIG. 29 is a schematic diagram of a film structure of an array substrate corresponding to FIG. 28.
- the array substrate 100 includes a plurality of sub-pixels of different colors, and each sub-pixel includes a light-transmitting area and a non-transmitting area; the plurality of sub-pixels of different colors includes a first sub-pixel ( 101, 102) and the second sub-pixel 103.
- the light-emitting color of the first sub-pixel 101 may be red
- the light-emitting color of the first sub-pixel 102 may be green
- the light-emitting color of the second sub-pixel 103 may be blue
- One sub-pixel 101 includes a light-emitting area 4011 and a non-light-emitting area 4012
- the first sub-pixel 102 includes a light-emitting area 4021 and a non-light-emitting area 4022
- the second sub-pixel 103 includes a light-emitting area 4031 and a non-light-emitting area 4032.
- the at least two color resist layers 40 of the array substrate 100 include a color resist layer 41 and a color resist layer 42, and the color resist pattern of the color resist layer 42 may be a block shape, and the color resist pattern of the color resist layer 41 may include Block-shaped first color resist patterns (401 and 402) and planar second color resist patterns 403; wherein, the first color resist pattern 401 may be a red color resist pattern, and the first color resist pattern 402 may be a green color resist Pattern, the second color resist pattern 403 may be a blue color resist pattern.
- the planar second color resist pattern 403 is provided with a second opening structure, and the first color resist patterns 401 and 402 are respectively located in different second opening structures; at this time, the first color resist pattern 401 is at least located in the first sub-pixel 101
- the first color resist pattern 402 is at least located in the light transmitting area 4021 of the first sub-pixel 102
- the second color resist pattern 403 is at least located in the light transmitting area 4032 of the second sub-pixel 103; at the same time.
- the second color resist pattern 403 is also located in the non-transmissive area 4012 of the first sub-pixel 101, the non-transmissive area 4022 of the first sub-pixel 102, and the non-transmissive area 4032 of the second sub-pixel 103;
- the via hole H of the film layer between the film layer and the film layer where the first electrode 23 of the thin film transistor 20 is located the via hole can be set between two adjacent first color resist patterns 401, and two adjacent first color resist patterns 401.
- the first color resist patterns 401 and 402 can be prevented from being damaged by the provided via H.
- the material of the second color resist pattern 403 is compared with the material of the red first color resist pattern 401 and the green first color resist pattern 402, It has better etchability; in this way, when a hole is opened at the position where the second color resist pattern 403 is provided, the residual phenomenon in the hole can be improved, so that the product yield and display effect can be improved.
- FIG. 28 and FIG. 29 are only exemplary drawings of the embodiments of the present application, and FIG. 28 and FIG.
- the color of the resist pattern may also include a white color resist pattern, a yellow color resist pattern, etc.; at the same time, the array substrate of the embodiment of the present application includes at least two color resist patterns, that is, at least two color resist layers may be two layers , Three or more layers, and at least one of the at least two color resist layers includes a first color resist pattern and a second color resist pattern, that is, all the color resist layers can be set to include the first color resist
- the pattern and the second color resist pattern, or part of the color resist layer includes the first color resist pattern and the second color resist pattern, and the shape of the color resist pattern of other color resist layers may be strips or blocks.
- the embodiment of the present application also provides a display panel.
- the display panel includes the array substrate provided in the embodiment of the present application, a counter substrate disposed opposite to the array substrate, and a liquid crystal layer and a support between the counter substrate and the array substrate. column. Since the display panel provided by the embodiment of the application includes the array substrate provided by the embodiment of the application, the display panel provided by the embodiment of the application has the beneficial effects of the array substrate provided by the embodiment of the application. For similarities, please refer to the above implementation of the application. The description of the array substrate provided in the example will not be repeated here.
- FIG. 30 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
- the display panel 500 includes an array substrate 100 provided by an embodiment of the present application, a counter substrate 200, a liquid crystal layer 300 and a supporting column 400 located between the array substrate 100 and the counter substrate 200; among them, the array substrate In 100, one side of the base substrate 10 is provided with at least a thin film transistor 20, a pixel electrode 30, and at least two color resist layers 40 between the thin film transistor 20 and the pixel electrode 30, compared with at least two color resist layers 40 Any one of the color resist layers is a single-layer color resist layer with the same thickness, the at least two color resist layers 40 have a thicker thickness, so as to improve the display color gamut of the display panel; in addition, the array substrate 100 of the display panel 500 A light-shielding layer 110 is also provided in the light-shielding layer.
- the light-shielding layer 110 is disposed on the side of the pixel electrode 30 away from the base substrate 10, the light-shielding layer 110 is affected by the patterning of the film layer where the pixel electrode 30 is located.
- the protrusions and depressions that appear have a certain leveling effect, so that the support pillars 400 disposed between the array substrate 100 and the counter substrate 200 are formed on a relatively flat plane, thereby improving the display panel 500 at each position.
- the difference in cell thickness of the display panel 500 can improve the display effect of the display panel 500; correspondingly, the support column 400 between the array substrate 100 and the counter substrate 200 can have a good supporting effect on the liquid crystal cell of the display panel 500, and it can be arranged in the display panel.
- the non-transmissive area of each sub-pixel in the panel 500 prevents the support column 400 from affecting the display light emission of the display panel 500.
- the array substrate 100 of the display panel 500 can also be provided with a common electrode 80, which can form an in-plane field with the pixel electrode 30 to drive the liquid crystal molecules in the liquid crystal layer 300 to twist, so that light can pass through the liquid crystal. After layer 300, a corresponding display screen is displayed on the display surface of the display panel 500.
- the embodiment of the present application also provides a display device, and the display device includes the display panel provided in the embodiment of the present application. Therefore, the display device provided by the embodiment of the present application has the technical effects of the above-mentioned display panel, and the similarities will not be repeated in the following, and can be understood with reference to the above explanation of the display panel.
- FIG. 31 is a schematic structural diagram of a display device provided by an embodiment of the present application.
- the display device 600 includes the display panel 500 provided by the embodiment of the present application, and the display device 600 may be, for example, a vehicle-mounted curved display device.
- An array substrate, a display panel, and a display device provided by an embodiment of the present application are provided with a thin film transistor, a pixel electrode, and at least two color resist layers between the thin film transistor and the pixel electrode on one side of the base substrate in the array substrate
- at least two color resist layers are provided between the thin film transistor on one side of the base substrate and the pixel electrode, and the at least two color resist layers have a relatively thick total thickness to meet the display requirements of high color gamut, Therefore, the display effect of the display panel is improved; on the other hand, the color resist layer that meets the requirements of high color gamut is divided into at least two color resist layers.
- each color resist layer of the color resist has a relatively thin thickness, and a dielectric layer is arranged between two adjacent color resist layers, so as to provide a gap between the film layer where the pixel electrode and the first electrode of the thin film transistor are provided.
- each color resist layer can be opened separately, and the color resist pattern in the corresponding color resist layer is protected from being damaged by the dielectric layer disposed between the two adjacent color resist layers, so that the color resist pattern in the corresponding color resist layer is not damaged.
- the difficulty of setting the via hole is reduced, and the phenomenon that the color resist pattern in the color resist layer is left or damaged in the hole is improved, which is beneficial to improve the product yield and thereby improve the display effect.
Abstract
Description
Claims (17)
- 一种阵列基板,包括:衬底基板;位于所述衬底基板一侧的薄膜晶体管,所述薄膜晶体管至少包括第一电极;位于所述薄膜晶体管背离所述衬底基板一侧的像素电极;位于所述薄膜晶体管与所述像素电极之间的至少两层色阻层,且任意相邻的两层所述色阻层之间设置有介质层;其中,所述像素电极通过过孔与所述薄膜晶体管的第一电极电连接,所述过孔贯穿所述至少两层色阻层和位于任意相邻的两层所述色阻层之间的所述介质层。
- 根据权利要求1所述的阵列基板,所述阵列基板还包括:平坦化层;所述平坦化层位于所述像素电极与所述薄膜晶体管之间;其中,所述至少两层色阻层位于所述平坦化层与所述像素电极之间;或者,所述至少两层色阻层位于所述平坦化层与所述薄膜晶体管之间;或者,所述至少两层色阻层包括至少一层第一色阻层和至少一层第二色阻层,所述至少一层第一色阻层位于所述平坦化层与所述像素电极之间,所述至少一层第二色阻层位于所述平坦化层与所述薄膜晶体管之间。
- 根据权利要求2所述的阵列基板,所述阵列基板还包括:第一搭接导电层;所述第一搭接导电层包括第一搭接结构;所述第一搭接导电层位于所述平坦化层背离所述衬底基板的一侧;所述过孔包括第一过孔和第二过孔;所述像素电极通过所述第一过孔与所述第一搭接结构电连接,所述第一搭接结构通过所述第二过孔与所述薄膜晶体管的第一电极电连接。
- 根据权利要求3所述的阵列基板,所述阵列基板还包括:至少一层第二搭接导电层;所述第二搭接导电层包括第二搭接结构;所述第二搭接导电层位于相邻的两层所述色阻层之间,且不同所述第二搭接导电层的所述第二搭接结构依次电连接;其中,所述至少两层色阻层位于所述平坦化层与所述像素电极之间,所述第一过孔包括第一子过孔和第二子过孔,所述像素电极通过所述第一子过孔与所述第二搭接结构电连接,所述第二搭接结构通过所述第二子过孔与所述第一搭接结构电连接;或者,所述至少两层色阻层位于所述平坦化层与所述薄膜晶体管之间,所述第二过孔包括第三子过孔和第四子过孔,所述第一搭接结构通 过所述第三子过孔与所述第二搭接结构电连接,所述第二搭接结构通过所述第四子过孔与所述薄膜晶体管的第一电极电连接。
- 根据权利要求3所述的阵列基板,所述阵列基板还包括:至少一层第三搭接导电层;所述第三搭接导电层包括第三搭接结构;所述至少两层色阻层包括至少两层所述第一色阻层和至少一层所述第二色阻层;所述第三搭接导电层位于相邻的两层所述第一色阻层之间,且不同所述第三搭接导电层的所述第三搭接结构依次电连接;所述第一过孔包括第一子过孔和第二子过孔;所述像素电极通过所述第一子过孔与所述第三搭接结构电连接;所述第三搭接结构通过所述第二子过孔与所述第一搭接结构电连接。
- 根据权利要求3所述的阵列基板,所述阵列基板还包括:至少一层第四搭接导电层;所述第四搭接导电层包括第四搭接结构;所述至少两层色阻层包括至少一层所述第一色阻层和至少两层所述第二色阻层;所述第四搭接导电层位于相邻的两层所述第二色阻层之间,且不同所述第四搭接导电层的第四搭接结构依次电连接;所述第二过孔包括第三子过孔和第四子过孔;所述第一搭接结构通过所述第三子过孔与所述第四搭接结构电连接;所述第四搭接结构通过所述第四子过孔与所述薄膜晶体管的第一电极电连接。
- 根据权利要求3所述的阵列基板,所述阵列基板还包括:至少一层第三搭接导电层和至少一层第四搭接导电层;所述第三搭接导电层包括第三搭接结构,所述第四搭接导电层包括第四搭接结构;所述至少两层色阻层包括至少两层所述第一色阻层和至少两层所述第二色阻层;所述第三搭接导电层位于相邻的两层所述第一色阻层之间,且不同所述第三搭接导电层的所述第三搭接结构依次电连接;所述第四搭接导电层位于相邻的两层第二色阻层之间,且不同所述第四搭接导电层的所述第四搭接结构依次电连接;所述第一过孔包括第一子过孔和第二子过孔,所述第二过孔包括第三子过孔和第四子过孔;所述像素电极通过所述第一子过孔与所述第三搭接结构电连接;所述第三搭接结构通过所述第二子过孔与所述第一搭接结构电连接;所述第一搭接结构通过所述第三子过孔与所述第四搭接结构电连接;所述第四搭接 结构通过所述第四子过孔与所述薄膜晶体管的第一电极电连接。
- 根据权利要求3所述的阵列基板,其中,所述第一搭接导电层还包括触控走线;所述阵列基板还包括触控电极,所述触控走线与所述触控电极电连接。
- 根据权利要求2所述的阵列基板,所述阵列基板还包括:公共电极;所述公共电极位于所述平坦化层与所述像素电极之间。
- 根据权利要求9所述的阵列基板,其中,所述至少两层色阻层位于所述像素电极与所述平坦化层之间;所述公共电极位于所述平坦化层与所述至少两层色阻层之间;或者,所述公共电极位于所述像素电极与所述至少两层色阻层之间;或者,所述公共电极位于相邻的两层色阻层之间。
- 根据权利要求9所述的阵列基板,其中,所述至少两层色阻层包括至少一层所述第一色阻层和至少一层所述第二色阻层,且所述至少一层第一色阻层位于所述平坦化层与所述像素电极之间;所述公共电极位于所述平坦化层与所述至少一层第一色阻层之间;或者,所述公共电极位于所述至少一层第一色阻层与所述像素电极之间;或者,所述公共电极位于相邻的两层所述第一色阻层之间。
- 根据权利要求9所述的阵列基板,其中,所述公共电极与所述像素电极之间还设置有至少一层绝缘层。
- 根据权利要求1所述的阵列基板,其中,每一所述色阻层包括多个不同颜色的色阻图案;其中,每一所述色阻图案为条状,且所述多个色阻图案沿第一方向排列且均沿第二方向延伸,所述第一方向与所述第二方向交叉,所述过孔在所述衬底基板的正投影位于所述色阻图案在所述衬底基板的正投影内;或者,每一所述色阻图案为块状,且所述多个色阻图案阵列排布,所述过孔位于相邻的两个颜色相同的所述色阻图案之间。
- 根据权利要求13所述的阵列基板,所述阵列基板还包括:遮光层;所述遮光层包括遮光区和多个第一开口区;所述第一开口区在所述衬底基板的正投影位于所述色阻图案在所述衬底基板的正投影内;所述过孔在所述衬底基板的正投影位于所述遮光区在所述衬底基板的正投影内。
- 根据权利要求1所述的阵列基板,其中,每一所述色阻层包括多个不 同颜色的色阻图案;所述阵列基板包括多个不同颜色的子像素,每一所述子像素包括透光区和围绕所述透光区的非透光区;所述色阻图案至少位于所述透光区内;所述至少两层色阻层中至少一层所述色阻层包括第一色阻图案和第二色阻图案,且所述第一色阻图案的颜色与所述第二色阻图案的颜色不同;所述多个不同颜色的子像素包括第一子像素和第二子像素;所述第一色阻图案至少位于所述第一子像素的透光区;所述第二色阻图案位于所述第二子像素的透光区、所述第二子像素非透光区和所述第一子像素的非透光区;所述过孔位于相邻的两个颜色相同的所述子像素的透光区之间;位于相邻的两个颜色相同的所述第一子像素的透光区之间的过孔为第一像素孔;所述第一像素孔位于相邻的两个颜色相同的所述第一色阻图案之间。
- 一种显示面板,包括:如权利要求1~15任一项所述的阵列基板;与所述阵列基板相对设置的对置基板;以及位于所述对置基板和所述阵列基板之间的液晶层和支撑柱。
- 一种显示装置,包括:如权利要求16所述的显示面板。
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