WO2021217468A1 - 显示面板、驱动方法及显示装置 - Google Patents

显示面板、驱动方法及显示装置 Download PDF

Info

Publication number
WO2021217468A1
WO2021217468A1 PCT/CN2020/087637 CN2020087637W WO2021217468A1 WO 2021217468 A1 WO2021217468 A1 WO 2021217468A1 CN 2020087637 W CN2020087637 W CN 2020087637W WO 2021217468 A1 WO2021217468 A1 WO 2021217468A1
Authority
WO
WIPO (PCT)
Prior art keywords
clock signal
transistor
electrically connected
base substrate
shift register
Prior art date
Application number
PCT/CN2020/087637
Other languages
English (en)
French (fr)
Inventor
庞玉乾
肖云升
青海刚
王苗
张跳梅
王梦奇
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP20933067.9A priority Critical patent/EP4036899A4/en
Priority to PCT/CN2020/087637 priority patent/WO2021217468A1/zh
Priority to KR1020227017659A priority patent/KR20230002266A/ko
Priority to CN202080000620.9A priority patent/CN113853642A/zh
Priority to US17/772,329 priority patent/US11929030B2/en
Priority to JP2022528658A priority patent/JP2023531843A/ja
Publication of WO2021217468A1 publication Critical patent/WO2021217468A1/zh
Priority to US18/434,932 priority patent/US20240177678A1/en

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a driving method, and a display device.
  • GOA Gate Driver on Array, array substrate row drive
  • TFT Thin Film Transistor, thin film transistor
  • the base substrate includes a display area and a non-display area
  • the display area includes:
  • Multiple sub-pixels are arranged in a matrix of multiple rows and multiple columns;
  • a plurality of driving lines, one row of the sub-pixels is correspondingly electrically connected to at least one of the driving lines;
  • a plurality of data lines, one column of the sub-pixels is correspondingly electrically connected to at least one of the data lines;
  • the non-display area includes:
  • the gate driving circuit includes: a plurality of clock signal lines, and a plurality of shift register units arranged in sequence along the extending direction of the clock signal lines; wherein, the plurality of clock signal lines are divided into a plurality of clock signal line groups ;
  • the plurality of shift register units are divided into a plurality of register unit groups; wherein, the shift register units in the same register unit group are arranged in cascade, adjacent to each other along the extension direction of the clock signal line
  • the two shift register units of are located in different register unit groups; and the different register unit groups correspond to different clock signal line groups;
  • Each of the shift register units includes an input transistor and an output transistor; wherein the gate of the input transistor is electrically connected to one clock signal line in the corresponding clock signal line group, and the first pole of the input transistor It is electrically connected to the input signal terminal, the second electrode of the input transistor is electrically connected to the gate of the output transistor; the second electrode of the output transistor is electrically connected to at least one drive line correspondingly.
  • the display panel further includes:
  • the semiconductor layer is located on the base substrate, and the semiconductor layer includes an active layer of the input transistor and an active layer of the output transistor; the active layer includes a source region, a drain region, and The channel region between the source region and the drain region;
  • a gate insulating layer located on the side of the semiconductor layer away from the base substrate;
  • the first conductive layer is located on the side of the gate insulating layer away from the base substrate, and the first conductive layer includes the plurality of driving lines, the plurality of first connecting lines, the plurality of second connecting lines, and the The gate of the input transistor and the gate of the output transistor; one of the shift register units corresponds to at least one of the first connection line and at least one of the second connection line;
  • the first insulating layer is located on the side of the first conductive layer away from the base substrate;
  • the second conductive layer is located on the side of the first insulating layer away from the base substrate, and the second conductive layer includes the plurality of data lines, the plurality of clock signal lines, and a plurality of first transitions Section; wherein one of the first switching section is electrically connected to a source region of the active layer of the output transistor; the second conductive layer further includes: a first power line;
  • one end of the first connection line is directly electrically connected to the gate of the input transistor in the shift register unit ,
  • the other end of the first connection line is electrically connected to a clock signal line in the clock signal line group through a first via hole
  • one end of the second connection line is electrically connected to the first via hole through a second via hole.
  • the connection part is electrically connected, and the other end of the second connection line is electrically connected to another clock signal line or the first power line in the clock signal line group through a third via;
  • the first via hole, the second via hole and the third via hole penetrate the first insulating layer and are arranged at intervals.
  • the multiple clock signal lines are divided into two clock signal line groups, and the two clock signal line groups include a first clock signal line group and a second clock signal line group;
  • the first clock signal line group includes a first clock signal line and a second clock signal line
  • the second clock signal line group includes a third clock signal line and a fourth clock signal line;
  • the plurality of shift register units are divided into 2 register unit groups, the 2 register unit groups include a first register unit group and a second register unit group, wherein the first register unit group includes the The odd-numbered shift register units arranged in sequence along the extending direction of the clock signal line, and the second register unit group includes the even-numbered shift register units arranged in sequence along the extending direction of the clock signal line;
  • the gate of the input transistor of the shift register unit of the odd-numbered stage is electrically connected to the first clock signal line through a corresponding first connection line
  • the first pole of the output transistor of the odd-numbered stage shift register unit is electrically connected to the second clock signal line or the first power line through a corresponding second connection line
  • the even-numbered stage shift register unit The gate of the input transistor is electrically connected to the second clock signal line through a corresponding first connection line
  • the first pole of the output transistor of the even-numbered stage shift register unit is electrically connected to the second clock signal line through a corresponding second connection line.
  • the gate of the input transistor of the shift register unit of the odd-numbered stage is electrically connected to the third clock signal line through the corresponding first connection line
  • the first pole of the output transistor of the odd-numbered stage shift register unit is electrically connected to the fourth clock signal line or the first power line through a corresponding second connection line
  • the even-numbered stage shift register The gate of the input transistor of the unit is electrically connected to the fourth clock signal line through a corresponding first connection line
  • the first pole of the output transistor of the even-numbered stage shift register unit is electrically connected to the fourth clock signal line through a corresponding second connection line.
  • the third clock signal line or the first power line is electrically connected.
  • each of the shift register units further includes a voltage stabilizing transistor; wherein, the second electrode of the input transistor is electrically connected to the first electrode of the voltage stabilizing transistor, and the The second pole of the voltage stabilizing transistor is electrically connected to the gate of the output transistor;
  • the second conductive layer further includes: a first power line; the gate of each of the voltage stabilizing transistors is electrically connected to the first power line through a fourth via; wherein the fourth via penetrates the first An insulating layer.
  • the orthographic projection of the input transistor on the base substrate is located at the same position as the orthographic projection of the first power line on the base substrate.
  • the plurality of clock signal lines are between the orthographic projections of the base substrate;
  • the orthographic projection of the voltage stabilizing transistor on the base substrate is located on the orthographic projection of the first power line on the base substrate away from the plurality of clock signal lines on the orthographic projection side of the base substrate;
  • the orthographic projection of the output transistor on the base substrate is located on a side of the orthographic projection of the voltage stabilizer transistor on the base substrate that is away from the first power line and is on the base substrate.
  • the shift register unit further includes a first control transistor and a second control transistor;
  • the semiconductor layer further includes an active layer of the first control transistor and an active layer of the second control transistor;
  • the first conductive layer further includes: a gate of the first control transistor and a gate of the second control transistor;
  • the second conductive layer further includes: a second power line, a plurality of second switching parts, and a plurality of third switching parts; wherein, one of the second switching parts corresponds to one of the first control transistors, and one The third switching part corresponds to one of the second control transistors;
  • the display panel further includes:
  • the fourth conductive layer is located between the first insulating layer and the second conductive layer, and the fourth conductive layer includes a plurality of first conductive portions; wherein, one of the first conductive portions corresponds to one of the Second control transistor;
  • a third insulating layer located between the fourth conductive layer and the second conductive layer
  • the gate of the first control transistor is directly electrically connected to the corresponding first connection line, and the source region of the active layer of the first control transistor is electrically connected to the first power line through a fifth via hole , The drain region of the active layer of the first control transistor is electrically connected to the gate of the second control transistor through the corresponding second switching portion; wherein, the fifth via hole penetrates the first control transistor An insulating layer and the third insulating layer;
  • the source region of the active layer of the second control transistor is electrically connected to one end of the corresponding third transfer portion through a sixth via hole, and the other end of the third transfer portion is electrically connected to one end of the third transfer portion through a seventh via hole.
  • One end of the corresponding first conductive part is electrically connected, the other end of the first conductive part is electrically connected to the second power line through an eighth via, and the drain of the active layer of the second control transistor Region is shared with the drain region of the active layer of the output transistor; wherein, the sixth via penetrates the first insulating layer and the third insulating layer, and the seventh via and the eighth The via hole penetrates the third insulating layer.
  • the orthographic projection of the second power line on the base substrate is located on the orthographic projection of the plurality of clock signal lines on the base substrate and the gate drive circuit Between the orthographic projections of the base substrate;
  • the orthographic projection of the first control transistor on the base substrate is located on the orthographic projection of the input transistor on the base substrate and the first power line is on the base substrate. Between the orthographic projections;
  • the orthographic projection of the second control transistor on the base substrate is located on the base substrate and the orthographic projection of the input transistor on the base substrate is away from the first power line on the base substrate The orthographic projection side.
  • the active layer of the output transistor and the active layer of the second control transistor are arranged in an integrated structure.
  • the shift register unit further includes: a first capacitor and a second capacitor; wherein, the first pole of the first capacitor is electrically connected to the second power line, so The second electrode of the first capacitor is electrically connected to the gate of the second control transistor; the first electrode of the second capacitor is electrically connected to the second electrode of the output transistor, and the second electrode of the second capacitor is electrically connected to the second electrode of the output transistor.
  • the pole is electrically connected to the gate of the output transistor;
  • the fourth conductive layer further includes a plurality of second conductive parts; wherein one second conductive part corresponds to one output transistor;
  • the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the gate of the second control transistor on the base substrate have an overlapping area, and the first conductive portion serves as the first A first pole of a capacitor, and the gate of the second control transistor serves as the second pole of the first capacitor;
  • the orthographic projection of the second conductive portion on the base substrate and the orthographic projection of the gate of the corresponding output transistor on the base substrate have an overlapping area, and the second conductive portion serves as the first The first pole of the two capacitors, and the gate of the output transistor serves as the second pole of the second capacitor.
  • the orthographic projection of the gate of the second control transistor on the base substrate covers the orthographic projection of the first conductive portion on the base substrate.
  • the orthographic projection of the gate of the second control transistor on the base substrate and the orthographic projection of the first conductive portion on the base substrate are respectively the same as those of the second control transistor.
  • a power line has an overlapping area on the orthographic projection of the base substrate.
  • the orthographic projection of the eighth via on the base substrate is located between the orthographic projection of the first power line and the second power line on the base substrate.
  • the orthographic projection of the seventh via on the base substrate is located on the orthographic projection of the first power line on the base substrate and the active layer of the second control transistor is on the base substrate Between the orthographic projections.
  • the display panel further includes:
  • a second insulating layer located on the side of the second conductive layer away from the base substrate;
  • the third conductive layer is located on the side of the second insulating layer away from the base substrate, and the second conductive layer includes: at least one auxiliary line;
  • One of the auxiliary lines and one of the clock signal lines are electrically connected through at least one ninth via, and the ninth via penetrates the second insulating layer.
  • the orthographic projection of the clock signal line on the base substrate covers the orthographic projection of the auxiliary line of the electrical connection on the base substrate.
  • the embodiment of the present disclosure also provides a display device including the above-mentioned display panel.
  • the embodiment of the present disclosure also provides a driving method of the above-mentioned display panel, including:
  • each of the shift register units is controlled to work sequentially to scan each of the drive lines row by row; wherein the odd-numbered shift register units are arranged in sequence along the extension direction of the clock signal line And the even number of shift register units are independently driven under the control of different clock signal line groups.
  • the embodiment of the present disclosure also provides the above-mentioned driving method of the display panel, which includes: the time for the signals applied to the multiple clock signal lines in different clock signal line groups to maintain an effective level does not overlap with each other.
  • FIG. 1 is a schematic diagram of the structure of some display panels provided by the embodiments of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a pixel driving circuit in some sub-pixels provided by an embodiment of the disclosure
  • FIG. 3 is a signal timing diagram of some pixel driving circuits provided by embodiments of the disclosure.
  • 4a is a schematic structural diagram of some shift register units provided by embodiments of the disclosure.
  • 4b is a signal timing diagram of some shift register units provided by embodiments of the disclosure.
  • 4c is a timing diagram of signals output by some gate driving circuits provided by embodiments of the disclosure.
  • FIG. 5a is a schematic structural diagram of other shift register units provided by the embodiments of the disclosure.
  • FIG. 5b is a signal timing diagram of other shift register units provided by the embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of the layout structure of some gate driving circuits provided by the embodiments of the disclosure.
  • FIG. 7a is a schematic diagram of the layout structure of some semiconductor layers provided by the embodiments of the present disclosure.
  • FIG. 7b is a schematic diagram of the layout structure of some gate conductive layers provided by the embodiments of the present disclosure.
  • FIG. 7c is a schematic diagram of the layout structure of some fourth conductive layers provided by the embodiments of the present disclosure.
  • FIG. 7d is a schematic diagram of the layout structure of some second conductive layers provided by the embodiments of the present disclosure.
  • Fig. 8a is a schematic cross-sectional structure view along the AA' direction in the schematic layout structure shown in Fig. 6;
  • Fig. 8b is a schematic cross-sectional structure view along the BB' direction in the schematic layout structure shown in Fig. 6;
  • FIG. 9 is a schematic diagram of the layout structure of still other gate driving circuits provided by the embodiments of the present disclosure.
  • FIG. 10 is a schematic diagram of the layout structure of some third conductive layers provided by the embodiments of the present disclosure.
  • Fig. 11 is a schematic cross-sectional view of the layout structure shown in Fig. 9 along the AA' direction;
  • FIG. 12 is a signal timing diagram of still other shift register units provided by an embodiment of the present invention.
  • the display panel provided by an embodiment of the present disclosure may include: a base substrate 1000.
  • the base substrate 1000 may include a display area AA and a non-display area BB.
  • the non-display area BB may surround the display area.
  • the display area AA may include a plurality of pixel units PX
  • the pixel unit PX may include a plurality of sub-pixels spx.
  • the multiple sub-pixels spx are arranged in a matrix of multiple rows and multiple columns.
  • At least one sub-pixel spx of the plurality of sub-pixels spx may include: a pixel driving circuit 0121 and a light emitting device 0120.
  • the pixel driving circuit 0121 has a transistor and a capacitor, and generates an electrical signal through the interaction of the transistor and the capacitor, and the generated electrical signal is input to the first electrode of the light-emitting device 0120.
  • a corresponding voltage is applied to the second electrode of the light-emitting device 0120 to drive the light-emitting device 0120 to emit light.
  • the pixel driving circuit 0121 may include: a driving control circuit 0122, a first light emission control circuit 0123, a second light emission control circuit 0124, a data writing circuit 0126, a storage circuit 0127, a threshold compensation circuit 0128, and a reset circuit 0129 .
  • the drive control circuit 0122 may include a control terminal, a first pole, and a second pole. And the driving control circuit 0122 is configured to provide the light-emitting device 0120 with a driving current for driving the light-emitting device 0120 to emit light.
  • the first light emission control circuit 0123 is connected to the first pole of the drive control circuit 0122 and the first voltage terminal VDD. And the first light emission control circuit 0123 is configured to realize the connection between the drive control circuit 0122 and the first voltage terminal VDD being turned on or off.
  • the second light emitting control circuit 0124 is electrically connected to the second electrode of the driving control circuit 0122 and the first electrode of the light emitting device 0120. And the second light emitting control circuit 0124 is configured to realize the connection between the driving control circuit 0122 and the light emitting device 0120 to be turned on or off.
  • the data writing circuit 0126 is electrically connected to the first pole of the drive control circuit 0122.
  • the second light emission control circuit 0124 is configured to write the signal on the data line VD into the storage circuit 0127 under the control of the signal on the scan line GA2.
  • the storage circuit 0127 is electrically connected to the control terminal of the drive control circuit 0122 and the first voltage terminal VDD. And the storage circuit 0127 is configured to store data signals.
  • the threshold compensation circuit 0128 is electrically connected to the control terminal and the second pole of the drive control circuit 0122. And the threshold compensation circuit 0128 is configured to perform threshold compensation for the drive control circuit 0122.
  • the reset circuit 0129 is electrically connected to the control terminal of the drive control circuit 0122 and the first electrode of the light emitting device 0120. And the reset circuit 0129 is configured to reset the control terminal of the drive control circuit 0122 and the first electrode of the light emitting device 0120 under the control of the signal on the scan line GA1.
  • the light emitting device 0120 can be configured as an electroluminescent diode, such as at least one of OLED and QLED.
  • the optical device 0120 may include a first electrode, a light-emitting function layer, and a second electrode that are stacked.
  • the first electrode may be an anode
  • the second electrode may be a cathode.
  • the light-emitting functional layer may include a light-emitting layer.
  • the light-emitting functional layer may also include film layers such as a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer.
  • the light emitting device 0120 can be designed and determined according to the requirements of the actual application environment, which is not limited here.
  • the drive control circuit 0122 includes: a drive transistor T1, the control terminal of the drive control circuit 0122 includes the gate of the drive transistor T1, and the first pole of the drive control circuit 0122 includes the first pole of the drive transistor T1.
  • the second electrode of the driving control circuit 0122 includes the second electrode of the driving transistor T1.
  • the data writing circuit 0126 includes a data writing transistor T2.
  • the storage circuit 0127 includes a storage capacitor CST.
  • the threshold compensation circuit 0128 includes a threshold compensation transistor T3.
  • the first light emission control circuit 0123 includes a first light emission control transistor T4.
  • the second light emission control circuit 0124 includes a second light emission control transistor T5.
  • the reset circuit 0129 includes a first reset transistor T6 and a second reset transistor T7.
  • the first electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1
  • the second electrode of the data writing transistor T2 is configured to be electrically connected to the data line VD to receive the data signal
  • the data writing transistor The gate of T2 is configured to be electrically connected to the second scan line GA2 to receive a scan signal.
  • the first electrode of the storage capacitor CST is electrically connected to the first power supply terminal VDD, and the second electrode of the storage capacitor CST is electrically connected to the gate of the driving transistor T1.
  • the first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1
  • the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1
  • the gate of the threshold compensation transistor T3 is configured to be connected to the second electrode.
  • the scan line GA2 is electrically connected to receive signals.
  • the first electrode of the first reset transistor T6 is configured to be electrically connected to the reset signal line VINIT to receive the reset signal
  • the second electrode of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1
  • the gate of the first reset transistor T6 The pole is configured to be electrically connected to the first scan line GA1 to receive a signal.
  • the first electrode of the second reset transistor T7 is configured to be electrically connected to the reset signal line VINIT to receive the reset signal
  • the second electrode of the second reset transistor T7 is electrically connected to the first electrode of the light emitting device 0120
  • the second electrode of the second reset transistor T7 The gate is configured to be electrically connected to the first scan line GA1 to receive a signal.
  • the first electrode of the first light-emission control transistor T4 is electrically connected to the first power supply terminal VDD, the second electrode of the first light-emission control transistor T4 is electrically connected to the first electrode of the driving transistor T1, and the gate of the first light-emission control transistor T4 is It is configured to be electrically connected to the light emission control line EM to receive the light emission control signal.
  • the first electrode of the second light emission control transistor T5 is electrically connected to the second electrode of the driving transistor T1
  • the second electrode of the second light emission control transistor T5 is electrically connected to the first electrode of the light emitting device 0120
  • the gate of the second light emission control transistor T5 The pole is configured to be electrically connected with the emission control line EM to receive the emission control signal.
  • the second electrode of the light emitting device 0120 is electrically connected to the second power supply terminal VSS.
  • the first electrode and the second electrode of the above-mentioned transistor can be determined as the source electrode or the drain electrode according to the actual application, which is not limited herein.
  • one of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal.
  • the first power terminal VDD is a voltage source to output a constant first voltage
  • the first voltage is a positive voltage
  • the second power terminal VSS may be a voltage source to output a constant first voltage.
  • Two voltages, the second voltage is a negative voltage, etc.
  • the second power supply terminal VSS may be grounded.
  • the signal timing diagram corresponding to the pixel driving circuit shown in FIG. 2 is shown in FIG. 3.
  • the working process of the pixel driving circuit has three stages: T10 stage, T20 stage, and T30 stage.
  • ga1 represents the signal transmitted on the first scan line GA1
  • ga2 represents the signal transmitted on the second scan line GA2
  • em represents the signal transmitted on the light-emitting control line EM.
  • the signal ga1 controls the first reset transistor T6 and the second reset transistor T7 to conduct.
  • the turned-on first reset transistor T6 provides the signal transmitted on the reset signal line VINIT to the gate of the driving transistor T1 to reset the gate of the driving transistor T1.
  • the turned-on second reset transistor T7 provides the signal transmitted on the reset signal line VINIT to the first electrode of the light-emitting device 0120 to reset the first electrode of the light-emitting device 0120.
  • the signal ga2 controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned off.
  • the signal em controls both the first light-emission control transistor T4 and the second light-emission control transistor T5 to be turned off.
  • the signal ga2 controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned on, so that the data signal transmitted on the data line VD can charge the gate of the driving transistor T1 to make the gate of the driving transistor T1
  • the voltage becomes: Vdata+
  • Vth represents the threshold voltage of the driving transistor T1
  • Vdata represents the voltage of the data signal.
  • the signal ga1 controls both the first reset transistor T6 and the second reset transistor T7 to be turned off.
  • the signal em controls both the first light-emission control transistor T4 and the second light-emission control transistor T5 to be turned off.
  • the signal em controls both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be turned on.
  • the turned-on first light-emitting control transistor T4 provides the voltage Vdd of the first power supply terminal VDD to the first pole of the driving transistor T1, so that the voltage of the first pole of the driving transistor T1 is Vdd.
  • the driving transistor T1 generates a driving current according to its gate voltage Vdata+
  • the driving current is provided to the light-emitting device 0120 through the turned-on second light-emitting control transistor T5 to drive the light-emitting device 0120 to emit light.
  • the signal ga1 controls both the first reset transistor T6 and the second reset transistor T7 to be turned off.
  • the signal ga2 controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned off.
  • the pixel driving circuit in the sub-pixel may not only have the structure shown in FIG. 2, but also may have a structure including other numbers of transistors, which is not limited in the embodiment of the present disclosure. .
  • the display area may include a plurality of driving lines and a plurality of data lines; wherein, a row of sub-pixels is correspondingly electrically connected to at least one of the driving lines, and a column of sub-pixels Correspondingly, at least one data line is electrically connected.
  • the driving line includes at least one of a plurality of scan lines and a plurality of light emission control lines. Wherein, a row of sub-pixels are electrically connected to at least one scan line and at least one light-emitting control line.
  • the pixel driving circuit is configured as shown in FIG.
  • a column of sub-pixels can be electrically connected to one data line or can be The sub-pixels located in different rows in a column of sub-pixels are respectively electrically connected to two data lines.
  • One row of sub-pixels corresponds to one light-emitting control line.
  • the plurality of scan lines may include a plurality of first scan lines and a plurality of second scan lines.
  • a row of sub-pixels is correspondingly electrically connected to two scan lines, that is, a row of sub-pixels is correspondingly electrically connected to a first scan line and a second scan line.
  • the second scan line corresponding to the first row is electrically connected to the first scan line corresponding to the second row, so as to transmit the same signal.
  • the non-display area BB may include: a gate driving circuit 01 and Multiple clock signal lines.
  • the extension direction of the clock signal line is different from the extension direction of the scan line, for example, the extension direction of the clock signal line crosses the extension direction of the scan line.
  • the multiple clock signal lines are arranged at intervals on the side of the gate driving circuit 01 away from the scan lines.
  • the gate driving circuit 01 may include: a plurality of shift register units sequentially arranged along the extension direction F1 of the clock signal line: SR2n-3, SR2n-2, SR2n-1, SR2n, SR2n+1, SR2n+ 2. SR2n+3, SR2n+4 (n is an integer greater than 0).
  • the output signal terminal OP of one shift register unit may be electrically connected to at least one drive line.
  • the output signal terminal OP of one shift register unit may be electrically connected to at least one scan line. It is also possible to electrically connect the output signal terminal OP of a shift register unit to at least one light-emitting control line.
  • op2n-3 is the signal output by the output signal terminal OP of the shift register unit SR2n-3
  • op2n-2 is the signal output by the output signal terminal OP of the shift register unit SR2n-2
  • op2n-1 is the shift register unit
  • op2n is the signal output by the output signal terminal OP of the shift register unit SR2n
  • op2n+1 is the signal output by the output signal terminal OP of the shift register unit SR2n+1
  • op2n+ 2 is the signal output by the output signal terminal OP of the shift register unit SR2n+2
  • op2n+3 is the signal output by the output signal terminal OP of the shift register unit SR2n+3
  • op2n+4 is the signal output by the shift register unit SR2n+4 The signal output by the output signal terminal OP.
  • the shift register unit may include: a plurality of transistors; the plurality of transistors may include: an input transistor M1, a voltage stabilizing transistor M2, an output transistor M3, a first The control transistor M4, the second control transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the first capacitor C01, and the second capacitor C02.
  • the gate of the input transistor M1 is electrically connected to the first clock signal terminal CK
  • the first electrode of the input transistor M1 is electrically connected to the input signal terminal IP
  • the second electrode of the input transistor M1 is electrically connected to the first electrode of the voltage stabilizing transistor M2. connect.
  • the gate of the voltage stabilizing transistor M2 is electrically connected to the first power line VGL
  • the second electrode of the voltage stabilizing transistor M2 is electrically connected to the gate of the output transistor M3
  • the first electrode of the output transistor M3 is electrically connected to the second clock signal terminal CB
  • the second pole of the output transistor M3 is electrically connected to the output signal terminal OP, that is, the second pole of the output transistor is electrically connected to at least one scan line.
  • the gate of the first control transistor M4 is electrically connected to the gate of the input transistor M1, the first electrode of the first control transistor M4 is electrically connected to the first power line VGL, and the second electrode of the first control transistor M4 is electrically connected to the second control transistor.
  • the gate of M5 is electrically connected.
  • the first electrode of the second control transistor M5 is electrically connected to the second power line VGH, and the second electrode of the second control transistor M5 is electrically connected to the second electrode of the output transistor.
  • the gate of the sixth transistor M6 is electrically connected to the second electrode of the input transistor M1, the first electrode of the sixth transistor M6 is electrically connected to the first clock signal terminal CK, and the second electrode of the sixth transistor M6 is electrically connected to the first control transistor M4.
  • the second pole is electrically connected.
  • the gate of the seventh transistor M7 is electrically connected to the second clock signal terminal CB, the first electrode of the seventh transistor M7 is electrically connected to the gate of the input transistor M1, and the second electrode of the seventh transistor M7 is electrically connected to the second electrode of the eighth transistor M8.
  • the gate of the eighth transistor M8 is electrically connected to the second electrode of the first control transistor M4, and the second electrode of the eighth transistor M8 is electrically connected to the second power line VGH.
  • the first electrode of the first capacitor C01 is electrically connected to the second power line VGH, the second electrode of the first capacitor C01 is electrically connected to the gate of the second control transistor M5; the first electrode of the second capacitor C02 is electrically connected to the first electrode of the output transistor M5 The two poles are electrically connected, and the second pole of the second capacitor C01 is electrically connected to the gate of the output transistor M3.
  • the signal timing diagram corresponding to the shift register shown in FIG. 4a is shown in FIG. 4b.
  • ck represents the clock signal input from the gate of the input transistor M1
  • cb represents the clock signal input from the first pole of the output transistor M3
  • ip represents the signal of the input signal terminal IP
  • op represents the signal of the output signal terminal OP.
  • the output transistor M3 can output the signal op.
  • the signal timing diagram corresponding to the shift register shown in FIG. 4a may be other forms of signal timing diagrams in addition to the signal timing diagram shown in FIG. 4b, which can be based on actual application requirements. The design is determined, which is not limited in the embodiments of the present disclosure.
  • each shift register unit in the above-mentioned gate driving circuit 01 may be the same in function and structure as the shift register unit shown in FIG. 4a of the present disclosure.
  • the gate driving circuit 01 can input signals for the first scan line GA1 and the second scan line GA2, thereby controlling the conduction of the first reset transistor T6, the second reset transistor T7, the data writing transistor T2, and the threshold compensation transistor T3. Pass and cut off.
  • the shift register unit may include a plurality of transistors; the plurality of transistors may include: an input transistor M1, an output transistor M3, a ninth transistor M09, and a tenth transistor.
  • the gate of the input transistor M1 is electrically connected to the first clock signal terminal CK
  • the first electrode of the input transistor M1 is electrically connected to the input signal terminal IP
  • the second electrode of the input transistor M1 is electrically connected to the gate of the output transistor M3.
  • the first pole of the output transistor M3 is electrically connected to the first power line VGL
  • the second pole of the output transistor M3 is electrically connected to the output signal terminal OP, that is, the second pole of the output transistor is electrically connected to at least one light-emitting control line correspondingly.
  • the gate of the ninth transistor M09 is electrically connected to the gate of the input transistor M1
  • the first electrode of the ninth transistor M09 is electrically connected to the first power line VGL
  • the second electrode of the ninth transistor M09 is electrically connected to the gate of the fourteenth transistor M014. Extremely electrical connection.
  • the first electrode of the fourteenth transistor M014 is electrically connected to the second clock signal terminal CB, and the second electrode of the fourteenth transistor M014 is electrically connected to the first electrode of the sixteenth transistor M016.
  • the second electrode of the sixteenth transistor M016 is electrically connected to the gate of the tenth transistor M010, and the gate of the sixteenth transistor M016 is electrically connected to the second clock signal terminal CB.
  • the first electrode of the tenth transistor M010 is electrically connected to the second power line VGH, and the second electrode of the tenth transistor M010 is electrically connected to the second electrode of the output transistor M3.
  • the gate of the eleventh transistor M011 is electrically connected to the second electrode of the input transistor M1, the first electrode of the eleventh transistor M011 is electrically connected to the first clock signal terminal CK, and the second electrode of the eleventh transistor M011 is electrically connected to the ninth terminal.
  • the second electrode of the transistor M09 is electrically connected.
  • the gate of the twelfth transistor M012 is electrically connected to the second clock signal terminal CB, the first electrode of the twelfth transistor M012 is electrically connected to the gate of the input transistor M1, and the second electrode of the twelfth transistor M012 is electrically connected to the thirteenth terminal.
  • the first electrode of the transistor M013 is electrically connected.
  • the gate of the thirteenth transistor M013 is electrically connected to the second electrode of the ninth transistor M09, and the second electrode of the thirteenth transistor M013 is electrically connected to the second power line VGH.
  • the first electrode of the fifth capacitor C05 is electrically connected to the second power line VGH, the second electrode of the fifth capacitor C05 is electrically connected to the gate of the tenth transistor M010; the first electrode of the third capacitor C03 is electrically connected to the second clock signal terminal CB is electrically connected, and the second electrode of the third capacitor C03 is electrically connected to the gate of the output transistor M3.
  • the first electrode of the fourth capacitor C04 is electrically connected to the gate of the fourteenth transistor M014, and the second electrode of the fourth capacitor C04 is electrically connected to the second electrode of the fourteenth transistor M014.
  • the signal timing diagram corresponding to the shift register shown in FIG. 5a is shown in FIG. 5b.
  • ck represents the clock signal input from the gate of the input transistor M1
  • cb represents the clock signal input from the gate of the twelfth transistor M012
  • ip represents the signal of the input signal terminal IP
  • op represents the signal of the output signal terminal OP.
  • the output transistor M3 can output the signal op.
  • the signal timing diagram corresponding to the shift register shown in FIG. 5a may be other forms of signal timing diagrams in addition to the signal timing diagram shown in FIG. 5b, which can be based on actual application requirements. The design is determined, which is not limited in the embodiments of the present disclosure.
  • each shift register unit in the above-mentioned gate driving circuit 01 may be the same in function and structure as the shift register unit shown in FIG. 5a of the present disclosure.
  • the gate driving circuit 01 can input a signal to the light-emission control line, so that the first light-emission control transistor T4 and the second light-emission control transistor T5 can be controlled to be turned on and off.
  • the shift register unit may also be a structure including other numbers of transistors, which is not limited in the embodiment of the present disclosure.
  • the structure of the shift register unit shown in FIG. 4a is taken as an example for description.
  • each shift register unit In order to input the corresponding clock signal to each shift register unit, generally only two clock signal lines are used to input the corresponding clock signal to each shift register unit in the gate drive circuit 01, which causes the clock signal line to be more loaded. Big. Especially in large-size display panels, the number of shift register units is increasing, which leads to a further increase in the load of the clock signal line, which in turn leads to increased signal instability output by the shift register unit, and affects the display effect of the display panel. .
  • the embodiments of the present disclosure provide some display panels, especially in large-size display panels, which can reduce the number of shift register units electrically connected to each clock signal line, thereby reducing the load on the clock signal line, thereby increasing The stability of the signal output by the shift register unit improves the display effect of the display panel.
  • multiple shift register units can be divided into multiple register unit groups GOA-m (1 ⁇ m ⁇ M, and both m and M are integers. .M is the total number of register unit groups.
  • the two shift register units are located in different register unit groups. For example, at least one remaining scan line is arranged between every scan line electrically connected to two adjacent shift register units in each register unit group GOA-m. In other words, the shift register units in different register unit groups are arranged alternately.
  • multiple clock signal lines can be divided into multiple clock signal line groups GC-m, and different register unit groups correspond to different clock signals.
  • the line group that is, a register unit group GOA-m is electrically connected to a clock signal line group GC-m.
  • the gate of the input transistor M1 is electrically connected to a clock signal line in the corresponding clock signal line group
  • the first electrode of the input transistor M1 is electrically connected to the input signal terminal IP
  • the second electrode of the input transistor M1 is electrically connected to the stable
  • the first electrode of the voltage transistor M2 is electrically connected
  • the second electrode of the voltage stabilizing transistor M2 is electrically connected to the gate of the output transistor M3
  • the first electrode of the output transistor M3 is electrically connected to another clock signal line in the corresponding clock signal line group.
  • the second pole of the output transistor M3 is electrically connected to at least one scan line.
  • the shift register units are grouped, and one register unit group corresponds to a clock signal line group, so as to load the corresponding clock signal to the corresponding register unit group through the clock signal line group.
  • the number of shift register units electrically connected to a clock signal line can be reduced, thereby reducing the load of the clock signal line, thereby improving the stability of the output signal of the shift register unit, and improving the display effect of the display panel.
  • one shift register unit can be electrically connected to two clock signal lines.
  • the multiple shift register units in the gate driving circuit 01 can be divided into two register unit groups.
  • the multiple clock signal lines are divided into two clock signal line groups.
  • multiple shift register units in the gate drive circuit 01 can also be divided into 3, 4, 5, 6 or more register unit groups, and multiple clock signal lines can be divided into 3, Four, five, six or more clock signal line groups are not limited here.
  • the above two register unit groups may include a first register unit group GOA-1 and a second register unit group GOA-2.
  • the above two clock signal line groups include a first clock signal line group GC-1 and a second clock signal line group GC-2.
  • the first register unit group GOA-1 is electrically connected with the first clock signal line group GC-1
  • the second register unit group GOA-2 is electrically connected with the second clock signal line group GC-2.
  • the first register unit group GOA-1 may include an odd number of shift register units sequentially arranged along the extension direction F1 of the clock signal line.
  • the first clock signal line group GC-1 includes a first clock signal line GCK1 and a second clock signal line GCB1.
  • the shift register units in the first register unit group GOA-1 are configured in cascade.
  • the input signal terminal of the first-stage shift register unit is electrically connected to the first frame trigger signal terminal, and the upper-stage shift register in every two adjacent stages of shift register units
  • the output signal end of the unit is electrically connected to the input signal end of the next stage shift register unit.
  • the first register unit group GOA-1 may include shift register units SR2n-3, SR2n-1, SR2n+1, SR2n+3, and so on.
  • the output signal terminal of the shift register unit SR2n-3 is electrically connected to the input signal terminal of the shift register unit SR2n-1
  • the output signal terminal of the shift register unit SR2n-1 is connected to the input signal of the shift register unit SR2n+1.
  • the output signal terminal of the shift register unit SR2n+1 is electrically connected with the input signal terminal of the shift register unit SR2n+3.
  • the gates of the input transistors of the shift register units of the odd-numbered stages and the first poles of the output transistors of the shift register units of the even-numbered stages are Both are electrically connected to the first clock signal line GCK1.
  • the first pole of the output transistor of the shift register unit of the odd-numbered stage and the gate of the input transistor of the shift register unit of the even-numbered stage are both electrically connected to the second clock signal line GCB1.
  • the gate of the input transistor of the shift register unit of the odd-numbered stage is electrically connected to the first clock signal line through the corresponding first connection line, and the first pole of the output transistor of the shift register unit of the odd-numbered stage passes through the corresponding second
  • the connecting line is electrically connected to the first power line
  • the gate of the input transistor of the even-numbered stage shift register unit is electrically connected to the second clock signal line through the corresponding first connecting line, and the output of the even-numbered stage shift register unit
  • the first pole of the transistor is electrically connected to the first power line through the corresponding second connection line.
  • the second register unit group GOA-2 may include an even-numbered shift register unit sequentially arranged along the extending direction of the clock signal line.
  • the second clock signal line group GC-2 includes a third clock signal line GCK2 and a fourth clock signal line GCB2.
  • the shift register units in the second register unit group GOA-2 are configured in cascade.
  • the input signal terminal of the first-stage shift register unit is electrically connected to the second frame trigger signal terminal, and the upper-stage shift register in every two adjacent stages of shift register units
  • the output signal end of the unit is electrically connected to the input signal end of the next stage shift register unit.
  • the second register unit group GOA-2 may include shift register units SR2n-2, SR2n, SR2n+2, SR2n+4, and so on.
  • the output signal terminal of the shift register unit SR2n-2 is electrically connected with the input signal terminal of the shift register unit SR2n
  • the output signal terminal of the shift register unit SR2n is electrically connected with the input signal terminal of the shift register unit SR2n+2
  • the output signal terminal of the shift register unit SR2n+2 is electrically connected to the input signal terminal of the shift register unit SR2n+4.
  • the gates of the input transistors of the shift register cells of the odd-numbered stages and the first poles of the output transistors of the shift register cells of the even-numbered stages Both are electrically connected to the third clock signal line GCK2.
  • the first pole of the output transistor of the shift register unit of the odd-numbered stage and the gate of the input transistor of the shift register unit of the even-numbered stage are both electrically connected to the fourth clock signal line GCB2.
  • the gate of the input transistor of the shift register unit of the odd-numbered stage is electrically connected to the third clock signal line through the corresponding first connection line, and the first pole of the output transistor of the shift register unit of the odd-numbered stage passes through the corresponding second
  • the connecting line is electrically connected to the first power line
  • the gate of the input transistor of the even-numbered stage shift register unit is electrically connected to the fourth clock signal line through the corresponding first connecting line, and the output of the even-numbered stage shift register unit
  • the first pole of the transistor is electrically connected to the first power line through the corresponding second connection line.
  • FIG. 6 is a schematic diagram of the Layout structure of the gate driving circuit 01 provided by some embodiments of the present disclosure.
  • 7a to 7d are schematic diagrams of various layers of the gate driving circuit 01 provided by some embodiments of the disclosure.
  • FIG. 8a is a schematic cross-sectional view of the layout structure of the gate driving circuit 01 shown in FIG. 6 along the AA' direction.
  • FIG. 8b is a schematic cross-sectional view of the layout structure of the gate driving circuit 01 shown in FIG. 6 along the BB' direction. Among them, the examples shown in FIGS.
  • 6 to 7d are based on the shift register units SR2n-3, SR2n-1, SR2n+1, SR2n+3 included in the first register unit group GOA-1, and the second register unit group GOA-2
  • the included shift register units SR2n-2, SR2n, SR2n+2, SR2n+4 are taken as examples.
  • the semiconductor layer 500 of the gate driving circuit 01 is shown.
  • the semiconductor layer 500 may be formed by patterning a semiconductor material.
  • the semiconductor layer 500 can be used to fabricate the active layers of the above-mentioned multiple transistors, for example, to fabricate the active layers of the input transistors to the eighth transistors M1 to M8.
  • each active layer may include a source region, a drain region, and a channel region located between the source region and the drain region.
  • the rectangular dashed frame in FIG. 7a indicates the channel region of the above-mentioned transistor.
  • the active layer of the output transistor and the active layer of the second control transistor can be arranged in an integrated structure.
  • the semiconductor layer 500 is also used to fabricate the driving transistor T1, the data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, Active layers of the first reset transistor T6 and the second reset transistor T7.
  • the semiconductor layer 500 may be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the aforementioned source and drain regions may be conductive regions doped with n-type impurities or p-type impurities.
  • a gate insulating layer 640 is formed on the aforementioned semiconductor layer 500 for protecting the aforementioned semiconductor layer 500.
  • the first conductive layer 100 of the gate driving circuit 01 is shown.
  • the first conductive layer 100 is disposed on the side of the gate insulating layer 640 away from the base substrate 1000 so as to be insulated from the semiconductor layer 500.
  • the first conductive layer 100 may include a plurality of scan lines, the gates of the above-mentioned plurality of transistors, a plurality of first connection lines 110 and a plurality of second connection lines 120.
  • the gate M1-G of the input transistor M1, the gate M2-G of the voltage regulator transistor M2, the gate M3-G of the output transistor M3, the gate M4-G of the first control transistor M4, and the second control transistor M5 The gate M5-G of the sixth transistor M6, the gate M6-G of the sixth transistor M6, the gate M7-G of the seventh transistor M7, and the gate M8-G of the eighth transistor M8.
  • the first conductive layer 100 may also include: a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, The gates of the first reset transistor T6 and the second reset transistor T7.
  • the first conductive layer 100 may also include: emission control lines EM and the like. It should be noted that the overlapping portion of the orthographic projection of the first conductive layer 100 on the base substrate 1000 and the orthographic projection of the channel region in the semiconductor layer 500 on the base substrate 1000 is set as the gate of the above-mentioned transistor.
  • one shift register unit corresponds to at least one first connection line 110 and at least one second connection line 120.
  • one end of the first connection line 110 is directly electrically connected to the gate of the input transistor in the shift register unit, and the other end of the first connection line 110 It is electrically connected to a clock signal line in the clock signal line group through the first via H1.
  • One end of the second connection line is electrically connected to the first transfer part through the second via hole, and the other end of the second connection line is electrically connected to the other clock signal line or the first power line in the clock signal line group through the third via hole. connect.
  • the gate of the input transistor of the shift register unit of the odd-numbered stage is electrically connected to the first clock signal line GCK1 through the corresponding first connecting line 110, and the shift register of the even-numbered stage The gate of the input transistor of the unit is electrically connected to the second clock signal line GCB1 through the corresponding first connection line 110.
  • the gate of the input transistor of the odd-numbered stage shift register unit is electrically connected to the third clock signal line GCK2 through the corresponding first connecting line 110, and the even-numbered stage shift register The gate of the input transistor of the unit is electrically connected to the fourth clock signal line GCB2 through the corresponding first connection line 110.
  • the gate of the first control transistor in the shift register unit is directly electrically connected to the corresponding first connection line 110, so that the gate of the first control transistor and the gate of the input transistor can be realized.
  • the pole is set as a one-piece structure.
  • a first insulating layer 610 is formed on the above-mentioned first conductive layer 100 to protect the above-mentioned first conductive layer 100.
  • the fourth conductive layer 400 of the gate driving circuit 01 is shown.
  • the fourth conductive layer 400 is disposed on the side of the first insulating layer 610 away from the base substrate 1000.
  • the fourth conductive layer 400 may include a plurality of first conductive parts C01-1 and a plurality of second conductive parts C 02-1, and a plurality of third conductive parts 410.
  • a first conductive portion C01-1 and a second conductive portion C02-1 are provided in a shift register. That is, one first conductive portion C01-1 corresponds to one second control transistor M5, and one second conductive portion C02-1 corresponds to one output transistor M3.
  • the orthographic projection of the first conductive portion C01-1 on the base substrate and the orthographic projection of the gate M5-G of the second control transistor M5 on the base substrate have an overlapping area, thereby forming the first capacitor C01.
  • the first conductive portion C01-1 serves as the first pole C01-1 of the first capacitor C01
  • the gate M5-G of the second control transistor M5 serves as the second pole of the first capacitor C01.
  • the orthographic projection of the second conductive portion C02-1 on the base substrate and the orthographic projection of the gate M3-G of the output transistor M3 on the base substrate have an overlapping area, thereby forming the second capacitor C02.
  • the second conductive portion C02-1 serves as the first pole of the second capacitor C02.
  • the gate M3-G of the output transistor M3 serves as the second pole of the second capacitor C02.
  • two shift register units connected in cascade can be electrically connected through a third conductive portion 410.
  • the first pole of the output transistor in the shift register unit of the previous stage passes through the third conductive portion 410 and the first pole of the input transistor in the shift register unit of the next stage is connected. Electric connection.
  • the orthographic projection of the gate of the second control transistor on the base substrate may cover the orthographic projection of the first conductive portion on the base substrate.
  • the fourth conductive layer 400 may also include the first pole of the storage capacitor CST and the reset signal line in the above-mentioned pixel driving circuit.
  • a third insulating layer 630 is formed on the fourth conductive layer 400 described above for protecting the fourth conductive layer 400 described above.
  • the second conductive layer 200 of the gate driving circuit 01 is shown.
  • the second conductive layer 200 is disposed on the side of the third insulating layer 630 away from the base substrate 1000.
  • the second conductive layer 200 may include: a plurality of data lines VD, a first power line VGL, a second power line VGH, and a plurality of clock signal lines (such as the first clock signal line GCK1, the second clock signal line GCB1, and the third clock signal line).
  • Signal line GCK2 fourth clock signal line GCB2
  • a plurality of first switching parts 210 a plurality of second switching parts 220, a plurality of third switching parts 230, a plurality of fourth switching parts 240, and a plurality of The fifth transfer part 250.
  • one shift register is provided with a first switching part 210, a second switching part 220, a third switching part 230, a fourth switching part 240, and a fifth switching part 250.
  • a first transfer portion 210 is provided corresponding to an output transistor, and a first transfer portion 210 passes through a source region of an active layer of an output transistor.
  • the tenth via is electrically connected.
  • one end of the second connection line 120 is electrically connected to the first transfer portion 210 through the second via H2, and the other end of the second connection line 120 is electrically connected to the clock signal line through the third via H3.
  • a second transfer portion 220 is provided corresponding to a first control transistor, and the drain region of the active layer of the first control transistor passes through the corresponding second transfer portion 220. It is electrically connected to the gate of the second control transistor.
  • one third switching portion 230 corresponds to one second control transistor.
  • the source region of the active layer of the second control transistor is electrically connected to one end of the corresponding third transfer portion 230 through the sixth via hole H6, and the other end of the third transfer portion 230 is electrically connected to the corresponding end through the seventh via hole H7.
  • One end of the first conductive portion is electrically connected, the other end of the first conductive portion is electrically connected to the second power line through the eighth via H8, and the drain region of the active layer of the second control transistor is connected to the active layer of the output transistor.
  • the drain region is shared.
  • one fourth switching portion 240 corresponds to one sixth transistor M6.
  • One end of the fourth transfer portion 240 is electrically connected to the gate M1-G of the input transistor M1 through the eleventh via hole H11, and the other end of the fourth transfer portion 240 is connected to the sixth transistor M6 through the twelfth via hole H11.
  • the source region of the source layer is electrically connected.
  • one fifth switching part 250 corresponds to one voltage stabilizing transistor M2.
  • One end of the fifth transfer part 250 is electrically connected to the drain region of the active layer of the voltage stabilizing transistor M2 through the thirteenth via H13, and the other end of the fifth transfer part 250 is electrically connected to the output transistor through the fourteenth via H14
  • the gate of M3 is electrically connected.
  • the first pole of the output transistor of the shift register cell of the odd-numbered stage passes through
  • the corresponding second connection line 120 is electrically connected to the second clock signal line GCB1
  • the first electrode of the output transistor of the even-numbered stage shift register unit passes through the corresponding second connection
  • the line 120 is electrically connected to the first clock signal line GCK1.
  • the first pole of the output transistor (for example, the source region of the active layer of the output transistor) of the shift register cell of the odd-numbered stage passes through the corresponding second connecting line 120 and the fourth pole.
  • the clock signal line GCB2 is electrically connected, and the first pole of the output transistor of the even-numbered stage shift register unit is electrically connected to the third clock signal line GCK2 through the corresponding second connection line 120.
  • the gate of each voltage stabilizing transistor is electrically connected to the first power line through the fourth via H4. To input the corresponding voltage signal to the gate of the voltage stabilizing transistor.
  • the orthographic projection of the input transistor on the base substrate is located at the orthographic projection of the first power line on the base substrate and multiple The clock signal line is between the orthographic projections of the base substrate.
  • the orthographic projection of the voltage stabilizer transistor on the base substrate is located on the side of the orthographic projection of the first power line on the base substrate away from the plurality of clock signal lines on the base substrate.
  • the orthographic projection of the output transistor on the base substrate is located on the side of the orthographic projection of the voltage stabilizer transistor on the base substrate away from the first power line on the base substrate.
  • the source region of the active layer of the first control transistor is electrically connected to the first power line through the fifth via H5, so that the first control transistor The source region of the active layer can input a corresponding voltage signal.
  • the orthographic projection of the second power line on the base substrate is located between the orthographic projection of the multiple clock signal lines on the base substrate and the orthographic projection of the gate drive circuit 01 on the base substrate. between. Furthermore, in the shift register unit, the orthographic projection of the first control transistor on the base substrate is located between the orthographic projection of the input transistor on the base substrate and the orthographic projection of the first power line on the base substrate. And, in the shift register unit, the orthographic projection of the second control transistor on the base substrate is located on the side of the orthographic projection of the input transistor on the base substrate that is away from the orthographic projection of the first power line on the base substrate.
  • the orthographic projection of the gate of the second control transistor on the base substrate and the orthographic projection of the first conductive portion on the base substrate are respectively the same as the orthographic projection of the first power line on the base substrate.
  • the projection has overlapping areas.
  • the orthographic projection of the eighth via H8 on the base substrate is located between the orthographic projection of the first power line and the second power line on the base substrate, and the seventh via H7 is located at The orthographic projection of the base substrate is located between the orthographic projection of the first power line on the base substrate and the orthographic projection of the active layer of the second control transistor on the base substrate.
  • a gate insulating layer 640 is provided between the semiconductor layer 500 and the first conductive layer 100, a first insulating layer 610 is provided between the first conductive layer 100 and the fourth conductive layer 400, and the fourth A third insulating layer 630 is provided between the conductive layer 400 and the second conductive layer 200, and a second insulating layer 620 is provided between the second conductive layer 200 and the third conductive layer 300.
  • the above-mentioned via holes are arranged at intervals.
  • the first via H1, the second via H2, the third via H3, the fourth via H4, the eleventh via H11, and the fourteenth via H14 penetrate the first insulating layer and the third insulating layer.
  • the fifth via H5, the sixth via H6, the twelfth via, and the thirteenth via H13 penetrate the first insulating layer, the third insulating layer, and the gate insulating layer.
  • the seventh via H7 and the eighth via H8 penetrate the third insulating layer.
  • FIG. 9 The schematic structural diagrams of other display panels provided by the embodiments of the present disclosure are shown in FIG. 9, which are modified with respect to the implementation of the foregoing embodiments.
  • FIG. 9 Only the differences between this embodiment and the above-mentioned embodiment will be described, and the similarities will not be repeated here.
  • a second insulating layer 620 is formed on the second conductive layer 200 to protect the second conductive layer 200 described above.
  • the third conductive layer 300 of the gate driving circuit 01 is shown, and the third conductive layer 300 is disposed on the side of the second insulating layer 620 away from the base substrate 1000.
  • the third conductive layer 300 may include: at least one auxiliary line. Wherein, one auxiliary line and one clock signal line are electrically connected through at least one ninth via H9, and the ninth via H9 penetrates the second insulating layer 620.
  • the orthographic projection of the clock signal line on the base substrate may cover the orthographic projection of the auxiliary line of the electrical connection on the base substrate. Further, the orthographic projection of the clock signal line on the base substrate and the orthographic projection of the electrical connection auxiliary line on the base substrate may overlap. In this way, the occupied area of the auxiliary line can be reduced, so that the occupied area of the non-display area BB can be reduced.
  • the second conductive layer may include: a plurality of auxiliary lines; one auxiliary line and one clock signal line are electrically connected through a plurality of ninth via holes H9. This can reduce the resistance of each clock signal line.
  • the ninth via H9 of every two adjacent clock signal lines may be arranged in a staggered manner. In this way, the ninth via holes H9 can be dispersedly arranged to improve uniformity.
  • the orthographic projection of the ninth via H9 on the base substrate does not overlap with the orthographic projections of the first via H1 and the third via H3 on the base substrate. The accuracy of the electrical connection.
  • embodiments of the present disclosure also provide a driving method of a display panel, including:
  • each shift register unit is controlled to work sequentially to scan each drive line row by row; among them, the odd-numbered shift register unit and the even-numbered shift register unit are arranged in sequence along the extension direction of the clock signal line
  • the register unit is independently driven under the control of different clock signal line groups.
  • the odd-numbered shift register unit (that is, the first register unit group GOA-1) is between the first clock signal line GCK1 and the first clock signal line GCK1 and the The second clock signal line GCB1 operates under the control of the clock signal input to input signals to the electrically connected scan lines.
  • the even-numbered shift register unit (ie, the second register unit group GOA-2) operates under the control of the clock signal input from the third clock signal line GCK2 and the fourth clock signal line GCB2 to scan the electrical connection Line input signal.
  • each scan line can be scanned line by line.
  • FIG. 12 shows the signal gck1 transmitted by the first clock signal line GCK1, the signal gcb1 transmitted by the second clock signal line GCB1, the signal gck2 transmitted by the third clock signal line GCK2, and the signal gcb2 transmitted by the fourth clock signal line GCB2.
  • the embodiment of the present disclosure also provides a method for driving a display panel, which includes: the time for the signals applied to the multiple clock signal lines in different clock signal line groups to maintain an effective level does not overlap with each other. For example, as shown in FIG. 12, the effective level of the signal added on the clock signal line is low, and the low level of the signal added on each clock signal line does not overlap.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure.
  • the implementation of the display device can be referred to the embodiment of the above-mentioned display panel, and the repetition will not be repeated.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the present disclosure.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Shift Register Type Memory (AREA)
  • Control Of El Displays (AREA)

Abstract

一种显示面板、驱动方法及显示装置，其中，显示面板包括：衬底基板(1000)，多个子像素(spx)、多条驱动线、多条数据线和栅极驱动电路（01），包括：多条时钟信号线及沿时钟信号线的延伸方向（F1）依次排列的多个移位寄存器单元(SR2n-3、SR2n-2、SR2n-1、SR2n、SR2n+1、SR2n+2、SR2n+3、SR2n+4)；多条时钟信号线分为多个时钟信号线组；多个移位寄存器单元(SR2n-3、SR2n-2、SR2n-1、SR2n、SR2n+1、SR2n+2、SR2n+3、SR2n+4)分为多个寄存器单元组；同一寄存器单元组中的移位寄存器单元级联，沿时钟信号线的延伸方向(F1)相邻的两个移位寄存器单元(SR2n-3、SR2n-2、SR2n-1、SR2n、SR2n+1、SR2n+2、SR2n+3、SR2n+4)位于不同的寄存器单元组；一个寄存器单元组对应一个时钟信号线组；输入晶体管(M1)的栅极与对应的时钟信号线组中的一条时钟信号线电连接，输入晶体管(M1)的第二极与输出晶体管(M3)的栅极电连接；输出晶体管(M3)的第二极与至少一条驱动线对应电连接。

Description

显示面板、驱动方法及显示装置 技术领域
本公开涉及显示技术领域，特别涉及显示面板、驱动方法及显示装置。
背景技术
随着显示技术的飞速发展，显示装置呈现出了高集成度和低成本的发展趋势。其中，GOA(Gate Driver on Array，阵列基板行驱动)技术将TFT(Thin Film Transistor，薄膜晶体管)栅极驱动电路集成在显示面板的衬底基板上以形成对显示面板的扫描驱动，从而可以省去栅极集成电路(IC，Integrated Circuit)的绑定(Bonding)区域以及扇出(Fan-out)区域的布线空间，降低产品成本。
发明内容
本公开实施例提供的显示面板，包括：
衬底基板，包括显示区和非显示区；
其中，显示区包括：
多个子像素，沿多个行和多个列矩阵排布；
多条驱动线，一行所述子像素对应电连接至少一条所述驱动线；
多条数据线，一列所述子像素对应电连接至少一条所述数据线；
所述非显示区包括：
栅极驱动电路，包括：多条时钟信号线，以及沿所述时钟信号线的延伸方向依次排列的多个移位寄存器单元；其中，所述多条时钟信号线分为多个时钟信号线组；
其中，所述多个移位寄存器单元分为多个寄存器单元组；其中，同一所述寄存器单元组中的各所述移位寄存器单元级联设置，沿所述时钟信号线的延伸方向相邻的两个移位寄存器单元位于不同的寄存器单元组；且，不同的 所述寄存器单元组对应不同的所述时钟信号线组；
每一个所述移位寄存器单元包括输入晶体管与输出晶体管；其中，所述输入晶体管的栅极与对应的所述时钟信号线组中的一条时钟信号线电连接，所述输入晶体管的第一极与输入信号端电连接，所述输入晶体管的第二极与所述输出晶体管的栅极电连接；所述输出晶体管的第二极与至少一条驱动线对应电连接。
可选地，在本公开实施例中，所述显示面板还包括：
半导体层，位于所述衬底基板上，且所述半导体层包括所述输入晶体管的有源层以及所述输出晶体管的有源层；所述有源层包括源极区、漏极区以及位于所述源极区和所述漏极区之间的沟道区；
栅绝缘层，位于所述半导体层背离所述衬底基板一侧；
第一导电层，位于所述栅绝缘层背离所述衬底基板一侧，且所述第一导电层包括所述多条驱动线、多条第一连接线、多条第二连接线、所述输入晶体管的栅极以及所述输出晶体管的栅极；一个所述移位寄存器单元对应至少一条所述第一连接线和至少一条所述第二连接线；
第一绝缘层，位于所述第一导电层背离所述衬底基板一侧；
第二导电层，位于所述第一绝缘层背离所述衬底基板一侧，且所述第二导电层包括所述多条数据线、所述多条时钟信号线以及多个第一转接部；其中，一个所述第一转接部与一个所述输出晶体管的有源层的源极区电连接；所述第二导电层还包括：第一电源线；
针对一个所述移位寄存器单元以及与所述移位寄存器单元对应的所述时钟信号线组，所述第一连接线的一端直接与所述移位寄存器单元中的输入晶体管的栅极电连接，所述第一连接线的另一端与所述时钟信号线组中的一条时钟信号线通过第一过孔电连接，所述第二连接线的一端通过第二过孔与所述第一转接部电连接，所述第二连接线的另一端与所述时钟信号线组中的另一条时钟信号线或者第一电源线通过第三过孔电连接；
所述第一过孔、所述第二过孔和所述第三过孔贯穿所述第一绝缘层且间 隔设置。
可选地，在本公开实施例中，所述多条时钟信号线分为2个时钟信号线组，所述2个时钟信号线组包括第一时钟信号线组和第二时钟信号线组；其中，所述第一时钟信号线组包括第一时钟信号线和第二时钟信号线，所述第二时钟信号线组包括第三时钟信号线和第四时钟信号线；
所述多个移位寄存器单元分为2个寄存器单元组，所述2个寄存器单元组包括第一寄存器单元组和第二寄存器单元组，其中，所述第一个寄存器单元组包括沿所述时钟信号线的延伸方向依次排列的第奇数个移位寄存器单元，第二个寄存器单元组包括沿所述时钟信号线的延伸方向依次排列的第偶数个移位寄存器单元；
针对所述第一个寄存器单元组中级联的多个移位寄存器单元，第奇数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线与所述第一时钟信号线电连接，所述第奇数级移位寄存器单元的输出晶体管的第一极通过对应的第二连接线与所述第二时钟信号线或者第一电源线电连接；以及，第偶数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线与所述第二时钟信号线电连接，所述第偶数级移位寄存器单元的输出晶体管的第一极通过对应的第二连接线与所述第一时钟信号线或者第一电源线电连接；
针对所述第二个寄存器单元组中级联的多个移位寄存器单元，第奇数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线与所述第三时钟信号线电连接，所述第奇数级移位寄存器单元的输出晶体管的第一极通过对应的第二连接线与所述第四时钟信号线或者第一电源线电连接；以及，所述第偶数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线与所述第四时钟信号线电连接，所述第偶数级移位寄存器单元的输出晶体管的第一极通过对应的第二连接线与所述第三时钟信号线或者第一电源线电连接。
可选地，在本公开实施例中，每一个所述移位寄存器单元还包括稳压晶体管；其中，所述输入晶体管的第二极与所述稳压晶体管的第一极电连接，所述稳压晶体管的第二极与所述输出晶体管的栅极电连接；
所述第二导电层还包括：第一电源线；各所述稳压晶体管的栅极通过第四过孔与所述第一电源线电连接；其中，所述第四过孔贯穿所述第一绝缘层。
可选地，在本公开实施例中，同一所述栅极驱动电路中，所述输入晶体管在所述衬底基板的正投影位于所述第一电源线在所述衬底基板的正投影与所述多个时钟信号线在所述衬底基板的正投影之间；
所述稳压晶体管在所述衬底基板的正投影位于所述第一电源线在所述衬底基板的正投影背离所述多个时钟信号线在所述衬底基板的正投影一侧；
所述输出晶体管在所述衬底基板的正投影位于所述稳压晶体管在所述衬底基板的正投影背离所述第一电源线在所述衬底基板的正投影一侧。
可选地，在本公开实施例中，所述移位寄存器单元还包括第一控制晶体管与第二控制晶体管；
所述半导体层还包括所述第一控制晶体管的有源层、和所述第二控制晶体管的有源层；
所述第一导电层还包括：所述第一控制晶体管的栅极与所述第二控制晶体管的栅极；
所述第二导电层还包括：第二电源线、多个第二转接部、多个第三转接部；其中，一个所述第二转接部对应一个所述第一控制晶体管，一个所述第三转接部对应一个所述第二控制晶体管；
并且，所述显示面板还包括：
第四导电层，位于所述第一绝缘层与所述第二导电层之间，且所述第四导电层包括多个第一导电部；其中，一个所述第一导电部对应一个所述第二控制晶体管；
第三绝缘层，位于所述第四导电层与所述第二导电层之间；
其中，所述第一控制晶体管的栅极直接与对应的第一连接线电连接，所述第一控制晶体管的有源层的源极区通过第五过孔与所述第一电源线电连接，所述第一控制晶体管的有源层的漏极区通过对应的所述第二转接部与所述第二控制晶体管的栅极电连接；其中，所述第五过孔贯穿所述第一绝缘层和所 述第三绝缘层；
所述第二控制晶体管的有源层的源极区通过第六过孔与对应的所述第三转接部的一端电连接，所述第三转接部的另一端通过第七过孔与对应的所述第一导电部的一端电连接，所述第一导电部的另一端通过第八过孔与所述第二电源线电连接，所述第二控制晶体管的有源层的漏极区与所述输出晶体管的有源层的漏极区共用；其中，所述第六过孔贯穿所述第一绝缘层和所述第三绝缘层，所述第七过孔和所述第八过孔贯穿所述第三绝缘层。
可选地，在本公开实施例中，所述第二电源线在所述衬底基板的正投影位于所述多个时钟信号线在所述衬底基板的正投影与所述栅极驱动电路在所述衬底基板的正投影之间；
所述移位寄存器单元中，所述第一控制晶体管在所述衬底基板的正投影位于所述输入晶体管在所述衬底基板的正投影与所述第一电源线在所述衬底基板的正投影之间；
所述移位寄存器单元中，所述第二控制晶体管在所述衬底基板的正投影位于所述输入晶体管在所述衬底基板的正投影背离所述第一电源线在所述衬底基板的正投影一侧。
可选地，在本公开实施例中，所述移位寄存器单元中，所述输出晶体管的有源层与所述第二控制晶体管的有源层一体结构设置。
可选地，在本公开实施例中，所述移位寄存器单元还包括：第一电容和第二电容；其中，所述第一电容的第一极与所述第二电源线电连接，所述第一电容的第二极与所述第二控制晶体管的栅极电连接；所述第二电容的第一极与所述输出晶体管的第二极电连接，所述第二电容的第二极与所述输出晶体管的栅极电连接；
所述第四导电层还包括多个第二导电部；其中，一个所述第二导电部对应一个所述输出晶体管；
所述第一导电部在所述衬底基板的正投影与所述第二控制晶体管的栅极在所述衬底基板的正投影具有交叠区域，且所述第一导电部作为所述第一电 容的第一极，所述第二控制晶体管的栅极作为所述第一电容的第二极；
所述第二导电部在所述衬底基板的正投影与对应的所述输出晶体管的栅极在所述衬底基板的正投影具有交叠区域，且所述第二导电部作为所述第二电容的第一极，所述输出晶体管的栅极作为所述第二电容的第二极。
可选地，在本公开实施例中，所述第二控制晶体管的栅极在所述衬底基板的正投影覆盖所述第一导电部在所述衬底基板的正投影。
可选地，在本公开实施例中，所述第二控制晶体管的栅极在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影分别与所述第一电源线在所述衬底基板的正投影具有交叠区域。
可选地，在本公开实施例中，所述第八过孔在所述衬底基板的正投影位于所述第一电源线和所述第二电源线在所述衬底基板的正投影之间，所述第七过孔在所述衬底基板的正投影位于所述第一电源线在所述衬底基板的正投影与所述第二控制晶体管的有源层在所述衬底基板的正投影之间。
可选地，在本公开实施例中，所述显示面板还包括：
第二绝缘层，位于所述第二导电层背离所述衬底基板一侧；
第三导电层，位于所述第二绝缘层背离所述衬底基板一侧，且所述第二导电层包括：至少一条辅助线；
一条所述辅助线与一条所述时钟信号线通过至少一个第九过孔电连接，且所述第九过孔贯穿所述第二绝缘层。
可选地，在本公开实施例中，所述时钟信号线在所述衬底基板的正投影覆盖电连接的辅助线在所述衬底基板的正投影。
本公开实施例还提供了显示装置，包括上述显示面板。
本公开实施例还提供了上述显示面板的驱动方法，包括：
在一帧扫描时间内，控制各个所述移位寄存器单元顺序工作，以对各所述驱动线逐行扫描；其中，沿所述时钟信号线的延伸方向依次排列的第奇数个移位寄存器单元和第偶数个移位寄存器单元在不同的时钟信号线组控制下独立驱动。
本公开实施例还提供了上述显示面板的驱动方法，包括：不同的时钟信号线组中多个时钟信号线上所加的信号保持有效电平的时间互不重叠。
附图说明
图1为本公开实施例提供的一些显示面板的结构示意图；
图2为本公开实施例提供的一些子像素中的像素驱动电路的结构示意图；
图3为本公开实施例提供的一些像素驱动电路的信号时序图；
图4a为本公开实施例提供的一些移位寄存器单元的结构示意图；
图4b为本公开实施例提供的一些移位寄存器单元的信号时序图；
图4c为本公开实施例提供的一些栅极驱动电路输出的信号时序图；
图5a为本公开实施例提供的另一些移位寄存器单元的结构示意图；
图5b为本公开实施例提供的另一些移位寄存器单元的信号时序图；
图6为本公开实施例提供的一些栅极驱动电路的布局结构示意图；
图7a为本公开实施例提供的一些半导体层的布局结构示意图；
图7b为本公开实施例提供的一些栅导电层的布局结构示意图；
图7c为本公开实施例提供的一些第四导电层的布局结构示意图；
图7d为本公开实施例提供的一些第二导电层的布局结构示意图；
图8a为图6所示的布局结构示意图中沿AA’方向上的剖视结构示意图；
图8b为图6所示的布局结构示意图中沿BB’方向上的剖视结构示意图；
图9为本公开实施例提供的又一些栅极驱动电路的布局结构示意图；
图10为本公开实施例提供的一些第三导电层的布局结构示意图；
图11为图9所示的布局结构示意图中沿AA’方向上的剖视结构示意图；
图12为本发明实施例提供的又一些移位寄存器单元的信号时序图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然， 所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
如图1所示，本公开实施例提供的显示面板，可以包括：衬底基板1000。其中，衬底基板1000可以包括显示区AA和非显示区BB。非显示区BB可以包围显示区。显示区AA可以包括多个像素单元PX，像素单元PX可以包括多个子像素spx。多个子像素spx沿多个行和多个列矩阵排布。
示例性地，结合图1与图2所示，多个子像素spx中的至少一个子像素spx可以包括：像素驱动电路0121和发光器件0120。其中，像素驱动电路0121具有晶体管和电容，并通过晶体管和电容的相互作用产生电信号，产生的电信号输入到发光器件0120的第一电极中。并且对发光器件0120的第二电极加载相应的电压，可以驱动发光器件0120发光。
结合图2所示，像素驱动电路0121可以包括：驱动控制电路0122、第一发光控制电路0123、第二发光控制电路0124、数据写入电路0126、存储电路0127、阈值补偿电路0128和复位电路0129。
驱动控制电路0122可以包括控制端、第一极和第二极。且驱动控制电路 0122被配置为发光器件0120提供驱动发光器件0120发光的驱动电流。例如，第一发光控制电路0123与驱动控制电路0122的第一极和第一电压端VDD连接。且第一发光控制电路0123被配置为实现驱动控制电路0122和第一电压端VDD之间的连接导通或断开。
第二发光控制电路0124与驱动控制电路0122的第二极和发光器件0120的第一电极电连接。且第二发光控制电路0124被配置为实现驱动控制电路0122和发光器件0120之间的连接导通或断开。
数据写入电路0126与驱动控制电路0122的第一极电连接。且第二发光控制电路0124被配置为在扫描线GA2上的信号的控制下将数据线VD上的信号写入存储电路0127。
存储电路0127与驱动控制电路0122的控制端和第一电压端VDD电连接。且存储电路0127被配置为存储数据信号。
阈值补偿电路0128与驱动控制电路0122的控制端和第二极电连接。且阈值补偿电路0128被配置为对驱动控制电路0122进行阈值补偿。
复位电路0129与驱动控制电路0122的控制端和发光器件0120的第一电极电连接。且复位电路0129被配置为在扫描线GA1上的信号的控制下对驱动控制电路0122的控制端和发光器件0120的第一电极进行复位。
其中，发光器件0120可以设置为电致发光二极管，例如OLED和QLED中的至少一种。其中，光器件0120可以包括层叠设置的第一电极、发光功能层、第二电极。示例性地，第一电极可以为阳极、第二电极可以为阴极。发光功能层可以包括发光层。进一步地，发光功能层还可以包括空穴注入层、空穴传输层、发光层、电子传输层、电子注入层等膜层。当然，在实际应用中，发光器件0120可以根据实际应用环境的需求进行设计确定，在此不作限定。
示例性地，结合图2所示，驱动控制电路0122包括：驱动晶体管T1，驱动控制电路0122的控制端包括驱动晶体管T1的栅极，驱动控制电路0122的第一极包括驱动晶体管T1的第一极，驱动控制电路0122的第二极包括驱动 晶体管T1的第二极。
示例性地，结合图2所示，数据写入电路0126包括数据写入晶体管T2。存储电路0127包括存储电容CST。阈值补偿电路0128包括阈值补偿晶体管T3。第一发光控制电路0123包括第一发光控制晶体管T4。第二发光控制电路0124包括第二发光控制晶体管T5。复位电路0129包括第一复位晶体管T6和第二复位晶体管T7。
具体地，数据写入晶体管T2的第一极与驱动晶体管T1的第一极电连接，数据写入晶体管T2的第二极被配置为与数据线VD电连接以接收数据信号，数据写入晶体管T2的栅极被配置为与第二扫描线GA2电连接以接收扫描信号。
存储电容CST的第一极与第一电源端VDD电连接，存储电容CST的第二极与驱动晶体管T1的栅极电连接。
阈值补偿晶体管T3的第一极与驱动晶体管T1的第二极电连接，阈值补偿晶体管T3的第二极与驱动晶体管T1的栅极电连接，阈值补偿晶体管T3的栅极被配置为与第二扫描线GA2电连接以接收信号。
第一复位晶体管T6的第一极被配置为与复位信号线VINIT电连接以接收复位信号，第一复位晶体管T6的第二极与驱动晶体管T1的栅极电连接，第一复位晶体管T6的栅极被配置为与第一扫描线GA1电连接以接收信号。
第二复位晶体管T7的第一极被配置为与复位信号线VINIT电连接以接收复位信号，第二复位晶体管T7的第二极与发光器件0120的第一电极电连接，第二复位晶体管T7的栅极被配置为与第一扫描线GA1电连接以接收信号。
第一发光控制晶体管T4的第一极与第一电源端VDD电连接，第一发光控制晶体管T4的第二极与驱动晶体管T1的第一极电连接，第一发光控制晶体管T4的栅极被配置为与发光控制线EM电连接以接收发光控制信号。
第二发光控制晶体管T5的第一极与驱动晶体管T1的第二极电连接，第二发光控制晶体管T5的第二极与发光器件0120的第一电极电连接，第二发光控制晶体管T5的栅极被配置为与发光控制线EM电连接以接收发光控制信 号。
发光器件0120的第二电极与第二电源端VSS电连接。其中，上述晶体管的第一极和第二极可以根据实际应用确定为源极或漏极，在此不作限定。
示例性地，第一电源端VDD和第二电源端VSS之一为高压端，另一个为低压端。例如，如图2所示的实施例中，第一电源端VDD为电压源以输出恒定的第一电压，第一电压为正电压；而第二电源端VSS可以为电压源以输出恒定的第二电压，第二电压为负电压等。例如，在一些示例中，第二电源端VSS可以接地。
图2所示的像素驱动电路对应的信号时序图，如图3所示。一帧显示时间中，像素驱动电路的工作过程具有三个阶段：T10阶段、T20阶段、T30阶段。其中，ga1代表第一扫描线GA1上传输的信号，ga2代表第二扫描线GA2上传输的信号，em代表发光控制线EM上传输的信号。
在T10阶段，信号ga1控制第一复位晶体管T6和第二复位晶体管T7导通。导通的第一复位晶体管T6将复位信号线VINIT上传输的信号提供给驱动晶体管T1的栅极，以对驱动晶体管T1的栅极进行复位。导通的第二复位晶体管T7将复位信号线VINIT上传输的信号提供给发光器件0120的第一电极，以对发光器件0120的第一电极进行复位。并且，此阶段中，信号ga2控制数据写入晶体管T2、阈值补偿晶体管T3均截止。信号em控制第一发光控制晶体管T4和第二发光控制晶体管T5均截止。
在T20阶段，信号ga2控制数据写入晶体管T2、阈值补偿晶体管T3均导通，从而可以使数据线VD上传输的数据信号对驱动晶体管T1的栅极进行充电，以使驱动晶体管T1的栅极的电压变为：Vdata+|Vth|。其中，Vth代表驱动晶体管T1的阈值电压，Vdata代表数据信号的电压。并且，此阶段中，信号ga1控制第一复位晶体管T6和第二复位晶体管T7均截止。信号em控制第一发光控制晶体管T4和第二发光控制晶体管T5均截止。
在T30阶段，信号em控制第一发光控制晶体管T4和第二发光控制晶体管T5均导通。导通的第一发光控制晶体管T4将第一电源端VDD的电压Vdd 提供给驱动晶体管T1的第一极，以使驱动晶体管T1的第一极的电压为Vdd。驱动晶体管T1根据其栅极电压Vdata+|Vth|，以及第一极的电压Vdd，产生驱动电流。该驱动电流通过导通的第二发光控制晶体管T5提供给发光器件0120，驱动发光器件0120发光。并且，此阶段中，信号ga1控制第一复位晶体管T6和第二复位晶体管T7均截止。信号ga2控制数据写入晶体管T2、阈值补偿晶体管T3均截止。
需要说明的是，在本公开实施例中，子像素中的像素驱动电路除了可以为图2所示的结构之外，还可以为包括其他数量的晶体管的结构，本公开实施例对此不作限定。
在具体实施时，在本公开实施例中，如图1所示，显示区可以包括多条驱动线和多条数据线；其中，一行子像素对应电连接至少一条所述驱动线，一列子像素对应电连接至少一条数据线。示例性地，驱动线包括多条扫描线和多条发光控制线中的至少一种。其中，一行子像素对应电连接至少一条扫描线和至少一条发光控制线，示例性地，若像素驱动电路设置为图2所示的结构时，可以使一列子像素对应电连接一条数据线或者可以使一列子像素中位于不同行的子像素分别对应电连接两条数据线。一行子像素对应一条发光控制线。多条扫描线可以包括多条第一扫描线和多条第二扫描线，一行子像素对应电连接两条扫描线，即一行子像素对应电连接一条第一扫描线和一条第二扫描线。并且，每相邻两行中，第一行对应电连接的第二扫描线和第二行对应电连接的第一扫描线电连接，以传输相同的信号。
为了使第一扫描线和第二扫描线上可以传输信号，在具体实施时，在本公开实施例中，如图1与图6所示，非显示区BB可以包括：栅极驱动电路01以及多条时钟信号线。其中，时钟信号线的延伸方向与扫描线的延伸方向不同，例如，时钟信号线的延伸方向与扫描线的延伸方向交叉。该多条时钟信号线间隔设置于栅极驱动电路01背离扫描线的一侧。示例性地，栅极驱动电路01可以包括：沿时钟信号线的延伸方向F1依次排列的多个移位寄存器单元：SR2n-3、SR2n-2、SR2n-1、SR2n、SR2n+1、SR2n+2、SR2n+3、SR2n+4 (n为大于0的整数)。示例性地，可以使一个移位寄存器单元的输出信号端OP对应电连接至少一条驱动线。示例性地，可以使一个移位寄存器单元的输出信号端OP对应电连接至少一条扫描线。也可以使一个移位寄存器单元的输出信号端OP对应电连接至少一条发光控制线。
并且，沿时钟信号线的延伸方向F1依次排列的多个移位寄存器单元SR2n-3、SR2n-2、SR2n-1、SR2n、SR2n+1、SR2n+2、SR2n+3、SR2n+4的输出信号端OP，可以输出图4c所示的信号。其中，op2n-3为移位寄存器单元SR2n-3的输出信号端OP输出的信号，op2n-2为移位寄存器单元SR2n-2的输出信号端OP输出的信号，op2n-1为移位寄存器单元SR2n-1的输出信号端OP输出的信号，op2n为移位寄存器单元SR2n的输出信号端OP输出的信号，op2n+1为移位寄存器单元SR2n+1的输出信号端OP输出的信号，op2n+2为移位寄存器单元SR2n+2的输出信号端OP输出的信号，op2n+3为移位寄存器单元SR2n+3的输出信号端OP输出的信号，op2n+4为移位寄存器单元SR2n+4的输出信号端OP输出的信号。
在具体实施时，在本公开实施例中，如图4a所示，移位寄存器单元可以包括：多个晶体管；多个晶体管可以包括：输入晶体管M1、稳压晶体管M2、输出晶体管M3、第一控制晶体管M4、第二控制晶体管M5、第六晶体管M6、第七晶体管M7、第八晶体管M8、第一电容C01以及第二电容C02。其中，输入晶体管M1的栅极与第一时钟信号端CK电连接，输入晶体管M1的第一极与输入信号端IP电连接，输入晶体管M1的第二极与稳压晶体管M2的第一极电连接。稳压晶体管M2的栅极与第一电源线VGL电连接，稳压晶体管M2的第二极与输出晶体管M3的栅极电连接，输出晶体管M3的第一极与第二时钟信号端CB电连接，输出晶体管M3的第二极与输出信号端OP电连接，即输出晶体管的第二极与至少一条扫描线对应电连接。
第一控制晶体管M4的栅极与输入晶体管M1的栅极电连接，第一控制晶体管M4的第一极与第一电源线VGL电连接，第一控制晶体管M4的第二极与第二控制晶体管M5的栅极电连接。第二控制晶体管M5的第一极与第二电 源线VGH电连接，第二控制晶体管M5的第二极与输出晶体管的第二极电连接。
第六晶体管M6的栅极与输入晶体管M1的第二极电连接，第六晶体管M6的第一极与第一时钟信号端CK电连接，第六晶体管M6的第二极与第一控制晶体管M4的第二极电连接。
第七晶体管M7的栅极与第二时钟信号端CB电连接，第七晶体管M7的第一极与输入晶体管M1的栅极电连接，第七晶体管M7的第二极与第八晶体管M8的第一极电连接。
第八晶体管M8的栅极与第一控制晶体管M4的第二极电连接，第八晶体管M8的第二极与第二电源线VGH电连接。
第一电容C01的第一极与第二电源线VGH电连接，第一电容C01的第二极与第二控制晶体管M5的栅极电连接；第二电容C02的第一极与输出晶体管的第二极电连接，第二电容C01的第二极与输出晶体管M3的栅极电连接。
图4a所示的移位寄存器对应的信号时序图，如图4b所示。其中，ck代表输入晶体管M1的栅极输入的时钟信号，cb代表输出晶体管M3的第一极输入的时钟信号，ip代表输入信号端IP的信号，op代表输出信号端OP的信号。通过时钟信号ck、cb，输入信号端IP的信号ip、各个晶体管以及第一电容C01和第二电容C02的相互配合，可以使输出晶体管M3输出信号op。需要说明的是，图4a所示的移位寄存器对应的信号时序图，除了可以为图4b所示的信号时序图之外，还可以为其他形式的信号时序图，这可以根据实际应用的需求进行设计确定，本公开实施例对此不作限定。
示例性地，在本公开实施例中，上述栅极驱动电路01中的每个移位寄存器单元的具体结构可以与本公开图4a所示的移位寄存器单元在功能和结构上均相同。这样可以使栅极驱动电路01为第一扫描线GA1和第二扫描线GA2输入信号，从而可以控制第一复位晶体管T6、第二复位晶体管T7、数据写入晶体管T2以及阈值补偿晶体管T3的导通和截止。
在具体实施时，在本公开实施例中，如图5a所示，移位寄存器单元可以包括：多个晶体管；多个晶体管可以包括：输入晶体管M1、输出晶体管M3、第九晶体管M09、第十晶体管M010、第十一晶体管M011、第十二晶体管M012、第十三晶体管M013、第十四晶体管M014、第十五晶体管M015、第十六晶体管M016、第三电容C03、第四电容C04以及第五电容C05。
其中，输入晶体管M1的栅极与第一时钟信号端CK电连接，输入晶体管M1的第一极与输入信号端IP电连接，输入晶体管M1的第二极与输出晶体管M3的栅极电连接，输出晶体管M3的第一极与第一电源线VGL电连接，输出晶体管M3的第二极与输出信号端OP电连接，即输出晶体管的第二极与至少一条发光控制线对应电连接。
第九晶体管M09的栅极与输入晶体管M1的栅极电连接，第九晶体管M09的第一极与第一电源线VGL电连接，第九晶体管M09的第二极与第十四晶体管M014的栅极电连接。
第十四晶体管M014的第一极与第二时钟信号端CB电连接，第十四晶体管M014的第二极与第十六晶体管M016的第一极电连接。
第十六晶体管M016的第二极与第十晶体管M010的栅极电连接，第十六晶体管M016的栅极与第二时钟信号端CB电连接。
第十晶体管M010的第一极与第二电源线VGH电连接，第十晶体管M010的第二极与输出晶体管M3的第二极电连接。
第十一晶体管M011的栅极与输入晶体管M1的第二极电连接，第十一晶体管M011的第一极与第一时钟信号端CK电连接，第十一晶体管M011的第二极与第九晶体管M09的第二极电连接。
第十二晶体管M012的栅极与第二时钟信号端CB电连接，第十二晶体管M012的第一极与输入晶体管M1的栅极电连接，第十二晶体管M012的第二极与第十三晶体管M013的第一极电连接。
第十三晶体管M013的栅极与第九晶体管M09的第二极电连接，第十三晶体管M013的第二极与第二电源线VGH电连接。
第五电容C05的第一极与第二电源线VGH电连接，第五电容C05的第二极与第十晶体管M010的栅极电连接；第三电容C03的第一极与第二时钟信号端CB电连接，第三电容C03的第二极与输出晶体管M3的栅极电连接。第四电容C04的第一极与第十四晶体管M014的栅极电连接，第四电容C04的第二极与第十四晶体管M014的第二极电连接。
图5a所示的移位寄存器对应的信号时序图，如图5b所示。其中，ck代表输入晶体管M1的栅极输入的时钟信号，cb代表第十二晶体管M012的栅极输入的时钟信号，ip代表输入信号端IP的信号，op代表输出信号端OP的信号。通过时钟信号ck、cb，输入信号端IP的信号ip、各个晶体管以及第一电容C01和第二电容C02的相互配合，可以使输出晶体管M3输出信号op。需要说明的是，图5a所示的移位寄存器对应的信号时序图，除了可以为图5b所示的信号时序图之外，还可以为其他形式的信号时序图，这可以根据实际应用的需求进行设计确定，本公开实施例对此不作限定。
示例性地，在本公开实施例中，上述栅极驱动电路01中的每个移位寄存器单元的具体结构可以与本公开图5a所示的移位寄存器单元在功能和结构上均相同。这样可以使栅极驱动电路01为发光控制线输入信号，从而可以控制第一发光控制晶体管T4、第二发光控制晶体管T5的导通和截止。
当然，在实际应用中，移位寄存器单元除了可以为图4a和图5a所示的结构之外，还可以为包括其他数量的晶体管的结构，本公开实施例对此不作限定。下面以图4a所示的移位寄存器单元的结构为例进行说明。
为了对每个移位寄存器单元输入相应的时钟信号，一般仅采用两条时钟信号线对栅极驱动电路01中的每个移位寄存器单元输入相应的时钟信号，这样导致时钟信号线的负载较大。尤其是大尺寸显示面板中，移位寄存器单元的数量越来越多，从而导致时钟信号线的负载进一步增大，进而导致移位寄存器单元输出的信号不稳定性增加，影响显示面板的显示效果。因此，本公开实施例提供了一些显示面板，尤其是在大尺寸显示面板中，可以降低每一条时钟信号线上电连接的移位寄存器单元的数量，从而可以降低时钟信号线 的负载，进而提高移位寄存器单元输出的信号稳定性，提高显示面板的显示效果。
在具体实施时，在本公开实施例中，如图6所示，可以将多个移位寄存器单元分为多个寄存器单元组GOA-m(1≤m≤M，且m和M均为整数。M为寄存器单元组的总数。图6以M＝2为例)；其中，同一寄存器单元组GOA-m中的各移位寄存器单元级联设置，且沿时钟信号线的延伸方向相邻的两个移位寄存器单元位于不同的寄存器单元组。例如，每个寄存器单元组GOA-m中的每相邻两个移位寄存器单元电连接的扫描线之间设置有至少一条其余扫描线。也就是说，不同寄存器单元组中的移位寄存器单元交替排列。
并且，在具体实施时，在本公开实施例中，如图6所示，可以将多条时钟信号线分为多个时钟信号线组GC-m，且不同的寄存器单元组对应不同的时钟信号线组，即一个寄存器单元组GOA-m对应电连接一个时钟信号线组GC-m。示例性地，输入晶体管M1的栅极与对应的时钟信号线组中的一条时钟信号线电连接，输入晶体管M1的第一极与输入信号端IP电连接，输入晶体管M1的第二极与稳压晶体管M2的第一极电连接；稳压晶体管M2的第二极与输出晶体管M3的栅极电连接；输出晶体管M3的第一极与对应的时钟信号线组中的另一条时钟信号线电连接，输出晶体管M3的第二极与至少一条扫描线对应电连接。
本公开实施例，通过将移位寄存器单元进行分组，并使一个寄存器单元组对应一个时钟信号线组，以通过时钟信号线组向对应的寄存器单元组加载相应的时钟信号。这样可以降低一条时钟信号线上电连接的移位寄存器单元的数量，从而可以降低时钟信号线的负载，进而提高移位寄存器单元输出的信号稳定性，提高显示面板的显示效果。
在具体实施时，在移位寄存器单元的结构如图4a所示时，一个移位寄存器单元可以电连接两条时钟信号线。在本公开实施例中，如图6所示，可以将栅极驱动电路01中的多个移位寄存器单元分为2个寄存器单元组。将多条时钟信号线分为2个时钟信号线组。当然，也可以将栅极驱动电路01中的多 个移位寄存器单元分为3个、4个、5个、6个或更多个寄存器单元组，将多条时钟信号线分为3个、4个、5个、6个或更多个时钟信号线组，在此不作限定。
示例性地，M＝2时，如图6所示，上述2个寄存器单元组可以包括第一寄存器单元组GOA-1和第二寄存器单元组GOA-2。上述2个时钟信号线组包括第一时钟信号线组GC-1和第二时钟信号线组GC-2。其中，第一寄存器单元组GOA-1与第一时钟信号线组GC-1电连接，第二寄存器单元组GOA-2与第二时钟信号线组GC-2电连接。
示例性地，M＝2时，如图6所示，第一寄存器单元组GOA-1可以包括沿时钟信号线的延伸方向F1依次排列的第奇数个移位寄存器单元。第一时钟信号线组GC-1包括第一时钟信号线GCK1和第二时钟信号线GCB1。第一寄存器单元组GOA-1中的移位寄存器单元进行级联设置。例如，第一寄存器单元组GOA-1中，第一级移位寄存器单元的输入信号端与第一帧触发信号端电连接，每相邻两级移位寄存器单元中的上一级移位寄存器单元的输出信号端与下一级移位寄存器单元的输入信号端电连接。例如，第一寄存器单元组GOA-1可以包括移位寄存器单元SR2n-3、SR2n-1、SR2n+1、SR2n+3等。其中，移位寄存器单元SR2n-3的输出信号端与移位寄存器单元SR2n-1的输入信号端电连接，移位寄存器单元SR2n-1的输出信号端与移位寄存器单元SR2n+1的输入信号端电连接，移位寄存器单元SR2n+1的输出信号端与移位寄存器单元SR2n+3的输入信号端电连接。
并且，针对第一寄存器单元组GOA-1中级联的多个移位寄存器单元，第奇数级移位寄存器单元的输入晶体管的栅极与第偶数级移位寄存器单元的输出晶体管的第一极均与第一时钟信号线GCK1电连接。以及，第奇数级移位寄存器单元的输出晶体管的第一极与第偶数级移位寄存器单元的输入晶体管的栅极均与第二时钟信号线GCB1电连接。或者，第奇数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线与第一时钟信号线电连接，第奇数级移位寄存器单元的输出晶体管的第一极通过对应的第二连接线与第一电 源线电连接；以及，第偶数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线与第二时钟信号线电连接，第偶数级移位寄存器单元的输出晶体管的第一极通过对应的第二连接线与第一电源线电连接。
示例性地，M＝2时，如图6所示，第二寄存器单元组GOA-2可以包括沿时钟信号线的延伸方向依次排列的第偶数个移位寄存器单元。第二时钟信号线组GC-2包括第三时钟信号线GCK2和第四时钟信号线GCB2。第二寄存器单元组GOA-2中的移位寄存器单元进行级联设置。例如，第二寄存器单元组GOA-2中，第一级移位寄存器单元的输入信号端与第二帧触发信号端电连接，每相邻两级移位寄存器单元中的上一级移位寄存器单元的输出信号端与下一级移位寄存器单元的输入信号端电连接。例如，第二寄存器单元组GOA-2可以包括移位寄存器单元SR2n-2、SR2n、SR2n+2、SR2n+4等。其中，移位寄存器单元SR2n-2的输出信号端与移位寄存器单元SR2n的输入信号端电连接，移位寄存器单元SR2n的输出信号端与移位寄存器单元SR2n+2的输入信号端电连接，移位寄存器单元SR2n+2的输出信号端与移位寄存器单元SR2n+4的输入信号端电连接。
并且，针对第二寄存器单元组GOA-2中级联的多个移位寄存器单元，第奇数级移位寄存器单元的输入晶体管的栅极与第偶数级移位寄存器单元的输出晶体管的第一极均与第三时钟信号线GCK2电连接。以及，第奇数级移位寄存器单元的输出晶体管的第一极与第偶数级移位寄存器单元的输入晶体管的栅极均与第四时钟信号线GCB2电连接。或者，第奇数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线与第三时钟信号线电连接，第奇数级移位寄存器单元的输出晶体管的第一极通过对应的第二连接线与第一电源线电连接；以及，第偶数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线与第四时钟信号线电连接，第偶数级移位寄存器单元的输出晶体管的第一极通过对应的第二连接线与第一电源线电连接。
图6为本公开一些实施例提供的栅极驱动电路01的布局(Layout)结构示意图。图7a至图7d为本公开一些实施例提供的栅极驱动电路01的各层的 示意图。图8a为图6所示的栅极驱动电路01的布局结构示意图沿AA’方向上的剖视结构示意图。图8b为图6所示的栅极驱动电路01的布局结构示意图沿BB’方向上的剖视结构示意图。其中，图6至图7d所示的示例以第一寄存器单元组GOA-1包括的移位寄存器单元SR2n-3、SR2n-1、SR2n+1、SR2n+3，第二寄存器单元组GOA-2包括的移位寄存器单元SR2n-2、SR2n、SR2n+2、SR2n+4为例。
示例性地，如图6、图7a以及图8a、图8b所示，示出了该栅极驱动电路01的半导体层500。半导体层500可采用半导体材料图案化形成。半导体层500可用于制作上述多个晶体管的有源层，例如制备输入晶体管至第八晶体管M1～M8的有源层。其中，各有源层可包括源极区、漏极区以及位于源极区和漏极区之间的沟道区。例如，输入晶体管M1的沟道区M1-A，稳压晶体管M2的沟道区M2-A，输出晶体管M3的沟道区M3-A，第一控制晶体管M4的沟道区M4-A，第二控制晶体管M5的沟道区M5-A，第六晶体管M6的沟道区M6-A，第七晶体管M7的沟道区M7-A，第八晶体管M8的沟道区M8-A。图7a中的矩形虚线框标示出了上述晶体管的沟道区。
在一些实施例中，如图6与图7a所示，可以使同一移位寄存器单元中，输出晶体管的有源层与第二控制晶体管的有源层一体结构设置。
并且，需要说明的是，半导体层500还用于制作上述的像素驱动电路中的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的有源层。
并且，示例性地，半导体层500可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区和漏极区可为掺杂有n型杂质或p型杂质而形成的导体化的区域。
示例性地，如图8a、图8b所示，在上述的半导体层500上形成有栅绝缘层640，用于保护上述的半导体层500。如图6、图7b以及图8a、图8b所示，示出了该栅极驱动电路01的第一导电层100。第一导电层100设置在栅绝缘 层640背离衬底基板1000一侧，从而与半导体层500绝缘。第一导电层100可以包括：多条扫描线、上述多个晶体管的栅极、多条第一连接线110以及多条第二连接线120。例如，输入晶体管M1的栅极M1-G，稳压晶体管M2的栅极M2-G，输出晶体管M3的栅极M3-G，第一控制晶体管M4的栅极M4-G，第二控制晶体管M5的栅极M5-G，第六晶体管M6的栅极M6-G，第七晶体管M7的栅极M7-G，第八晶体管M8的栅极M8-G。并且，需要说明的是，第一导电层100还可以包括：像素驱动电路中的驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7的栅极。以及第一导电层100还可以包括：发光控制线EM等。需要说明的是，第一导电层100在衬底基板1000的正投影与半导体层500中的沟道区在衬底基板1000的正投影交叠的部分设置为上述晶体管的栅极。
在一些实施例中，一个移位寄存器单元对应至少一条第一连接线110和至少一条第二连接线120。针对一个移位寄存器单元以及与移位寄存器单元对应的时钟信号线组，第一连接线110的一端直接与移位寄存器单元中的输入晶体管的栅极电连接，第一连接线110的另一端与时钟信号线组中的一条时钟信号线通过第一过孔H1电连接。第二连接线的一端通过第二过孔与第一转接部电连接，第二连接线的另一端与时钟信号线组中的另一条时钟信号线或者第一电源线通过第三过孔电连接。例如，第一寄存器单元组GOA-1中，第奇数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线110与第一时钟信号线GCK1电连接，且第偶数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线110与第二时钟信号线GCB1电连接。以及，第二寄存器单元组GOA-2中，第奇数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线110与第三时钟信号线GCK2电连接，且第偶数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线110与第四时钟信号线GCB2电连接。
并且，针对一个移位寄存器单元，该移位寄存器单元中的第一控制晶体 管的栅极直接与对应的第一连接线110电连接，从而可以实现第一控制晶体管的栅极与输入晶体管的栅极设置为一体结构。
示例性地，如图8a、图8b所示，在上述的第一导电层100上形成有第一绝缘层610，用于保护上述的第一导电层100。如图6、图7c以及图8a、图8b所示，示出了该栅极驱动电路01的第四导电层400。第四导电层400设置在第一绝缘层610背离衬底基板1000一侧。第四导电层400可以包括：多个第一导电部C01-1和多个第二导电部C02-1，多个第三导电部410。其中，一个移位寄存器中设置一个第一导电部C01-1和一个第二导电部C02-1。即一个第一导电部C01-1对应一个第二控制晶体管M5，一个第二导电部C02-1对应一个输出晶体管M3。
示例性地，第一导电部C01-1在衬底基板的正投影与第二控制晶体管M5的栅极M5-G在衬底基板的正投影具有交叠区域，从而形成了第一电容C01。其中，第一导电部C01-1作为第一电容C01的第一极C01-1，第二控制晶体管M5的栅极M5-G作为第一电容C01的第二极。
在一些实施例中，第二导电部C02-1在衬底基板的正投影与输出晶体管M3的栅极M3-G在衬底基板的正投影具有交叠区域，从而形成了第二电容C02。其中，第二导电部C02-1作为第二电容C02的第一极。输出晶体管M3的栅极M3-G作为第二电容C02的第二极。
在一些实施例中，级联的两个移位寄存器单元可以通过一个第三导电部410进行电连接。例如，级联的两个移位寄存器单元中，上一级移位寄存器单元中的输出晶体管的第一极通过第三导电部410与下一级移位寄存器单元中的输入晶体管的第一极电连接。
在一些实施例中，可以使第二控制晶体管的栅极在衬底基板的正投影覆盖第一导电部在衬底基板的正投影。
需要说明的是，第四导电层400还可以包括上述像素驱动电路中的存储电容CST的第一极以及复位信号线。
示例性地，如图8a、图8b所示，在上述的第四导电层400上形成有第三 绝缘层630，用于保护上述的第四导电层400。如图6、图7d以及图8a、图8b所示，示出了该栅极驱动电路01的第二导电层200，第二导电层200设置在第三绝缘层630背离衬底基板1000一侧。第二导电层200可以包括：多条数据线VD、第一电源线VGL，第二电源线VGH、多条时钟信号线(例如第一时钟信号线GCK1、第二时钟信号线GCB1、第三时钟信号线GCK2、第四时钟信号线GCB2)、多个第一转接部210、多个第二转接部220、多个第三转接部230、多个第四转接部240以及多个第五转接部250。其中，一个移位寄存器中设置一个第一转接部210、一个第二转接部220、一个第三转接部230、一个第四转接部240、一个第五转接部250。
在一些实施例中，如图6与图8b所示，一个第一转接部210与一个输出晶体管对应设置，且一个第一转接部210与一个输出晶体管的有源层的源极区通过第十过孔电连接。并且，第二连接线120的一端通过第二过孔H2与第一转接部210电连接，第二连接线120的另一端与时钟信号线通过第三过孔H3电连接。
在一些实施例中，如图6所示，一个第二转接部220与一个第一控制晶体管对应设置，且第一控制晶体管的有源层的漏极区通过对应的第二转接部220与第二控制晶体管的栅极电连接。
在一些实施例中，如图6与图8a所示，一个第三转接部230对应一个第二控制晶体管。第二控制晶体管的有源层的源极区通过第六过孔H6与对应的第三转接部230的一端电连接，第三转接部230的另一端通过第七过孔H7与对应的第一导电部的一端电连接，第一导电部的另一端通过第八过孔H8与第二电源线电连接，第二控制晶体管的有源层的漏极区与输出晶体管的有源层的漏极区共用。
在一些实施例中，如图6与图8a所示，一个第四转接部240对应一个第六晶体管M6。第四转接部240的一端通过第十一过孔H11与输入晶体管M1的栅极M1-G电连接，第四转接部240的另一端通过第十二过孔与第六晶体管M6的有源层的源极区电连接。
在一些实施例中，如图6与图8a所示，一个第五转接部250对应一个稳压晶体管M2。第五转接部250的一端通过第十三过孔H13与稳压晶体管M2的有源层的漏极区电连接，第五转接部250的另一端通过第十四过孔H14与输出晶体管M3的栅极电连接。
需要说明的是，其他晶体管相互之间的电连接关系，可以采用其他转接部实现电连接，在此不作赘述。
在一些实施例中，如图6所示，第一寄存器单元组GOA-1中，第奇数级移位寄存器单元的输出晶体管的第一极(例如输出晶体管的有源层的源极区)通过对应的第二连接线120与第二时钟信号线GCB1电连接，第偶数级移位寄存器单元的输出晶体管的第一极(例如输出晶体管的有源层的源极区)通过对应的第二连接线120与第一时钟信号线GCK1电连接。以及，第二寄存器单元组GOA-2中，第奇数级移位寄存器单元的输出晶体管的第一极(例如输出晶体管的有源层的源极区)通过对应的第二连接线120与第四时钟信号线GCB2电连接，第偶数级移位寄存器单元的输出晶体管的第一极通过对应的第二连接线120与第三时钟信号线GCK2电连接。
在一些实施例中，如图6与图8a、图8b所示，各稳压晶体管的栅极通过第四过孔H4与第一电源线电连接。以向稳压晶体管的栅极输入相应的电压信号。
在一些实施例中，如图6与图8a、图8b所示，同一栅极驱动电路01中，输入晶体管在衬底基板的正投影位于第一电源线在衬底基板的正投影与多个时钟信号线在衬底基板的正投影之间。稳压晶体管在衬底基板的正投影位于第一电源线在衬底基板的正投影背离多个时钟信号线在衬底基板的正投影一侧。输出晶体管在衬底基板的正投影位于稳压晶体管在衬底基板的正投影背离第一电源线在衬底基板的正投影一侧。
在一些实施例中，如图6与图8a、图8b所示，第一控制晶体管的有源层的源极区通过第五过孔H5与第一电源线电连接，以使第一控制晶体管的有源层的源极区可以输入相应的电压信号。
在一些实施例中，如图6所示，第二电源线在衬底基板的正投影位于多个时钟信号线在衬底基板的正投影与栅极驱动电路01在衬底基板的正投影之间。并且，移位寄存器单元中，第一控制晶体管在衬底基板的正投影位于输入晶体管在衬底基板的正投影与第一电源线在衬底基板的正投影之间。以及，移位寄存器单元中，第二控制晶体管在衬底基板的正投影位于输入晶体管在衬底基板的正投影背离第一电源线在衬底基板的正投影一侧。
在一些实施例中，如图6所示，第二控制晶体管的栅极在衬底基板的正投影与第一导电部在衬底基板的正投影分别与第一电源线在衬底基板的正投影具有交叠区域。
在一些实施例中，如图6所示，第八过孔H8在衬底基板的正投影位于第一电源线和第二电源线在衬底基板的正投影之间，第七过孔H7在衬底基板的正投影位于第一电源线在衬底基板的正投影与第二控制晶体管的有源层在衬底基板的正投影之间。
如图8a、图8b所示，半导体层500与第一导电层100之间设置有栅绝缘层640，第一导电层100与第四导电层400之间设置有第一绝缘层610，第四导电层400与第二导电层200之间设置有第三绝缘层630，第二导电层200与第三导电层300之间设置有第二绝缘层620。其中，上述各过孔间隔设置。并且，第一过孔H1、第二过孔H2、第三过孔H3、第四过孔H4、第十一过孔H11以及第十四过孔H14贯穿第一绝缘层和第三绝缘层。第五过孔H5、第六过孔H6、第十二过孔以及第十三过孔H13贯穿第一绝缘层、第三绝缘层以及栅绝缘层。第七过孔H7和第八过孔H8贯穿第三绝缘层。
本公开实施例提供的另一些显示面板的结构示意图，如图9所示，其针对上述实施例的实施方式进行了变形。下面仅说明本实施例与上述实施例的区别之处，其相同之处在此不作赘述。
示例性地，如图9至图11所示，在第二导电层200上形成有第二绝缘层620，用于保护上述的第二导电层200。如图9至图11所示，示出了该栅极驱动电路01的第三导电层300，第三导电层300设置在第二绝缘层620背离衬 底基板1000一侧。并且，第三导电层300可以包括：至少一条辅助线。其中，一条辅助线与一条时钟信号线通过至少一个第九过孔H9电连接，且第九过孔H9贯穿第二绝缘层620。
在一些实施例中，如图9所示，可以使时钟信号线在衬底基板的正投影覆盖电连接的辅助线在衬底基板的正投影。进一步地，可以使时钟信号线在衬底基板的正投影与电连接的辅助线在衬底基板的正投影重叠。这样可以降低辅助线的占用面积，从而可以降低非显示区BB的占用面积。
在一些实施例中，如图9所示，可以使第二导电层包括：多条辅助线；一条辅助线与一条时钟信号线通过多个第九过孔H9电连接。这样可以使每一条时钟信号线的电阻降低。
在一些实施例中，如图9所示，可以使每相邻两条时钟信号线的第九过孔H9错位排列。这样可以将第九过孔H9分散设置，提高均一性。
在一些实施例中，如图9所示，第九过孔H9在衬底基板的正投影与第一过孔H1和第三过孔H3在衬底基板的正投影不交叠，从而可以提高电连接的精确性。
基于同一发明构思，本公开实施例还提供了显示面板的驱动方法，包括：
在一帧扫描时间内，控制各个移位寄存器单元顺序工作，以对各驱动线逐行扫描；其中，沿时钟信号线的延伸方向依次排列的第奇数个移位寄存器单元和第偶数个移位寄存器单元在不同的时钟信号线组控制下独立驱动。
示例性地，结合图4c、图6以及图12所示，在一帧扫描时间内，第奇数个移位寄存器单元(即第一寄存器单元组GOA-1)在第一时钟信号线GCK1和第二时钟信号线GCB1输入的时钟信号的控制下进行工作，以对电连接的扫描线输入信号。并且，第偶数个移位寄存器单元(即第二寄存器单元组GOA-2)在第三时钟信号线GCK2和第四时钟信号线GCB2输入的时钟信号的控制下进行工作，以对电连接的扫描线输入信号。从而可以使各扫描线逐行扫描。
图12中示出了第一时钟信号线GCK1传输的信号gck1，第二时钟信号线 GCB1传输的信号gcb1，第三时钟信号线GCK2传输的信号gck2，第四时钟信号线GCB2传输的信号gcb2。
本公开实施例还提供了显示面板的驱动方法，包括：不同的时钟信号线组中多个时钟信号线上所加的信号保持有效电平的时间互不重叠。例如，图12所示，时钟信号线上所加的信号有效电平为低电平，各时钟信号线上所加的信号的低电平不重叠。
基于同一发明构思，本公开实施例还提供了显示装置，包括本公开实施例提供的上述显示面板。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
在具体实施时，在本公开实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (17)

  1. 一种显示面板，其中，包括：
    衬底基板，包括显示区和非显示区；
    其中，显示区包括：
    多个子像素，沿多个行和多个列矩阵排布；
    多条驱动线，一行所述子像素对应电连接至少一条所述驱动线；
    多条数据线，一列所述子像素对应电连接至少一条所述数据线；
    所述非显示区包括：
    栅极驱动电路，包括：多条时钟信号线，以及沿所述时钟信号线的延伸方向依次排列的多个移位寄存器单元；其中，所述多条时钟信号线分为多个时钟信号线组；
    其中，所述多个移位寄存器单元分为多个寄存器单元组；其中，同一所述寄存器单元组中的各所述移位寄存器单元级联设置，沿所述时钟信号线的延伸方向相邻的两个移位寄存器单元位于不同的寄存器单元组；且，不同的所述寄存器单元组对应不同的所述时钟信号线组；
    每一个所述移位寄存器单元包括输入晶体管与输出晶体管；其中，所述输入晶体管的栅极与对应的所述时钟信号线组中的一条时钟信号线电连接，所述输入晶体管的第一极与输入信号端电连接，所述输入晶体管的第二极与所述输出晶体管的栅极电连接；所述输出晶体管的第二极与至少一条驱动线对应电连接。
  2. 如权利要求1所述的显示面板，其中，所述显示面板还包括：
    半导体层，位于所述衬底基板上，且所述半导体层包括所述输入晶体管的有源层以及所述输出晶体管的有源层；所述有源层包括源极区、漏极区以及位于所述源极区和所述漏极区之间的沟道区；
    栅绝缘层，位于所述半导体层背离所述衬底基板一侧；
    第一导电层，位于所述栅绝缘层背离所述衬底基板一侧，且所述第一导 电层包括所述多条驱动线、多条第一连接线、多条第二连接线、所述输入晶体管的栅极以及所述输出晶体管的栅极；一个所述移位寄存器单元对应至少一条所述第一连接线和至少一条所述第二连接线；
    第一绝缘层，位于所述第一导电层背离所述衬底基板一侧；
    第二导电层，位于所述第一绝缘层背离所述衬底基板一侧，且所述第二导电层包括所述多条数据线、所述多条时钟信号线以及多个第一转接部；其中，一个所述第一转接部与一个所述输出晶体管的有源层的源极区电连接；所述第二导电层还包括：第一电源线；
    针对一个所述移位寄存器单元以及与所述移位寄存器单元对应的所述时钟信号线组，所述第一连接线的一端直接与所述移位寄存器单元中的输入晶体管的栅极电连接，所述第一连接线的另一端与所述时钟信号线组中的一条时钟信号线通过第一过孔电连接，所述第二连接线的一端通过第二过孔与所述第一转接部电连接，所述第二连接线的另一端与所述时钟信号线组中的另一条时钟信号线或者第一电源线通过第三过孔电连接；
    所述第一过孔、所述第二过孔和所述第三过孔贯穿所述第一绝缘层且间隔设置。
  3. 如权利要求2所述的显示面板，其中，所述多条时钟信号线分为2个时钟信号线组，所述2个时钟信号线组包括第一时钟信号线组和第二时钟信号线组；其中，所述第一时钟信号线组包括第一时钟信号线和第二时钟信号线，所述第二时钟信号线组包括第三时钟信号线和第四时钟信号线；
    所述多个移位寄存器单元分为2个寄存器单元组，所述2个寄存器单元组包括第一寄存器单元组和第二寄存器单元组，其中，所述第一个寄存器单元组包括沿所述时钟信号线的延伸方向依次排列的第奇数个移位寄存器单元，第二个寄存器单元组包括沿所述时钟信号线的延伸方向依次排列的第偶数个移位寄存器单元；
    针对所述第一个寄存器单元组中级联的多个移位寄存器单元，第奇数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线与所述第一时钟 信号线电连接，所述第奇数级移位寄存器单元的输出晶体管的第一极通过对应的第二连接线与所述第二时钟信号线或者第一电源线电连接；以及，第偶数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线与所述第二时钟信号线电连接，所述第偶数级移位寄存器单元的输出晶体管的第一极通过对应的第二连接线与所述第一时钟信号线或者第一电源线电连接；
    针对所述第二个寄存器单元组中级联的多个移位寄存器单元，第奇数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线与所述第三时钟信号线电连接，所述第奇数级移位寄存器单元的输出晶体管的第一极通过对应的第二连接线与所述第四时钟信号线或者第一电源线电连接；以及，所述第偶数级移位寄存器单元的输入晶体管的栅极通过对应的第一连接线与所述第四时钟信号线电连接，所述第偶数级移位寄存器单元的输出晶体管的第一极通过对应的第二连接线与所述第三时钟信号线或者第一电源线电连接。
  4. 如权利要求3所述的显示面板，其中，每一个所述移位寄存器单元还包括稳压晶体管；其中，所述输入晶体管的第二极与所述稳压晶体管的第一极电连接，所述稳压晶体管的第二极与所述输出晶体管的栅极电连接；
    所述第二导电层还包括：第一电源线；各所述稳压晶体管的栅极通过第四过孔与所述第一电源线电连接；其中，所述第四过孔贯穿所述第一绝缘层。
  5. 如权利要求4所述的显示面板，其中，同一所述栅极驱动电路中，所述输入晶体管在所述衬底基板的正投影位于所述第一电源线在所述衬底基板的正投影与所述多个时钟信号线在所述衬底基板的正投影之间；
    所述稳压晶体管在所述衬底基板的正投影位于所述第一电源线在所述衬底基板的正投影背离所述多个时钟信号线在所述衬底基板的正投影一侧；
    所述输出晶体管在所述衬底基板的正投影位于所述稳压晶体管在所述衬底基板的正投影背离所述第一电源线在所述衬底基板的正投影一侧。
  6. 如权利要求3-5任一项所述的显示面板，其中，所述移位寄存器单元还包括第一控制晶体管与第二控制晶体管；
    所述半导体层还包括所述第一控制晶体管的有源层、和所述第二控制晶 体管的有源层；
    所述第一导电层还包括：所述第一控制晶体管的栅极与所述第二控制晶体管的栅极；
    所述第二导电层还包括：第二电源线、多个第二转接部、多个第三转接部；其中，一个所述第二转接部对应一个所述第一控制晶体管，一个所述第三转接部对应一个所述第二控制晶体管；
    并且，所述显示面板还包括：
    第四导电层，位于所述第一绝缘层与所述第二导电层之间，且所述第四导电层包括多个第一导电部；其中，一个所述第一导电部对应一个所述第二控制晶体管；
    第三绝缘层，位于所述第四导电层与所述第二导电层之间；
    其中，所述第一控制晶体管的栅极直接与对应的第一连接线电连接，所述第一控制晶体管的有源层的源极区通过第五过孔与所述第一电源线电连接，所述第一控制晶体管的有源层的漏极区通过对应的所述第二转接部与所述第二控制晶体管的栅极电连接；其中，所述第五过孔贯穿所述第一绝缘层和所述第三绝缘层；
    所述第二控制晶体管的有源层的源极区通过第六过孔与对应的所述第三转接部的一端电连接，所述第三转接部的另一端通过第七过孔与对应的所述第一导电部的一端电连接，所述第一导电部的另一端通过第八过孔与所述第二电源线电连接，所述第二控制晶体管的有源层的漏极区与所述输出晶体管的有源层的漏极区共用；其中，所述第六过孔贯穿所述第一绝缘层和所述第三绝缘层，所述第七过孔和所述第八过孔贯穿所述第三绝缘层。
  7. 如权利要求6所述的显示面板，其中，所述第二电源线在所述衬底基板的正投影位于所述多个时钟信号线在所述衬底基板的正投影与所述栅极驱动电路在所述衬底基板的正投影之间；
    所述移位寄存器单元中，所述第一控制晶体管在所述衬底基板的正投影位于所述输入晶体管在所述衬底基板的正投影与所述第一电源线在所述衬底 基板的正投影之间；
    所述移位寄存器单元中，所述第二控制晶体管在所述衬底基板的正投影位于所述输入晶体管在所述衬底基板的正投影背离所述第一电源线在所述衬底基板的正投影一侧。
  8. 如权利要求7所述的显示面板，其中，所述移位寄存器单元中，所述输出晶体管的有源层与所述第二控制晶体管的有源层一体结构设置。
  9. 如权利要求6-8任一项所述的显示面板，其中，所述移位寄存器单元还包括：第一电容和第二电容；其中，所述第一电容的第一极与所述第二电源线电连接，所述第一电容的第二极与所述第二控制晶体管的栅极电连接；所述第二电容的第一极与所述输出晶体管的第二极电连接，所述第二电容的第二极与所述输出晶体管的栅极电连接；
    所述第四导电层还包括多个第二导电部；其中，一个所述第二导电部对应一个所述输出晶体管；
    所述第一导电部在所述衬底基板的正投影与所述第二控制晶体管的栅极在所述衬底基板的正投影具有交叠区域，且所述第一导电部作为所述第一电容的第一极，所述第二控制晶体管的栅极作为所述第一电容的第二极；
    所述第二导电部在所述衬底基板的正投影与对应的所述输出晶体管的栅极在所述衬底基板的正投影具有交叠区域，且所述第二导电部作为所述第二电容的第一极，所述输出晶体管的栅极作为所述第二电容的第二极。
  10. 如权利要求9所述的显示面板，其中，所述第二控制晶体管的栅极在所述衬底基板的正投影覆盖所述第一导电部在所述衬底基板的正投影。
  11. 如权利要求10所述的显示面板，其中，所述第二控制晶体管的栅极在所述衬底基板的正投影与所述第一导电部在所述衬底基板的正投影分别与所述第一电源线在所述衬底基板的正投影具有交叠区域。
  12. 如权利要求6-11任一项所述的显示面板，其中，所述第八过孔在所述衬底基板的正投影位于所述第一电源线和所述第二电源线在所述衬底基板的正投影之间，所述第七过孔在所述衬底基板的正投影位于所述第一电源线 在所述衬底基板的正投影与所述第二控制晶体管的有源层在所述衬底基板的正投影之间。
  13. 如权利要求2-12任一项所述的显示面板，其中，所述显示面板还包括：
    第二绝缘层，位于所述第二导电层背离所述衬底基板一侧；
    第三导电层，位于所述第二绝缘层背离所述衬底基板一侧，且所述第二导电层包括：至少一条辅助线；
    一条所述辅助线与一条所述时钟信号线通过至少一个第九过孔电连接，且所述第九过孔贯穿所述第二绝缘层。
  14. 如权利要求13所述的显示面板，其中，所述时钟信号线在所述衬底基板的正投影覆盖电连接的辅助线在所述衬底基板的正投影。
  15. 一种显示装置，其中，包括如权利要求1-14任一项所述的显示面板。
  16. 一种如权利要求1-14任一项所述的显示面板的驱动方法，其中，包括：
    在一帧扫描时间内，控制各个所述移位寄存器单元顺序工作，以对各所述驱动线逐行扫描；其中，沿所述时钟信号线的延伸方向依次排列的第奇数个移位寄存器单元和第偶数个移位寄存器单元在不同的时钟信号线组控制下独立驱动。
  17. 一种如权利要求16所述的显示面板的驱动方法，其中，包括：不同的时钟信号线组中多个时钟信号线上所加的信号保持有效电平的时间互不重叠。
PCT/CN2020/087637 2020-04-28 2020-04-28 显示面板、驱动方法及显示装置 WO2021217468A1 (zh)

Priority Applications (7)

Application Number Priority Date Filing Date Title
EP20933067.9A EP4036899A4 (en) 2020-04-28 2020-04-28 DISPLAY BOARD, ATTACK METHOD AND DISPLAY DEVICE
PCT/CN2020/087637 WO2021217468A1 (zh) 2020-04-28 2020-04-28 显示面板、驱动方法及显示装置
KR1020227017659A KR20230002266A (ko) 2020-04-28 2020-04-28 표시 패널, 구동 방법 및 표시 장치
CN202080000620.9A CN113853642A (zh) 2020-04-28 2020-04-28 显示面板、驱动方法及显示装置
US17/772,329 US11929030B2 (en) 2020-04-28 2020-04-28 Display panel, driving method, and display device
JP2022528658A JP2023531843A (ja) 2020-04-28 2020-04-28 ディスプレイパネル、駆動方法およびディスプレイデバイス
US18/434,932 US20240177678A1 (en) 2020-04-28 2024-02-07 Display panel, driving method, and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/087637 WO2021217468A1 (zh) 2020-04-28 2020-04-28 显示面板、驱动方法及显示装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US17/772,329 A-371-Of-International US11929030B2 (en) 2020-04-28 2020-04-28 Display panel, driving method, and display device
US18/434,932 Continuation US20240177678A1 (en) 2020-04-28 2024-02-07 Display panel, driving method, and display device

Publications (1)

Publication Number Publication Date
WO2021217468A1 true WO2021217468A1 (zh) 2021-11-04

Family

ID=78373269

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/087637 WO2021217468A1 (zh) 2020-04-28 2020-04-28 显示面板、驱动方法及显示装置

Country Status (6)

Country Link
US (2) US11929030B2 (zh)
EP (1) EP4036899A4 (zh)
JP (1) JP2023531843A (zh)
KR (1) KR20230002266A (zh)
CN (1) CN113853642A (zh)
WO (1) WO2021217468A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11925067B2 (en) * 2020-05-11 2024-03-05 Boe Technology Group Co., Ltd. Display panel and display device
US11694607B2 (en) * 2021-03-04 2023-07-04 Boe Technology Group Co., Ltd. Light emitting substrate, display apparatus, and method of driving light emitting substrate
CN114967249B (zh) * 2022-05-31 2023-10-20 京东方科技集团股份有限公司 一种显示基板、显示装置
WO2024036626A1 (zh) * 2022-08-19 2024-02-22 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010097986A1 (ja) * 2009-02-25 2010-09-02 シャープ株式会社 シフトレジスタおよび表示装置
CN104008779A (zh) * 2014-05-27 2014-08-27 上海天马有机发光显示技术有限公司 移位寄存器及其驱动方法、移位寄存器组及其驱动方法
CN104616616A (zh) * 2015-02-12 2015-05-13 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、阵列基板、显示装置
WO2016190186A1 (ja) * 2015-05-25 2016-12-01 シャープ株式会社 シフトレジスタ回路
CN109801577A (zh) * 2017-11-16 2019-05-24 京东方科技集团股份有限公司 栅极驱动电路、显示装置及其驱动方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102527817B1 (ko) * 2018-04-02 2023-05-04 삼성디스플레이 주식회사 표시 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010097986A1 (ja) * 2009-02-25 2010-09-02 シャープ株式会社 シフトレジスタおよび表示装置
CN104008779A (zh) * 2014-05-27 2014-08-27 上海天马有机发光显示技术有限公司 移位寄存器及其驱动方法、移位寄存器组及其驱动方法
CN104616616A (zh) * 2015-02-12 2015-05-13 京东方科技集团股份有限公司 栅极驱动电路及其驱动方法、阵列基板、显示装置
WO2016190186A1 (ja) * 2015-05-25 2016-12-01 シャープ株式会社 シフトレジスタ回路
CN109801577A (zh) * 2017-11-16 2019-05-24 京东方科技集团股份有限公司 栅极驱动电路、显示装置及其驱动方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4036899A4 *

Also Published As

Publication number Publication date
US20240177678A1 (en) 2024-05-30
US20220406260A1 (en) 2022-12-22
EP4036899A4 (en) 2022-11-16
EP4036899A1 (en) 2022-08-03
CN113853642A (zh) 2021-12-28
JP2023531843A (ja) 2023-07-26
US11929030B2 (en) 2024-03-12
KR20230002266A (ko) 2023-01-05

Similar Documents

Publication Publication Date Title
WO2021217468A1 (zh) 显示面板、驱动方法及显示装置
US11508298B2 (en) Display panel and driving method thereof and display device
CN112967682B (zh) 一种显示面板及显示装置
CN112771601B (zh) 显示基板、显示装置及显示基板的制作方法
CN113078174B (zh) 阵列基板、显示面板及显示装置
US20210225974A1 (en) Amoled display panel and corresponding display device
US11450270B2 (en) Pixel circuit and method of driving the same, display device
US20210272517A1 (en) Pixel circuit, display panel, display device and driving method
CN113362762B (zh) 一种显示面板及其控制方法、显示装置
EP4002337A1 (en) Display substrate, display panel, and display device
CN110335567B (zh) 阵列基板、显示面板及显示装置
CN110853576A (zh) 显示基板和显示装置
US20230343286A1 (en) Pixel structure, method for driving the same and display substrate
WO2022104615A1 (zh) 显示面板、驱动方法及显示装置
CN112992246A (zh) 发光控制移位寄存器及方法、栅极驱动电路、显示装置
US20220319408A1 (en) Display panel and display apparatus
US11893937B2 (en) Pixel circuit, driving method thereof, array substrate, display panel, and display device
CN114026629B (zh) 显示基板及显示装置
CN114822411B (zh) 显示面板和显示装置
CN115735244A (zh) 像素电路及驱动方法、显示基板及驱动方法、显示装置
CN114005411A (zh) 阵列基板、显示面板及显示装置
JP7474786B2 (ja) ディスプレイパネルおよびディスプレイデバイス
US20220310753A1 (en) Display panel and display device
US20220328009A1 (en) Display Panel, Driving Method for Same, and Display Device
CN114464137B (zh) 显示基板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20933067

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020933067

Country of ref document: EP

Effective date: 20220429

ENP Entry into the national phase

Ref document number: 2022528658

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE