WO2021212368A1 - 具有多通道异质结构的半导体器件及其制造方法 - Google Patents

具有多通道异质结构的半导体器件及其制造方法 Download PDF

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WO2021212368A1
WO2021212368A1 PCT/CN2020/086140 CN2020086140W WO2021212368A1 WO 2021212368 A1 WO2021212368 A1 WO 2021212368A1 CN 2020086140 W CN2020086140 W CN 2020086140W WO 2021212368 A1 WO2021212368 A1 WO 2021212368A1
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semiconductor
semiconductor device
layer
conductive
ranges
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PCT/CN2020/086140
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English (en)
French (fr)
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张安邦
黄敬源
李�浩
郑浩宁
王剑
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英诺赛科（珠海）科技有限公司
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Priority to CN202080001200.2A priority Critical patent/CN111602248A/zh
Priority to US17/266,618 priority patent/US11961902B2/en
Priority to PCT/CN2020/086140 priority patent/WO2021212368A1/zh
Publication of WO2021212368A1 publication Critical patent/WO2021212368A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Definitions

  • This disclosure relates to a semiconductor device and a manufacturing method thereof, and particularly relates to a heterostructure device with a multi-channel heterostructure and a manufacturing method thereof.
  • High-power devices often use semiconductor materials with a large energy gap to form field emission transistors (FETs), such as GaN, AlN, and other large energy gap semiconductor materials to provide large breakdown voltage and low reverse current.
  • FETs field emission transistors
  • the narrow band gap semiconductor forming the "channel layer” is adjacent to the wide band gap semiconductor forming the "electron supply layer", which allows the electron supply layer to generate high concentration of electrons, which accumulate in the channel layer and At the interface of the electron supply layer, these accumulated electrons form a flake-like distribution, which can also be called “two-dimensional electron gas (2DEG)".
  • 2DEG two-dimensional electron gas
  • 2DEG has a very high electron mobility and can be used in high-speed electronic components and power components.
  • the semiconductor device includes: a semiconductor heterostructure layer, which includes alternating first and second semiconductor material layers, wherein each adjacent first semiconductor material layer and second semiconductor material layer are It can generate two-dimensional electron gas (2DEG); and a conductive structure, including a plurality of conductive fingers extending from the surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer, wherein the plurality of conductive fingers extend along a direction substantially parallel to the surface Arranged, and the length of the plurality of conductive fingers increases along the direction, so that the end of each conductive finger is located on a different second semiconductor material layer and does not contact the 2DEG.
  • 2DEG two-dimensional electron gas
  • the semiconductor device includes: a semiconductor heterostructure layer, which includes alternating first and second semiconductor material layers, wherein 2DEG can be generated between each adjacent first semiconductor material layer and second semiconductor material layer
  • the drain structure includes a plurality of first conductive fingers extending from the surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer, wherein the plurality of first conductive fingers are arranged along a direction substantially parallel to the surface, and The length of the plurality of first conductive fingers increases along the direction, so that the end of each first conductive finger is located in a different second semiconductor material layer and does not contact the 2DEG; the source structure includes a plurality of first conductive fingers.
  • Two conductive fingers extend from the surface into the semiconductor heterostructure layer, wherein the plurality of second conductive fingers are arranged along the direction, and the length of the plurality of second conductive fingers decreases along the direction , The end of each second conductive finger is located in a different second semiconductor material layer and does not contact the 2DEG; and a gate structure between the drain structure and the source structure.
  • Some embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including: forming a semiconductor heterostructure layer, including alternately forming a first semiconductor material layer and a second semiconductor material layer, wherein each adjacent first semiconductor material 2DEG can be generated between the layer and the second semiconductor material layer; patterning the surface of the semiconductor heterostructure layer to form a plurality of openings in a first direction substantially parallel to the surface of the semiconductor heterostructure layer; and The semiconductor heterostructure layer is etched from the plurality of openings to form a plurality of trenches in the semiconductor heterostructure layer, wherein the grooves of the plurality of trenches increase in the first direction, and the etching stops In a different second semiconductor layer, and the bottom of each trench does not contact the 2DEG; depositing conductive material in a plurality of trenches to form a conductive structure; and annealing.
  • Figure 1A is a cross-sectional view of a semiconductor device according to some embodiments of the present case
  • 1B is a schematic diagram of electrons flowing in a two-dimensional electron gas channel in a semiconductor device
  • Figure 2 is an enlarged view of a conductive finger according to some embodiments of the present case
  • Figure 3 is a cross-sectional view of a semiconductor device according to some embodiments of the present case.
  • Fig. 5 is a cross-sectional view of a semiconductor device of a comparative embodiment
  • 6A is a cross-sectional view of a semiconductor device according to some embodiments of the present case.
  • 6B is a schematic diagram of electrons flowing in a two-dimensional electron gas channel in a semiconductor device
  • FIG. 7 is a cross-sectional view of a semiconductor device according to some embodiments of the present case.
  • FIG. 8 is a cross-sectional view of a semiconductor device according to some embodiments of the present case.
  • FIG. 9 is a cross-sectional view of a semiconductor device according to some embodiments of the present case.
  • 10A, 10B, 10C, and 10D show the steps of forming a semiconductor device according to some embodiments of the present application.
  • the description that the first feature is formed on or above the second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include that additional features may be formed on the first feature.
  • An embodiment between the feature and the second feature so that the first feature and the second feature may not be in direct contact.
  • the present disclosure may repeat reference numerals and/or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself prescribe the relationship between the various embodiments and/or configurations discussed.
  • FIG. 1A is a cross-sectional view of a semiconductor device 100 according to some embodiments of the present application.
  • the semiconductor device 100 includes a semiconductor heterostructure layer 110 and a conductive structure 130.
  • the semiconductor device 100 further includes a buffer layer 140 and a carrier 150.
  • the carrier 150 can be a semiconductor substrate, a glass substrate, a PCB substrate, a flexible substrate (for example, polymer, paper), or any medium that can carry the semiconductor heterostructure layer 110.
  • a buffer layer 140 may be further included between the semiconductor heterostructure layer 110 and the carrier 150.
  • the buffer layer 140 is formed between the semiconductor material layer 111 and the carrier 150.
  • the buffer layer 140 may be a superlattice structure composed of AlGaN and GaN. The thickness of the buffer layer 140 ranges from about 0.5 ⁇ m-10 ⁇ m.
  • the semiconductor heterostructure layer 110 includes a stack of alternating semiconductor material layers 111 and semiconductor material layers 112.
  • the semiconductor material layer 111 and the semiconductor material layer 112 are composed of semiconductor materials with different energy gaps, so that 2DEG (not shown) can be generated between each adjacent semiconductor material layer 111 and the semiconductor material layer 112.
  • the semiconductor material layer 111 and the semiconductor material layer 112 are composed of semiconductor materials with different energy gaps. Piezoelectricity forms a 2DEG at the interface between the semiconductor material layer 111 and the semiconductor material layer 112 under the dual effects of spontaneous polarization and piezoelectric polarization. Compared with the semiconductor material layer 111, the semiconductor material 112 has a wider energy gap.
  • the semiconductor material layer 111 is GaN, and the energy gap is about 3.4 eV; the semiconductor material layer 112 is AlGaN, and the energy gap is 4 eV.
  • the semiconductor material layer 111 and the semiconductor material layer 112 may respectively include III-V compounds.
  • the combination of the semiconductor material layer 111 and the semiconductor material layer 112 may include, but is not limited to, one of the following: a combination of GaN and AlGaN, a combination of GaN and InAlN, a combination of GaN and AlN, a combination of GaN and InAlGaN.
  • the thickness of the semiconductor heterostructure layer 110 ranges from 8 nm to 1000 nm. In an embodiment, the thickness of each semiconductor material layer 111 in the semiconductor heterostructure layer 110 ranges from 2 nm to 70 nm. In a preferred embodiment, the thickness of each semiconductor material layer 111 ranges from 3 nm to 20 nm. The thickness of the semiconductor layer 111 in the semiconductor heterostructure layer 110 may be greater than or equal to the semiconductor layer 112. In an embodiment, the thickness of each semiconductor material layer 112 in the semiconductor heterostructure layer 110 ranges from 2 nm to 30 nm. In a preferred embodiment, the thickness of each semiconductor material layer 112 ranges from 3 nm to 10 nm.
  • an intermediate layer (not shown in the figure) may be included between the semiconductor material layer 111 and the semiconductor material layer 112, wherein the intermediate layer may include AlN and the thickness may be about 1 nm.
  • the 2DEG between the semiconductor material layer 111 and the semiconductor material layer 112 provides multi-channels for the semiconductor device to conduct electrons, and forms a multi-channel heterostructure device.
  • the 2DEG between the semiconductor material layer 111 and the semiconductor material layer 112 in the semiconductor heterostructure layer 110 is at least 2 layers. In a preferred embodiment, the number of 2DEG layers ranges from 2 to 10 layers.
  • the conductive structure 130 includes conductive fingers 131, 132, and 133, and the conductive fingers 131, 132, and 133 are substantially arranged along a direction parallel to the surface 110a of the semiconductor heterostructure layer 110.
  • the ends 131E, 132E, and 133E of each conductive finger are located in the semiconductor material layer 112 of different depths and do not contact the 2DEG.
  • the conductive structure 130 includes three conductive fingers 131, 132 and 133.
  • the number of conductive fingers can be any integer greater than or equal to 2, and is not limited to the foregoing embodiment.
  • the conductive structure 130 may include 2 to 10 conductive fingers.
  • the number of conductive fingers is related to the number of interfaces between the semiconductor material layer 111 and the semiconductor material layer 112. Taking FIG. 1A as an example, the number of interfaces between the semiconductor material layer 111 and the semiconductor material layer 112 and the number of conductive fingers are both three. According to other embodiments, the number of interfaces between the semiconductor material layer 111 and the semiconductor material layer 112 and the number of conductive fingers may both be four, five or other integers.
  • the conductive fingers can be arranged along the X direction as shown in FIG. 1A, and the length of the conductive fingers 131, 132, and 133 deep into the semiconductor heterostructure layer 110 gradually increases along the X direction, that is, the conductive finger 131 is the shortest; the conductive finger 132 is the second ; Conductive finger 133 is the longest.
  • the conductive fingers 131, 132, and 133 can also be arranged along other directions substantially parallel to the surface 110a, and the length of the conductive fingers 131, 132, and 133 deep into the semiconductor heterostructure layer 110 is also along the length The arrangement direction gradually increases.
  • the widths of the conductive fingers are substantially the same. In some preferred embodiments of the present disclosure, the width of the conductive finger increases as the length increases. For example, in FIG. 1A, the conductive fingers 131, 132, and 133 gradually increase in length along the X direction, and also gradually increase in width along the X direction. In some preferred embodiments, the length of the conductive fingers ranges from 1 nm to 1000 nm, and the width ranges from 5 nm to 800 nm. In some preferred embodiments, the length of the conductive finger ranges from 1 nm to 300 nm, and the width ranges from 5 nm to 200 nm.
  • FIG. 1B is a schematic diagram of electrons flowing in a two-dimensional electron gas channel in the semiconductor device 100.
  • a two-dimensional electron gas 2DEG can be generated between each adjacent semiconductor material layer 111 and semiconductor material layer 112. Therefore, multiple 2DEGs 115, 117, and 119 are generated at different depths of the semiconductor heterostructure layer 110 (as shown in the Z direction in FIG. 1B). These 2DEGs 115, 117, and 119 are along the semiconductor material layer 111 and the semiconductor material layer. 112's interface extends.
  • electrons When the semiconductor device is connected to the power supply, electrons will flow in the 2DEG channel and form an electron flow path.
  • the electrons in 2DEG 115, 117, and 119 all flow in the X direction.
  • electrons Near any conductive finger, electrons will enter the conductive finger through an ohmic contact between the approaching conductive finger and the semiconductor material layer 112.
  • the electrons will first flow through the vicinity of the conductive finger 131.
  • they enter the conductive finger 131 mainly through the ohmic contact between the conductive finger 131 and the semiconductor material layer 112.
  • the electron flow path is EP1 as shown in FIG.
  • the second layer 2DEG117 is under the surface 110a.
  • the electrons first flow through the vicinity of the conductive finger 132.
  • the electron approaches the conductive finger 132, it mainly enters the conductive finger 132 through the ohmic contact between the conductive finger 132 and the semiconductor material layer 112.
  • the electron flow path is EP2; similarly, in the 2DEG 119 that is the furthest from the surface 110a , The electrons will first flow through the vicinity of the conductive finger 133.
  • electrons approach the conductive finger 133, they enter the conductive finger 133 mainly through the ohmic contact between the conductive finger 133 and the semiconductor material layer 112, and the electron flow path is EP3 at this time.
  • the conductive finger of the present disclosure can be composed of one or more conductive material layers. Taking the conductive finger of FIG. 1A as an example, it is formed by a single metal material layer.
  • the conductive finger may include one of the following conductive materials: Ti (titanium), aluminum (Al), nickel (Ni), copper (Cu), titanium nitride (TiN), gold (Au), platinum (Pt), Palladium (Pd), Tungsten (W) and their alloys.
  • the conductive finger 230 may include a metal material layer 230a and a metal material layer 230b, where the metal material layer 230b is in contact with the semiconductor heterostructure layer 110, and the metal material layer 230a is formed on the formation 220b.
  • the metal material layer 230b may be one or more layers of metal material, and may include at least one of the following: Ti (titanium), aluminum (Al), nickel (Ni), copper (Cu), titanium nitride (TiN), Gold (Au), platinum (Pt), palladium (Pd), tungsten (W) and their alloys.
  • the metal material layer 230a may include at least one of the following: a titanium (Ti) layer, aluminum (Al), copper (Cu), gold (Au), platinum (Pt), palladium (Pd), and tungsten (W) layer.
  • Ti titanium
  • Al aluminum
  • Cu copper
  • Au gold
  • Pt platinum
  • Pd palladium
  • W tungsten
  • FIG. 3 is a cross-sectional view of a semiconductor device 300 according to some embodiments of the present application.
  • the semiconductor device 300 includes a semiconductor heterostructure layer 110 and a conductive structure 330.
  • the conductive structure 330 includes conductive fingers 331, 332, and 333.
  • the conductive fingers 331, 332, and 333 may be formed of one or more layers of metal materials and may include trenches. That is, the centers of the conductive fingers 331, 332, and 333 are not completely filled with the metal material.
  • the conductive fingers 331, 332, and 333 may include at least one of the following: Ti (titanium), aluminum (Al), nickel (Ni), copper (Cu), titanium nitride (TiN), gold (Au), platinum (Pt) ), Palladium (Pd), Tungsten (W) and their alloys.
  • the conductive finger may include one or more metal material layers and a titanium layer or a titanium nitride (TiN) layer between the one or more metal material layers and the semiconductor heterostructure layer 110.
  • FIG. 4 is a cross-sectional view of a semiconductor device 400 of a comparative embodiment.
  • the semiconductor device 400 includes a semiconductor heterostructure layer 110, a conductive structure 430, a buffer layer 140 and a carrier 150.
  • Some components of the semiconductor device 400 have the same numbers as those of the semiconductor device 100 of FIG. 1 and are made of similar materials, so the details are not repeated here.
  • the conductive structure 430 includes conductive fingers 431 extending from the surface of the semiconductor heterostructure layer 110 along the direction Z to the semiconductor heterostructure layer 110.
  • conductive fingers 431 extending from the surface of the semiconductor heterostructure layer 110 along the direction Z to the semiconductor heterostructure layer 110.
  • FIG. 5 is a cross-sectional view of a semiconductor device 500 of another comparative embodiment.
  • the semiconductor device 500 includes a semiconductor heterostructure layer 110 and a conductive structure 530. Some of the components of the semiconductor device 500 have the same numbers as those of the semiconductor device 100 of FIG. 1 and are made of similar materials, so they will not be repeated here.
  • the conductive structure 530 is formed on the surface of the semiconductor heterostructure layer 110, is in direct contact with the semiconductor heterostructure layer 110, and forms an ohmic junction with the surface of the semiconductor heterostructure layer 110.
  • the electrons in the semiconductor heterostructure layer 110 mainly flow in the 2DEG channel, and the 2DEG, especially the 2DEG farther from the conductive structure 530, has a considerable resistance between the conductive structure 530, which will cause the semiconductor device 500 forms a considerable ohmic resistance.
  • FIG. 6A is a cross-sectional view of a semiconductor device 600 according to some embodiments of the present application.
  • the semiconductor device 600 includes a semiconductor heterostructure layer 110, a drain structure 620, a source structure 630 and a gate structure 640.
  • the semiconductor device 600 further includes a buffer layer 140 and a carrier 150.
  • Some components of the semiconductor device 600 have the same numbers as those of the semiconductor device 100 of FIG. 1 and are made of similar materials, so the details are not repeated here.
  • the gate structure 640 is disposed between the drain structure 620 and the source structure 630 to control the flow of electrons between the drain structure 620 and the source structure 630 and further control the on and off of the semiconductor device 600.
  • the drain structure 620 includes conductive fingers 621, 622, and 623, and the conductive fingers 621, 622, and 623 are substantially arranged along a direction parallel to the surface 110a of the semiconductor heterostructure layer 110.
  • the end portions 621E, 622E, and 623E of each conductive finger of the drain structure 620 are located in the semiconductor material layer 112 of different depths and do not contact the 2DEG.
  • the drain structure 620 includes three conductive fingers.
  • the number of conductive fingers of the drain structure 620 can be any integer greater than or equal to 2, and is not limited to the foregoing embodiment.
  • the drain structure 620 may include 2 to 10 conductive fingers.
  • the number of conductive fingers is related to the number of interfaces between the semiconductor material layer 111 and the semiconductor material layer 112.
  • the conductive fingers can be arranged along the X direction as shown in FIG. 6A, and the length of the conductive fingers 621, 622, and 623 deep into the semiconductor heterostructure layer 110 gradually increases along the X direction, that is, Conductive finger 621 is the shortest; conductive finger 622 is the second; conductive finger 623 is the longest.
  • the conductive fingers 621, 622, and 623 of the drain structure 620 may also be arranged along other directions substantially parallel to the surface 110a. At this time, the length of the conductive fingers 621, 622, and 623 of the drain structure 620 into the semiconductor heterostructure layer 110 will gradually increase along the arrangement direction.
  • the width of each conductive finger is substantially the same. In some preferred embodiments of the present disclosure, the width of the conductive finger increases as the length increases. For example, the conductive fingers 621, 622, and 623 of the drain structure 620 in FIG. 6A gradually increase in length along the X direction and gradually increase in width along the X direction. In some preferred embodiments, the length of the conductive finger of the drain structure ranges from 1 nm to 1000 nm, and the width ranges from 5 nm to 800 nm. In some more preferred embodiments, the length of the conductive finger of the drain structure ranges from 1 nm to 300 nm, and the width ranges from 5 nm to 200 nm.
  • the source structure 630 includes conductive fingers 631, 632, and 633, and the conductive fingers 631, 632, and 633 are substantially arranged along a direction parallel to the surface 110a of the semiconductor heterostructure layer 110.
  • the end portions 631E, 632E, and 633E of each conductive finger of the source structure 630 are located in the semiconductor material layer 112 of different depths and do not contact the 2DEG.
  • the source structure 630 includes three conductive fingers.
  • the number of conductive fingers of the source structure 630 can be any integer greater than or equal to 2, and is not limited to the above-mentioned embodiment.
  • the source structure 630 may include 2 to 10 conductive fingers.
  • the number of conductive fingers is related to the number of interfaces between the semiconductor material layer 111 and the semiconductor material layer 112.
  • the conductive fingers 631, 632, and 633 can be arranged along the X direction as shown in FIG. 631 is the shortest; conductive finger 632 is second; conductive finger 633 is the longest.
  • the conductive fingers 631, 632, and 633 of the source structure 630 can also be arranged along other directions substantially parallel to the surface 110a. At this time, the length of the conductive fingers 631, 632, and 633 of the source structure 630 deep into the semiconductor heterostructure layer 110 will gradually decrease along the arrangement direction.
  • the width of the conductive fingers 631, 632, and 633 decreases as the length decreases.
  • the conductive fingers 631, 632, and 633 gradually decrease in length along the X direction, and also gradually decrease in width along the X direction.
  • the length of the conductive fingers of the source structure ranges from 1 nm to 1000 nm, and the width ranges from 5 nm to 800 nm.
  • the length of the conductive finger of the source structure ranges from 1 nm to 300 nm, and the width range from 5 nm to 200 nm.
  • FIG. 6B is a schematic diagram of electrons flowing in a two-dimensional electron gas channel in the semiconductor device 600.
  • 2DEG can be generated between each adjacent semiconductor material layer 111 and semiconductor material layer 112. Therefore, multiple 2DEGs 115, 117, and 119 can be generated at different depths of the semiconductor heterostructure layer 110 (as shown in the Z direction in FIG. 6B). These 2DEGs 115, 117, and 119 are along the semiconductor material layer 111 and the semiconductor material. The layer 112 interface extends.
  • electrons When the semiconductor device is connected to the power supply, electrons will flow in the 2DEG and form an electron flow path.
  • the electrons in 2DEG 115, 117, and 119 all flow in the X direction.
  • electrons Near any conductive finger, electrons will leave or enter the conductive finger via the ohmic contact between the approaching conductive finger and the semiconductor material layer 112.
  • the source structure 630 For example, in the 2DEG 115 closest to the surface 110a, electrons leave the source structure 630 from the ohmic contact between the conductive finger 631 and the semiconductor material layer 112 and enter the 2DEG 115.
  • the drain structure 620 at this time, the electron flow path is EP62 as shown in Figure 6B; in the same way, in the 2DEG 119 farthest from the surface 610a, the electrons leave the source from the ohmic contact between the conductive finger 633 and the semiconductor material layer 112
  • the electrode structure 630 enters the 2DEG 117.
  • electrons approach the conductive finger 623 of the drain structure 620, they enter the drain structure 620 mainly through the ohmic contact between the conductive finger 623 and the semiconductor material layer 112.
  • the electron flow path is as shown in the figure EP63 shown in 6B.
  • the drain structure 620 and the source structure 630 of the present disclosure are not limited to the embodiment of FIG. 6A.
  • the drain structure 620 and the source structure 630 may respectively include a titanium (Ti) layer or a titanium nitride (TiN) layer in contact with the semiconductor heterostructure layer 110.
  • the titanium (Ti) layer or titanium nitride (TiN) layer in contact with the semiconductor heterostructure layer 110 may further include one or more metal material layers, including at least one of the following conductive materials: Ti (titanium), Aluminum (Al), nickel (Ni), copper (Cu), titanium nitride (TiN), gold (Au), platinum (Pt), palladium (Pd), tungsten (W) and their alloys.
  • the conductive fingers of the drain structure 620 and the source structure 630 may also include multiple metal material layers like the conductive fingers of FIG. 2.
  • the conductive fingers 621, 622, and 623 of the drain structure 620 and the conductive fingers 631, 632, and 633 of the source structure 630 may be completely filled with conductive materials.
  • one or more of the conductive fingers 621, 622, and 623 of the drain structure 620 and/or the conductive fingers 631, 632, and 633 of the source structure 630 may include trenches, that is, conductive Refers to not being completely filled with conductive material.
  • FIG. 7 is a cross-sectional view of a semiconductor device 700 according to some embodiments of the present application.
  • the semiconductor device 700 includes a semiconductor heterostructure layer 110, a drain structure 620, a source structure 730, and a gate structure 640.
  • the semiconductor device 700 further includes a buffer layer 140 and a carrier 150.
  • Some components of the semiconductor device 700 have the same numbers as those of the semiconductor device 600 of FIG. 6A, and are made of similar materials, so they will not be repeated here.
  • the gate structure 640 is disposed between the drain structure 620 and the source structure 730 to control the flow of electrons between the drain structure 620 and the source structure 730 and further control the on and off of the semiconductor device 700.
  • the source electrode 730 includes conductive fingers 731, and the conductive fingers 731 extend from the surface 110 a of the semiconductor heterostructure layer 110 to the semiconductor heterostructure layer 110 along the direction Z.
  • the numbers of the source structure and the drain structure are interchangeable, that is, the source structure is represented by 620 and the drain structure is represented by 730.
  • the current direction will be opposite, that is, the electrons will pass through
  • the conductive fingers 621, 622, and 623 leave the source structure 620, enter the 2DEG at various depths, and then enter the drain structure 730.
  • FIG. 8 is a cross-sectional view of a semiconductor device 800 according to some embodiments of the present application.
  • the semiconductor device 800 includes a semiconductor heterostructure layer 110, a drain structure 620, a source 830 and a gate structure 640.
  • the semiconductor device 800 further includes a buffer layer 140 and a carrier 150.
  • Some of the components in the semiconductor device 800 have the same numbers as those of the semiconductor device 600 in FIG. 6A and are made of similar materials, so they will not be repeated here.
  • the source electrode 830 is formed on the surface 110a of the semiconductor heterostructure layer 110 and is in direct contact with the semiconductor heterostructure layer 110, and the source electrode 830 forms an ohmic junction with the surface 110a of the semiconductor heterostructure layer 110.
  • the electrons will leave the source 830 and enter the 2DEG at various depths, and then enter the drain via the conductive fingers 621, 622, and 623 Structure 620.
  • the numbers of the source structure and the drain structure are interchangeable, that is, the source structure is represented by 620 and the drain structure is represented by 830.
  • the current direction will be opposite, that is, the electrons will pass through
  • the conductive fingers 621, 622, and 623 leave the source structure 620, enter the 2DEG at various depths, and then enter the drain structure 830.
  • FIG. 9 is a cross-sectional view of a semiconductor device 900 according to some embodiments of the present application.
  • the semiconductor device 900 may be a diode, and includes a semiconductor heterostructure layer 110, a cathode structure 920, and an anode structure 940.
  • the semiconductor device 900 further includes a buffer layer 140 and a carrier 150.
  • Some components of the semiconductor device 900 have the same numbers as those of the semiconductor device 600 of FIG. 6A, and are made of similar materials, so they will not be repeated here.
  • the cathode structure 920 includes conductive fingers 921, 922, and 923, and the conductive fingers 921, 922, and 923 are arranged substantially along a direction parallel to the surface 110a of the semiconductor heterostructure layer 110.
  • the end portions of each conductive finger of the cathode structure 920 are located at different depths of the semiconductor material layer 112 921E, 922E, and 923E, and are not in contact with the 2DEG.
  • the anode structure 940 is formed on the surface 110a of the semiconductor heterostructure layer 110 and is in direct contact with the semiconductor heterostructure layer 110.
  • the anode structure 940 and the surface 110a of the semiconductor heterostructure layer 110 form a base junction.
  • 10A, 10B, and 10C show a step of manufacturing the semiconductor device 100.
  • FIG. 10A shows that the semiconductor material layer 111 and the semiconductor material layer 112 are alternately stacked on the carrier 150 to form the semiconductor heterostructure layer 110.
  • the semiconductor material layer 111 and the semiconductor material layer 112 may be formed by any one or more of epitaxial growth, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc., respectively.
  • a buffer layer 140 may be formed on the carrier 150 before forming the semiconductor heterostructure layer 110.
  • the buffer layer 140 may be formed by one or more of methods such as epitaxial growth, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).
  • FIG. 10B shows that a plurality of trenches 131T, 132T, and 133T are formed on the semiconductor heterostructure layer 110 and are arranged substantially along a direction parallel to the surface 110a of the semiconductor heterostructure layer 110.
  • the surface 110a of the semiconductor heterostructure layer 110 is patterned (for example, by lithography) to form a plurality of openings.
  • the semiconductor heterostructure layer 110 is etched to form a plurality of trenches 131T, 132T, and 133T.
  • the plurality of trenches can be formed by one or more of chemical wet etching, dry etching, such as plasma etching, reactive ion etching (RIE), and the like.
  • the plurality of openings are designed as openings of different sizes. Since the size of each opening is different, the etching speed of the semiconductor heterostructure layer 110 in each opening will be different. For example, in wet and/or dry etching, the larger the opening size, the faster the etching speed in the Z direction in the semiconductor heterostructure layer 110.
  • the size of the opening is gradually increased along the X direction on the surface 110a, and the depth of the plurality of trenches 131T, 132T, and 133T is gradually increased along the direction X after the etching process.
  • the plurality of trenches 131T, 132T, and 133T can also be arranged along other directions substantially parallel to the surface 110a. At this time, the length of the plurality of trenches 131T, 132T, and 133T deep into the semiconductor heterostructure layer 110 will gradually increase along the arrangement direction.
  • the dimensions of the plurality of openings are designed so that the plurality of trenches 131T, 132T, and 133T can be etched at one time, and the ends 131TE, 132TE and 133TE are located in the semiconductor material layer 112 of different depths in the semiconductor heterostructure layer 110, and do not contact the 2DEG.
  • the size design of the plurality of openings will be adjusted according to the material of the semiconductor heterostructure layer 110, such as GaN/AlGaN/GaN, GaN/InAlN/GaN, GaN/AlN/GaN, GaN/InAlGaN/GaN, etc.
  • the heterogeneous layer has its own opening size design.
  • the semiconductor material layer 111 in the semiconductor heterostructure layer 110 is GaN, and the thickness of each semiconductor material layer 111 is about 10 nm; the semiconductor material layer 112 is AlGaN, and the thickness of each semiconductor material layer 112 is about 5nm. Dry etching is performed with a chlorine-based etchant, such as at least one of Cl 2 and BCl 3. Table 1 exemplarily shows that a plurality of trenches with different opening widths and trench depths are etched at one time.
  • FIG. 10C shows that a conductive material is deposited in a plurality of trenches 131T, 132T, and 133T to form a conductive structure 130 having conductive fingers 131, 132, and 133, and annealing is further performed to form the semiconductor device 100 of FIG. 1.
  • the conductive structure 130 may be formed by one or more deposition steps, such as one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc., to form one or more metal material layers.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • forming the conductive structure 130 may include first forming a titanium (Ti) layer or a titanium nitride (TiN) layer in contact with the semiconductor heterostructure layer 110 on the surfaces of the trenches 131T, 132T, and 133T, and then further forming a layer Or multilayer metal material layers, such as at least one of the following: Ti (titanium), aluminum (Al), nickel (Ni), copper (Cu), titanium nitride (TiN), gold (Au), platinum (Pt) , Palladium (Pd), tungsten (W) and their alloys, and completely fill the trenches 131T, 132T, and 133T to form conductive fingers 131, 132, and 133.
  • Ti titanium
  • TiN titanium nitride
  • the semiconductor device 100 is annealed at 750°C-950°C. In some embodiments, the semiconductor device 100 may be annealed between 800°C and 900°C.
  • the conductive fingers 131, 132, and 133 of the conductive structure 130 and the semiconductor heterostructure layer 110 form an ohmic junction.
  • the step of FIG. 10C may be replaced by FIG. 10D to form the semiconductor device 300 of FIG. 3.
  • FIG. 10D shows that a conductive material is deposited in a plurality of trenches 131T, 132T, and 133T to form a conductive structure 330 having conductive fingers 331, 332, and 333, and then annealing is further performed.
  • FIG. 10D The difference between FIG. 10D and FIG. 10C is that the conductive material covers the bottom and side surfaces of the trenches 131T, 132T, and 133T, so that the conductive fingers 331, 332, and 333 still have trenches.
  • Forming the conductive structure 330 may include first forming a titanium (Ti) layer or a titanium nitride (TiN) layer on the surface of the trenches 131T, 132T, and 133T to contact the semiconductor heterostructure layer 110, and then further forming one or more layers of metal materials , Such as at least one of the following: Ti (titanium), aluminum (Al), nickel (Ni), copper (Cu), titanium nitride (TiN), gold (Au), platinum (Pt), palladium (Pd), Tungsten (W) and its alloys.
  • the conductive structure 330 may be formed by one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc., and a portion of the trenches are left in the conductive fingers 331, 332, and 333.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the semiconductor device 100 is annealed at 750°C-950°C. In some embodiments, the semiconductor device 100 may be annealed between 800°C and 900°C.
  • the conductive fingers 331, 332, and 333 of the conductive structure 330 and the semiconductor heterostructure layer 110 form an ohmic junction.
  • the terms “approximately”, “substantially”, “substantially” and “about” are used to describe and explain small changes.
  • the term may refer to an example in which the event or situation occurs precisely and an example in which the event or situation occurs in close proximity.
  • the term when used in combination with a value, can refer to a range of variation less than or equal to ⁇ 10% of the stated value, for example, less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3% , Less than or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%.
  • the difference between two values is less than or equal to ⁇ 10% of the average value of the value (for example, less than or equal to ⁇ 5%, less than or equal to ⁇ 4%, less than or equal to ⁇ 3%, less than Or equal to ⁇ 2%, less than or equal to ⁇ 1%, less than or equal to ⁇ 0.5%, less than or equal to ⁇ 0.1%, or less than or equal to ⁇ 0.05%), then the two values can be considered “substantially” or " About” is the same.
  • substantially parallel may refer to a range of angular variation less than or equal to ⁇ 10° relative to 0°, for example, less than or equal to ⁇ 5°, less than or equal to ⁇ 4°, less than or equal to ⁇ 3°, Less than or equal to ⁇ 2°, less than or equal to ⁇ 1°, less than or equal to ⁇ 0.5°, less than or equal to ⁇ 0.1°, or less than or equal to ⁇ 0.05°.
  • substantially perpendicular may refer to an angular variation range of less than or equal to ⁇ 10° relative to 90°, for example, less than or equal to ⁇ 5°, less than or equal to ⁇ 4°, less than or equal to ⁇ 3°, Less than or equal to ⁇ 2°, less than or equal to ⁇ 1°, less than or equal to ⁇ 0.5°, less than or equal to ⁇ 0.1°, or less than or equal to ⁇ 0.05°.
  • the two surfaces can be considered to be coplanar or substantially coplanar.
  • the terms "conductive,””electricallyconductive,” and “conductivity” refer to the ability to transmit electrical current.
  • Conductive materials generally indicate those materials that exhibit little or zero resistance to current flow.
  • One measure of conductivity is Siemens/meter (S/m).
  • the conductive material is a material with a conductivity greater than approximately 10 4 S/m (for example, at least 10 5 S/m or at least 10 6 S/m).
  • the electrical conductivity of a material can sometimes change with temperature. Unless otherwise specified, the electrical conductivity of the material is measured at room temperature.
  • a/an and “the” may include plural indicators.
  • the provision of a component “on” or “on” another component may cover the case where the former component is directly on the latter component (for example, in physical contact with the latter component), and one or more A situation in which an intermediate component is located between the previous component and the next component.

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Abstract

本公开的一些实施例提供一种半导体器件及其制造方法。所述半导体器件包含：半导体异质结构层和导电结构。半导体异质结构(heterostructure)层，其包含交替的第一半导体材料层及第二半导体材料层，其中每一相邻的第一半导体材料层与第二半导体材料层之间可产生二维电子气体(2DEG)。导电结构，包含复数个导电指自半导体异质结构层的表面延伸进入所述半导体异质结构层，其中复数个导电指沿着大体上与表面平行的第一方向上排列，且复数个导电指的长度沿着第一方向递增，使得每一导电指的端部分别位于不同深度的第二半导体材料层且不接触2DEG。

Description

具有多通道异质结构的半导体器件及其制造方法 技术领域
本揭露系关于一种半导体器件及其制造方法，特别系关于具有多通道异质结构的异质结构器件及其制造方法。
背景技术
高功率器件常使用具有较大能隙的半导体材料形成场发射电晶体(FET)，例如GaN、AlN等大能隙的半导体材料，以提供大崩溃电压及低反向电流。
在叠层半导体结构的FET中，形成「通道层」的窄能隙半导体相邻于形成「电子供应层」的宽能隙半导体，这使得电子供应层产生高浓度的电子，累积于通道层与电子供应层的接口，这些这些累积的电子形成薄片状分布，亦可称之为「二维电子气体(two-dimensional electron gas；2DEG)」。
2DEG具有非常高的电子迁移率，可应用于在高速电子组件及功率组件。
发明内容
本公开的一些实施例提供一种半导体器件。所述半导体器件包含：半导体异质结构(heterostructure)层，其包含交替的第一半导体材料层及第二半导体材料层，其中每一相邻的第一半导体材料层与第二半导体材料层之间可产生二维电子气体(2DEG)；及导电结构，包含复数个导电指自半导体异质结构层的表面延伸进入半导体异质结构层，其中复数个导电指沿着大体上与表面平行的一方向上排列，且复数个导电指的长度沿着所述所述方向递增，使得每一导电指的端部分别位于不同的第二半导体材料层且不接触2DEG。
本公开的另一些实施例提供一种半导体器件。所述半导体器件包含：半导体异质结构层，其包含交替的第一半导体材料层及第二半导体材料层，其中每一相邻的第一半导体材料层与第二半导体材料层之间可产生2DEG；漏极结构，包含复数个第一导电指自半导体异质结构层的表面延伸进入半导体异质结构层，其中复数个第一导电指沿着大体上与所述表面平行的一方向上排列，且所述复数个第一导电指的长度沿着所述方向递增，使得每一第一导电指的端部分别位于不同的第二半导体材料层内且不接触2DEG；源极结构，包含复数个第二导电指自所述表面延伸进入所述半导体异质结构层，其中所述复数个第二导电指沿着所述方向排列，且所述复数个第二导电指的长度沿着所述方向 递减，每一第二导电指的端部分别位于不同的第二半导体材料层内且不接触2DEG；及介于漏极结构与源极结构之间的闸极结构。
本公开的一些实施例提供一种制造半导体器件的方法，包含：形成半导体异质结构层，包含交替地形成第一半导体材料层及第二半导体材料层，其中每一相邻的第一半导体材料层与第二半导体材料层之间可产生2DEG；在半导体异质结构层的表面图案化以沿着大体上与所述半导体异质结构层的表面平行的第一方向上形成复数个开口；及由所述复数个开口蚀刻所述半导体异质结构层，以在所述半导体异质结构层中形成复数个沟槽，其中所述复数个沟槽的沿所述第一方向递增，并且蚀刻停止于不同的第二半导体层内，且每一沟槽的底部不接触2DEG；在复数个沟槽中沉积导电材料，以形成导电结构；及进行退火。
附图说明
当结合附图阅读时，从以下具体实施方式容易理解本公开的各方面。应注意，各个特征可以不按比例绘制。实际上，为了论述清晰起见，可任意增大或减小各种特征的尺寸。
图1A为根据本案之某些实施例的半导体器件的截面图；
图1B为半导体器件中电子在二维电子气通道中流动的示意图；
图2为根据本案之某些实施例的导电指的放大图；
图3为根据本案之某些实施例的半导体器件的截面图；
图4为比较性实施例的半导体器件之截面图；
图5为比较性实施例的半导体器件之截面图；
图6A为根据本案之某些实施例的半导体器件的截面图；
图6B为半导体器件中电子在二维电子气通道中流动的示意图；
图7为根据本案之某些实施例的半导体器件的截面图；
图8为根据本案之某些实施例的半导体器件的截面图；
图9为根据本案之某些实施例的半导体器件的截面图；
图10A、10B、10C及10D显示为根据本案之某些实施例之形成半导体器件的步骤。
具体实施方式
以下公开内容提供用于实施所提供的标的物的不同特征的许多不同实施例或实例。下文描述组件和布置的具体实例。当然，这些只是实例且并不意欲为限制性的。在本公开中，在以下描述中对第一特征形成在第二特征上或上方的叙述可包含第一特征与第二 特征直接接触形成的实施例，并且还可包含额外特征可形成于第一特征与第二特征之间从而使得第一特征与第二特征可不直接接触的实施例。另外，本公开可以在各种实例中重复参考标号和/或字母。此重复是出于简化和清楚的目的，且本身并不规定所论述的各种实施例和/或配置之间的关系。
下文详细论述本公开的实施例。然而，应了解，本公开提供的许多适用概念可实施在多种具体环境中。所论述的具体实施例仅仅是说明性的且并不限制本公开的范围。
图1A为根据本案之某些实施例的半导体器件100之截面图。半导体器件100包含半导体异质结构层110及导电结构130。依据本揭露的部分实施例，半导体器件100还包括缓冲层140及载体150。
载体150可以系半导体基板、玻璃基板、PCB基板、挠性基板(例如：聚合物、纸)或任何可乘载半导体异质结构层110之介质。半导体异质结构层110与载体150之间可进一步包含一缓冲层140。在部分实施例中，缓冲层140形成于半导体材料层111及载体150之间。在部分实施例中，缓冲层140可以系AlGaN及GaN所组成的超晶格结构。缓冲层140的厚度范围系约0.5μm–10μm。
半导体异质结构层110包含交替的半导体材料层111及半导体材料层112堆叠。半导体材料层111及半导体材料层112是利用具有不同能隙的半导体材料所构成，使得每一相邻的半导体材料层111及半导体材料层112之间可产生2DEG(未图示)。
半导体材料层111及半导体材料层112系由具有不同能隙的半导体材料所组成。压电性在自发极化和压电极化的双重作用下在半导体材料层111及半导体材料层112的界面处形成2DEG。相较于半导体材料层111，半导体材料112具有更宽的能隙。例如：在一实施例中，半导体材料层111系GaN，能隙约为3.4eV；半导体材料层112系AlGaN，能隙为4eV。
依据本揭露的部分实施例，半导体材料层111及半导体材料层112分别可包括III-V族化合物。半导体材料层111及半导体材料层112之组合可包括，但不限于，以下之一者：GaN及AlGaN之组合、GaN及InAlN之组合、GaN及AlN之组合、GaN及InAlGaN之组合。
在一实施例中，半导体异质结构层110的厚度范围系8nm–1000nm。在一实施例中，半导体异质结构层110中每一层半导体材料层111的厚度范围系2nm–70nm。在一较佳实施例中，每一层半导体材料层111的厚度范围系3nm–20nm。半导体异质结构层110中的半导体层111的厚度可大于或等于半导体层112。在一实施例中，半导体异质结构层110中每一层半导体材料层112的厚度范围系2nm–30nm。在一较佳实施 例中，每一层半导体材料层112的厚度范围系3nm–10nm。
在部分实施例中，半导体材料层111及半导体材料层112之间可包含中介层(未显示于图中)，其中中介层可包含AlN，厚度可为约1nm。
依据本揭露，半导体材料层111及半导体材料层112之间的2DEG为半导体器件提供多通道以传导电子，并且形成多通道异质结构器件。在部分实施例中，半导体异质结构层110中半导体材料层111及半导体材料层112之间的2DEG至少2层，在较佳实施例中，2DEG的层数范围系2层至10层之间，
导体结构130包括导电指131、132及133，导电指131、132及133大体上沿着与半导体异质结构层110的表面110a平行的方向排列。每一导电指的端部131E、132E及133E位于不同深度的半导体材料层112，并且不接触2DEG。
在本实施例中，导体结构130包括3个导电指131、132及133。然而，依据本揭露，导电指的数目可以是任何大于或等于2的整数，并不以上述实施例为限。依据本揭露的部分较佳实施例，导体结构130可包含2到10个导电指。在部分实施例中，导电指的数量与半导体材料层111及半导体材料层112之间接口的数量相关连。以图1A为例，半导体材料层111及半导体材料层112之间接口的数量与导电指的数量都是三。依据其他实施例，半导体材料层111及半导体材料层112之间接口的数量与导电指的数量可以都是四、五或其他整数。
导电指可以如图1A所示沿着X方向排列，并且导电指131、132及133深入半导体异质结构层110的长度沿着X方向逐渐增加，亦即导电指131最短；导电指132次之；导电指133最长。然而，在其他实施例中，导电指131、132及133也可以沿着其他大体上与表面110a平行的方向排列，且导电指131、132及133深入半导体异质结构层110的长度也会沿着排列方向逐渐增加。
在本揭露之某些实施例中，导电指的宽度实质上相同。在本揭露之某些较佳实施例中，导电指的宽度随着长度增加而增加。例如，图1A中导电指131、132及133沿X方向逐渐增加长度，也沿着X方向逐渐增加宽度。在部分较佳实施例中，导电指的长度范围系1nm–1000nm，宽度范围系5nm–800nm。在部分更佳实施例中，导电指的长度范围系1nm–300nm，宽度范围系5nm–200nm。
图1B为半导体器件100中电子在二维电子气通道中流动的示意图。如图1B所示，每一相邻的半导体材料层111及半导体材料层112之间可产生二维电子气体2DEG。因此，在半导体异质结构层110的不同深度(如图1B中所示Z方向)中产生多个2DEG 115、117、119，这些2DEG 115、117、119沿着半导体材料层111及半导体材料层112的界 面延伸。
当半导体器件与电源接通时，电子会在2DEG通道内流动而行成电子的流动路径。在图1B的实施例中，2DEG 115、117、119中的电子皆往X方向流动。在接近任一导电指处，电子将经由所接近的导电指与半导体材料层112之间的欧姆接触(Ohmic contact)进入导电指。例如，在最接近表面110a的2DEG 115中，电子首先会流经导电指131附近。当电子接近导电指131时，主要经由导电指131与半导体材料层112之间的欧姆接触进入导电指131，此时电子流动路径系如图1B所示的EP1；在表面110a下第二层2DEG117中，电子首先会流经导电指132附近。当电子接近导电指132时，主要经由导电指132与半导体材料层112之间的欧姆接触进入导电指132，此时电子流动路径系EP2；同理，在最距离表面110a最远的2DEG 119中，电子首先会流经导电指133附近。当电子接近导电指133时，主要经由导电指133与半导体材料层112之间的欧姆接触进入导电指133，此时电子流动路径系EP3。
由于在不同深度的2DEG115、117、119中流动的电子会经由不同深度的导电指131、132及133进入导电结构130，如此可以达到电子分流的效果。
本揭露的导电指可以由一或多层导电材料层所构成。以图1A的导电指为例，其系由单一种金属材料层形成。在部分实施例中，导电指可包括以下导电材料之一者：Ti(钛)、铝(Al)、镍(Ni)、铜(Cu)、氮化钛(TiN)、金(Au)、铂(Pt)、钯(Pd)、钨(W)及其合金。
然而，本揭露所使用的导电指并不以图1A的实施例为限。例如在图2的实施例中，导电指230可以包含金属材料层230a及金属材料层230b，其中金属材料层230b与半导体异质结构层110接触，而金属材料层230a于形成220b上。金属材料层230b可以系一或多层金属材料层，且可包含以下至少之一者：Ti(钛)、铝(Al)、镍(Ni)、铜(Cu)、氮化钛(TiN)、金(Au)、铂(Pt)、钯(Pd)、钨(W)及其合金。金属材料层230a可包含以下至少之一者：钛(Ti)层、铝(Al)、铜(Cu)、金(Au)、铂(Pt)、钯(Pd)及钨(W)层。金属材料层230a可降低导电指230的电阻。
图3为根据本案之某些实施例的半导体器件300之截面图。半导体器件300包含半导体异质结构层110及导电结构330。导电结构330包含有导电指331、332、333。在部分实施例中导电指331、332、333可以由一或多层金属材料形成且可包含沟槽。亦即，导电指331、332、333的中心未由金属材料所完全填充。
导电指331、332、333可包含以下至少之一者：Ti(钛)、铝(Al)、镍(Ni)、铜(Cu)、氮化钛(TiN)、金(Au)、铂(Pt)、钯(Pd)、钨(W)及其合金。在某些实施例中，导电指可包含一或多层金属材料层以及介于一或多层金属材料层与半导体异质结构层110之间的钛 层或氮化钛(TiN)层。
图4为一比较性实施例的半导体器件400之截面图。半导体器件400包含半导体异质结构层110、导电结构430、缓冲层140及载体150。半导体器件400中部分组件与图1的半导体器件100的部分组件具有相同编号，且系由类似材质构成，故不在此重复赘述。
导电结构430包含有导电指431自半导体异质结构层110的表面沿着方向Z往半导体异质结构层110延伸。2DEG中的电子进入导电指431时，集聚在2DEG与导电指接口附近，即电子进入或离开导电指431的接口将发生电流集聚，进而温度升高、不易散热，进而降低半导体器件400的电性效能。
图5为另一比较性实施例的半导体器件500之截面图。半导体器件500包含半导体异质结构层110及导电结构530。半导体器件500中部分组件与图1的半导体器件100的部分组件具有相同编号，且系由类似材质构成，故不在此重复赘述。
导电结构530形成于半导体异质结构层110的表面上，与半导体异质结构层110直接接触，并且与半导体异质结构层110的表面形成欧姆接面。然而，由于在半导体异质结构层110中电子主要在2DEG通道中流动，而2DEG，特别是距离导电结构530较远的2DEG，与导电结构530之间具有相当大的电阻，这将造成半导体器件500形成相当大的欧姆电阻。
图6A为根据本案之某些实施例的半导体器件600之截面图。半导体器件600包含半导体异质结构层110、漏极结构620、源极结构630及闸极结构640。依据本揭露的部分实施例，半导体器件600还包括缓冲层140及载体150。半导体器件600中部分组件与图1的半导体器件100的部分组件具有相同编号，且系由类似材质构成，故不在此重复赘述。
闸极结构640配置于漏极结构620及源极结构630之间，以控制漏极结构620及源极结构630之间电子的流动，进一步控制半导体器件600的导通与关断。
漏极结构620包含导电指621、622及623，导电指621、622及623大体上沿着与半导体异质结构层110的表面110a平行的方向排列。漏极结构620每一导电指的端部621E、622E及623E位于不同深度的半导体材料层112，并且不接触2DEG。
在本实施例中，漏极结构620包括3个导电指。然而，依据本揭露，漏极结构620导电指的数目可以是任何大于或等于2的整数，并不以上述实施例为限。依据本揭露的部分较佳实施例，漏极结构620可包含2到10个导电指。在部分较佳实施例中，导电指的数量与半导体材料层111及半导体材料层112之间接口的数量相关连。
依据本揭露之某些实施例中，导电指可以如图6A所示沿着X方向排列，并且导电指621、622及623深入半导体异质结构层110的长度沿着X方向逐渐增加，亦即导电指621最短；导电指622次之；导电指623最长。然而，在其他实施例中，漏极结构620的导电指621、622及623也可以沿着其他大体上与表面110a平行的方向排列。此时，漏极结构620的导电指621、622及623深入半导体异质结构层110的长度也会沿着排列方向逐渐增加。
在本揭露之某些较佳实施例中，每一导电指的宽度实质上相同。在本揭露之某些较佳实施例中，导电指的宽度随着长度增加而增加。例如，图6A中漏极结构620的导电指621、622及623沿X方向逐渐增加长度，也沿着X方向逐渐增加宽度。在部分较佳实施例中，漏极结构导电指的长度范围系1nm–1000nm，宽度范围系5nm–800nm。在部分更佳实施例中，漏极结构导电指的长度范围系1nm–300nm，宽度范围系5nm–200nm。
源极结构630包含导电指631、632及633，导电指631、632及633大体上沿着与半导体异质结构层110的表面110a平行的方向排列。源极结构630每一导电指的端部631E、632E及633E位于不同深度的半导体材料层112，并且不接触2DEG。
在本实施例中，源极结构630包括3个导电指。然而，依据本揭露，源极结构630导电指的数目可以是任何大于或等于2的整数，并不以上述实施例为限。依据本揭露的部分较佳实施例，源极结构630可包含2到10个导电指。在部分较佳实施例中，导电指的数量与半导体材料层111及半导体材料层112之间接口的数量相关连。
此外，导电指631、632及633可以如图6A所示沿着X方向排列，并且导电指631、632及633深入半导体异质结构层110的长度沿着X方向逐渐减小，亦即导电指631最短；导电指632次之；导电指633最长。然而，在其他实施例中，源极结构630的导电指631、632及633也可以沿着其他大体上与表面110a平行的方向排列。此时，源极结构630的导电指631、632及633深入半导体异质结构层110的长度也会沿着排列方向逐渐减小。
在本揭露之某些较佳实施例中，导电指631、632及633的宽度随着长度递减而递减。例如，图6A中导电指631、632及633沿X方向逐渐减小长度，也沿着X方向逐渐减小宽度。在部分较佳实施例中，源极结构导电指的长度范围系1nm–1000nm，宽度范围系5nm–800nm。在部分更佳实施例中，源极结构导电指的长度范围系1nm–300nm，宽度范围系5nm–200nm。
图6B为半导体器件600中电子在二维电子气通道中流动的示意图。如图6B所示， 每一相邻的半导体材料层111及半导体材料层112之间可产生2DEG。因此，在半导体异质结构层110的不同深度(如图6B中所示Z方向)可中产生多个2DEG 115、117、119，这些2DEG 115、117、119沿着半导体材料层111及半导体材料层112界面延伸。
当半导体器件与电源接通时，电子会在2DEG内流动而行成电子的流动路径。在图6B的实施例中，2DEG 115、117、119中的电子皆往X方向流动。在接近任一导电指处，电子将经由所接近的导电指与半导体材料层112之间的欧姆接触离开或进入所述导电指。例如，在最接近表面110a的2DEG 115中，电子从导电指631与半导体材料层112之间的欧姆接触离开源极结构630，进入2DEG 115，当电子接近漏极结构620的导电指621时，主要经由导电指621与半导体材料层112之间的欧姆接触进入漏极结构620，此时电子流动路径系如图6B所示的EP61；在表面110a下第二层2DEG 117中，电子从导电指632与半导体材料层112之间的欧姆接触离开源极结构630，进入2DEG 117，当电子接近漏极结构620的导电指622时，主要经由导电指622与半导体材料层112之间的欧姆接触进入漏极结构620，此时电子流动路径系如图6B所示的EP62；同理，在距离表面610a最远的2DEG 119中，电子从导电指633与半导体材料层112之间的欧姆接触离开源极结构630，进入2DEG 117，当电子接近漏极结构620的导电指623时，主要经由导电指623与半导体材料层112之间的欧姆接触进入漏极结构620，此时电子流动路径系如图6B所示的EP63。
由于在不同深度的2DEG 115、117、119中流动的电子会经由不同深度的导电指631、632及633离开源极结构630，并且经由不同深度的导电指621、622及623进入漏极结构620，如此可以达到电子分流的效果。
然而，本揭露的漏极结构620与源极结构630并不以图6A的实施例为限。在部分实施例，漏极结构620与源极结构630分别可包含钛(Ti)层或氮化钛(TiN)层与半导体异质结构层110接触。而在与半导体异质结构层110接触的钛(Ti)层或氮化钛(TiN)层上可进一步包含一或多层金属材料层，包括以下导电材料至少之一者：Ti(钛)、铝(Al)、镍(Ni)、铜(Cu)、氮化钛(TiN)、金(Au)、铂(Pt)、钯(Pd)、钨(W)及其合金。在部分实施例，漏极结构620与源极结构630的导电指也可如同图2的导电指包括多层金属材料层。
在某些实施例中，漏极结构620的导电指621、622及623与源极结构630的导电指631、632及633可以系由导电材料完全填充。在某些实施例中，漏极结构620的导电指621、622及623及/或源极结构630的导电指631、632及633中的一或多个导电指可包含沟槽，亦即导电指未由导电材料所完全填充。
图7为根据本案之某些实施例的半导体器件700之截面图。半导体器件700包含半 导体异质结构层110、漏极结构620、源极结构730及闸极结构640。依据本揭露的部分实施例，半导体器件700还包括缓冲层140及载体150。半导体器件700中的部分组件与图6A半导体器件600的部分组件具有相同编号，且系由类似材质构成，故不在此重复赘述。
闸极结构640配置于漏极结构620及源极结构730之间，以控制漏极结构620与源极结构730之间电子的流动，进一步控制半导体器件700的导通与关断。
源极730包含有导电指731，导电指731自半导体异质结构层110的表面110a沿着方向Z往半导体异质结构层110延伸。
当漏极结构620与源极730之间为导通状态时，电子将离开源极结构730进入各个深度的2DEG，然后经由导电指621、622及623进入漏极结构620。
依据本揭露的部分实施例，上述源极结构与漏极结构的编号可互换，也就是源极结构由620表示、漏极结构由730表示，此时电流方向会相反，亦即电子将由经由导电指621、622及623离开源极结构620进入各个深度的2DEG，然后进入漏极结构730。
图8为根据本案之某些实施例的半导体器件800之截面图。半导体器件800包含半导体异质结构层110、漏极结构620、源极830及闸极结构640。依据本揭露的部分实施例，半导体器件800还包括缓冲层140及载体150。半导体器件800中的部分组件与图6A半导体器件600的部分组件具有相同编号，且系由类似材质构成，故不在此重复赘述。
源极830形成于半导体异质结构层110的表面110a上，与半导体异质结构层110直接接触，源极830与半导体异质结构层110的表面110a形成欧姆接面。
当半导体器件800与电源接通，漏极结构620与源极830之间为导通状态时，电子将离开源极830并进入各个深度的2DEG，然后经由导电指621、622及623进入漏极结构620。
依据本揭露的部分实施例，上述源极结构与漏极结构的编号可互换，也就是源极结构由620表示、漏极结构由830表示，此时电流方向会相反，亦即电子将由经由导电指621、622及623离开源极结构620进入各个深度的2DEG，然后进入漏极结构830。
图9为根据本案之某些实施例的半导体器件900之截面图。半导体器件900可以是二极管，包含半导体异质结构层110，阴极结构920及阳极结构940。依据本揭露的部分实施例，半导体器件900还包括缓冲层140及载体150。半导体器件900中的部分组件与图6A半导体器件600的部分组件具有相同编号，且系由类似材质构成，故不在此重复赘述。
阴极结构920包含导电指921、922及923，导电指921、922及923大体上沿着与半导体异质结构层110的表面110a平行的方向排列。阴极结构920每一导电指的端部指921E、922E及923E位于不同深度的半导体材料层112，并且不接触2DEG。
阳极结构940形成于半导体异质结构层110的表面110a上，与半导体异质结构层110直接接触，阳极结构940与半导体异质结构层110的表面110a形成萧基接面。
当半导体器件900与电源接通，电子将经由导电指921、922及923离开阴极结构920并进入各个深度的2DEG，然后进入阳极结构940，如此可以达到阴极结构处电子分流的效果。
图10A、10B及10C显示一种制造半导体器件100的步骤。
图10A显示于载体150上交替地形成半导体材料层111及半导体材料层112堆栈，以形成半导体异质结构层110。半导体材料层111及半导体材料层112分别可藉由磊晶成长、物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)等方式之任一或多者形成。
在部分实施例中，在形成半导体异质结构层110之前，可先在载体150上形成一缓冲层140。缓冲层140可藉由磊晶成长、物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)等方式之一或多者形成。
图10B显示在半导体异质结构层110上形成复数个沟槽131T、132T及133T大体上沿着与半导体异质结构层110的表面110a平行的方向排列。本揭露的某些实施例系图案化(例如微影方式)半导体异质结构层110的表面110a，以形成复数个开口。经复数个开口，藉由对半导体异质结构层110蚀刻，以形成复数个沟槽131T、132T及133T。复数个沟槽可以藉由化学湿式蚀刻、干式蚀刻，例如电浆蚀刻、反应离子蚀刻(RIE)，等方式之一或多者形成。
在一实施例中，复数个开口经设计为不同尺寸的开口。由于每一开口的尺寸不同，将造成半导体异质结构层110在每一开口的蚀刻速度不同。例如在湿式及/或干式蚀刻中，开口尺寸越大，在半导体异质结构层110中往Z方向的蚀刻速度越快。
在本实施例中，在表面110a沿着X方向逐渐增加开口的尺寸，则经蚀刻制程，复数个沟槽131T、132T及133T的深度沿着方向X逐渐增加。然而，在其他实施例中，复数个沟槽131T、132T及133T也可以沿着其他大体上与表面110a平行的方向排列。此时，复数个复数个沟槽131T、132T及133T深入半导体异质结构层110的长度也会沿着排列方向逐渐增加。藉由设计不同尺寸的开口，使半导体异质结构层110在方向Z蚀刻速度不同，可以一次性地达成不同深度的沟槽蚀刻，而避免繁复的蚀刻程序。
依据本揭露之部分较佳实施例，复数个开口的尺寸经设计使得，复数个沟槽131T、132T及133T可一次性的蚀刻完成，且每一沟槽131T、132T及133T的端部131TE、132TE及133TE位于半导体异质结构层110中不同深度的半导体材料层112，并且不接触2DEG。
复数个开口的尺寸设计会随半导体异质结构层110的材质不同而有所调整，例如GaN/AlGaN/GaN、GaN/InAlN/GaN、GaN/AlN/GaN、GaN/InAlGaN/GaN等结构的半导体异质层有各自的开口的尺寸设计。在一实施例中，半导体异质结构层110中的半导体材料层111为GaN，每一层半导体材料层111的厚度大约10nm；半导体材料层112为AlGaN，每一层半导体材料层112的厚度大约5nm。藉由以氯为基的蚀刻剂，例如包含Cl 2及BCl 3至少之一者，进行干式蚀刻，表1示例性地显示一次性蚀刻不同开口宽度及沟槽深度之复数个沟槽。
沟槽 开口宽度 沟槽深度
131T 5-100nm 1-10nm
132T 100-200nm 10-25nm
133T 200-800nm 25-40nm
表1
图10C显示在复数个沟槽131T、132T及133T中沉积导电材料，以形成具有导电指131、132及133的导电结构130，并且进一步进行退火以形成图1的半导体器件100。
导电结构130可以藉由一或多个沉积步骤，例如物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)等之一或多者方式形成一或多层金属材料层。
在部分实施例中，形成导电结构130可包含在沟槽131T、132T及133T的表面首先形成钛(Ti)层或氮化钛(TiN)层与半导体异质结构层110接触，再进一步形成一或多层金属材料层，例如以下至少之一者：Ti(钛)、铝(Al)、镍(Ni)、铜(Cu)、氮化钛(TiN)、金(Au)、铂(Pt)、钯(Pd)、钨(W)及其合金，并且完全填充沟槽131T、132T及133T而形成导电指131、132及133。形成导电结构130之后，在750℃-950℃下对半导体器件100进行退火。在部分实施例中，可以在800℃-900℃之间对半导体器件100进行退火。使导体结构130的导电指131、132及133与半导体异质结构层110中形成欧姆接面。
在本揭露的部分实施例中，图10C的步骤可以被图10D取代以形成图3的半导体器件300。图10D显示在复数个沟槽131T、132T及133T中沉积导电材料，以形成具有导电指331、332及333的导电结构330，并且进一步进行退火。
图10D与图10C不同之处在于导电材料覆盖沟槽131T、132T及133T的底部与侧 面，使得导电指331、332及333中仍具有沟槽。
形成导电结构330可包含在沟槽131T、132T及133T的表面首先形成钛(Ti)层或氮化钛(TiN)层与半导体异质结构层110接触，再进一步形成一或多层金属材料层，例如以下至少之一者：Ti(钛)、铝(Al)、镍(Ni)、铜(Cu)、氮化钛(TiN)、金(Au)、铂(Pt)、钯(Pd)、钨(W)及其合金。导电结构330可以藉由物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)等方式之一或多者形成，并在导电指331、332及333中保留部分沟槽。
形成导电结构330之后，在750℃-950℃下对半导体器件100进行退火。在部分实施例中，可以在800℃-900℃之间对半导体器件100进行退火。使导体结构330的导电指331、332及333与半导体异质结构层110中形成欧姆接面。
如本文中所使用，术语“近似地”、“基本上”、“实质”和“约”用于描述和解释小的变化。当与事件或情况结合使用时，所述术语可指事件或情况精确发生的例子以及事件或情况极近似地发生的例子。举例来说，当与数值结合使用时，术语可指小于或等于所述数值的±10％的变化范围，例如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果两个数值之间的差小于或等于所述值的平均值的±10％(例如，小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％)，那么可认为所述两个数值“基本上”或“约”相同。举例来说，“基本上”平行可以指相对于0°的小于或等于±10°的角度变化范围，例如，小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°,或小于或等于±0.05°。举例来说，“基本上”垂直可以指相对于90°的小于或等于±10°的角度变化范围，例如，小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°，或小于或等于±0.05°。
如果两个表面之间的位移不超过5μm、不超过2μm、不超过1μm或不超过0.5μm，那么可认为所述两个表面是共面的或基本上共面的。
如本文中所使用，术语“导电(conductive)”、“导电(electrically conductive)”和“电导率”指代传送电流的能力。导电材料通常指示对电流流动呈现极少或零对抗的那些材料。电导率的一个量度是西门子(Siemens)/米(S/m)。通常，导电材料是电导率大于近似地10 4S/m(例如，至少10 5S/m或至少10 6S/m)的一种材料。材料的电导率有时可随温度而变化。除非另外规定，否则材料的电导率是在室温下测量的。
如本文中所使用，除非上下文另外明确规定，否则单数术语“一(a/an)”和“所述”可包 含复数指示物。在一些实施例的描述中，组件提供于另一组件“上”或“之上”可涵盖前一组件直接在后一组件上(例如，与后一组件物理接触)的情况，以及一或多个中间组件位于前一组件与后一组件之间的情况。
虽然已参考本申请的特定实施例描述并说明本申请，但这些描述和说明并不限制本申请。所属领域的技术人员可清楚地理解，在不脱离如由所附权利要求书界定的本申请的真实精神和范围的情况下，可作出各种改变，且可在实施例内取代等效组件。所述图示可能未必按比例绘制。由于制造过程中的变数等等，本申请中的艺术再现与实际设备之间可能存在区别。可能存在并未特定说明的本申请的其它实施例。应将本说明书和图式视为说明性而非限定性的。可作出修改，以使特定情况、材料、物质组成、方法或过程适应于本申请的目标、精神和范围。所有此类修改都意图在此所附权利要求书的范围内。虽然本文中所公开的方法已参考按特定次序执行的特定操作加以描述，但可以理解，可在不脱离本申请的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序和分组并非本申请的限制。

Claims (38)

  1. 一种半导体器件，包含：
    半导体异质结构(heterostructure)层，其包含交替的第一半导体材料层及第二半导体材料层，其中每一相邻的第一半导体材料层与第二半导体材料层之间可产生二维电子气体(two-dimensional electron gas；2DEG)；及
    导电结构，包含复数个导电指自所述半导体异质结构层的表面延伸进入所述半导体异质结构层，其中所述复数个导电指沿着大体上与所述表面平行的第一方向上排列，且所述复数个导电指的长度沿着所述第一方向递增，使得每一导电指的端部分别位于不同深度的第二半导体材料层且不接触2DEG。
  2. 根据权利要求1所述的半导体器件，所述复数个导电指的宽度沿所述第一方向增加。
  3. 根据权利要求1所述的半导体器件，所述第一半导体材料层及所述第二半导体材料层之组合为以下之一者：GaN及AlGaN之组合、GaN及InAlN之组合、GaN及AlN之组合、GaN及InAlGaN之组合。
  4. 根据权利要求1所述的半导体器件，所述第一方向系电子在2DEG内的流动方向，或相反于电子在的2DEG内的流动方向。
  5. 根据权利要求1所述的半导体器件，所述导电结构包含一或多个金属材料层。
  6. 根据权利要求5所述的半导体器件，所述一或多个金属材料层包含钛层，所述钛层与所述半导体异质结构层接触。
  7. 根据权利要求1所述的半导体器件，所述第一半导体材料层及所述第二半导体材料层之间的2DEG的层数范围系2层至10层之间。
  8. 根据权利要求1所述的半导体器件，所述第一半导体的厚度范围系2nm–70nm。
  9. 根据权利要求8所述的半导体器件，所述第一半导体的厚度范围系3nm–20nm。
  10. 根据权利要求1所述的半导体器件，所述第二半导体的厚度范围系2nm–30nm。
  11. 根据权利要求10所述的半导体器件，所述第二半导体的厚度范围系3nm–10nm。
  12. 根据权利要求1所述的半导体器件，其中所述半导体异质结构层之厚度范围系8nm–1000nm。
  13. 根据权利要求1所述的半导体器件，所述导电指的长度范围系1nm–1000nm。
  14. 根据权利要求13所述的半导体器件，所述导电指的长度范围系1nm–300nm。
  15. 根据权利要求2所述的半导体器件，所述导电指的宽度范围系5nm–800nm。
  16. 根据权利要求15所述的半导体器件，所述导电指的宽度范围系5nm–200nm。
  17. 根据权利要求1所述的半导体器件，进一步包含：
    载体；及
    缓冲层，位于所述载体及所述半导体异质结构层之间。
  18. 根据权利要求17所述的半导体器件，其中所述缓冲层形成于第一半导体材料层及所述载体之间。
  19. 根据权利要求18所述的半导体器件，其中所述缓冲层系由AlGaN及GaN所组成的超晶格结构。
  20. 根据权利要求17所述的半导体器件，所述缓冲层的厚度范围系约0.5μm–10μm。
  21. 一种半导体器件，包含：
    半导体异质结构层，其包含交替的第一半导体材料层及第二半导体材料层，其中每一相邻的第一半导体材料层与第二半导体材料层之间可产生二维电子气体(2DEG)；
    漏极结构，包含复数个第一导电指自所述半导体异质结构层的表面延伸进入所述半导体异质结构层，其中所述复数个第一导电指沿着大体上与所述表面平行的第一方向上排列，且所述复数个第一导电指的长度沿着所述第一方向递增，使得每一第一导电指的端部分别位于不同深度的第二半导体材料层内且不接触2DEG；
    源极结构，包含复数个第二导电指自所述表面延伸进入所述半导体异质结构层，其中所述复数个第二导电指沿着所述第一方向排列，且所述复数个第二导电指的长度沿着所述第一方向递减，每一第二导电指的端部分别位于不同深度的第二半导体材料层内且不接触2DEG；及
    介于漏极结构与源极结构之间的闸极结构。
  22. 根据权利要求21所述的半导体器件，所述复数个第一导电指的宽度沿所述第一方向增加，且所述复数个第二导电指的宽度沿所述第一方向递减。
  23. 根据权利要求21所述的半导体器件，所述第一半导体材料层及所述第二半导体材料层之组合为以下之一者：GaN及AlGaN之组合、GaN及InAlN之组合、GaN及AlN之组合、GaN及InAlGaN之组合。
  24. 根据权利要求21所述的半导体器件，所述第一方向系电子在2DEG内的流动方向，或相反于电子在的2DEG内的流动方向。
  25. 根据权利要求21所述的半导体器件，所述第一半导体材料层及所述第二半导体材料 层之间的2DEG的层数范围系2层至10层之间。
  26. 根据权利要求21所述的半导体器件，所述第一半导体的厚度范围系2nm–70nm。
  27. 根据权利要求26所述的半导体器件，所述第一半导体的厚度范围系3nm–20nm。
  28. 根据权利要求21所述的半导体器件，所述第二半导体的厚度范围系2nm–30nm。
  29. 根据权利要求28所述的半导体器件，所述第二半导体的厚度范围系3nm–10nm。
  30. 根据权利要求21所述的半导体器件，其中所述半导体异质结构层之厚度范围系8nm–1000nm。
  31. 根据权利要求21所述的半导体器件，所述第一与第二导电指的长度范围系1nm–1000nm。
  32. 根据权利要求31所述的半导体器件，所述第一与第二导电指的长度范围系1nm–300nm。
  33. 根据权利要求21所述的半导体器件，所述第一与第二导电指的宽度范围系5nm–800nm。
  34. 根据权利要求33所述的半导体器件，所述第一与第二导电指的宽度范围系5nm–200nm。
  35. 一种制造半导体器件的方法，包含：
    形成半导体异质结构层，包含交替地形成第一半导体材料层及第二半导体材料层，其中每一相邻的第一半导体材料层与第二半导体材料层之间可产生二维电子气体(two-dimensional electron gas；2DEG)；
    在所述半导体异质结构层的表面图案化以沿着大体上与所述半导体异质结构层的表面平行的第一方向上形成复数个开口；及
    由所述复数个开口蚀刻所述半导体异质结构层，以在所述半导体异质结构层中形成复数个沟槽，其中所述复数个沟槽的深度沿所述第一方向递增，并且蚀刻停止于不同深度的第二半导体层内，且每一沟槽的底部不接触2DEG；
    在复数个沟槽中沈积导电材料，以形成导电结构；及
    在退火温度下进行退火。
  36. 根据权利要求35所述制造半导体器件的方法，其中所述复数个开口的横截面积沿所述第一方向递增。
  37. 根据权利要求36所述制造半导体器件的方法，其中所述复数个开口的横截面积经设计使得可在单一次蚀刻中形成具有不同深度的所述复数个构槽。
  38. 根据权利要求35所述制造半导体器件的方法，进一步包含：
    在载体上形成缓冲层；
    在所述缓冲层上形成所述半导体异质结构层。
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