WO2021208692A1 - 一种掩膜版的布局方法及装置、掩膜版 - Google Patents

一种掩膜版的布局方法及装置、掩膜版 Download PDF

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Publication number
WO2021208692A1
WO2021208692A1 PCT/CN2021/082795 CN2021082795W WO2021208692A1 WO 2021208692 A1 WO2021208692 A1 WO 2021208692A1 CN 2021082795 W CN2021082795 W CN 2021082795W WO 2021208692 A1 WO2021208692 A1 WO 2021208692A1
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WIPO (PCT)
Prior art keywords
marking
pattern
mask
cutting
patterns
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PCT/CN2021/082795
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English (en)
French (fr)
Inventor
李静
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长鑫存储技术有限公司
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Priority to US17/310,664 priority Critical patent/US20220320001A1/en
Publication of WO2021208692A1 publication Critical patent/WO2021208692A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70—Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines

Definitions

  • the present disclosure relates to the field of semiconductor layout technology, and in particular to a mask layout method and device, and a mask.
  • the photolithography process is the most important circuit pattern transfer process.
  • the mask is an important material for realizing the photolithography process and can be used to make the circuit layout of the semiconductor chip.
  • the IC design company first designs the wafer circuit diagram, and the mask company designs the mask frame data, and merges the wafer circuit diagram and the mask frame data to form a mask.
  • the mask frame data generally includes marks of various process and electrical parameters related to the production process. According to the required marking graphics and chip size, the size of various marking graphics can be calculated, and the marking graphics that need to be split are manually divided into multiple marking units of different lengths, and manual layout and setting are performed , The split and layout process makes the entire manual layout process cumbersome and complicated, resulting in a lot of waste of labor costs, and the layout structure is not highly optimized, and it has the shortcomings of instability and inaccuracy.
  • the embodiments of the present disclosure provide a mask layout method and device, and a mask to solve the problem of low efficiency and poor accuracy of manual layout of marking graphics.
  • embodiments of the present disclosure provide a mask layout method, including:
  • a dicing lane is formed between every two adjacent chip patterns, and the dicing lane is used to set a marking pattern;
  • the marking pattern includes at least a first marking pattern;
  • a first marking pattern unit is provided to replace at least two adjacently arranged dividing units, and arranged on the cutting path; wherein, the first marking pattern unit is formed by splicing with the at least two adjacently arranged dividing units The graphics completely overlap.
  • embodiments of the present disclosure provide a mask layout device, including:
  • the chip pattern layout module is used to form chip patterns arranged in an array on the mask; a cutting channel is formed between every two adjacent chip patterns, and the cutting channel is used to set a marking pattern; the marking pattern Includes at least the first marking graphic;
  • a quantity acquiring module configured to acquire the set number of dividing units of the first marking pattern according to the measurement and alignment needs of the first marking pattern
  • An automatic layout module configured to sequentially arrange the set number of dividing units on the cutting path so that the first marking pattern does not cover other marking patterns
  • the unit replacement module is used to set a single unit of the first marking pattern to replace at least two adjacently arranged dividing units, and is arranged on the cutting path; wherein, the unit of the first marking pattern is adjacent to the at least two adjacent division units.
  • the graphics formed by the splicing of the set division units are completely overlapped.
  • the embodiments of the present disclosure also provide a mask, which adopts the layout method of the mask provided by any embodiment of the present disclosure for layout, and the mask includes chip patterns arranged in an array.
  • a dicing path is formed between every two adjacent chip patterns, and the dicing path is used to set a marking pattern; the marking pattern includes at least a first marking pattern.
  • the longer first mark pattern can be divided into smaller length division units.
  • the number of division units that need to be set on the cutting path can be known.
  • all the dividing units are automatically arranged in the cutting path.
  • the dividing units may be arranged separately, or multiple dividing units may be arranged adjacently. In this embodiment, at least two phases can be arranged.
  • the adjacently arranged dividing units are replaced by the corresponding first marking pattern monomer, and the size of the first marking pattern monomer is exactly the same as the size of the pattern formed by splicing at least two adjacently arranged dividing units, thereby completing the first marking The layout of the graphics.
  • the first marking pattern monomers of different lengths are formed by stacking different numbers of dividing units, so that the first marking pattern monomers can be filled in the gaps between other marking patterns, and the first marking pattern that is manually split is avoided. The situation that a single mark pattern cannot be placed in the above gap can realize the optimal position placement of various mark patterns on the cutting path, improve the space utilization rate of the cutting path, solve the problem of time-consuming manual placement, and improve the pendulum Put accuracy.
  • FIG. 1 is a schematic flowchart of a mask layout method provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of the structure of a mask provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a partial structure of a mask provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of another mask provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic flowchart of another mask layout method provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of another mask layout method provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic flowchart of another mask layout method provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a mask layout device provided by an embodiment of the present disclosure.
  • FIG. 1 is a schematic diagram of the flow chart of a mask layout method provided by an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a mask layout method for implementing various patterns of the mask by the layout device, especially It is the automatic layout of the first mark graphic that needs to be split.
  • the mask layout method of this embodiment includes the following steps:
  • S110 forming an array of chip patterns on the mask; a cutting lane is formed between every two adjacent chip patterns, and the cutting lane is used to set a marking pattern; the marking pattern includes at least a first marking pattern.
  • FIG. 2 is a schematic structural diagram of a mask provided by an embodiment of the present disclosure.
  • An array of chip patterns 11 is formed on the mask 1.
  • the chip patterns 11 correspond to the positions of the chips on the wafer during the actual photolithography process, and the chip pattern array formed by multiple chip patterns corresponds to the chip array on the wafer. And the chip pattern 11 has the same size as the corresponding chip.
  • a dicing lane 12 is formed between every two adjacent chip patterns 11. In one embodiment, as shown in FIG. 2, a circle of dicing lanes 12 is provided around the entire chip pattern array.
  • the cutting lane 12 is a frame part constituting the mask. A larger mask master can be cut by cutting through the dicing lane 12 to form the mask shown in FIG. 2.
  • the 3*3 chip pattern array shown in FIG. 2 is formed by cutting the dicing lane 12 from the mask mother board including the N*N chip pattern array, where N is an integer greater than 2.
  • Figure 2 shows a 3*3 chip pattern array.
  • the chip pattern array can also be a 4*3 or 2*6 chip pattern array. Not limited.
  • Alignment can form a marking pattern on the cutting lane 12.
  • S120 Acquire the set number of dividing units of the first mark pattern according to the measurement and alignment needs of the first mark pattern.
  • the marking pattern 13 at least includes the first marking pattern 131.
  • the set total length of the first marking pattern 131 on the entire mask is relatively long.
  • the set total length of the first marking pattern is 28790 ⁇ m. Therefore, when laying out the first marking graphic 131, the related art often divides the first marking graphic 131 into a single first marking graphic by means of manual layout, and sets them at different positions of the cutting lane 12. Specifically, as shown in FIG. 2 As shown, the first marking patterns are individually arranged in different cutting lanes 12 along the first direction X and the second direction Y. Because the marking pattern 13 includes a variety of marking patterns, some marking patterns need to be set at a fixed position.
  • the first marking pattern 131 In order to adapt to the placement rules of other marking patterns, the first marking pattern 131 needs to be divided to form first marking pattern units of different lengths.
  • errors are prone to occur during manual segmentation.
  • the length of the first marking graphic is too large, which causes other markings to be unable to be placed in the cutting lane 12 at the corresponding position, and the manual layout process is cumbersome and complicated, resulting in a great waste of labor costs.
  • the length of the first marking pattern unit described in this embodiment is the length along the extension direction of the cutting track, because in the width direction of the cutting track, the width of each first marking pattern unit is fixed. . This embodiment only limits the size and length of the first marking pattern along the extension direction of the cutting lane.
  • the first marking pattern 131 can be divided into smaller division units 131a, and a plurality of division units 131a are stacked one by one to form a single shape of the first marking pattern with a desired length.
  • FIG. 3 is a schematic diagram of a partial structure of a mask provided by an embodiment of the present disclosure. If the length of the gap formed between two other types of mark patterns 13 is d1, only five dividing units 131a can be placed, and the sixth dividing unit 131a cannot be placed. Compared with the manual placement method, if The length of the first marking figure unit manually split is greater than d1, the first marking figure unit cannot be placed here, and the first marking figure unit needs to be reset.
  • the operation process is very complicated, and in this example, if it can’t Putting the sixth dividing unit 131a, the figure formed by splicing the five dividing units 131a as the first marking pattern unit 131b is placed at this position, and no rework is required, which improves the layout efficiency.
  • the width d2 of the cutting lane 12 may be less than or equal to 80 ⁇ m; the width d3 of the first marking pattern 131 or the dividing unit 131a is less than or equal to 60 ⁇ m; the length of each dividing unit 131a ranges from 40 ⁇ m to 500 ⁇ m. In this embodiment, the width d3 of the first marking pattern 131 or the dividing unit 131a is smaller than the width d2 of the cutting lane 12.
  • the width d2 of the cutting lane 12 can be less than or equal to 60 ⁇ m
  • the width d3 of the dividing unit 131a can be It is less than or equal to 45 ⁇ m
  • the value range of the length d4 of each dividing unit 131a may be 40 ⁇ m to 500 ⁇ m.
  • segmentation units 131a with different lengths can be provided to meet different layout requirements.
  • segmentation units 131a with a length of 180 ⁇ m and 436 ⁇ m can be provided. If the dividing unit 131a is 180 ⁇ m in length, the dividing unit 131a with a length of 180 ⁇ m can be placed in the space.
  • a variety of different dividing units 131a can implement a more diverse dividing unit 131a, which is convenient for realizing an optimal layout.
  • each division unit 131a is equal, and the specifications of the division unit 131a are unified.
  • the length of the first marking pattern unit 131b can be intuitively obtained by the number of division units 131a, and further The simplified layout algorithm and layout process of the dividing unit 131a.
  • the set total length of the first marking pattern 131 is divided by the length d4 of the dividing unit 131a, and the value obtained is the value obtained by the dividing unit 131a.
  • the set number of dividing units are sequentially arranged on the cutting path, so that the first marking pattern does not cover other marking patterns.
  • the division units 131a can be arranged by the positions of other marking patterns on the cutting lane 12, and the set number of division units 131a are all set or filled in the free positions of the cutting lane 12 in turn, and
  • the layout device can be used to compare the size of the space on the cutting lane 12 and the length of the dividing unit 131a to automatically lay out the first marking pattern units 131b of different lengths, so that the first marking pattern 131 does not cover other marking patterns 13.
  • the first mark pattern 131 is a film layer alignment mark pattern; other mark patterns include at least one of the following: an electrical property measurement mark pattern, a mask quality measurement mark pattern, and a mask alignment mark pattern.
  • the first mark pattern 131 can be set as a film layer alignment mark pattern, so that the discretely arranged dividing units 131a can effectively mark the position of the film layer in multiple directions, and improve the chip's performance. Production yield.
  • other mark patterns may also include electrical measurement mark patterns, mask quality measurement mark patterns, and mask alignment mark patterns, etc., to improve the accuracy of the photolithography process.
  • Other mark patterns in this embodiment may also include For other types of marking graphics, this embodiment does not limit the specific marking graphics types of other marking graphics.
  • arranging the set number of dividing units 131a on the cutting lane 12 sequentially may include: arranging the set number of cutting units 131a on the cutting lane 12 in sequence according to the preset cutting unit position setting rules; Wherein, the position setting rule of the cutting unit can be set on the inner side of the outer ring cutting lane 121 of the chip pattern array, and the distance d5 between the cutting unit 131a and the outer ring cutting lane 121 is greater than or equal to the set threshold; the set threshold is greater than or Equal to 3000um.
  • Position setting rules can be set for each type of marking pattern.
  • the cutting unit position setting rules can be set to be set inside the chip pattern array, and the distance from the outer ring cutting lane 121 exceeds a set threshold.
  • the cutting unit 131a can be set at the center of the chip pattern array, which is not limited in this embodiment.
  • the cutting unit 131a is automatically laid out, on the premise that the first marking pattern 131 does not cover other marking patterns 13, the cutting unit 131a is placed according to the above-mentioned cutting unit position setting rules, so as to automatically realize a better first marking
  • the layout of graphics 131 is highly systematic, highly repeatable, fast in layout, and can be produced automatically in large quantities, saving manpower.
  • S140 Set a first marking pattern unit to replace at least two adjacently arranged segmentation units, and set them on the cutting path; wherein the first marking pattern unit and at least two adjacently arranged segmentation units are spliced to form a pattern that completely overlaps.
  • FIG. 4 is a schematic structural diagram of another mask provided by an embodiment of the present disclosure.
  • a plurality of adjacently arranged dividing units 131a can be spliced with each other to form a first marking pattern monomer 131b
  • the first mark pattern 131 can be replaced with the first mark pattern unit 131b as a whole
  • the single unit 131b is manufactured as a unit, instead of multiple division units 131a being manufactured multiple times to finally form the first marking pattern unit 131b, so as to improve the efficiency of the mask manufacturing process.
  • the first marking pattern unit 131b is set to replace the multiple adjacently arranged dividing units 131b covered by the first marking pattern unit 131b, and finally realizes the automatic disassembly of the first marking pattern unit 131b of different lengths on the first marking pattern 131. Therefore, the layout efficiency and accuracy of the first marking graphic 131 are improved.
  • the first mark pattern with a longer total length can be divided into smaller length division units.
  • the number of division units that need to be set on the cutting path can be known.
  • all the division units are automatically arranged in the cutting lane.
  • the division units may be arranged separately, or multiple division units may be arranged adjacently.
  • the size of the first marking pattern monomer is exactly the same as the size of the pattern formed by splicing at least two adjacently arranged dividing units, thereby completing the first marking pattern.
  • the first marking pattern monomers of different lengths are formed by stacking different numbers of dividing units, so that the first marking pattern monomers can be filled in the gaps between other marking patterns, and the first marking pattern that is manually split is avoided. The situation that a single mark pattern cannot be placed in the above gap can realize the optimal position placement of various mark patterns on the cutting path, improve the space utilization rate of the cutting path, solve the problem of time-consuming manual placement, and improve the pendulum Put accuracy.
  • each type of marking graphic has its own setting rules and positions.
  • the above rules and positions are operated.
  • the form of the script is stored in the layout device of the mask.
  • FIG. 5 is another mask layout provided by an embodiment of the present disclosure.
  • the mask layout method of this embodiment includes the following steps:
  • the mask layout parameters include chip pattern size, scribe lane size, mask size and scribe lane extension direction, array distribution mode, and word line extension direction.
  • the above step S110 includes the contents of steps S210 and S220 of this embodiment.
  • forming an array of chip patterns on the mask includes obtaining the mask layout parameters input by the user.
  • the mask layout parameters include : Chip pattern size, that is, the length and width of the chip pattern; cutting lane size, that is, the width of the cutting lane; mask size, the length and width of the entire mask; the extending direction of the cutting lane, that is, the chip pattern array Arrangement direction; word line extension direction; array distribution mode, for example, arranged in a matrix, or arranged in a magenta shape.
  • the largest chip pattern that can be arranged can be formed on the mask along the set direction and the set chip size.
  • the set number of dividing units are sequentially arranged at the remaining positions on the cutting path, so that the first marking pattern does not cover other marking patterns.
  • the above step S120 includes the content of steps S230 and S240 in this embodiment.
  • the set number of dividing units are sequentially arranged on the cutting path, so that the first marking pattern does not cover other marking patterns. If a marking pattern is divided to form a larger number of cutting units, then other marking patterns except the first marking pattern can be set first, and each partitioning unit may be filled in the remaining positions on the cutting path in order to realize the optimization of the first marking pattern Split.
  • the chip pattern array can be automatically laid out according to the local parameters of the mask, and before the first mark pattern is automatically laid out, other mark patterns are laid out first.
  • the position of other mark patterns is relatively fixed, so as not to hinder other mark patterns.
  • the optimized layout of the first marking graphics is implemented, which effectively prevents the first marking graphics from occupying the setting positions of other marking graphics, and improves the layout efficiency and accuracy of the layout.
  • step S230 is further described in detail.
  • FIG. 6 is a schematic flowchart of another mask layout method provided by an embodiment of the present disclosure.
  • other The marking graphic includes a second marking graphic, and setting other marking graphics except the first marking graphic on the cutting path specifically includes the following steps:
  • Each kind of mark graphics can be set with a fixed mark size and number of marks according to user requirements.
  • each type of mark pattern can be set with a corresponding position setting rule.
  • the position setting rule of the second mark pattern 132 is set on the four corners of the chip pattern 11.
  • other marking patterns may include the second marking pattern 132. Then, before laying out the first marking graphic 131, the second marking graphic 132 may be laid out according to the second marking layout parameters.
  • the other marking graphics include the second marking graphic.
  • the second marking graphic can be laid out on the cutting path according to the layout parameters of the second marking graphic to enhance The accuracy of the automatic layout process.
  • step S230 is further described in detail.
  • FIG. 7 is a schematic flowchart of another mask layout method provided by an embodiment of the present disclosure.
  • Other marking graphics include a third marking graphic and a fourth marking graphic, and setting other marking graphics except the first marking graphic on the cutting path specifically includes the following steps:
  • other marking patterns include a third marking pattern 133 and a fourth marking pattern 134.
  • the third marking pattern 133 and the fourth marking pattern 134 may be set in priority order.
  • the priority order is: the fourth marking graphic 134 and the third marking graphic 133.
  • the corresponding layout parameters can be set for each type of mark graphic.
  • each type of mark graphic is laid out according to the corresponding layout parameters.
  • the layout parameters of the third mark graphic include the third mark size and the third mark size.
  • the marking quantity and the third marking position setting rule, and the layout parameters of the fourth marking graphic include the fourth marking size, the fourth marking quantity and the fourth marking position setting rule.
  • the priority order is set for multiple marking graphics, and different types of marking graphics are laid out in sequence to further improve the accuracy of the layout.
  • FIG. 8 is a schematic structural diagram of a mask layout device provided by an embodiment of the present disclosure.
  • the mask layout device provided by an embodiment of the present disclosure can be used to execute the mask layout method provided by any embodiment of the present disclosure. As shown in FIG. 8, the mask layout device in this embodiment includes:
  • the chip pattern layout module 21 is used to form chip patterns arranged in an array on the mask; a cutting channel is formed between every two adjacent chip patterns, and the cutting channel is used to set a marking pattern; the marking pattern includes at least a first mark Graphics
  • the quantity acquiring module 22 is configured to acquire the set number of dividing units of the first marking pattern according to the measurement and alignment needs of the first marking pattern;
  • the automatic layout module 23 is used to sequentially arrange the set number of dividing units on the cutting path so that the first marking pattern does not cover other marking patterns;
  • the unit replacement module 24 is used to set a single unit of the first marking pattern to replace at least two adjacently arranged segmentation units, and is arranged on the cutting path; wherein the first unit of the marking pattern is spliced with at least two adjacently arranged segmentation units The formed patterns are completely overlapped.
  • the first mark pattern with longer length can be divided into smaller length division units. According to the measurement and alignment requirements of the first mark pattern set by the user, the number of division units that need to be set on the cutting path can be obtained. , And according to the standard that the dividing unit does not affect the placement of other marking graphics, all the dividing units are automatically arranged in the cutting lane in sequence.
  • the dividing units may be arranged separately, or multiple dividing units may be arranged adjacently.
  • the first marking pattern monomers of different lengths are formed by stacking different numbers of dividing units, so that the first marking pattern monomers can be filled in the gaps between other marking patterns, and the first marking pattern that is manually split is avoided. The situation that a single mark pattern cannot be placed in the above gap can realize the optimal position placement of various mark patterns on the cutting path, improve the space utilization rate of the cutting path, solve the problem of time-consuming manual placement, and improve the pendulum Put accuracy.
  • the embodiment of the present disclosure also provides a mask, which adopts the layout method of the mask provided by any embodiment of the present disclosure for layout.
  • the mask includes: chip patterns 11 arranged in an array; A dicing lane 12 is formed between two adjacent chip patterns 11, and the dicing lane 12 is used to set a marking pattern 13; the marking pattern 12 includes at least a first marking pattern 131.
  • This embodiment includes the technical features of the mask layout method provided by any embodiment of the present disclosure, and has the technical effects of the mask layout method provided by any embodiment of the present disclosure.
  • the layout of the first mark pattern of the mask can be optimized, which improves the space utilization rate on the cutting path, avoids the instability of manually placing the first mark pattern, and makes the mask layout repetitive and systematic. , And the accuracy is high.

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Abstract

一种掩膜版的布局方法及装置、掩膜版，其中，掩膜版的布局方法包括：在掩膜版（1）上形成阵列排布的芯片图形（11）；每相邻两个芯片图形（11）之间形成有切割道（12），切割道（12）用于设置标记图形（13）；标记图形（13）至少包括第一标记图形（131）；根据第一标记图形（131）的量测对准需要，获取第一标记图形（131）的分割单元（131a）的设定个数；将设定个数的分割单元（131a）依次设置于切割道（12）上，使得第一标记图形（131）未覆盖其他标记图形；设置第一标记图形单体（131b）替换至少两个相邻设置的分割单元（131a），设置于切割道（12）上；其中，第一标记图形单体（131b）与至少两个相邻设置的分割单元（131a）拼接形成的图形完全重合。由此可解决人工布局标记图形效率低，且精确度低的问题。

Description

一种掩膜版的布局方法及装置、掩膜版
交叉引用
本公开要求于2020年4月13日提交的申请号为202010287352.5、名称为“一种掩膜版的布局方法及装置、掩膜版”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体布局技术领域，尤其涉及一种掩膜版的布局方法及装置、掩膜版。
背景技术
在半导体制造的过程中，光刻工艺是最重要的电路图形转移工艺，其中，掩膜版(mask)是实现光刻工艺的重要材料，可以用于制作半导体芯片的电路版图。在半导体加工模式中，首先由集成电路设计公司设计晶片电路图，并由光罩公司设计掩膜版框架数据，并将晶片电路图和掩膜版框架数据合并，形成掩膜版。
掩膜版框架数据一般包含各种制作流程相关的工艺和电学参数的标记图形(mark)。根据需要的标记图形，以及芯片尺寸，可计算出各种标记图形的尺寸，并通过人工的方式将需要拆分的标记图形分割成长度不等的多条标记单体，并进行人工布局和设置，拆分和布局过程使得整个手工布局过程繁琐复杂，造成大量人力成本的浪费，并且布局结构优化程度不高，并且具有不稳定、不精确的缺点。
发明内容
本公开实施例提供了一种掩膜版的布局方法及装置、掩膜版，以解决人工布局标记图形效率低，且精确性较差的问题。
根据本公开的一方面，本公开实施例提供了一种掩膜版的布局方法，包括：
在掩膜版上形成阵列排布的芯片图形；每相邻两个所述芯片图形之间形成有切割道，所述切割道用于设置标记图形；所述标记图形至少包括第一标记图形；
根据所述第一标记图形的量测对准需要，获取第一标记图形的分割单元的设定个数；
将所述设定个数的分割单元依次设置于所述切割道上，使得所述第一标记图形未覆盖其他标记图形；
设置第一标记图形单体替换至少两个相邻设置的分割单元，设置于所述切割道上；其中，所述第一标记图形单体与所述至少两个相邻设置的分割单元拼接形成的图形完全重合。
根据本公开的另一方面，本公开实施例提供了一种掩膜版的布局装置，包括：
芯片图形布局模块，用于在掩膜版上形成阵列排布的芯片图形；每相邻两个所述芯片图形之间形成有切割道，所述切割道用于设置标记图形；所述标记图形至少包括第一标记图形；
数量获取模块，用于根据所述第一标记图形的量测对准需要，获取第一标记图形的分割单元的设定个数；
自动布局模块，用于将所述设定个数的分割单元依次设置于所述切割道上，使得所述第一标记图形未覆盖其他标记图形；
单体替换模块，用于设置第一标记图形单体替换至少两个相邻设置的分割单元，设置于所述切割道上；其中，所述第一标记图形单体与所述至少两个相邻设置的分割单元拼接形成的图形完全重合。
根据本公开的再一方面，本公开实施例还提供了一种掩膜版，采用本公开任意实施例提供的掩膜版的布局方法进行布局，所述掩膜版包括阵列排布的芯片图形；每相邻两个所述芯片图形之间形成有切割道，所述切割道用于设置标记图形；所述标记图形至少包括第一标记图形。
本公开中，对掩膜版进行布局时，需要对芯片图形阵列上相邻芯片图形之间的切割道进行标记图形设置，以用于光刻工艺的对位和测量需求，其中，对于总长度较长的第一标记图形，可将其分割成长度较小的分割单元，根据用户设定的第一标记图形的量测对准需要，可获知需要在切割道上设置的分割单元的个数，并按照分割单元不影响其他标记图形的摆放的标准将所有分割单元自动依次设置在切割道，分割单元可能分离设置，也可能多个分割单元相邻设置，本实施例可将至少两个相邻设置的分割单元由对应的第一标记图形单体进行替换，并且第一标记图形单体的尺寸与至少两个相邻设置的分割单元拼接形成的图形的尺寸完全相同，从而完成第一标记图形的布局。本公开实施例通过不同个数的分割单元的堆叠形成不同长度的第一标记图形单体，从而使得第一标记图形单体能够填充在其他标记图形之间的间隙处，避免人工拆分的第一标记图形单体无法放入上述间隙的情况，能够实现切割道上各种标记图形的最佳位置摆放，提高切割道的空间利用率，解决人工摆放耗费时间长的问题，并且提高了摆放精确度。
附图说明
通过参照附图详细描述其示例实施方式，本发明的上述和其它特征及优点将变得更加明显。
图1是本公开实施例提供的一种掩膜版的布局方法流程示意图；
图2是本公开实施例提供的一种掩膜版的结构示意图；
图3是本公开实施例提供的一种掩膜版的局部结构示意图；
图4是本公开实施例提供的另一种掩膜版的结构示意图；
图5是本公开实施例提供的另一种掩膜版的布局方法流程示意图；
图6是本公开实施例提供的另一种掩膜版的布局方法流程示意图；
图7是本公开实施例提供的另一种掩膜版的布局方法流程示意图；
图8是本公开实施例提供的一种掩膜版布局装置的结构示意图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本公开，而非对本公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本公开相关的部分而非全部结构。
图1是本公开实施例提供的一种掩膜版的布局方法流程示意图，本公开实施例提供了一种掩膜版的布局方法，用于实现布局装置对掩膜版的各种图形，尤其是需要拆分的第一标记图形的自动布局，如图1所示，本实施例的掩膜版的布局方法包括如下步骤：
S110、在掩膜版上形成阵列排布的芯片图形；每相邻两个芯片图形之间形成有切割道，切割道用于设置标记图形；标记图形至少包括第一标记图形。
如图2所示，图2是本公开实施例提供的一种掩膜版的结构示意图。掩膜版1上形成阵列排布的芯片图形11，芯片图形11与实际光刻过程中晶片上的芯片的位置相对应，多个芯片图形形成的芯片图形阵列与晶片上的芯片阵列相对应。并且芯片图形11与对应芯片的尺寸相同。每相邻两个芯片图形11之间形成有切割道12，在一实施例中，如图2所示，在整个芯片图形阵列的周围设置有一圈切割道12。切割道12是组成掩膜版的框架部分。可通过切割道12切割将一个较大的掩膜版母板切割形成图2所示的掩膜版。例如，图2中示出的为3*3的芯片图形阵列，即为从包括N*N的芯片图形阵列的掩膜版母板上通过切割切割道12形成的，其中N为大于2的整数。图2中以3*3的芯片图形阵列进行 示意，本示例中，芯片图形阵列还可以为4*3或2*6等形式的芯片图形阵列，本实施例对阵列所含芯片图形11的数量不进行限定。
为了实现后续掩膜版与晶片之间的对位，或者实现掩膜版与曝光机之间的对位，或者为了在晶片上留下对位标记以实现晶片上形成的各个膜层之间的对位，可在切割道12上形成标记图形。
S120、根据第一标记图形的量测对准需要，获取第一标记图形的分割单元的设定个数。
继续参考图2，本实施例中，标记图形13至少包括第一标记图形131。本实施例中，第一标记图形131在整个掩膜版上的设定总长度较长，示例性的，第一标记图形的设定总长度为28790μm。所以在布局第一标记图形131时，相关技术常通过人工布局的方式，将第一标记图形131分割成第一标记图形单体，设置在切割道12的不同位置，具体的，如图2所示，第一标记图形单体，分别设置在沿第一方向X和第二方向Y的不同的切割道12中。因为标记图形13包括多种标记图形，某些标记图形需要设置在固定位置，为了适应其他标记图形的摆放规则，第一标记图形131需要被分割形成不同的长度的第一标记图形单体，但是人工分割时容易出现错误，例如，第一标记图形单体的长度过大，导致其他标记图形无法放入对应位置的切割道12中，并且手工布局过程繁琐复杂，造成人力成本的极大浪费。需要注意的是，本实施例所述的第一标记图形单体的长度为沿所处切割道的延伸方向的长度，因为在切割道的宽度方向上，各第一标记图形单体的宽度固定。本实施仅对第一标记图形在沿切割道的延伸方向上的尺寸，以及长度进行限定。
本实施例，参考图2，可通过将第一标记图形131分割成更小的分割单元131a，以多个分割单元131a的逐个堆积，拼接形成所需长度的第一标记图形单体的形状，示例性的，如图3所示，图3是本公开实施例提供的一种掩膜版的局部结构示意图。若两个其他种类的标记图形13之间形成间隔的长度为d1，则仅能放入5个分割单元131a，而不能再放入第6个分割单元131a，相对于人工摆放的方式，若人工拆分的第一标记图形单体长度大于d1，则第一标记图形单体不能被放入此处，需要重新设置第一标记图形单体，操作过程十分繁杂，而本示例中，若不能放入第6个分割单元131a，则将5个分割单元131a拼接形成的图形作为第一标记图形单体131b放置在该位置，不需要进行返工，提高了布局效率。
继续参考图3，切割道12的宽度d2可以小于或等于80μm；第一标记图形131或分割单元131a的宽度d3小于或等于60μm；每个分割单元131a的长度范围为40μm～500μm。本实施例中，第一标记图形131或分割单元131a的宽度d3小于切割道12的宽度d2，本实施例中若切割道12的宽度d2可以小于或等于60μm，则分割单元131a的宽度 d3可小于或等于45μm，每个分割单元131a的长度d4的取值范围可以为40μm～500μm。
本实施例可设置多种长度不同的分割单元131a，以实现不同排布需求，例如，设置长度为180μm和436μm两种规格的分割单元131a，若当前切割道的空间若无法放入长度为436μm的分割单元131a，则可将长度为180μm的分割单元131a放入该空间内。多种不同的分割单元131a能够实现更加多样化的分割单元131a，便于实现最佳布局。
每个分割单元131a的长度相等，统一化分割单元131a的规格，则在摆放分割单元131a，则可直观的通过分割单元131a的摆放个数获取第一标记图形单体131b的长度，进一步简化的分割单元131a的布局算法和布局过程，具体的，本实施例中，将第一标记图形131的设定总长度与分割单元131a的长度d4相除，得到的数值即为分割单元131a所需的设定个数。
S130、将设定个数的分割单元依次设置于切割道上，使得第一标记图形未覆盖其他标记图形。
继续参考图2，本实施例可通过切割道12上其他标记图形的位置进行分割单元131a的布置，依次将设定个数的分割单元131a全部设置或填充在切割道12的空闲位置处，并且可通过布局装置，比对切割道12上空间的大小以及分割单元131a的长度，自动布局出不同长度的第一标记图形单体131b，并使得第一标记图形131未覆盖其他标记图形13。
第一标记图形131为膜层对位标记图形；其他标记图形包括下述至少一种：电性测量标记图形、光罩质量测量标记图形和掩膜版对位标记图形。为了增强最终形成在晶片上的膜层的精准性，可设置第一标记图形131为膜层对位标记图形，从而分散设置的各个分割单元131a可多方位有效标定膜层的位置，提高芯片的制作良率。此外，其他标记图形还可以包括电性测量标记图形、光罩质量测量标记图形和掩膜版对位标记图形等，用于提高光刻工艺的精准性，本实施例的其他标记图形还可以包括其他种类的标记图形，本实施例对其他标记图形具体的标记图形类型不进行限定。
继续参考图2，将设定个数的分割单元131a依次设置于切割道12上，可以包括：将设定个数的切割单元131a按照预设切割单元位置设置规则依次设置于切割道12上；其中，切割单元位置设置规则可以为设置于芯片图形阵列的外圈切割道121的内侧，且切割单元131a与外圈切割道121之间的距离d5大于或等于设定阈值；设定阈值大于或等于3000um。可对每种标记图形均设定位置设置规则，本实施例可设置切割单元位置设置规则为设置在芯片图形阵列的内侧，且距离外圈切割道121的距离超过设定阈值。可设置切割单元131a 在芯片图形阵列的中心，本实施例对此不进行限定。在对切割单元131a进行自动布局时，本着第一标记图形131未覆盖其他标记图形13的前提下，遵循上述切割单元位置设置规则进行切割单元131a摆放，从而自动实现较优的第一标记图形131的布局，系统性较强，可重复性高，布局速度快，可大批量自动生产，节约人力。
S140、设置第一标记图形单体替换至少两个相邻设置的分割单元，设置于切割道上；其中，第一标记图形单体与至少两个相邻设置的分割单元拼接形成的图形完全重合。
图4是本公开实施例提供的另一种掩膜版的结构示意图，在完成全部的切割单元131a的布局之后，相邻设置的多个分割单元131a相互拼接可形成第一标记图形单体131b的图形，并设置作为一个整体的第一标记图形单体131b替换上述相邻设置的多个分割单元131a，则在布局完成后的实际制作过程中，第一标记图形131可以以第一标记图形单体131b为单位进行制作，而不是多次制作多个分割单元131a以最终形成第一标记图形单体131b，以提高掩膜版制作工艺效率。本实施例设置第一标记图形单体131b替换其覆盖的多个相邻设置的分割单元131b，最终实现了对第一标记图形131进行多种不同长度的第一标记图形单体131b的自动化拆分，提高了第一标记图形131的布局效率和精确度。
本公开实施例中，对掩膜版进行布局时，需要对芯片图形阵列上相邻芯片图形之间的切割道进行标记图形设置，以用于光刻工艺的对位和测量需求，其中，对于总长度较长的第一标记图形，可将其分割成长度较小的分割单元，根据用户设定的第一标记图形的量测对准需要，可获知需要在切割道上设置的分割单元的个数，并按照分割单元不影响其他标记图形的摆放的标准将所有分割单元自动依次设置在切割道，分割单元可能分离设置，也可能多个分割单元相邻设置，本实施例可将至少两个相邻设置的分割单元由对应的第一标记图形单体进行替换，并且第一标记图形单体的尺寸与至少两个相邻设置的分割单元拼接形成的图形的尺寸完全相同，从而完成第一标记图形的布局。本公开实施例通过不同个数的分割单元的堆叠形成不同长度的第一标记图形单体，从而使得第一标记图形单体能够填充在其他标记图形之间的间隙处，避免人工拆分的第一标记图形单体无法放入上述间隙的情况，能够实现切割道上各种标记图形的最佳位置摆放，提高切割道的空间利用率，解决人工摆放耗费时间长的问题，并且提高了摆放精确度。
在上述实施例的基础上，上述步骤S130中，在摆放各个第一标记图形以及其他标记图形时，每种标记图形均具有各自的设置规则和位置，本实施例将上述规则和位置以运行脚本的形式存储在掩膜版的布局装置中，当掩膜版的布局装置运行时，各种标记图形均按照对应的设置规则和位置进行最佳布局，并且使得各标记图形之间互不重叠，互不影响。
在另一实施例中，对在掩膜版上形成阵列排布的芯片图形进行详述，具体的，如图5所示，图5是本公开实施例提供的另一种掩膜版的布局方法流程示意图，本实施例的掩膜版的布局方法包括如下步骤：
S210、获取掩膜版布局参数；掩膜版布局参数包括芯片图形尺寸、切割道尺寸、掩膜版尺寸和切割道延伸方向、阵列分布方式和字线延伸方向。
S220、根据掩膜版布局参数，在掩膜版中生成芯片图形阵列；芯片图形阵列标示了芯片的位置和尺寸。
上述步骤S110包括本实施例步骤S210和S220的内容，本实施例中，在掩膜版上形成阵列排布的芯片图形，具体包括获取用户输入的掩膜版布局参数，掩膜版布局参数包括：芯片图形尺寸，也即，芯片图形的长度和宽度；切割道尺寸，即切割道的宽度；掩膜版尺寸，整个掩膜版的长度和宽度；切割道延伸方向，也即芯片图形阵列的排布方向；字线延伸方向；阵列分布方式，例如，成矩阵型排布，或者呈品字形排布等。根据上述参数，可沿设定的方向和设定的芯片尺寸在掩膜版上形成所能排布开的最大芯片图形。
S230、将除第一标记图形之外的其他标记图形设置于切割道上。
S240、将设定个数的分割单元依次设置于切割道上的剩余位置处，使得第一标记图形未覆盖其他标记图形。
上述步骤S120包括本实施例步骤S230和S240的内容，将所述设定个数的分割单元依次设置于所述切割道上，使得所述第一标记图形未覆盖其他标记图形的过程中，因为第一标记图形分割形成数量较多的切割单元，则可首先设置除第一标记图形之外的其他标记图形，并将各分割单元依次填充在切割道上的剩余位置处，实现第一标记图形的优化拆分。
S250、设置第一标记图形单体替换至少两个相邻设置的分割单元，设置于切割道上；其中，第一标记图形单体与至少两个相邻设置的分割单元拼接形成的图形完全重合。
本实施例，可根据掩膜版局部参数自动布局芯片图形阵列，并在自动布局第一标记图形之前，首先布局其他标记图形，一般情况下，其他标记图形的位置设置较为固定，在不妨碍其他标记图形的摆放的前提下，对第一标记图形实行优化布局，有效避免第一标记图形占用其他标记图形的设置位置，提高布局效率和布局准确性。
在本实施例的一个示例性中，对步骤S230进一步进行详述，如图6所示，图6是本公开实施例提供的另一种掩膜版的布局方法流程示意图，本示例中，其他标记图形包括第二标记图形，将除第一标记图形之外的其他标记图形设置于切割道上，具体包括如下步骤：
S310、获取第二标记图形的布局参数；第二标记图形的布局参数包括第二标记尺寸、第二标记数量和第二标记位置设置规则。
每种标记图形根据用户需求可设置固定的标记尺寸和标记数量。并且每种标记图形可设置有对应的位置设置规则，示例性的，继续参考图2，第二标记图形132的位置设置规则为设置在芯片图形11的四个角上，此外，还可以存在其他的位置设置规则，本实施例对此不进行限定。本实施例中，其他标记图形可包括第二标记图形132。则在布局第一标记图形131之前，可对第二标记图形132根据第二标记布局参数进行布局。
S320、依据第二标记图形的布局参数，在切割道上设置第二标记图形。
本实施例中，在布局第一标记图形之前，需要对其他标记图形进行放置，其他标记图形包括第二标记图形，可按照第二标记图形的布局参数将第二标记图形布局在切割道上，增强自动布局过程的精准性。
在本实施例的另一个示例性中，对步骤S230进一步进行详述，如图7所示，图7是本公开实施例提供的另一种掩膜版的布局方法流程示意图，本示例中，其他标记图形包括第三标记图形和第四标记图形，将除第一标记图形之外的其他标记图形设置于切割道上，具体包括如下步骤：
S410、为第三标记图形和第四标记图形设置优先级顺序。
当其他标记图形包括多种标记图形时，可以按照重要量级对各种标记图形设置布局优先级，并将比较重要的，或者位置固定的标记图形排在靠前位置，依次按照优先级顺序进行布局，进一步提高自动布局的精准性。
如图2所示，本实施例中，其他标记图形包括第三标记图形133和第四标记图形134，本实施例可首先将第三标记图形133和第四标记图形134设置优先级顺序，示例性的，优先级顺序为：第四标记图形134、第三标记图形133。
S420、按照优先级顺序在切割道上依次设置第三标记图形和第四标记图形；其中，第三标记图形和第四标记图形均按照对应的布局参数进行设置；相邻标记图形之间互不重叠。
同理，每种标记图形均可设置对应的布局参数，在逐类布局过程中，对每类标记图形按照对应的布局参数进行布局，第三标记图形的布局参数包括第三标记尺寸、第三标记数量和第三标记位置设置规则，第四标记图形的布局参数包括第四标记尺寸、第四标记数量和第四标记位置设置规则。
本实施例为除第一标记图形之外的其他标记图形进行布局时，为多种标记图形设置优 先级顺序，并依次对不同种类标记图形进行布局，进一步提高布局精准性。
本公开实施例还提供一种掩膜版布局装置。图8是本公开实施例提供的一种掩膜版布局装置的结构示意图，本公开实施例提供的掩膜版布局装置可用于执行本公开任意实施例提供的掩膜版的布局方法。如图8所示，本实施例中掩膜版布局装置包括：
芯片图形布局模块21，用于在掩膜版上形成阵列排布的芯片图形；每相邻两个芯片图形之间形成有切割道，切割道用于设置标记图形；标记图形至少包括第一标记图形；
数量获取模块22，用于根据第一标记图形的量测对准需要，获取第一标记图形的分割单元的设定个数；
自动布局模块23，用于将设定个数的分割单元依次设置于切割道上，使得第一标记图形未覆盖其他标记图形；
单体替换模块24，用于设置第一标记图形单体替换至少两个相邻设置的分割单元，设置于切割道上；其中，第一标记图形单体与至少两个相邻设置的分割单元拼接形成的图形完全重合。
本实施例中，对掩膜版进行布局时，需要对芯片图形阵列上相邻芯片图形之间的切割道进行标记图形设置，以用于光刻工艺的对位和测量需求，其中，对于总长度较长的第一标记图形，可将其分割成长度较小的分割单元，根据用户设定的第一标记图形的量测对准需要，可获知需要在切割道上设置的分割单元的个数，并按照分割单元不影响其他标记图形的摆放的标准将所有分割单元自动依次设置在切割道，分割单元可能分离设置，也可能多个分割单元相邻设置，本实施例可将至少两个相邻设置的分割单元由对应的第一标记图形单体进行替换，并且第一标记图形单体的尺寸与至少两个相邻设置的分割单元拼接形成的图形的尺寸完全相同，从而完成第一标记图形的布局。本公开实施例通过不同个数的分割单元的堆叠形成不同长度的第一标记图形单体，从而使得第一标记图形单体能够填充在其他标记图形之间的间隙处，避免人工拆分的第一标记图形单体无法放入上述间隙的情况，能够实现切割道上各种标记图形的最佳位置摆放，提高切割道的空间利用率，解决人工摆放耗费时间长的问题，并且提高了摆放精确度。
本公开实施例还提供一种掩膜版，采用本公开任意实施例提供的掩膜版的布局方法进行布局，如图2所示，掩膜版包括：阵列排布的芯片图形11；每相邻两个芯片图形11之间形成有切割道12，切割道12用于设置标记图形13；标记图形12至少包括第一标记图形131。
本实施例包括本公开任意实施例提供的掩膜版的布局方法的技术特征，具有本公开任 意实施例提供的掩膜版的布局方法的技术效果。本实施例中掩膜版第一标记图形布局可达到最优，提高了切割道上空间利用率，避免了人工摆放第一标记图形的不稳定性，使得掩膜版布局重复性好，系统化，且精确度较高。
注意，上述仅为本公开的较佳实施例及所运用技术原理。本领域技术人员会理解，本公开不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本公开的保护范围。因此，虽然通过以上实施例对本公开进行了较为详细的说明，但是本公开不仅仅限于以上实施例，在不脱离本公开构思的情况下，还可以包括更多其他等效实施例，而本公开的范围由所附的权利要求范围决定。

Claims (10)

  1. 一种掩膜版的布局方法，包括：
    在掩膜版上形成阵列排布的芯片图形；每相邻两个所述芯片图形之间形成有切割道，所述切割道用于设置标记图形；所述标记图形至少包括第一标记图形；
    根据所述第一标记图形的量测对准需要，获取第一标记图形的分割单元的设定个数；
    将所述设定个数的分割单元依次设置于所述切割道上，使得所述第一标记图形未覆盖其他标记图形；
    设置第一标记图形单体替换至少两个相邻设置的分割单元，设置于所述切割道上；其中，所述第一标记图形单体与所述至少两个相邻设置的分割单元拼接形成的图形完全重合。
  2. 根据权利要求1所述的掩膜版的布局方法，在所述掩膜版上形成阵列排布的芯片图形，包括：
    获取掩膜版布局参数；所述掩膜版布局参数包括芯片图形尺寸、切割道尺寸、切割道延伸方向、阵列分布方式和字线延伸方向；
    根据所述掩膜版布局参数，在所述掩膜版中生成芯片图形阵列；所述芯片图形阵列标示了芯片的位置和尺寸。
  3. 根据权利要求1所述的掩膜版的布局方法，将所述设定个数的分割单元依次设置于所述切割道上，使得所述第一标记图形未覆盖其他标记图形，包括：
    将除所述第一标记图形之外的其他标记图形设置于所述切割道上；
    将所述设定个数的分割单元依次设置于所述切割道上的剩余位置处，使得所述第一标记图形未覆盖所述其他标记图形。
  4. 根据权利要求3所述的掩膜版的布局方法，所述其他标记图形包括第二标记图形；
    将除所述第一标记图形之外的其他标记图形设置于所述切割道上，包括：
    获取所述第二标记图形的布局参数；所述第二标记图形的布局参数包括第二标记尺寸、第二标记数量和第二标记位置设置规则；
    依据所述第二标记图形的布局参数，在所述切割道上设置所述第二标记图形。
  5. 根据权利要求3所述的掩膜版的布局方法，所述其他标记图形包括第三标记图形和第四标记图形；
    将除所述第一标记图形之外的其他标记图形设置于所述切割道上，包括：
    为所述第三标记图形和所述第四标记图形设置优先级顺序；
    按照所述优先级顺序在所述切割道上依次设置所述第三标记图形和所述第四标记图形；其中，所述第三标记图形和所述第四标记图形均按照对应的布局参数进行设置；相邻所述标记图形之间互不重叠。
  6. 根据权利要求1所述的掩膜版的布局方法，将所述设定个数的分割单元依次设置于所述切割道上，包括：
    将所述设定个数的切割单元按照预设切割单元位置设置规则依次设置于所述切割道上；其中，所述切割单元位置设置规则为设置于芯片图形阵列的外圈切割道的内侧，且所述切割单元与所述外圈切割道之间的距离大于或等于设定阈值；所述设定阈值大于或等于3000um。
  7. 根据权利要求1所述的掩膜版的布局方法，所述切割道的宽度小于或等于80μm；所述第一标记图形或所述分割单元的宽度小于或等于60μm；
    每个所述分割单元的长度范围为40μm～500μm。
  8. 根据权利要求1所述的掩膜版的布局方法，所述第一标记图形为膜层对位标记图形；
    所述其他标记图形包括下述至少一种：电性测量标记图形、光罩质量测量标记图形和掩膜版对位标记图形。
  9. 一种掩膜版的布局装置，包括：
    芯片图形布局模块，用于在掩膜版上形成阵列排布的芯片图形；每相邻两个所述芯片图形之间形成有切割道，所述切割道用于设置标记图形；所述标记图形至少包括第一标记图形；
    数量获取模块，用于根据所述第一标记图形的量测对准需要，获取第一标记图形的分割单元的设定个数；
    自动布局模块，用于将所述设定个数的分割单元依次设置于所述切割道上，使得所述第一标记图形未覆盖其他标记图形；
    单体替换模块，用于设置第一标记图形单体替换至少两个相邻设置的分割单元，设置于所述切割道上；其中，所述第一标记图形单体与所述至少两个相邻设置的分割单元拼接形成的图形完全重合。
  10. 一种掩膜版，采用上述权利要求1-8中任一项所述的掩膜版的布局方法进行布局， 所述掩膜版包括：
    阵列排布的芯片图形；每相邻两个所述芯片图形之间形成有切割道，所述切割道用于设置标记图形；所述标记图形至少包括第一标记图形。
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CN113296351B (zh) * 2021-05-13 2022-03-04 长鑫存储技术有限公司 掩模板、半导体装置及半导体装置的制作方法

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