WO2021203552A1 - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

Info

Publication number
WO2021203552A1
WO2021203552A1 PCT/CN2020/096285 CN2020096285W WO2021203552A1 WO 2021203552 A1 WO2021203552 A1 WO 2021203552A1 CN 2020096285 W CN2020096285 W CN 2020096285W WO 2021203552 A1 WO2021203552 A1 WO 2021203552A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
dielectric layer
refractive index
angstroms
array
Prior art date
Application number
PCT/CN2020/096285
Other languages
English (en)
French (fr)
Inventor
张骢泷
宋奥奇
张婷
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/057,076 priority Critical patent/US20220190206A1/en
Publication of WO2021203552A1 publication Critical patent/WO2021203552A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/1336—Illuminating devices
    • G02F1/133602—Direct backlight
    • G02F1/133603—Direct backlight with LEDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H01L33/60—Reflective elements

Definitions

  • This application relates to the field of display technology, and in particular to an array substrate and a display device.
  • white oil is coated on a backlight module composed of sub-millimeter light-emitting diodes (mini-LED) to reflect the light emitted by the sub-millimeter light-emitting diodes, and at the same time, it can prevent scratches.
  • mini-LED sub-millimeter light-emitting diodes
  • the purpose of the present application is to provide an array substrate and a display device to solve the problem that traditional white oil used as a reflective layer requires a separate manufacturing process, which results in high manufacturing costs.
  • an array substrate which includes a substrate, an array layer, a passivation layer, and a light-emitting element
  • the array layer is disposed on the substrate, and the light-emitting element is disposed on the array layer;
  • the passivation layer is formed on a side of the array layer away from the substrate, and the passivation layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer that are sequentially stacked.
  • the first dielectric layer Close to the array layer, the third dielectric layer is far from the array layer, the refractive index of the first dielectric layer is different from the refractive index of the second dielectric layer, and the refractive index of the second dielectric layer is different from the refractive index of the second dielectric layer.
  • the refractive index of the third dielectric layer is different.
  • the refractive index of the second dielectric layer is greater than the refractive index of the first dielectric layer and the refractive index of the third dielectric layer.
  • the difference between the refractive index of the second dielectric layer and the refractive index of the first dielectric layer is greater than or equal to 1 and less than or equal to 3.
  • the refractive index of the second dielectric layer is greater than or equal to 1 and less than or equal to 3.
  • the difference in refractive index of the third dielectric layer is greater than or equal to 1 and less than or equal to 3.
  • the first dielectric layer and the third dielectric layer are silicon nitride layers
  • the second dielectric layer is an amorphous silicon layer
  • the thickness of the first dielectric layer is 640 angstroms to 660 angstroms. Angstroms
  • the thickness of the second dielectric layer is 160 Angstroms to 180 Angstroms
  • the thickness of the third dielectric layer is 600 Angstroms to 1200 Angstroms.
  • the passivation layer further includes a fourth dielectric layer formed on a side of the third dielectric layer away from the array layer, and the refractive index of the fourth dielectric layer
  • the difference between the refractive index of the third medium layer and the refractive index of the third medium layer is greater than the difference between the refractive index of the second medium layer and the refractive index of the first medium layer.
  • the first dielectric layer is a silicon nitride layer
  • the third dielectric layer is a silicon oxide layer
  • the second dielectric layer and the fourth dielectric layer are both amorphous silicon layers, so
  • the thickness of the first dielectric layer is 2400 angstroms to 2500 angstroms
  • the thickness of the second dielectric layer is 235 angstroms to 255 angstroms
  • the thickness of the third dielectric layer is 1050 angstroms to 1080 angstroms
  • the fourth dielectric layer The thickness is 190 angstroms-220 angstroms.
  • the array substrate further includes an indium tin oxide layer, the indium tin oxide layer is located on the side of the passivation layer away from the array layer, and the thickness of the indium tin oxide layer is 480 angstroms. 520 angstroms.
  • the passivation layer has a through hole, the through hole is enclosed by an inner wall, and the slope angle of the inner wall ranges from 18° to 87°.
  • the light-emitting element is one of sub-millimeter light-emitting diodes or miniature light-emitting diodes.
  • a display device includes an array substrate, the array substrate includes a substrate, an array layer, a passivation layer, and a light-emitting element,
  • the array layer is disposed on the substrate, and the light-emitting element is disposed on the array layer;
  • the passivation layer is formed on a side of the array layer away from the substrate, and the passivation layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer that are sequentially stacked.
  • the first dielectric layer Close to the array layer, the third dielectric layer is far from the array layer, the refractive index of the first dielectric layer is different from the refractive index of the second dielectric layer, and the refractive index of the second dielectric layer is different from the refractive index of the second dielectric layer.
  • the refractive index of the third dielectric layer is different.
  • the refractive index of the second medium layer is greater than the refractive index of the first medium layer and the refractive index of the third medium layer.
  • the difference between the refractive index of the second dielectric layer and the refractive index of the first dielectric layer is greater than or equal to 1 and less than or equal to 3.
  • the refractive index of the second dielectric layer is greater than or equal to 1 and less than or equal to 3.
  • the difference in refractive index of the third dielectric layer is greater than or equal to 1 and less than or equal to 3.
  • the first dielectric layer and the third dielectric layer are silicon nitride layers
  • the second dielectric layer is an amorphous silicon layer
  • the thickness of the first dielectric layer is 640 angstroms to 660 angstroms. Angstroms
  • the thickness of the second dielectric layer is 160 Angstroms to 180 Angstroms
  • the thickness of the third dielectric layer is 600 Angstroms to 1200 Angstroms.
  • the passivation layer further includes a fourth dielectric layer formed on a side of the third dielectric layer away from the array layer, and the refractive index of the fourth dielectric layer
  • the difference between the refractive index of the third medium layer and the refractive index of the third medium layer is greater than the difference between the refractive index of the second medium layer and the refractive index of the first medium layer.
  • the first dielectric layer is a silicon nitride layer
  • the third dielectric layer is a silicon oxide layer
  • the second dielectric layer and the fourth dielectric layer are both amorphous silicon layers, so
  • the thickness of the first dielectric layer is 2400 angstroms to 2500 angstroms
  • the thickness of the second dielectric layer is 235 angstroms to 255 angstroms
  • the thickness of the third dielectric layer is 1050 angstroms to 1080 angstroms
  • the fourth dielectric layer The thickness is 190 angstroms-220 angstroms.
  • the array substrate further includes an indium tin oxide layer, the indium tin oxide layer is located on the side of the passivation layer away from the array layer, and the thickness of the indium tin oxide layer is 480 angstroms. 520 angstroms.
  • the passivation layer has a through hole, the through hole is enclosed by an inner wall, and the slope angle of the inner wall ranges from 18° to 87°.
  • the light-emitting element is one of sub-millimeter light-emitting diodes or micro light-emitting diodes.
  • the application provides an array substrate and a display device.
  • the array substrate includes a substrate, an array layer, a passivation layer, and a light-emitting element.
  • the array layer is disposed on the substrate, the light-emitting element is disposed on the array layer, and the passivation layer is formed on the array layer away from the substrate.
  • the passivation layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked in sequence. The first dielectric layer is close to the array layer, and the third dielectric layer is far away from the array layer.
  • the refractive index of the first dielectric layer is The refractive index of the second dielectric layer is different, and the refractive index of the second dielectric layer is different from the refractive index of the third dielectric layer.
  • the passivation layer of the present application plays a reflective role, and compared with coating white oil as a separate process, it saves the manufacturing cost of the array substrate and improves the yield of the array substrate. Compared with the traditional reflective layer consisting of two dielectric layers with different refractive indexes, the passivation layer of the present application reflects light with a wavelength of 450 nanometers with a suitable thickness, and the reflectivity of light with a wavelength of 450 nanometers is as high as 88%.
  • FIG. 1 is a schematic diagram of a backlight module according to an embodiment of the application
  • FIG. 2 is a schematic diagram of the reflectivity of the passivation layer to light of different wavelengths in a backlight module implemented in this application;
  • FIG. 3 is a schematic diagram of the reflectivity of the passivation layer to light of different wavelengths in the backlight module of the third embodiment of the application;
  • FIG. 4 is a schematic diagram of the reflectivity of the reflective layer composed of the passivation layer and the indium tin oxide layer in the backlight module of the fifth embodiment of the application to light of different wavelengths.
  • FIG. 1 is a schematic diagram of a backlight module according to an embodiment of the application.
  • the backlight module 100 includes an array substrate, and the array substrate includes a substrate 101, an array layer 102, a passivation layer 103, a light-emitting element 105, and an indium tin oxide layer 104.
  • the substrate 101 is a glass substrate.
  • the array layer 102 is disposed on the substrate 101.
  • the light-emitting element 105 is disposed on the array layer 102.
  • the array layer 102 includes a plurality of thin film transistors (not shown) arranged in an array, and the thin film transistors may be back-etched channel type thin film transistors or etch stop type thin film transistors.
  • the array layer 102 also includes conductive electrodes. Each light-emitting element 105 is connected to two conductive electrodes in the array layer 102 by conductive glue or solder, and one of the conductive electrodes is connected to the drain of the thin film transistor.
  • the light-emitting element 105 is a sub-millimeter light-emitting diode. Each light-emitting element 105 includes a red sub-millimeter light-emitting diode, a blue sub-millimeter light-emitting diode, and a green sub-millimeter light-emitting diode.
  • the passivation layer 103 is formed on the side of the array layer 102 away from the substrate 101.
  • the passivation layer 103 includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked in sequence.
  • the first dielectric layer is close to the array layer 102.
  • the three dielectric layer is far away from the array layer 102, the refractive index of the first dielectric layer is different from the refractive index of the second dielectric layer, and the refractive index of the second dielectric layer is different from the refractive index of the third dielectric layer.
  • the refractive index of the first medium layer and the refractive index of the second medium layer are different to reflect light, and the refractive index of the second medium layer is different from the refractive index of the third medium layer to realize the reflection of light.
  • the backlight module of the present application includes a first medium layer, a second medium layer, and a third medium layer stacked in sequence through the passivation layer.
  • the refractive index of the first medium layer is different from that of the second medium layer.
  • the refractive index of the layer is different from the refractive index of the third dielectric layer to realize the reflectivity of the passivation layer to light.
  • the passivation layer is a manufacturing process of the backlight module. Compared with the traditional white ink coating, a separate manufacturing process is required. , Adjust the film structure and film quality of the passivation layer, and achieve the light reflection effect and anti-scratch effect of the white ink reflectivity level.
  • the inventor found that when the traditional passivation layer is a silicon nitride and silicon oxide film layer stacked on the array layer, the maximum reflectance of light at 450 nanometers is 68%, which cannot be compared with the reflectance of white ink. Equivalent reflectivity, and this application uses the passivation layer as three film layers, which can achieve reflectivity equivalent to that of white ink.
  • the refractive index of the second medium layer is greater than the refractive index of the first medium layer and the refractive index of the third medium layer, and the incidence of light from the second medium to the first medium layer is from the optically dense medium to the optically thinner medium.
  • the refractive index of the first dielectric layer is greater than or equal to the refractive index of the third dielectric layer.
  • the difference between the refractive index of the second dielectric layer and the refractive index of the first dielectric layer is greater than or equal to 1 and less than or equal to 3.
  • the refractive index of the second dielectric layer is less than or equal to that of the third dielectric layer.
  • the difference is greater than or equal to 1 and less than or equal to 3.
  • the difference between the refractive index of the second dielectric layer and the refractive index of the first dielectric layer is 1.2, 1.5, 1.8, 2.0, 2.4, 2.8
  • the difference between the refractive index of the second dielectric layer and the refractive index of the third dielectric layer The values are 1.2, 1.5, 1.8, 2.0, 2.2, 2.4, 2.8.
  • the difference between the refractive index of the second medium layer and the refractive index of the third medium layer is greater than the difference between the refractive index of the second medium layer and the refractive index of the first medium layer.
  • the first dielectric layer and the third dielectric layer are silicon nitride layers
  • the second dielectric layer is an amorphous silicon layer
  • the thickness of the first dielectric layer is 640-660 angstroms
  • the thickness of the second dielectric layer is 160 angstroms -180 angstroms
  • the thickness of the third dielectric layer is 600 angstroms-1200 angstroms.
  • the refractive index of the first dielectric layer, the second dielectric layer, and the third dielectric layer are matched to achieve the reflectivity of light. With the choice of appropriate thickness, the selective light of the wavelength of 440 nanometers to 460 nanometers can be achieved. reflection.
  • the passivation layer further includes a fourth dielectric layer.
  • the fourth dielectric layer is formed on the side of the third dielectric layer away from the array layer.
  • the difference between the refractive index of the fourth dielectric layer and the refractive index of the third dielectric layer is The value is greater than the difference between the refractive index of the second medium layer and the refractive index of the first medium layer to further increase the reflectivity to light.
  • the first dielectric layer is silicon nitride
  • the third dielectric layer is a silicon oxide layer
  • the second dielectric layer and the fourth dielectric layer are both amorphous silicon layers
  • the thickness of the first dielectric layer is 2400 angstroms to 2500 angstroms.
  • the thickness of the second dielectric layer is 235 angstroms to 255 angstroms
  • the thickness of the third dielectric layer is 1050 angstroms to 1080 angstroms
  • the thickness of the fourth dielectric layer is 190 angstroms to 220 angstroms.
  • the refractive index of silicon nitride is 1.88
  • the refractive index of silicon oxide is 1.4
  • the refractive index of amorphous silicon is 3.0-4.0.
  • the indium tin oxide layer 104 is located on the side of the passivation layer 103 away from the array layer 102, and the thickness of the indium tin oxide layer 104 is 480 angstroms to 520 angstroms. On the one hand, the indium tin oxide layer 104 plays a role for bonding the chip, and on the other hand, a proper thickness is selected to match the passivation layer 103 to achieve light reflection.
  • the passivation layer 103 has through holes, which are enclosed by the inner wall 103a.
  • the slope toe of the inner wall 103a ranges from 18° to 87°, for example, the slope toe is 20°, 30° , 40° and 65°.
  • etching the passivation layer 103 to form through holes will cause the passivation layer to be composed of different film layers, and different film etching rates exist.
  • the difference causes the taper pin to be too large, which causes the indium tin oxide layer 104 to form a discontinuous film layer in the through hole, which leads to a decrease in the bonding yield of the chip connected to the indium tin oxide layer 104, and causes the array layer 102 to form a discontinuous film.
  • Undercut (excessive etching of the gate insulating layer) occurs in the gate insulating layer of the battery.
  • the value range of the slope foot of the inner wall 103a is 18°-87°, which can be achieved by optimizing the etching process of the passivation layer 103, or by optimizing the film composition of the passivation layer 103.
  • the present application also provides a display device.
  • the display device includes a liquid crystal display panel and the above-mentioned backlight module, or, the display device includes a display panel, and the display panel includes the above-mentioned array substrate. The difference is that when the display panel includes the above-mentioned array substrate, light is emitted.
  • the element 105 is a miniature light emitting diode.
  • the backlight module includes an array substrate and a passivation layer.
  • the array substrate includes a substrate, an array layer and sub-millimeter light-emitting diodes.
  • the array layer is disposed on the substrate, and the sub-millimeter light-emitting diodes are disposed on the array layer.
  • the passivation layer is disposed on the array layer, and the passivation layer includes a silicon nitride layer (thickness of 2400 angstroms), an amorphous silicon layer (thickness of 240 angstroms), a silicon oxide layer (thickness of 1080 angstroms) and Amorphous silicon layer (thickness 210 angstroms).
  • the reflectivity of the passivation layer to light with a wavelength of 450 nanometers is 78.6%
  • the reflectivity of the passivation layer to light of different wavelengths is shown in FIG. 2.
  • This embodiment provides a backlight module.
  • the backlight module of this embodiment is basically similar to the backlight module of the first embodiment. The difference is that the passivation layer includes a silicon nitride layer (thickness 2420) sequentially disposed on the array layer. Angstroms), an amorphous silicon layer (thickness of 250 angstroms), a silicon oxide layer (thickness of 1060 angstroms), an amorphous silicon layer (thickness of 200 angstroms) and a silicon oxide layer (thickness of 760 angstroms), the backlight module also includes The passivation layer is away from the indium tin oxide layer (thickness of 500 angstroms) on the side of the array layer. Among them, the reflective layer composed of the passivation layer and the indium tin oxide layer has a reflectivity of 88% for light with a wavelength of 450 nanometers.
  • the backlight module of this embodiment is basically similar to the implementation of a backlight module, except that the passivation layer includes a silicon nitride layer (thickness 2400 angstroms) sequentially arranged on the array layer , Indium tin oxide layer (thickness of 500 angstroms), silicon oxide layer (thickness of 750 angstroms), amorphous silicon layer (thickness of 250 angstroms), silicon oxide layer (thickness of 1050 angstroms) and amorphous silicon layer (thickness of 750 angstroms) 196 Angstroms).
  • the reflectivity of the passivation layer to a wavelength of 450 nanometers is 78.6%
  • the reflectivity of the passivation layer to light of different wavelengths is shown in FIG. 3.
  • the backlight module of this embodiment is basically similar to the backlight module of the first embodiment, except that the passivation layer includes a silicon nitride layer (with a thickness of 658 angstroms), amorphous silicon layer (thickness 170 angstroms) and silicon nitride layer (thickness 1200 angstroms). Among them, the passivation layer and the indium tin oxide layer have a reflectivity of 79% for light with a wavelength of 450 nanometers.
  • the backlight module of this embodiment is basically similar to the backlight module of the first embodiment, except that the passivation layer includes a silicon nitride layer (with a thickness of 650 angstroms), an amorphous silicon layer (thickness of 178 angstroms) and a silicon nitride layer (thickness of 600 angstroms), the backlight module also includes an indium tin oxide layer (thickness of 500 angstroms) arranged on the side of the passivation layer away from the array layer ). Among them, the reflectivity of the passivation layer and the indium tin oxide layer to light with a wavelength of 450 nanometers is 83.8%. The reflectivity of the reflective layer composed of the passivation layer and the indium tin oxide layer in this embodiment to light of different wavelengths is shown in FIG. 4.
  • This embodiment provides a backlight module.
  • the backlight module of this embodiment is similar to the backlight module substrate of the first embodiment, except that the passivation layer includes silicon nitride (with a thickness of 950) sequentially disposed on the array layer. Angstroms) and a silicon oxide layer (1500 Angstroms). Among them, the reflectivity of the passivation layer to light with a wavelength of 450 nanometers is 68%.
  • implementation one, implementation two and implementation three that the selection of an indium tin oxide layer with a suitable thickness and the proper position setting of the indium tin oxide can significantly increase the refractive index of the reflective layer composed of the passivation layer and the indium tin oxide layer.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Planar Illumination Modules (AREA)

Abstract

本申请提供一种阵列基板及显示装置，阵列层设置于基板上，钝化层形成于阵列层远离基板的一侧，钝化层包括依次叠置的第一介质层、第二介质层以及第三介质层，第一介质层靠近阵列层，第三介质层远离阵列层，第一介质层的折射率与第二介质层的折射率相异，第二介质层的折射率与第三介质层的折射率相异。

Description

阵列基板及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种阵列基板及显示装置。
 背景技术
目前，在亚毫米发光二极管（mini-LED）组成的背光模组上涂覆白油用来反射亚毫米发光二极管发出的光的同时，且能起到防刮伤的作用。然而，涂覆白油作为一道单独的制程会增加背光模组的制造成本。
因此，有必要提出一种技术方案以制作反射层的同时能降低制造成本。
 技术问题
本申请的目的在于提供一种阵列基板及显示装置，以解决传统白油作为反射层需要单独制程导致制造成本高的问题。
 技术解决方案
为实现上述目的，本申请提供一种阵列基板，所述阵列基板包括基板、阵列层、钝化层以及发光元件，
所述阵列层设置于所述基板上，所述发光元件设置于所述阵列层上；
所述钝化层形成于所述阵列层远离所述基板的一侧，所述钝化层包括依次叠置的第一介质层、第二介质层以及第三介质层，所述第一介质层靠近所述阵列层，所述第三介质层远离所述阵列层，所述第一介质层的折射率与所述第二介质层的折射率相异，所述第二介质层的折射率与所述第三介质层的折射率相异。
在上述阵列基板中，所述第二介质层的折射率大于所述第一介质层的折射率和所述第三介质层的折射率。
在上述阵列基板中，所述第二介质层的折射率与所述第一介质层的折射率的差值大于或等于1且小于或等于3，所述第二介质层的折射率与所述第三介质层的折射率的差值大于或等于1且小于或等于3。
在上述阵列基板中，所述第一介质层和所述第三介质层为氮化硅层，所述第二介质层为非晶硅层，所述第一介质层的厚度为640埃-660埃，所述第二介质层的厚度为160埃-180埃，所述第三介质层的厚度为600埃-1200埃。
在上述阵列基板中，所述钝化层还包括第四介质层，所述第四介质层形成于所述第三介质层远离所述阵列层的一侧，所述第四介质层的折射率与所述第三介质层的折射率的差值大于所述第二介质层的折射率与所述第一介质层的折射率的差值。
在上述阵列基板中，所述第一介质层为氮化硅层，所述第三介质层为氧化硅层，所述第二介质层和所述第四介质层均为非晶硅层，所述第一介质层的厚度为2400埃-2500埃，所述第二介质层的厚度为235埃-255埃，所述第三介质层的厚度为1050埃-1080埃，所述第四介质层的厚度为190埃-220埃。
在上述阵列基板中，所述阵列基板还包括氧化铟锡层，所述氧化铟锡层位于所述钝化层远离所述阵列层的一侧，所述氧化铟锡层的厚度为480埃-520埃。
在上述阵列基板中，所述钝化层上具有通孔，所述通孔由内壁围合而成，所述内壁的坡角的取值范围为18°-87°。
在上述阵列基板中，所述发光元件为亚毫米发光二极管或微型发光二极管中的一种。
一种显示装置，所述显示装置包括阵列基板，所述阵列基板包括基板、阵列层、钝化层以及发光元件，
所述阵列层设置于所述基板上，所述发光元件设置于所述阵列层上；
所述钝化层形成于所述阵列层远离所述基板的一侧，所述钝化层包括依次叠置的第一介质层、第二介质层以及第三介质层，所述第一介质层靠近所述阵列层，所述第三介质层远离所述阵列层，所述第一介质层的折射率与所述第二介质层的折射率相异，所述第二介质层的折射率与所述第三介质层的折射率相异。
在上述显示装置中，所述第二介质层的折射率大于所述第一介质层的折射率和所述第三介质层的折射率。
在上述显示装置中，所述第二介质层的折射率与所述第一介质层的折射率的差值大于或等于1且小于或等于3，所述第二介质层的折射率与所述第三介质层的折射率的差值大于或等于1且小于或等于3。
在上述显示装置中，所述第一介质层和所述第三介质层为氮化硅层，所述第二介质层为非晶硅层，所述第一介质层的厚度为640埃-660埃，所述第二介质层的厚度为160埃-180埃，所述第三介质层的厚度为600埃-1200埃。
在上述显示装置中，所述钝化层还包括第四介质层，所述第四介质层形成于所述第三介质层远离所述阵列层的一侧，所述第四介质层的折射率与所述第三介质层的折射率的差值大于所述第二介质层的折射率与所述第一介质层的折射率的差值。
在上述显示装置中，所述第一介质层为氮化硅层，所述第三介质层为氧化硅层，所述第二介质层和所述第四介质层均为非晶硅层，所述第一介质层的厚度为2400埃-2500埃，所述第二介质层的厚度为235埃-255埃，所述第三介质层的厚度为1050埃-1080埃，所述第四介质层的厚度为190埃-220埃。
在上述显示装置中，所述阵列基板还包括氧化铟锡层，所述氧化铟锡层位于所述钝化层远离所述阵列层的一侧，所述氧化铟锡层的厚度为480埃-520埃。
在上述显示装置中，所述钝化层上具有通孔，所述通孔由内壁围合而成，所述内壁的坡角的取值范围为18°-87°。
在上述显示装置中，所述发光元件为亚毫米发光二极管或微型发光二极管中的一种。
 有益效果
本申请提供一种阵列基板及显示装置，阵列基板包括基板、阵列层、钝化层以及发光元件，阵列层设置于基板上，发光元件设置于阵列层上，钝化层形成于阵列层远离基板的一侧，钝化层包括依次叠置的第一介质层、第二介质层以及第三介质层，第一介质层靠近阵列层，第三介质层远离阵列层，第一介质层的折射率与第二介质层的折射率相异，第二介质层的折射率与第三介质层的折射率相异。本申请钝化层起到反射作用，相对于涂覆白油作为一道单独制程，节省阵列基板的制造成本且提升阵列基板的良率。相对于传统反射层由两个不同折射率介质层组成，本申请钝化层配合合适的厚度对波长为450纳米的光进行反射，且对波长为450纳米的光的反射率高达88%。
 附图说明
图1为本申请实施例背光模组的示意图；
图2为本申请实施一背光模组中钝化层对不同波长的光的反射率的示意图；
图3为本申请实施例三背光模组中钝化层对不同波长的光的反射率的示意图；
图4为本申请实施例五背光模组中钝化层以及氧化铟锡层构成的反射层对不同波长的光的反射率的示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参阅图1，其为本申请实施例背光模组的示意图。背光模组100包括阵列基板，阵列基板包括基板101、阵列层102、钝化层103、发光元件105以及氧化铟锡层104。
基板101为玻璃基板。阵列层102设置于基板101上。发光元件105设置于阵列层102上。阵列层102包括多个阵列排布的薄膜晶体管（未示出），薄膜晶体管可以为背蚀沟道型薄膜晶体管或刻蚀阻挡型薄膜晶体管。阵列层102还包括导电电极，每个发光元件105与阵列层102中的两个导电电极通过导电胶或焊锡连接，其中一个导电电极与薄膜晶体管的漏极连接。发光元件105为亚毫米发光二极管。每个发光元件105包括一个红光亚毫米发光二极管、一个蓝光亚毫米发光二极管以及一个绿光亚毫米发光二极管。
钝化层103形成于阵列层102远离基板101的一侧，钝化层103包括依次叠置的第一介质层、第二介质层以及第三介质层，第一介质层靠近阵列层102，第三介质层远离阵列层102，第一介质层的折射率与第二介质层的折射率相异，第二介质层的折射率与第三介质层的折射率相异。第一介质层的折射率和第二介质层的折射率不同对光起到反射作用，配合第二介质层的折射率与第三介质层的折射率不同，实现对光的反射。
本申请背光模组通过钝化层包括依次叠置的第一介质层、第二介质层以及第三介质层，第一介质层的折射率与第二介质层的折射率相异，第二介质层的折射率与第三介质层的折射率相异，以实现钝化层对光的反射率，钝化层为背光模组的一道制程，相对于传统白色油墨涂覆需要增加一道单独的制程，调试钝化层膜层结构以及膜质，达到白色油墨反射率水准相当的光反射效果以及防刮伤效果。发明人基于大量实验发现，传统钝化层为叠置于阵列层上的氮化硅以及氧化硅膜层时，对450纳米的光的反射率最大值为68%，无法与白色油墨的反射率相当的反射率，而本申请采用钝化层为三个膜层，能实现与白色油墨相当的反射率。
在一些实施例中，第二介质层的折射率大于第一介质层的折射率和第三介质层的折射率，光从第二介质入射至第一介质层为从光密介质到光疏介质，以使光在第一介质层和第二介质层之间的反射的可能性提高。第一介质层的折射率大于或等于第三介质层的折射率。
在一些实施例中，第二介质层的折射率与第一介质层的折射率的差值大于或等于1且小于或等于3，第二介质层的折射率与第三介质层的折射率的差值大于或等于1且小于或等于3。例如，第二介质层的折射率与第一介质层的折射率的差值为1.2、1.5、1.8、2.0、2.4、2.8，第二介质层的折射率与第三介质层的折射率的差值为1.2、1.5、1.8、2.0、2.2、2.4、2.8。
在一些实施例中，第二介质层的折射率与第三介质层的折射率的差值大于第二介质层的折射率与第一介质层的折射率的差值。
具体地，第一介质层和第三介质层为氮化硅层，第二介质层为非晶硅层，第一介质层的厚度为640埃-660埃，第二介质层的厚度为160埃-180埃，第三介质层的厚度为600埃-1200埃。通过第一介质层、第二介质层以及第三介质层的折射率高低匹配，以实现光的反射率，配合合适厚度的选择，以实现对波长为440纳米-460纳米的光进行选择性的反射。
在一些实施例中，钝化层还包括第四介质层，第四介质层形成于第三介质层远离阵列层的一侧，第四介质层的折射率与第三介质层的折射率的差值大于第二介质层的折射率与第一介质层的折射率的差值，以进一步增加对光的反射率。
具体地，第一介质层为氮化硅，第三介质层为氧化硅层，第二介质层和第四介质层均为非晶硅层，第一介质层的厚度为2400埃-2500埃，第二介质层的厚度为235埃-255埃，第三介质层的厚度为1050埃-1080埃，第四介质层的厚度为190埃-220埃。氮化硅的折射率为1.88，氧化硅的折射率为1.4，非晶硅的折射率为3.0-4.0。
氧化铟锡层104位于钝化层103远离阵列层102的一侧，氧化铟锡层104的厚度为480埃-520埃。氧化铟锡层104一方面起到用于绑定芯片的作用，另一方面选择合适的厚度配合钝化层103实现光的反射。
如图1所示，钝化层103上具有通孔，通孔由内壁103a围合而成，内壁103a的坡脚的取值范围为18°-87°，例如坡脚为20°、30°、40°以及65°。相对于传统钝化层为单层，钝化层103由不同膜层组成以实现反射时，蚀刻钝化层103以形成通孔会由于钝化层由不同膜层组成，不同膜层蚀刻速率存在差异导致坡(Taper)脚过大而导致氧化铟锡层104在通孔中形成不连续的膜层，导致与氧化铟锡层104连接的芯片绑定良率降低，且会导致阵列层102中的栅极绝缘层等出现undercut（栅极绝缘层过度蚀刻）现象。内壁103a的坡脚的取值范围为18°-87°可以通过优化钝化层103的蚀刻工艺实现，也可以通过优化钝化层103的膜层组成实现。
本申请还提供一种显示装置，显示装置包括液晶显示面板以及上述背光模组，或，显示装置包括显示面板，显示面板包括上述阵列基板，不同之处在于，显示面板包括上述阵列基板时，发光元件105为微型发光二极管。
以下结合具体实施例和对比例对上述方案进行详述。
实施例一
本实施例提供一种背光模组，背光模组包括阵列基板以及钝化层，阵列基板包括基板、阵列层以及亚毫米发光二极管，阵列层设置于基板上，亚毫米发光二极管设置于阵列层上，钝化层设置于阵列层上，钝化层包括依次设置于阵列层上的氮化硅层(厚度2400埃)、非晶硅层（厚度240埃）、氧化硅层（厚度1080埃）以及非晶硅层(厚度210埃)。其中，钝化层对波长为450纳米的光的反射率为78.6%，钝化层对不同波长的光的反射率如图2所示。
实施例二
本实施例提供一种背光模组，本实施例背光模组与实施例一中背光模组基本相似，不同之处在于，钝化层包括依次设置于阵列层上的氮化硅层(厚度2420埃)、非晶硅层（厚度250埃）、氧化硅层（厚度为1060埃）、非晶硅层(厚度200埃)以及氧化硅层（厚度为760埃），背光模组还包括设置于钝化层远离阵列层一侧的氧化铟锡层（厚度为500埃）。其中，钝化层以及氧化铟锡层组成的反射层对波长为450纳米的光的反射率为88%。
实施例三
本实施例提供一种背光模组，本实施例背光模组与实施一背光模组基本相似，不同之处在于，钝化层包括依次设置于阵列层上的氮化硅层（厚度2400埃）、氧化铟锡层（厚度为500埃）、氧化硅层（厚度为750埃）、非晶硅层（厚度为250埃）、氧化硅层（厚度为1050埃）以及非晶硅层（厚度为196埃）。其中，钝化层对波长为450纳米的反射率为78.6%，钝化层对不同波长的光的反射率如图3示。
实施例四
本实施例提供一种背光模组，本实施例背光模组与实施例一中背光模组基本相似，不同之处在于，钝化层包括依次设置于阵列层上的氮化硅层（厚度为658埃）、非晶硅层（厚度为170埃）以及氮化硅层（厚度1200埃）。其中，钝化层以及氧化铟锡层对波长为450纳米的光的反射率为79%。
实施例五
本实施例提供一种背光模组，本实施例背光模组与实施例一中背光模组基本相似，不同之处在于，钝化层包括依次设置于阵列层上的氮化硅层（厚度为650埃）、非晶硅层（厚度为178埃）以及氮化硅层（厚度600埃），背光模组还包括设置于钝化层远离阵列层一侧的氧化铟锡层（厚度为500埃）。其中，钝化层以及氧化铟锡层对波长为450纳米的光的反射率为83.8%。本实施例钝化层以及氧化铟锡层构成的反射层对不同波长的光的反射率如图4所示。
对比例一
本实施例提供一种背光模组，本实施例背光模组与实施例一中背光模组基板相似，不同之处在于，钝化层包括依次设置于阵列层上的氮化硅（厚度为950埃）以及氧化硅层（1500埃）。其中，钝化层对波长为450纳米的光的反射率为68%。
由实施一至实施五可知，本申请实施例钝化层为三层或三层以上介质层组成时，配合合适的厚度选择，对波长为450纳米的光的反射率大于或等于78.6%。而对比例中钝化层为两个不同折射率膜层时，钝化层对波长为450纳米的光的反射率为68%，钝化层为两个不同折射率膜层时对波长为450纳米的光的反射率小于钝化层为三个介质层对波长为450纳米的光的反射率。由实施一、实施二以及实施三可知，合适厚度的氧化铟锡层选择以及氧化铟锡的合适位置设置，才会明显增加钝化层以及氧化铟锡层构成的反射层的折射率。
以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (18)

  1. 一种阵列基板，其中，所述阵列基板包括基板、阵列层、钝化层以及发光元件，
    所述阵列层设置于所述基板上，所述发光元件设置于所述阵列层上；
    所述钝化层形成于所述阵列层远离所述基板的一侧，所述钝化层包括依次叠置的第一介质层、第二介质层以及第三介质层，所述第一介质层靠近所述阵列层，所述第三介质层远离所述阵列层，所述第一介质层的折射率与所述第二介质层的折射率相异，所述第二介质层的折射率与所述第三介质层的折射率相异。
  2. 根据权利要求1所述的阵列基板，其中，所述第二介质层的折射率大于所述第一介质层的折射率和所述第三介质层的折射率。
  3. 根据权利要求1所述的阵列基板，其中，所述第二介质层的折射率与所述第一介质层的折射率的差值大于或等于1且小于或等于3，所述第二介质层的折射率与所述第三介质层的折射率的差值大于或等于1且小于或等于3。
  4. 根据权利要求3所述的阵列基板，其中，所述第一介质层和所述第三介质层为氮化硅层，所述第二介质层为非晶硅层，所述第一介质层的厚度为640埃-660埃，所述第二介质层的厚度为160埃-180埃，所述第三介质层的厚度为600埃-1200埃。
  5. 根据权利要求1所述的阵列基板，其中，所述钝化层还包括第四介质层，所述第四介质层形成于所述第三介质层远离所述阵列层的一侧，所述第四介质层的折射率与所述第三介质层的折射率的差值大于所述第二介质层的折射率与所述第一介质层的折射率的差值。
  6. 根据权利要求5所述的阵列基板，其中，所述第一介质层为氮化硅层，所述第三介质层为氧化硅层，所述第二介质层和所述第四介质层均为非晶硅层，所述第一介质层的厚度为2400埃-2500埃，所述第二介质层的厚度为235埃-255埃，所述第三介质层的厚度为1050埃-1080埃，所述第四介质层的厚度为190埃-220埃。
  7. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括氧化铟锡层，所述氧化铟锡层位于所述钝化层远离所述阵列层的一侧，所述氧化铟锡层的厚度为480埃-520埃。
  8. 根据权利要求1所述的阵列基板，其中，所述钝化层上具有通孔，所述通孔由内壁围合而成，所述内壁的坡角的取值范围为18°-87°。
  9. 根据权利要求1所述的阵列基板，其中，所述发光元件为亚毫米发光二极管或微型发光二极管中的一种。
  10. 一种显示装置，其中，所述显示装置包括阵列基板，所述阵列基板包括基板、阵列层、钝化层以及发光元件，
    所述阵列层设置于所述基板上，所述发光元件设置于所述阵列层上；
    所述钝化层形成于所述阵列层远离所述基板的一侧，所述钝化层包括依次叠置的第一介质层、第二介质层以及第三介质层，所述第一介质层靠近所述阵列层，所述第三介质层远离所述阵列层，所述第一介质层的折射率与所述第二介质层的折射率相异，所述第二介质层的折射率与所述第三介质层的折射率相异。
  11. 根据权利要求10所述的显示装置，其中，所述第二介质层的折射率大于所述第一介质层的折射率和所述第三介质层的折射率。
  12. 根据权利要求10所述的显示装置，其中，所述第二介质层的折射率与所述第一介质层的折射率的差值大于或等于1且小于或等于3，所述第二介质层的折射率与所述第三介质层的折射率的差值大于或等于1且小于或等于3。
  13. 根据权利要求12所述的显示装置，其中，所述第一介质层和所述第三介质层为氮化硅层，所述第二介质层为非晶硅层，所述第一介质层的厚度为640埃-660埃，所述第二介质层的厚度为160埃-180埃，所述第三介质层的厚度为600埃-1200埃。
  14. 根据权利要求10所述的显示装置，其中，所述钝化层还包括第四介质层，所述第四介质层形成于所述第三介质层远离所述阵列层的一侧，所述第四介质层的折射率与所述第三介质层的折射率的差值大于所述第二介质层的折射率与所述第一介质层的折射率的差值。
  15. 根据权利要求14所述的显示装置，其中，所述第一介质层为氮化硅层，所述第三介质层为氧化硅层，所述第二介质层和所述第四介质层均为非晶硅层，所述第一介质层的厚度为2400埃-2500埃，所述第二介质层的厚度为235埃-255埃，所述第三介质层的厚度为1050埃-1080埃，所述第四介质层的厚度为190埃-220埃。
  16. 根据权利要求10所述的显示装置，其中，所述阵列基板还包括氧化铟锡层，所述氧化铟锡层位于所述钝化层远离所述阵列层的一侧，所述氧化铟锡层的厚度为480埃-520埃。
  17. 根据权利要求10所述的显示装置，其中，所述钝化层上具有通孔，所述通孔由内壁围合而成，所述内壁的坡角的取值范围为18°-87°。
  18. 根据权利要求10所述的显示装置，其中，所述发光元件为亚毫米发光二极管或微型发光二极管中的一种。
PCT/CN2020/096285 2020-04-09 2020-06-16 阵列基板及显示装置 WO2021203552A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/057,076 US20220190206A1 (en) 2020-04-09 2020-06-16 Array substrate and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010275257.3A CN111430376B (zh) 2020-04-09 2020-04-09 阵列基板及显示装置
CN202010275257.3 2020-04-09

Publications (1)

Publication Number Publication Date
WO2021203552A1 true WO2021203552A1 (zh) 2021-10-14

Family

ID=71556129

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/096285 WO2021203552A1 (zh) 2020-04-09 2020-06-16 阵列基板及显示装置

Country Status (3)

Country Link
US (1) US20220190206A1 (zh)
CN (1) CN111430376B (zh)
WO (1) WO2021203552A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101911313A (zh) * 2008-08-01 2010-12-08 Lg电子株式会社 太阳能电池和制造该太阳能电池的方法
US20110140090A1 (en) * 2009-12-10 2011-06-16 Samsung Mobile Display Co., Ltd. Organic light emitting diode display
CN103715276A (zh) * 2012-09-28 2014-04-09 茂迪股份有限公司 太阳能电池及其模组
CN104299978A (zh) * 2013-07-17 2015-01-21 精工爱普生株式会社 发光装置及其制造方法、受光发光装置、电子设备
JP2016058586A (ja) * 2014-09-10 2016-04-21 シャープ株式会社 表示装置及びテレビ受信装置
CN108183156A (zh) * 2017-12-26 2018-06-19 深圳市华星光电技术有限公司 微型发光二极管显示面板及其制作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3028902B2 (ja) * 1993-10-06 2000-04-04 三菱化学株式会社 光学的情報記録用媒体
TWI326491B (en) * 2006-11-09 2010-06-21 Chunghwa Picture Tubes Ltd Trans-reflective liquid crystal display and manufacturing method thereof
KR20100062544A (ko) * 2008-12-02 2010-06-10 삼성전자주식회사 박막 트랜지스터 기판의 제조 방법
KR102115564B1 (ko) * 2013-09-24 2020-05-27 삼성디스플레이 주식회사 표시기판 및 이를 포함하는 표시패널
US10319880B2 (en) * 2016-12-02 2019-06-11 Innolux Corporation Display device
CN106935546B (zh) * 2017-04-12 2019-09-06 京东方科技集团股份有限公司 阵列基板的制备方法、阵列基板、显示面板和显示装置
CN107134482A (zh) * 2017-05-09 2017-09-05 京东方科技集团股份有限公司 一种薄膜晶体管及其制作方法、显示面板、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101911313A (zh) * 2008-08-01 2010-12-08 Lg电子株式会社 太阳能电池和制造该太阳能电池的方法
US20110140090A1 (en) * 2009-12-10 2011-06-16 Samsung Mobile Display Co., Ltd. Organic light emitting diode display
CN103715276A (zh) * 2012-09-28 2014-04-09 茂迪股份有限公司 太阳能电池及其模组
CN104299978A (zh) * 2013-07-17 2015-01-21 精工爱普生株式会社 发光装置及其制造方法、受光发光装置、电子设备
JP2016058586A (ja) * 2014-09-10 2016-04-21 シャープ株式会社 表示装置及びテレビ受信装置
CN108183156A (zh) * 2017-12-26 2018-06-19 深圳市华星光电技术有限公司 微型发光二极管显示面板及其制作方法

Also Published As

Publication number Publication date
CN111430376B (zh) 2022-12-23
CN111430376A (zh) 2020-07-17
US20220190206A1 (en) 2022-06-16

Similar Documents

Publication Publication Date Title
JP2019510989A (ja) 反射減少構造及びその製造方法、ディスプレイ装置及びその製造方法
JP2008242410A (ja) 多層膜
WO2020073627A1 (zh) 一种量子点偏光片
TW202038493A (zh) 顯示面板
US20230161194A1 (en) Light emitting device, backlight, and display panel
WO2021022587A1 (zh) 显示面板及其制作方法
US10788618B2 (en) Backlight module as well as display panel and electronic device comprising the same
JP3835319B2 (ja) マイクロレンズ用凹部付き基板の製造方法、マイクロレンズ用凹部付き基板、マイクロレンズ基板、液晶パネル用対向基板、液晶パネルおよび投射型表示装置
WO2023108695A1 (zh) 显示面板及显示装置
WO2021203552A1 (zh) 阵列基板及显示装置
WO2017206284A1 (zh) 超薄型液晶显示器
WO2022252269A1 (zh) 一种盖板及显示装置
WO2024040751A1 (zh) 显示面板及其制备方法、显示装置
WO2021208176A1 (zh) 显示面板及其制备方法
CN112992998B (zh) 显示面板、显示装置及显示面板的制作方法
WO2023142165A1 (zh) 显示面板及显示装置
TWI776654B (zh) 顯示裝置及其製造方法
WO2024082507A1 (zh) 显示面板及其制作方法、显示终端
TWI791245B (zh) 顯示裝置
TWI804456B (zh) 顯示裝置
WO2023236280A1 (zh) 背光模组及显示模组
US10866483B2 (en) Optical switching device
US20240038744A1 (en) Substrate encapsulating method, display panel, and display device
WO2022246745A1 (zh) 背光模组、其制作方法及显示装置
WO2024077471A1 (zh) 显示母板、显示面板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20929827

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20929827

Country of ref document: EP

Kind code of ref document: A1