WO2021203485A1 - Circuit goa et panneau d'affichage - Google Patents

Circuit goa et panneau d'affichage Download PDF

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Publication number
WO2021203485A1
WO2021203485A1 PCT/CN2020/086024 CN2020086024W WO2021203485A1 WO 2021203485 A1 WO2021203485 A1 WO 2021203485A1 CN 2020086024 W CN2020086024 W CN 2020086024W WO 2021203485 A1 WO2021203485 A1 WO 2021203485A1
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WIPO (PCT)
Prior art keywords
transistor
node
potential
signal
output terminal
Prior art date
Application number
PCT/CN2020/086024
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English (en)
Chinese (zh)
Inventor
陶健
Original Assignee
武汉华星光电技术有限公司
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Priority to US16/966,032 priority Critical patent/US11749166B2/en
Publication of WO2021203485A1 publication Critical patent/WO2021203485A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the embodiments of the present application relate to the field of display technology, and in particular, to a GOA circuit and a display panel.
  • GOA Gate Driver On Array
  • GOA technology can reduce the bonding process of external IC, can reduce product cost, and is more suitable for manufacturing narrow-frame or borderless display products.
  • the existing GOA circuit includes a plurality of cascaded GOA units, and each level of GOA unit correspondingly drives a level of horizontal scan line.
  • Each level of GOA unit mainly includes a pull-up circuit, a pull-up control circuit, a pull-down circuit, and a pull-down sustain circuit.
  • the pull-up circuit is mainly responsible for outputting the clock signal as the gate signal, that is, the Gate signal; the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit, and is generally connected to the Gate signal transmitted by the previous GOA unit; the pull-down circuit is responsible for the first time The Gate signal is pulled down to a low level, that is, the Gate signal is turned off; the pull-down sustain circuit is responsible for maintaining the Gate signal and the Gate signal of the pull-up circuit (usually called the Q point) in the off state.
  • FIG. 1 is a circuit diagram of an existing GOA circuit
  • FIG. 2 is an ideal timing diagram of an existing GOA circuit
  • FIG. 3 is a simulation timing diagram of an existing GOA circuit.
  • the potentials of node Qb and node Qa are maintained by capacitor C1, but in the case of long-term maintenance, such as in the t1 and t2 stages of Figure 2 and Figure 3, the capacitor C1 will pass through NT2 and NT10 If the two leakage paths leak, the potentials of node Qb and node Qa will decrease over time, especially when the holding time is long, the voltage of node Qb and node Qa will drop faster, so that the bootstrap voltage of node Qa ( Phase t2) will become lower, which will affect the gate output waveform, causing an abnormal screen, that is, the bootstrap voltage (the gate voltage of the driving transistor T3), that is, the potential of the node Qb and the node Qa will decrease due to leakage, thereby affecting the bootstrap voltage. Amplitude, leading to serious distortion of the gate output waveform, causing abnormal display of the screen.
  • the present application provides a GOA circuit and a display panel to solve the problem that when the screen holding time is longer during the touch scan phase during the normal display phase, the potential of the node Qb and the node Qa is reduced, which causes serious distortion of the gate output waveform and causes the screen The problem of abnormal display.
  • the present application provides a GOA circuit.
  • the GOA circuit includes a plurality of cascaded GOA units.
  • the GOA units of each stage include: a positive and negative scanning module 100, a reset module 200, a pull-up module 300, a pull-down module 400, and a voltage regulator Module 500, anti-leakage module 500, voltage stabilization module 600, signal control module 700, and pull-up maintenance module 800.
  • the positive and negative scanning module 100 includes a first transistor T1 and a second transistor T2, wherein the gate of the first transistor T1 is connected to the output terminal G(N-1) of the upper-level GOA unit, and the source is connected to the forward The scan signal U2D, the drain is electrically connected to the first node Qb; the gate of the second transistor T2 is connected to the output terminal G(N+1) of the lower-level GOA unit, the source is connected to the reverse scan signal D2U, and the drain is Electrically connected to the first node Qb.
  • the reset module 200 includes a seventh transistor T7, wherein the gate and source of the seventh transistor T7 are both connected to the reset signal Reset, and the drain is electrically connected to the second node P.
  • the pull-up module 300 includes a third transistor T3, wherein the gate of the third transistor T3 is electrically connected to the pull-up node Qa, the source is connected to the Nth clock signal CK(N), and the drain is electrically connected The output terminal G (N).
  • the pull-down module 400 includes a fourth transistor T4 and a tenth transistor T10, wherein the gates of the fourth transistor T4 and the tenth transistor T10 are both electrically connected to the second node P, and the fourth transistor T4 and The source of the tenth transistor T10 is connected to the first potential, the drain of the fourth transistor T4 is electrically connected to the output terminal G(N), and the drain of the tenth transistor T10 is electrically connected to the output terminal G(N).
  • the first node Qb is a fourth transistor T4 and a tenth transistor T10, wherein the gates of the fourth transistor T4 and the tenth transistor T10 are both electrically connected to the second node P, and the fourth transistor T4 and The source of the tenth transistor T10 is connected to the first potential, the drain of the fourth transistor T4 is electrically connected to the output terminal G(N), and the drain of the tenth transistor T10 is electrically connected to the output terminal G(N).
  • the first node Qb is
  • the leakage prevention module 500 includes a ninth transistor T9, wherein the gate of the ninth transistor T9 is connected to the second potential, the source is electrically connected to the first node Qb, and the drain is electrically connected to the Pull up node Qa.
  • the voltage stabilizing module 600 includes a first capacitor C1 and a second capacitor C2, wherein one end of the first capacitor C1 is electrically connected to the first node Qb, and the other end is connected to the first potential; One end of the two capacitors C2 is electrically connected to the second node P, and the other end is connected to the first potential.
  • the signal control module 700 includes a fifth transistor T5 and a sixth transistor T6, wherein the gate of the fifth transistor T5 is electrically connected to the first node Qb, the source is connected to the first potential, and the drain is connected to the first node Qb. Is electrically connected to the second node P; the gate of the sixth transistor T6 is connected to the N+1th clock signal CK(N+1), the source is connected to the second potential, and the drain is electrically connected The second node P.
  • the pull-up maintenance module 800 includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13, wherein the gate and source of the eleventh transistor T11 are both connected to the second potential, The drain is electrically connected to the third node K; the gate of the twelfth transistor T12 is electrically connected to the third node K, the source is connected to the second potential, and the drain is electrically connected to the first node Qb; the gate of the thirteenth transistor T13 is electrically connected to the second node P, the source is connected to the first potential, and the drain is electrically connected to the third node K.
  • the GOA circuit has a reset phase and a normal display phase.
  • the reset signal Reset provides a single pulse signal of the second potential to control the seventh transistor T7 to turn on so that the second node P is at the second potential, and the second node P controls
  • the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13 are turned on so that the output terminal G(N), the first node Qb, the pull-up node Qa, and the third node K Is the first potential.
  • the normal display phase includes a pre-charge sub-phase t1, an output sub-phase t2, and a pull-down sub-phase t3.
  • the output terminal G(N-1) of the upper-level GOA unit or the output terminal G(N+1) of the lower-level GOA unit provides a second level so that the first transistor T1 or The second transistor T2 is turned on, so that the first node Qb and the pull-up node Qa are converted to the second potential and the first capacitor C1 is charged.
  • the third transistor T3 and the The fifth transistor T5 is turned on; the fifth transistor T5 is turned on to convert the second node P to the first potential so that the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13 are turned off .
  • the output terminal G(N-1) of the upper-level GOA unit and the output terminal G(N+1) of the lower-level GOA unit provide a first level so that the first transistor T1 and The second transistor T2 is turned off, the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on to keep the first node Qb at the second potential, and the pull-up node
  • the potential of Qa is converted from the second potential to a bootstrap potential; at the same time, the Nth clock signal CK(N) provides the second potential and is output as the output terminal G( N) Signal.
  • the thirteenth transistor T13 is turned off so that the third node K is converted to the second potential under the control of the eleventh transistor, so that all The twelfth transistor T12 is turned on to charge the first node Qb so that the first node Qb maintains the second potential.
  • the output terminal G(N-1) of the upper-level GOA unit or the output terminal G(N+1) of the lower-level GOA unit provides a second potential to enable the first transistor T1 or the second transistor T2 to turn on.
  • the scan signal U2D or the reverse scan signal D2U provides a first potential to the first node Qb and the pull-up node Qa, and the N+1th clock signal CK(N+1) turns on the sixth transistor T6 to
  • the second node P is converted to the second potential and the second capacitor C2 is charged.
  • the second node P causes the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor to be charged.
  • the transistor T13 is turned on to convert the output terminal G(N), the first node Qb, the pull-up node Qa, and the third node K into a first potential; the third node K enables the The twelfth transistor is turned off so that the twelfth transistor T12 stops charging the first node Qb.
  • the first capacitor C1 keeps the first node Qb and the pull-up node Qa at the first potential to keep the third transistor T3 off, and the second capacitor C2 keeps the second node P The second potential is maintained to keep the fourth transistor T4 turned on, and the output terminal G(N) is maintained at the first potential.
  • one of the forward scan signal U2D and the reverse scan signal D2U is at a high level and the other signal is at a low level.
  • the output terminal G(N-1) of the upper-level GOA unit controls the first transistor T1 to turn on, and the gate of the first transistor T1 of the first-level GOA unit is connected to the start signal STV.
  • the output terminal G(N+1) of the lower-level GOA unit controls the second transistor T2 to turn on, and the gate of the second transistor T2 of the final-level GOA unit is connected to the start signal STV.
  • each transistor in the GOA circuit is an N-type thin film transistor, the first potential is a constant voltage low potential VGL, and the second potential is a constant voltage high potential VGH.
  • the reset signal Reset provides a single high-potential pulse signal to make the second node P high, the first node Qb, the pull-up node Qa, the third node K,
  • the output terminal G(N-1) of the upper-level GOA unit and the output terminal G(N+1) of the lower-level GOA unit are both low potential.
  • the forward scan signal U2D is a constant voltage high potential VGH during forward scanning and the reverse scan signal D2U is a constant voltage low potential VGL during reverse scanning.
  • the forward scan signal U2D is a constant voltage low potential VGL and the reverse scan signal D2U is a constant voltage high potential VGH
  • the second node P, the Nth clock signal CK(N), the first N+1 clock signals CK(N+1), the output terminal G(N), and the output terminal (G+1) of the lower-level GOA unit are all low potentials
  • the first node Qb, the pull-up node Qa, and the third node K are all high potentials.
  • the second node P, the N+1th clock signal CK(N+1), and the upper-level GOA unit output terminal G(N-1) And the output terminal G(N+1) of the lower-level GOA unit are both low potentials, the first node Qb, the pull-up node Qa, the third node K, and the Nth clock signal CK(N ) And the output terminal G(N) are both high potential;
  • the first node Qb, the pull-up node Qa, the third node K, the Nth clock signal CK(N), the output The terminal G(N) and the output terminal G(N-1) of the upper-level GOA unit are both low, the second node P, the N+1th clock signal CK(N+1) and the The output terminal G(N+1) of the lower-level GOA unit is all high potential.
  • the GOA circuit further includes an output control module 900
  • the output control module 900 includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the global control signal GAS, and the source is connected to the The first potential, the drain is electrically connected to the output terminal G(N).
  • the GOA circuit further includes a touch scan phase after the normal display phase
  • the global control signal GAS controls the output terminals G(N) of all GOA units to be converted to a first potential.
  • each transistor in the GOA circuit is an N-type thin film transistor, and the global control signal GAS is at a low level during the reset phase and the normal display phase, and during the touch scan phase For high potential.
  • each clock signal is a periodic pulse signal; during the touch scan phase, each clock signal is synchronized with the frequency of the touch scan signal Pulse signal.
  • the GOA circuit includes a first clock signal CK1 and a second clock signal CK2; when the Nth clock signal CK(N) is the first clock signal CK1, the Nth clock signal CK1 +1 clock signal CK(N+1) is CK2; in the reset phase and the normal display phase, the period of the first clock signal CK1 and the second clock signal CK2 are the same, and the previous clock signal When the pulse signal of the signal ends, the next clock pulse signal is generated.
  • An embodiment of the present application also provides a display panel including the GOA circuit described above.
  • the GOA circuit includes a plurality of cascaded GOA units, and the GOA units at each stage include: a positive and negative scanning module 100, a reset module 200, a pull-up module 300, a pull-down module 400, a voltage stabilizing module 500, an anti-leakage module 500, The voltage stabilization module 600, the signal control module 700, and the pull-up maintenance module 800.
  • the positive and negative scanning module 100 includes a first transistor T1 and a second transistor T2, wherein the gate of the first transistor T1 is connected to the output terminal G(N-1) of the upper-level GOA unit, and the source is connected to the forward The scan signal U2D, the drain is electrically connected to the first node Qb; the gate of the second transistor T2 is connected to the output terminal G(N+1) of the lower-level GOA unit, the source is connected to the reverse scan signal D2U, and the drain is Electrically connected to the first node Qb.
  • the reset module 200 includes a seventh transistor T7, wherein the gate and source of the seventh transistor T7 are both connected to the reset signal Reset, and the drain is electrically connected to the second node P.
  • the pull-up module 300 includes a third transistor T3, wherein the gate of the third transistor T3 is electrically connected to the pull-up node Qa, the source is connected to the Nth clock signal CK(N), and the drain is electrically connected The output terminal G (N).
  • the pull-down module 400 includes a fourth transistor T4 and a tenth transistor T10, wherein the gates of the fourth transistor T4 and the tenth transistor T10 are both electrically connected to the second node P, and the fourth transistor T4 and The source of the tenth transistor T10 is connected to the first potential, the drain of the fourth transistor T4 is electrically connected to the output terminal G(N), and the drain of the tenth transistor T10 is electrically connected to the output terminal G(N).
  • the first node Qb is a fourth transistor T4 and a tenth transistor T10, wherein the gates of the fourth transistor T4 and the tenth transistor T10 are both electrically connected to the second node P, and the fourth transistor T4 and The source of the tenth transistor T10 is connected to the first potential, the drain of the fourth transistor T4 is electrically connected to the output terminal G(N), and the drain of the tenth transistor T10 is electrically connected to the output terminal G(N).
  • the first node Qb is
  • the leakage prevention module 500 includes a ninth transistor T9, wherein the gate of the ninth transistor T9 is connected to the second potential, the source is electrically connected to the first node Qb, and the drain is electrically connected to the Pull up node Qa.
  • the voltage stabilizing module 600 includes a first capacitor C1 and a second capacitor C2, wherein one end of the first capacitor C1 is electrically connected to the first node Qb, and the other end is connected to the first potential; One end of the two capacitors C2 is electrically connected to the second node P, and the other end is connected to the first potential.
  • the signal control module 700 includes a fifth transistor T5 and a sixth transistor T6, wherein the gate of the fifth transistor T5 is electrically connected to the first node Qb, the source is connected to the first potential, and the drain is connected to the first node Qb. Is electrically connected to the second node P; the gate of the sixth transistor T6 is connected to the N+1th clock signal CK(N+1), the source is connected to the second potential, and the drain is electrically connected The second node P.
  • the pull-up maintenance module 800 includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13, wherein the gate and source of the eleventh transistor T11 are both connected to the second potential, The drain is electrically connected to the third node K; the gate of the twelfth transistor T12 is electrically connected to the third node K, the source is connected to the second potential, and the drain is electrically connected to the first node Qb; the gate of the thirteenth transistor T13 is electrically connected to the second node P, the source is connected to the first potential, and the drain is electrically connected to the third node K.
  • the GOA circuit has a reset phase and a normal display phase.
  • the reset signal Reset provides a single pulse signal of the second potential to control the seventh transistor T7 to turn on so that the second node P is at the second potential, and the second node P controls
  • the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13 are turned on so that the output terminal G(N), the first node Qb, the pull-up node Qa, and the third node K Is the first potential.
  • the normal display phase includes a pre-charge sub-phase t1, an output sub-phase t2, and a pull-down sub-phase t3.
  • the output terminal G(N-1) of the upper-level GOA unit or the output terminal G(N+1) of the lower-level GOA unit provides a second level so that the first transistor T1 or The second transistor T2 is turned on, so that the first node Qb and the pull-up node Qa are converted to the second potential and the first capacitor C1 is charged.
  • the third transistor T3 and the The fifth transistor T5 is turned on; the fifth transistor T5 is turned on to convert the second node P to the first potential so that the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13 are turned off .
  • the output terminal G(N-1) of the upper-level GOA unit and the output terminal G(N+1) of the lower-level GOA unit provide a first level so that the first transistor T1 and The second transistor T2 is turned off, the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on to keep the first node Qb at the second potential, and the pull-up node
  • the potential of Qa is converted from the second potential to a bootstrap potential; at the same time, the Nth clock signal CK(N) provides the second potential and is output as the output terminal G( N) Signal.
  • the thirteenth transistor T13 is turned off so that the third node K is converted to the second potential under the control of the eleventh transistor, so that all The twelfth transistor T12 is turned on to charge the first node Qb so that the first node Qb maintains the second potential.
  • the output terminal G(N-1) of the upper-level GOA unit or the output terminal G(N+1) of the lower-level GOA unit provides a second potential to enable the first transistor T1 or the second transistor T2 to turn on.
  • the scan signal U2D or the reverse scan signal D2U provides a first potential to the first node Qb and the pull-up node Qa, and the N+1th clock signal CK(N+1) turns on the sixth transistor T6 to
  • the second node P is converted to the second potential and the second capacitor C2 is charged.
  • the second node P causes the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor to be charged.
  • the transistor T13 is turned on to convert the output terminal G(N), the first node Qb, the pull-up node Qa, and the third node K into a first potential; the third node K enables the The twelfth transistor is turned off so that the twelfth transistor T12 stops charging the first node Qb.
  • the first capacitor C1 keeps the first node Qb and the pull-up node Qa at the first potential to keep the third transistor T3 off, and the second capacitor C2 keeps the second node P The second potential is maintained to keep the fourth transistor T4 turned on, and the output terminal G(N) is maintained at the first potential.
  • one of the forward scan signal U2D and the reverse scan signal D2U is at a high level and the other signal is at a low level.
  • the output terminal G(N-1) of the upper-level GOA unit controls the first transistor T1 to turn on, and the gate of the first transistor T1 of the first-level GOA unit is connected to the start signal STV.
  • the output terminal G(N+1) of the lower-level GOA unit controls the second transistor T2 to turn on, and the gate of the second transistor T2 of the final-level GOA unit is connected to the start signal STV.
  • each transistor in the GOA circuit is an N-type thin film transistor, the first potential is a constant voltage low potential VGL, and the second potential is a constant voltage high potential VGH.
  • the reset signal Reset provides a single high-potential pulse signal to make the second node P high, the first node Qb, the pull-up node Qa, the third node K,
  • the output terminal G(N-1) of the upper-level GOA unit and the output terminal G(N+1) of the lower-level GOA unit are both low potential.
  • the forward scan signal U2D is a constant voltage high potential VGH during forward scanning and the reverse scan signal D2U is a constant voltage low potential VGL during reverse scanning.
  • the forward scan signal U2D is a constant voltage low potential VGL and the reverse scan signal D2U is a constant voltage high potential VGH
  • the second node P, the Nth clock signal CK(N), the first N+1 clock signals CK(N+1), the output terminal G(N), and the output terminal (G+1) of the lower-level GOA unit are all low potentials
  • the first node Qb, the pull-up node Qa, and the third node K are all high potentials.
  • the second node P, the N+1th clock signal CK(N+1), and the upper-level GOA unit output terminal G(N-1) And the output terminal G(N+1) of the lower-level GOA unit are both low potentials, the first node Qb, the pull-up node Qa, the third node K, and the Nth clock signal CK(N ) And the output terminal G(N) are both high potential;
  • the first node Qb, the pull-up node Qa, the third node K, the Nth clock signal CK(N), the output The terminal G(N) and the output terminal G(N-1) of the upper-level GOA unit are both low, the second node P, the N+1th clock signal CK(N+1) and the The output terminal G(N+1) of the lower-level GOA unit is all high potential.
  • the GOA circuit further includes an output control module 900
  • the output control module 900 includes an eighth transistor T8, the gate of the eighth transistor T8 is connected to the global control signal GAS, and the source is connected to the The first potential, the drain is electrically connected to the output terminal G(N).
  • the GOA circuit further includes a touch scan phase after the normal display phase
  • the global control signal GAS controls the output terminals G(N) of all GOA units to be converted to a first potential.
  • each transistor in the GOA circuit is an N-type thin film transistor, and the global control signal GAS is at a low level during the reset phase and the normal display phase, and during the touch scan phase For high potential.
  • each clock signal is a periodic pulse signal; during the touch scan phase, each clock signal is synchronized with the frequency of the touch scan signal Pulse signal.
  • the GOA circuit includes a first clock signal CK1 and a second clock signal CK2; when the Nth clock signal CK(N) is the first clock signal CK1, the Nth clock signal CK1 +1 clock signal CK(N+1) is CK2; in the reset phase and the normal display phase, the first clock signal CK1 and the second clock signal CK2 have the same period, and the previous clock signal When the pulse signal of the signal ends, the next clock pulse signal is generated.
  • the pull-up sustaining module 800 composed of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 is provided between the forward and reverse scanning module 100 and the first node Qb, so In the pre-charge sub-phase t1 and the output sub-phase t2 of the normal display phase, since the first node Qb is at a high potential, the second node P is pulled down to turn off the thirteenth transistor T13, so that the third node K is turned off by the eleventh transistor T11 is controlled to switch to a high potential, so that the twelfth transistor T12 is turned on and the first node Qb maintains the second potential, and the pull-up node Qa maintains the second potential during the precharge sub-phase t1 and the bootstrap potential during the output sub-phase t2.
  • the second node P is set high to turn on the thirteenth transistor T13, so that the third node K is pulled low. In this way, the third node K turns off the twelfth transistor T12 and stops charging the first node Qb, without affecting the pull-down process.
  • Fig. 1 is a circuit diagram of an existing GOA.
  • Figure 2 is an ideal timing diagram of an existing GOA circuit.
  • Fig. 3 is a simulation timing diagram of an existing GOA circuit.
  • Figure 4 is a GOA circuit diagram of an embodiment of the application.
  • FIG. 5 is a simulation timing diagram of the GOA circuit according to an embodiment of the application.
  • FIG. 6 is a simulation comparison diagram of the pull-up node Qa in the existing GOA circuit and the GOA circuit of the embodiment of the present application when the holding time is 0 seconds.
  • FIG. 7 is a simulation comparison diagram of the pull-up node Qa in the existing GOA circuit and the GOA circuit of the embodiment of the present application when the holding time is 200 microseconds.
  • FIG. 4 is a GOA circuit provided by an embodiment of the application.
  • the GOA circuit includes cascaded multi-level GOA units.
  • Each level of GOA unit includes: a positive and negative scan module 100, a reset module 200, a pull-up module 300, The pull-down module 400, the voltage stabilization module 500, the anti-leakage module 500, the voltage stabilization module 600, the signal control module 700, and the pull-up maintenance module 800.
  • the positive and negative scanning module 100 includes a first transistor T1 and a second transistor T2.
  • the gate of the first transistor T1 is connected to the output terminal G(N-1) of the upper-level GOA unit, and the source is connected to the forward scanning signal U2D.
  • the drain is electrically connected to the first node Qb;
  • the gate of the second transistor T2 is connected to the output terminal G(N+1) of the lower-level GOA unit, the source is connected to the reverse scan signal D2U, and the drain is electrically connected to the first node Qb.
  • the reset module 200 includes a seventh transistor T7.
  • the gate and source of the seventh transistor T7 are both connected to the reset signal Reset, and the drain is electrically connected to the second node P.
  • the pull-up module 300 includes a third transistor T3.
  • the gate of the third transistor T3 is electrically connected to the pull-up node Qa, the source is connected to the Nth clock signal CK(N), and the drain is electrically connected to the output terminal G(N). .
  • the pull-down module 400 includes a fourth transistor T4 and a tenth transistor T10.
  • the gates of the fourth transistor T4 and the tenth transistor T10 are electrically connected to the second node P, the sources are connected to the first potential, and the drain of the fourth transistor T4
  • the pole is electrically connected to the output terminal G(N), and the drain of the tenth transistor T10 is electrically connected to the first node Qb.
  • the leakage prevention module 500 includes a ninth transistor T9.
  • the gate of the ninth transistor T9 is connected to the second potential, the source is electrically connected to the first node Qb, and the drain is electrically connected to the pull-up node Qa.
  • the voltage stabilizing module 600 includes a first capacitor C1 and a second capacitor C2. One end of the first capacitor C1 is electrically connected to the first node Qb, and the other end is connected to the first potential; one end of the second capacitor C2 is electrically connected to the second node P , The other end is connected to the first potential.
  • the signal control module 700 includes a fifth transistor T5 and a sixth transistor T6.
  • the gate of the fifth transistor T5 is electrically connected to the first node Qb, the source is connected to the first potential, and the drain is electrically connected to the second node P;
  • the gate of the transistor T6 is connected to the N+1th clock signal CK(N+1), the source is connected to the second potential, and the drain is electrically connected to the second node P.
  • the pull-up maintenance module 800 includes an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13.
  • the gate and source of the eleventh transistor T11 are both connected to the second potential, and the drain is electrically connected to the third node K;
  • the gate of the twelfth transistor T12 is electrically connected to the third node K, the source is connected to the second potential, and the drain is electrically connected to the first node Qb;
  • the gate of the thirteenth transistor T13 is electrically connected to the second node P, the source is connected to the first potential, and the drain is electrically connected to the third node K.
  • the working process of the GOA circuit has a reset stage and a normal display stage.
  • the reset signal Reset provides a single second potential pulse signal to control the seventh transistor T7 to turn on to make the second node P the second potential, and the second node P controls the fourth transistor T4, the tenth transistor T10 and the thirteenth transistor T13 is turned on so that the output terminal G(N), the first node Qb, the pull-up node Qa, and the third node K are at the first potential.
  • the normal display stage includes a pre-charge sub-stage t1, an output sub-stage t2, and a pull-down sub-stage t3.
  • the output terminal G(N-1) of the upper-level GOA unit or the output terminal G(N+1) of the lower-level GOA unit provides a second level to enable the first transistor T1 or the second transistor T2 to turn on
  • the first node Qb and the pull-up node Qa are converted to the second potential and the first capacitor C1 is charged, while the third transistor T3 and the fifth transistor T5 are turned on; the fifth transistor T5 is turned on to convert the second node P to the first potential So that the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13 are turned off.
  • the output terminal G(N-1) of the upper-level GOA unit and the output terminal G(N+1) of the lower-level GOA unit provide the first level to turn off the first transistor T1 and the second transistor T2.
  • the transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on to keep the first node Qb at the second potential, and the potential of the pull-up node Qa is converted from the second potential to the bootstrap potential; at the same time, the Nth clock signal CK( N) Provide a second potential and output it as an output terminal G(N) signal through the third transistor T3.
  • the thirteenth transistor T13 is turned off to convert the third node K from the eleventh transistor to the second potential, so that the twelfth transistor T12 is turned on and the first node Qb is charged to make The first node Qb maintains the second potential.
  • the output terminal G(N-1) of the upper-level GOA unit or the output terminal G(N+1) of the lower-level GOA unit provides a second potential to turn on the first transistor T1 or the second transistor T2, and scan forward
  • the signal U2D or the reverse scan signal D2U provides a first potential to the first node Qb and the pull-up node Qa, and the N+1th clock signal CK(N+1) turns on the sixth transistor T6 to switch the second node P
  • the second node P turns on the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13 to make the output terminal G(N), the first node Qb, and the pull-up node Qa and the third node K are converted to the first potential;
  • the third node K turns off the twelfth transistor and causes the twelfth transistor T12 to stop charging the first node Qb.
  • the first capacitor C1 keeps the first node Qb and the pull-up node Qa at the first potential to keep the third transistor T3 off
  • the second capacitor C2 keeps the second node P at the second potential to keep the fourth transistor T4 on
  • the output terminal G(N) maintains the first potential.
  • one of the forward scanning signal U2D and the reverse scanning signal D2U is at a high level and the other signal is at a low level; during forward scanning, the output terminal G(N-1) of the upper-level GOA unit controls the first The transistor T1 is turned on, and the gate of the first transistor T1 of the first-level GOA unit is connected to the start signal STV (not shown in Fig. 5); during reverse scanning, the output terminal G(N+1) of the lower-level GOA unit controls the second The transistor T2 is turned on, and the gate of the second transistor T2 of the final GOA unit is connected to the start signal STV.
  • FIG. 5 is a simulation timing diagram of the GOA circuit of the embodiment of the application.
  • FIG. 5 corresponds to that each transistor in the GOA circuit is an N-type thin film transistor, the first potential is a constant voltage low potential VGL, and the second potential is a constant voltage high The situation of potential VGH.
  • the forward scanning signal U2D When scanning in the forward direction, the forward scanning signal U2D is a constant voltage high potential VGH and the reverse scanning signal D2U is a constant voltage low potential VGL.
  • the forward scanning signal U2D When scanning in a reverse direction, the forward scanning signal U2D is a constant voltage low potential VGL and the reverse scanning signal D2U is Constant voltage and high potential VGH (not shown in FIG. 5), the embodiment of the present application takes forward scanning as an example.
  • the GOA circuit workflow includes a reset phase and a normal display phase, as described in detail below.
  • the reset signal Reset provides a single high-potential pulse signal earlier than other control signals to control the seventh transistor to turn on, so that the second node P is high.
  • the second node P controls the fourth transistor T4, the tenth transistor T10 and The thirteenth transistor T13 is turned on, thereby pre-pulling the output terminal G(N), the first node Qb, the pull-up node Qa and the third node K low, so that the initial potential of the output terminal G(N) is the constant voltage low potential VGL .
  • the reset signal Reset is set low, and the seventh transistor T7 is turned off, waiting for the arrival of the normal display stage.
  • the normal display phase also includes a pre-charge sub-phase t1, an output sub-phase t2, and a pull-down sub-phase t3.
  • the output terminal G(N-1) of the upper-level GOA unit provides a high level to turn on the first transistor T1, so that the first node Qb and the pull-up node Qa are pulled up to a constant voltage.
  • the first capacitor C1 is charged, and the third transistor T3 and the fifth transistor T5 are turned on; the fifth transistor T5 causes the second node P to be pulled down to the constant voltage low potential VHL, so that the fourth transistor T4,
  • the tenth transistor T10 and the thirteenth transistor T13 are turned off.
  • the Nth clock signal CKN is at a high potential
  • the third transistor T3 outputs the Nth clock signal CK(N) as the output terminal G(N) signal.
  • the output terminal G(N-1) of the upper-level GOA unit and the output terminal G(N+1) of the lower-level GOA unit are both low potential
  • the first transistor T1 and the second transistor T2 are both turned off
  • the third transistor T3 Turned on, the first node Qb and the pull-up node Qa have no leakage paths, so they still maintain a high potential.
  • the pull-up node Qa is due to The lifting effect is pulled higher, from the constant voltage high potential VGH to a higher bootstrap potential.
  • the thirteenth transistor T13 is turned off so that the third node K is controlled by the eleventh transistor T11 to switch to the second potential, so that the twelfth transistor T12 is turned on and the first node Qb is turned on. Maintain the second potential.
  • the leakage prevention module 500 includes a twelfth transistor T12.
  • the gate of the twelfth transistor T12 is connected to a constant voltage high potential VGH to keep the twelfth transistor T12 open, and the first node Qb is at a constant voltage high potential At VGH, the twelfth transistor T12 is equivalent to a diode that is turned on in the direction of pulling up the node Qa from the first node Qb to prevent the high potential of the pull-up node Qa from being higher than the high potential of the first node Qb. Backflow to the first node Qb, so as to maintain the high potential of the bootstrap of the pull-up node Qa.
  • the output terminal G(N+1) of the lower-level GOA unit provides a high potential to turn on the first transistor T1 or the second transistor T2, and the reverse scan signal D2U provides a low level to the first node Qb and the pull-up node Qa.
  • the N+1th clock signal CK(N+1) provides a high potential to turn on the sixth transistor T6 so that the second node P is pulled up to the constant voltage high potential VGH.
  • the second capacitor C2 is charged, and the second The node P turns on the fourth transistor T4, the tenth transistor T10, and the thirteenth transistor T13, so that the output terminal G(N), the first node Qb, the pull-up node Qa, and the third node K are pulled down to a constant voltage low Potential VGL.
  • the third node K is pulled low to turn off the twelfth transistor T12 and stop charging the first node Qb.
  • the first capacitor C1 keeps the first node Qb and the pull-up node Qa at a constant voltage low potential VGL to keep the third transistor T3 off
  • the second capacitor C2 keeps the second node P at a constant voltage high potential VGH to make the fourth
  • the transistor T4 remains open, and the output terminal G (N) maintains a constant voltage low potential VGL.
  • the pull-up maintenance module 800 composed of the eleventh transistor T11, the twelfth transistor T12, and the thirteenth transistor T13 is provided between the forward and backward scanning module 100 and the first node Qb. Therefore, in the pre-charge sub-phase t1 and the output sub-phase t2 of the normal display phase, since the first node Qb is at a high potential, the second node P is pulled down to turn off the thirteenth transistor T13, so that the third node K is changed from the tenth node.
  • a transistor T11 is controlled to switch to a high potential, so that the twelfth transistor T12 is turned on and the first node Qb maintains the second potential, and the pull-up node Qa maintains the second potential during the precharge sub-phase t1 and maintains the bootstrap during the output sub-phase t2 Potential.
  • the pull-down sub-phase t3 when the output terminal G(N+1) of the lower-level GOA unit receives the pull-down signal, the second node P is set high to turn on the thirteenth transistor T13, so that the third node K is pulled low. In this way, the third node K turns off the twelfth transistor T12 and stops charging the first node Qb, without affecting the pull-down process.
  • the holding time is 0 seconds and 200 microseconds
  • the original output waveform of the pull-up node Qa in the precharge sub-phase t1 and output sub-phase t2 (the pull-up node Qa in Figure 3 Figure 6 and Figure 7 are obtained by comparing the waveform) with the current output waveform (the waveform of the pull-up node Qa in Figure 5).
  • Figure 6 shows the current GOA circuit with a holding time of 0 microseconds and the GOA circuit in the embodiment of the application.
  • FIG. 7 is a simulation comparison diagram of the pull-up node Qa in the existing GOA circuit and the GOA circuit of the embodiment of the present application when the holding time is 200 microseconds, where the dashed curve is the pull-up node Qa The original output waveform of, the solid curve is the current output waveform of the pull-up node Qa. .
  • the amplitude of the current output waveform of the pull-up node Qa in the pre-charge sub-phase t1 and output sub-phase t2 is higher than the original output waveform.
  • the original output waveform is in the charging process of the pre-charge sub-phase t1
  • the bootstrap voltage of the output sub-phase t2 also shows a voltage drop behavior, and when the holding time is long, the pull-up node Qa has been dropping, the drop amplitude is about 0.5V, and the bootstrap voltage is about 0.5V. The potential is also affected.
  • the GOA circuit further includes an output control module 900.
  • the output control module 900 includes an eighth transistor T8.
  • the gate of the eighth transistor T8 is connected to the global control signal GAS, the source is connected to the first potential, and the drain is electrically connected. Connect the output terminal G(N).
  • the GOA circuit also includes a touch scanning stage after the normal display stage; in the touch scanning stage, the global control signal GAS controls the output terminals G(N) of all stages of GOA units to be converted to the first potential, which is called All gate
  • the off function is to turn off the G(N) signal at the output terminals of all GOA units to suspend the cascade when the touch scan phase comes, so as to prevent interference between the scan drive signal and the touch signal.
  • each transistor in the GOA circuit is an N-type thin film transistor, that is, the eighth transistor T8 is an N-type thin film transistor, and the global control signal GAS is at a low level during the reset phase and the normal display phase.
  • the stage is high potential.
  • each clock signal is a periodic pulse signal
  • each clock signal is a pulse signal synchronized with the frequency of the touch scan signal.
  • the GOA circuit includes a first clock signal CK1 and a second clock signal CK2; when the Nth clock signal CK(N) is the first clock signal CK1, the N+1th clock signal CK (N+1) is CK2; in the reset phase and the normal display phase, the cycles of the first clock signal CK1 and the second clock signal CK2 are the same, and the pulse signal of the previous clock signal ends while the next clock pulse signal is generated.
  • An embodiment of the present application also provides a display panel including the GOA circuit as described above, and the display panel has the same structure and beneficial effects as the GOA circuit provided in the foregoing embodiments. Since the foregoing embodiment has described the structure and beneficial effects of the GOA circuit in detail, it will not be repeated here.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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Abstract

La présente invention concerne un circuit GOA et un panneau d'affichage. L'invention concerne un module de maintien d'excursion haute composé d'un T11, d'un T12 et d'un T13 ; dans un sous-étage de précharge t1 et un sous-étage de sortie t2, du fait qu'un nœud Qb est à un potentiel élevé, un nœud P est soumis à un abaissement pour mettre hors tension le T13 de telle sorte qu'un nœud K soit commandé par le t11 et converti en un potentiel élevé, le T12 est mis sous tension, que le nœud Qb soit maintenu dans le potentiel élevé, et qu'un nœud Qa soit maintenu à un potentiel élevé dans le sous-étage de précharge et soit maintenu dans un potentiel d'amorçage dans le sous-étage de sortie.
PCT/CN2020/086024 2020-04-07 2020-04-22 Circuit goa et panneau d'affichage WO2021203485A1 (fr)

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