WO2021196631A1 - 半导体存储器 - Google Patents

半导体存储器 Download PDF

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Publication number
WO2021196631A1
WO2021196631A1 PCT/CN2020/128959 CN2020128959W WO2021196631A1 WO 2021196631 A1 WO2021196631 A1 WO 2021196631A1 CN 2020128959 W CN2020128959 W CN 2020128959W WO 2021196631 A1 WO2021196631 A1 WO 2021196631A1
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WO
WIPO (PCT)
Prior art keywords
voltage
resistor
operational amplifier
pmos transistor
memory
Prior art date
Application number
PCT/CN2020/128959
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English (en)
French (fr)
Inventor
寗树梁
Original Assignee
长鑫存储技术有限公司
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Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP20920794.3A priority Critical patent/EP3920186A4/en
Priority to US17/396,689 priority patent/US11869573B2/en
Publication of WO2021196631A1 publication Critical patent/WO2021196631A1/zh

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    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1436—Dynamic random-access memory [DRAM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to the field of memory, in particular to a semiconductor memory.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers, and its memory array area is composed of many repeated memory cells. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. After the voltage signal on the word line drive circuit is output to the word line, the transistor can be controlled. Turn on or off, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor through the bit line for storage.
  • DRAM Dynamic Random Access Memory
  • the power consumption of the memory is Larger, low efficiency, and the voltage applied to the word line drive circuit may be less than a predetermined value.
  • the technical problem to be solved by the present invention is how to reduce the power consumption of the memory, improve the efficiency and prevent the voltage applied to the word line drive circuit from being less than a predetermined value.
  • the present invention provides a semiconductor memory including:
  • a memory chip at least includes a storage array
  • a voltage adjustment unit which is used to convert a first voltage input from an external source into a second voltage for use by a word line driving circuit in the memory array, wherein the first voltage is greater than the second voltage.
  • the number of the memory chips is 1 or greater than or equal to 2, and when the number of memory chips is greater than or equal to 2, several memory chips are sequentially stacked upwards or several memory chips are arranged in a plane.
  • the number of the voltage adjustment unit is one, and the one voltage adjustment unit outputs the converted second voltage to the word line drive circuit in the one memory chip or outputs to the word line drive circuit in the one memory chip respectively.
  • the word line drive circuit in the memory chip equal to 2.
  • the number of the voltage adjustment units is greater than or equal to 2, the number of memory chips is greater than or equal to 2, and the number of voltage adjustment units is equal to the number of memory chips, and each voltage adjustment unit will be converted
  • the second voltage is correspondingly output to the word line driving circuit in a corresponding memory chip.
  • the number of the voltage adjustment units is two or more, the number of the memory chips is one or more, the word line drive circuit in the one memory chip is connected to at least two voltage adjustment units, so The at least two voltage adjustment units correspondingly output the converted second voltage to the word line driving circuit in a corresponding memory chip, and the at least two voltage adjustment units are integrated in the corresponding memory chip.
  • the one voltage regulation unit is integrated into the one memory chip.
  • the one voltage regulation unit is integrated in one of the memory chips.
  • the voltage adjustment unit is an independent voltage adjustment chip
  • the semiconductor memory further includes a circuit substrate, the circuit has a connection line, the memory chip and the voltage adjustment chip are located on the substrate, and the voltage adjustment chip It is connected to the memory chip through the connection line, and the second voltage output by the voltage regulation chip is applied to the word line drive circuit of the memory chip through the connection line on the circuit substrate.
  • the memory chip is a DRAM memory chip.
  • the voltage adjustment unit includes an operational amplifier, a first resistor, and a second resistor.
  • One end of the first resistor is connected to a first voltage input from outside, and the other end of the first resistor is connected to one end of the second resistor.
  • the other end of the second resistor is grounded, the electrical connection point between the first resistor and the second resistor is connected to the positive input terminal of the operational amplifier, and the negative input terminal of the operational amplifier is connected to the output of the operational amplifier
  • the terminals are connected to and output the second voltage, and the power supply terminal of the operational amplifier is connected to the first voltage input from the outside.
  • the ratio of the resistance of the first resistor to the resistance of the second resistor is 3/2.9 to 4/2.5.
  • the voltage adjustment unit includes an operational amplifier, a first resistor, a second resistor, and a PMOS transistor.
  • One end of the first resistor is connected to one end of the second resistor, and the other end of the first resistor is connected to the PMOS transistor.
  • the output terminal of the operational amplifier is connected to the gate of the PMOS transistor, the power supply terminal of the operational amplifier is connected to the first voltage input from outside, the source of the PMOS transistor is connected to the first voltage input from outside, and the PMOS transistor The electrical connection point between the drain and the first resistor outputs a second voltage.
  • the voltage adjustment unit further includes a capacitor, one end of the capacitor is connected to the electrical connection point between the drain of the PMOS transistor and the first resistor, and the other end is grounded, and the capacitance value of the capacitor is 5 picofarads ⁇ 30 picofarads, the bias current of the operational amplifier is fixed, and the bias current is 5 microamperes to 50 microamperes.
  • the voltage adjustment unit includes an operational amplifier, a first resistor, a second resistor, and a PMOS transistor.
  • One end of the first resistor is connected to one end of the second resistor, and the other end of the first resistor is connected to the PMOS transistor.
  • the output terminal of the operational amplifier is connected to the gate of the PMOS transistor, the power supply terminal of the operational amplifier is connected to the first voltage input from the outside, the enable terminal of the operational amplifier is connected to the enable signal, and the source of the PMOS transistor
  • the electrode is connected to the first voltage input from the outside, and the electrical connection point between the drain of the PMOS transistor and the first resistor outputs a second voltage.
  • the voltage regulation unit further includes a capacitor, one end of the capacitor is connected to the electrical connection point between the drain of the PMOS transistor and the first resistor, the other end of the capacitor is grounded, and the capacitance value of the capacitor is 5 picofarads to 30 picofarads, the operational amplifier is controlled to work in normal operating mode or sleep mode through the enable signal, the bias current of the operational amplifier is 10-100 microamps in the normal working mode, and the time bias in sleep mode The set current is 0.5 to 3 microamperes.
  • the voltage adjustment unit includes an operational amplifier, a first resistor, a second resistor, a PMOS transistor, and a mirror current source, one end of the first resistor is connected to one end of the second resistor, and the other of the first resistor One end is connected to the drain of the PMOS transistor, the other end of the second resistor is grounded, the positive input end of the operational amplifier is connected to the electrical connection point between the first resistor and the second resistor, and the negative input of the operational amplifier Terminal is connected to the reference voltage, the output terminal of the operational amplifier is connected to the gate of the PMOS transistor, the power supply terminal of the operational amplifier is connected to an externally input first voltage, and the first input terminal of the mirror current source is connected to an externally input second A voltage, the second input terminal of the mirror current source is connected to the output terminal of the operational amplifier, the output terminal of the mirror current source generates an output current to adjust the bias current of the operational amplifier, and the source of the PMOS transistor is connected For the first voltage input from the outside, the electrical connection point between the drain
  • the voltage adjustment unit further includes a capacitor, one end of the capacitor is connected to the electrical connection point between the drain of the PMOS transistor and the first resistor, the other end of the capacitor is grounded, and the capacitance of the capacitor is It is 5 picofarads to 30 picofarads, and the ratio of the output current in the mirror current source to the working current of the PMOS transistor is 1:1000 to 1:100.
  • the voltage adjustment unit includes an operational amplifier, a first resistor, a second resistor, a first PMOS transistor, and a second PMOS transistor, one end of the first resistor is connected to one end of the second resistor, and the first resistor The other end of the resistor is connected to the drain of the first PMOS transistor, the other end of the second resistor is grounded, the positive input end of the operational amplifier is connected to the electrical connection point between the first resistor and the second resistor, the The negative input terminal of the operational amplifier is connected to the reference voltage, the output terminal of the operational amplifier is connected to the gate of the first PMOS transistor, the power supply terminal of the operational amplifier is connected to the first voltage input from outside, and the source of the first PMOS transistor The electrode is connected to the first voltage input from outside, the electrical connection point between the drain of the first PMOS transistor and the first resistor outputs a second voltage, and the source of the second PMOS transistor is connected to the first voltage input from outside, The gate of the second PMOS transistor is connected to the output terminal of the operational amplifier,
  • the voltage adjustment unit further includes a capacitor, one end of the capacitor is connected to the electrical connection point between the drain of the first transistor and the first resistor, the other end of the capacitor is grounded, and the The capacitance value is 5 picofarads to 30 picofarads.
  • the semiconductor memory of the present invention includes: a memory chip including at least a memory array; a voltage adjustment unit for converting a first voltage input externally into a second voltage for the storage
  • the word line driving circuit in the array is used, wherein the first voltage is greater than the second voltage. That is, the voltage supplied to the word line drive circuit (or word line) in the memory chip in this application is a higher first voltage (such as 3V-4V) input from the outside into a second voltage (the second voltage It is equal to the voltage applied to the word line drive circuit when reading and writing.
  • the second voltage can be 2.9V, for example.
  • the external input current during reading and writing of this application can be smaller (at the same power, when the voltage increases, the current will decrease accordingly), so the energy consumed by various metal connections or conductive structures and parasitic resistances will be reduced. Reduce, thereby reducing the power consumption of the memory chip (or semiconductor memory) and improving the efficiency. At the same time, the voltage consumption by the parasitic resistance is also small, so that the voltage actually available on the word line drive circuit reaches a predetermined value.
  • the number of the memory chips is greater than or equal to 2
  • the corresponding number of the voltage adjustment units is greater than or equal to 2
  • the number of the voltage adjustment units is equal to the number of the memory chips, so that the burden of the voltage adjustment unit can be reduced. If it is smaller, it can avoid the voltage loss (IR drop) caused by the excessively long conductive path, so that the accuracy of the adjusted second voltage is higher, and the integration level of the semiconductor memory can be improved.
  • Figures 1-4 are schematic diagrams of the structure of a semiconductor memory in an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a voltage adjustment unit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a word line driving circuit circuit according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a voltage adjustment unit according to another embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a voltage adjustment unit according to another embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a voltage adjusting unit according to another embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a voltage adjusting unit according to another embodiment of the present invention.
  • the memory in order to increase the writing speed of the memory, it is usually necessary to boost the externally input voltage and provide it to the word line drive circuit, so that the power consumption of the memory is relatively high, especially for the multi-layer stacked memory. , The memory consumes more power, and the voltage actually available on the word line drive circuit may be less than a predetermined value.
  • a charge pump circuit is usually used to boost the external input voltage (such as 2.5V) and then provide it to the word line drive circuit (2.9V after the boost), and then provide it to the corresponding word line through the word line drive circuit.
  • the charge pump circuit has low conversion efficiency, high power consumption, and the charge pump circuit occupies a larger chip area.
  • multiple memory chips such as HMC, HBM, etc., will be packaged together. In this case, this multilayer packaging structure will further increase the demand for power consumption and the number of memory chips packaged together.
  • the present invention provides a memory including: a memory chip including at least a memory array; a voltage adjustment unit for converting an externally input first voltage into a second voltage, For use by a word line driving circuit in the memory array, wherein the first voltage is greater than the second voltage. That is, the voltage supplied to the word line drive circuit (or word line) in the memory chip in this application is a higher first voltage (such as 3V-4V) input from the outside into a second voltage (the second voltage) through the voltage adjustment unit. It is equal to the voltage applied to the word line during reading and writing.
  • the second voltage can be 2.9V, for example.) It is output to the word line drive circuit, so it uses the same power as the existing memory when reading and writing.
  • the magnitude of the external input current when reading and writing can be smaller (under the same power, when the voltage increases, the current will decrease accordingly), so various metal connections or conductive structures and parasitic resistance consume The energy is reduced, thereby reducing the power consumption of the memory chip (or semiconductor memory), and the voltage consumption by the parasitic resistance is also smaller, so that the second voltage actually available on the word line driving circuit reaches the predetermined value.
  • an embodiment of the present invention provides a semiconductor memory, including:
  • a memory chip 201 the memory chip 201 at least includes a memory array (not shown in the figure);
  • the voltage adjustment unit 204 is configured to convert the externally input first voltage Vext into a second voltage for use by the word line drive circuit 206 in the memory array, wherein the first voltage Vext Greater than the second voltage.
  • the memory chip 201 is a memory capable of data writing, data reading, and/or data erasing.
  • the memory chip 201 is formed through a semiconductor integrated manufacturing process.
  • the specific memory chip 201 may include a memory array.
  • a peripheral circuit connected to the memory array, the memory array includes a number of memory cells, bit lines connected to the memory cells, word lines, word line drive circuits connected to the word lines, and metal connections (metal contacts), so
  • the storage unit is used for storing data, and the peripheral circuit is a related circuit when the storage array is operated.
  • the memory chip 201 is a DRAM memory chip.
  • the DRAM memory chip includes a number of storage units. Each of the storage units usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line and the The drain of the transistor is connected to the bit line, the source of the transistor is connected to the capacitor, and the word line is connected to the word line driving circuit 206.
  • the memory chip 201 may be other types of memory chips.
  • the number of the memory chip 201 is at least one. Specifically, the number of the memory chip 201 may be one or greater than or equal to two. When the number of the memory chips 201 is greater than or equal to 2, several memory chips are sequentially stacked up or down to form a memory chip stack structure. In this embodiment, referring to FIG. 1, taking the number of the memory chips 201 as an example, the 4 memory chips 201 are sequentially stacked from bottom to top to form a memory chip stack structure, and adjacent memory chips 201 are bonded by bonding Process or bonding process to fit together.
  • a through silicon via interconnect structure (TSV) 203 is formed in the memory chip 201, and the electrical connection points in the memory chip 201 are led out through the through silicon via interconnect structure (TSV) 203.
  • TSV through silicon via interconnect structure
  • the number of the memory chips 201 is greater than or equal to 2
  • several memory chips are arranged in a plane.
  • several memory chips can be arranged in a plane and distributed on a circuit base (such as a PCB substrate) board.
  • a memory chip stack structure when a plurality of memory chips 201 are stacked, two memory chips 201 adjacent to each other are bonded together by an existing bonding process to form a memory chip stack structure, and the bonding process may be a metal bond. Bonding process, direct bonding process or other bonding process. During bonding, an isolation layer 202 is provided between adjacent memory chips 201 for isolation.
  • a circuit substrate (or circuit layer) 301 may be formed on the back of the memory chip stack structure or the back of a single memory chip, between the circuit substrate (or circuit layer) 301 and the back of the memory chip stack structure Isolation is performed by an isolation layer 202.
  • the circuit substrate (or circuit layer) 301 has a rewiring layer (or metal circuit layer) 302, and the rewiring layer (or metal circuit layer) 302 is connected to the TSV interconnection structure ( TSV) 203 connection, the surface of the circuit substrate (or circuit layer) 301 away from the back of the memory chip stack structure has bumps or solder balls 303 connected to the rewiring layer (or metal circuit layer) 302.
  • TSV TSV interconnection structure
  • connection pads 208 on each memory chip 201 are connected to the rewiring layer in the circuit substrate (or circuit layer) 301 through metal leads 209. (Or metal wiring layer) 302 is connected.
  • the metal wire 209 may be formed by a wire bonding process.
  • the semiconductor memory further includes a voltage adjustment unit 204, which is used to convert a first voltage Vext input from the outside into a second voltage and output to the word line driving circuit 206, and then through the word line The driving current 206 is provided to the corresponding word line, and the first voltage Vext is greater than the second voltage.
  • a voltage adjustment unit 204 which is used to convert a first voltage Vext input from the outside into a second voltage and output to the word line driving circuit 206, and then through the word line
  • the driving current 206 is provided to the corresponding word line, and the first voltage Vext is greater than the second voltage.
  • the voltage supplied to the word line drive circuit 206 in the memory chip 201 in this application is a higher first voltage (such as 3V-4V) input from the outside into a second voltage (the second voltage is equal to the current
  • the voltage applied to the word line drive circuit during reading and writing, the second voltage may be, for example, 2.9V) output to the word line drive circuit 206, so under the same power as the existing memory when reading and writing, this application
  • the external input current can be smaller, so the energy consumed by various metal connections or conductive structures and parasitic resistances will be reduced, thereby reducing the power consumption of the memory chip (or semiconductor memory),
  • the voltage consumption by the parasitic resistance is also small, so that the magnitude of the second voltage actually available on the word line drive circuit reaches the predetermined value.
  • the number of the voltage adjustment unit 204 is at least one. Specifically, the number of the voltage adjustment unit 204 may be one or greater than or equal to two.
  • each voltage adjusting unit 204 outputs the converted second voltage to the word line driving circuit 206 in the corresponding memory chip 201 correspondingly.
  • the number of memory chips 201 is 4, and the number of corresponding voltage adjustment units 204 is also 4, that is, each memory chip 201 has one voltage adjustment unit 204 correspondingly, and Each voltage adjustment unit 204 can be integrated and fabricated in the corresponding memory chip 201.
  • the foregoing arrangement makes the burden of the voltage adjustment unit 204 smaller, avoids voltage loss (IR drop) caused by an excessively long conductive path, makes the adjusted second voltage more accurate, and can improve the semiconductor memory The degree of integration.
  • the externally input first voltage Vext can be interconnected through the solder balls 302 on the circuit substrate 301, the rewiring layer 302 in the circuit substrate 301, and the through silicon vias in the memory chip 201.
  • the structure (TSV) 205 is sent to the voltage adjustment unit 204, and the voltage adjustment unit 204 delivers the second voltage to the word line drive circuit 206 through a part of the metal connection formed in the memory chip 201.
  • TSV tunnel voltage
  • the externally input first voltage Vext can specifically pass through the solder balls 302 on the circuit substrate 301, the rewiring layer 302 in the circuit substrate 301, the leads 208, the pads 208, and the The metal wire 215 in the memory chip is sent to the voltage adjustment unit 204.
  • the one voltage adjustment unit 204 when the number of the voltage adjustment unit 204 is one, the one voltage adjustment unit 204 outputs the converted second voltage to the word line driver in the one memory chip 201
  • the circuit may be output to the word line driving circuit in the memory chip 201 of more than or equal to 2 respectively. That is, the one voltage adjusting unit 204 can convert the externally input first voltage Vext into the second voltage and then send it to the word line drive circuit in one memory chip 201 or simultaneously to the word line drive circuit in multiple memory chips 201.
  • the semiconductor memory has four memory chips 201 and one voltage regulation unit 204, and the one voltage regulation unit 204 is integrated in one of the memory chips 201.
  • the one The voltage adjustment unit 204 is integrated in a memory chip 201 at the bottom of the memory stack structure.
  • the one voltage adjustment unit 204 receives a first voltage input from the outside, converts the first voltage into a second voltage, and converts the second voltage to a second voltage. They are respectively output to the corresponding word line drive circuits 206 in the 4 memory chips.
  • the number of the voltage adjustment units is 2 or more, the number of the memory chips is 1 or more, and the word line drive circuit in the one memory chip and at least 2 voltage adjustment units Connection (a specific memory chip can have multiple drive circuits for word lines, and each drive circuit can drive one or several word lines.
  • the word line drive circuit in the present invention can refer to all word lines in the memory chip.
  • the at least two voltage adjustment units output the converted second voltage to the word line drive circuit in a corresponding memory chip, and
  • the at least two voltage regulation units are integrated in the corresponding memory chip.
  • the voltage adjustment unit 204 may be an independent voltage adjustment chip.
  • the voltage adjustment unit (voltage adjustment chip) 204 Located on the circuit substrate 301, the voltage regulating unit 204 is connected to the memory chip 201 through a connection line on the circuit substrate 301.
  • the externally input first voltage Vext is delivered to the voltage regulation unit (voltage regulation chip) 204 through the solder balls 303 and the rewiring layer 302, and the voltage regulation unit (voltage regulation chip) 204 converts the first voltage Vext into the second voltage ,
  • the second voltage is applied to the word line driver in the memory chip through a part of the connection circuit (or metal wiring layer) on the circuit substrate 301 and the connection structure in the memory chip 201 (such as a through silicon via interconnection structure (TSV) 205) On circuit 206.
  • the number of the voltage adjustment unit (voltage adjustment chip) 204 may be one or more (more than or equal to two).
  • the one voltage adjustment unit (voltage adjustment chip) 204 delivers the second voltage to one memory chip 201 or to multiple memory chips 201 at the same time.
  • the number of voltage regulation units (voltage regulation chips) 204 is multiple, the number of corresponding memory chips 201 is also multiple, and each voltage regulation unit (voltage regulation chip) 204 can send a second signal to the corresponding memory chip 201.
  • Voltage, or multiple voltage regulation units (voltage regulation chips) 204 deliver the second voltage to one memory chip.
  • the memory chip is a DRAM memory chip.
  • the externally input first voltage Vext is 3V-4V, and specifically can be 3V, 3.1V, 3.2V, 3.3V, 3.4V, 3.5V, 3.6V, 3.7V, 3.8V, 3.9V, 4V, and the pass voltage
  • the second voltage obtained by the adjusting unit 204 after the voltage is reduced is 2.5V-2.9V, and specifically may be 2.5V, 2.6V, 2.7V, 2.8V, 2.9V.
  • the specific circuit structure of the voltage adjustment unit 204 will be described in detail below.
  • the voltage adjustment unit 204 includes an operational amplifier OPAMP, a first resistor R1, and a second resistor R2.
  • One end of the first resistor R1 is connected to the first voltage Vext input from outside.
  • the other end of the first resistor R1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is grounded, and the electrical connection point between the first resistor R1 and the second resistor R2 is connected to the
  • the positive input terminal of the operational amplifier OPAMP, the negative input terminal of the operational amplifier OPAMP is connected to the output terminal of the operational amplifier OPAMP and outputs the second voltage Vpp, and the power supply terminal of the operational amplifier OPAMP is connected to the externally input first voltage Vext connect.
  • the voltage regulation unit 204 adopts this circuit, which has a simple structure, a small area of a memory chip, high voltage conversion efficiency, and low power consumption.
  • the externally input first voltage Vext is 3V-4V, specifically it may be 3.3V, and the ratio of the resistance value of the first resistor R1 to the resistance value of the second resistor R2 is 3/2.9 To 4/2.5, specifically 3.3/2.9, the second voltage Vpp output from the output terminal of the corresponding operational amplifier OPAMP is 2.9V.
  • FIG. 6 is a schematic structural diagram of a word line driving circuit circuit in an embodiment.
  • the word line driving circuit 206 includes a first A PMOS transistor P1, a first NMOS transistor N1, a second NMOS transistor N2, and a word line.
  • the word line is one of several word lines, denoted by WLxy.
  • the source of the first PMOS transistor P1 and the voltage regulating unit 204 The output terminal of the operational amplifier OPAMP is connected (that is, the second voltage Vpp output from the output terminal of the operational amplifier OPAMP (refer to Figure 5) is applied to the source of the first PMOS transistor P1), the drain of the first PMOS transistor P1 is connected to the first NMOS transistor The drain of N1 is connected, the gate of the first PMOS transistor P1 is connected to the gate of the first NMOS transistor N1 and connected to the row control voltage Rowx, and the source of the first NMOS transistor N1 is connected to the well voltage Vnwl Connected or grounded. The figure shows only the connection with the well voltage Vnwl.
  • the well voltage Vnwl may be set to a negative voltage.
  • the second NMOS transistor N2 The drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 are connected, the gate of the second NMOS transistor N2 is connected to the row control voltage Rowy, and the source of the second NMOS transistor N2 Connected to the well voltage Vnwl, the drain of the first PMOS transistor P1 and the drain of the first NMOS transistor N1 are connected together and connected to the word line WLxy.
  • the second voltage Vpp can be applied to a selected word line WLxy.
  • Transistor connection in a certain memory cell a memory cell usually includes a capacitor and a transistor, the gate of the transistor is connected to the word line, the drain of the transistor is connected to the bit line, and the source of the transistor is connected to the capacitor
  • the second voltage Vpp applied on the word line controls the transistor to turn on, so that the bit line connected to the drain of the transistor can read data from the capacitor or write data to the capacitor.
  • the voltage adjustment unit 204 includes an operational amplifier OPAMP, a first resistor R1, a second resistor R2, a capacitor C, and a PMOS transistor.
  • One end of the first resistor R1 is connected to One end of the second resistor R2 is connected, the other end of the first resistor R1 is connected to the drain of the PMOS transistor P, the other end of the second resistor R2 is grounded, and the positive input end of the operational amplifier OPAMP is connected to the first resistor.
  • the electrical connection point between R1 and the second resistor R2 is connected, the negative input terminal of the operational amplifier OPAMP is connected to the reference voltage Vref, the output terminal of the operational amplifier OPAMP is connected to the gate of the PMOS transistor P, and the operational amplifier OPAMP
  • the power supply terminal is connected to the first voltage Vext input from the outside, the source N of the PMOS transistor is connected to the first voltage Vext input from the outside, and the electrical connection point between the drain of the PMOS transistor P and the first resistor R1 outputs the first voltage Vext.
  • Two voltages Vpp (connected to the word line drive circuit), one end of the capacitor C is connected to the electrical connection point between the drain of the PMOS transistor P and the first resistor R1, and the other end of the capacitor C is grounded.
  • the voltage adjustment unit 204 adopts this circuit to have a simple structure, occupy a small area of a memory chip, and has high voltage conversion efficiency, low power consumption, and low output voltage noise.
  • the ratio of the resistance of the first resistor R1 to the resistance of the second resistor R2 is related to the selected reference voltage Vref.
  • the capacitance value of C is 5 picofarads to 30 picofarads.
  • the bias current of the operational amplifier is fixed. Excessive bias current will cause high power consumption, and small bias current will cause slow response and affect voltage stability.
  • the set current is 5 microampere ⁇ 50 microampere, which can be 5 microampere, 10 microampere, 15 microampere, 20 microampere, 25 microampere, 30 microampere, 35 microampere, 40 microampere, 45 microampere, and 50 microampere. microampere.
  • the voltage adjusting unit of the voltage adjusting unit 204 includes an operational amplifier OPAMP, a first resistor R1, a second resistor R2, a capacitor C, and a PMOS transistor P.
  • One end of a resistor R1 is connected to one end of a second resistor R2, the other end of the first resistor R1 is connected to the drain of the PMOS transistor P, the other end of the second resistor R2 is grounded, and the positive of the operational amplifier OPAMP
  • the input terminal is connected to the electrical connection point between the first resistor R1 and the second resistor R2, the negative input terminal of the operational amplifier OPAMP is connected to the reference voltage, the output terminal of the operational amplifier OPAMP is connected to the gate of the PMOS transistor P, so
  • the power supply terminal of the operational amplifier OPAMP is connected to the externally input first voltage Vext, the enable terminal of the operational amplifier OPAMP is connected to the enable signal En, and the source of the PMOS transistor P is connected to the externally input first voltage Vext, so
  • the voltage adjustment unit 204 adopts this circuit, which has a simple structure and occupies a smaller area of the memory chip, has high voltage conversion efficiency, low power consumption, and has an enable signal, which can be adjusted according to the working mode of the memory. Bias current, which can reduce the overall power consumption.
  • the value of the capacitance C of the capacitor C is 5 picofarads to 30 picofarads
  • the operational amplifier OPAMP is controlled to work in the normal operating mode or the sleep mode through the enable signal, and the operational amplifier OPAMP is normal
  • the bias current is 10-100 microamps in the working mode to ensure the voltage stability requirements of the memory during normal reading.
  • the bias current is 0.5 to 3 microamps in the sleep mode, which greatly reduces the power consumption of the sleep mode.
  • the voltage adjustment unit 204 includes an operational amplifier OPAMP, a first resistor R1, a second resistor R2, a capacitor C, a PMOS transistor P, and a mirror current source Ie.
  • One end of the resistor R1 is connected to one end of the second resistor R2, the other end of the first resistor R1 is connected to the drain of the PMOS transistor P, the other end of the second resistor R2 is grounded, and the positive input of the operational amplifier OPAMP
  • the terminal is connected to the electrical connection point between the first resistor R1 and the second resistor R2, the negative input terminal of the operational amplifier OPAMP is connected to the reference voltage Vref, and the output terminal of the operational amplifier OPAMP is connected to the gate of the PMOS transistor P, so
  • the power supply terminal of the operational amplifier OPAMP is connected to the externally input first voltage Vext, the negative voltage input terminal of the operational amplifier OPAMP is grounded, and the first input terminal of the mirror current source Ie is connected to the externally input first voltage Vext
  • the output terminal of the mirror current source Ie generates an output current to adjust the bias current of the operational amplifier OPAMP.
  • PMOS transistor P the PMOS transistor P
  • the source of the PMOS transistor P is connected to the first voltage Vext input from the outside, the electrical connection point between the drain of the PMOS transistor P and the first resistor R1 outputs a second voltage Vpp (connected to the word line drive circuit), and one end of the capacitor C
  • Vpp connected to the word line drive circuit
  • the voltage adjustment unit 204 adopts this circuit, which has a simple structure and occupies a smaller area of the memory chip, and has high voltage conversion efficiency, low power consumption, and low output voltage noise.
  • the bias current can be adjusted in real time according to the size of the output current to further improve voltage stability and reduce power consumption.
  • the capacitance value of the capacitor C is 5 picofarads to 30 picofarads
  • the ratio of the output current of the mirror current source Ie to the operating current of the PMOS transistor is 1:1000 to 1:100, and the ratio Too small can reduce power consumption but also reduces voltage stability, and too large a ratio will improve voltage stability but also increase circuit power consumption.
  • the voltage adjustment unit 204 includes an operational amplifier OPAMP, a first resistor R1, a second resistor R2, a capacitor C, a first PMOS transistor P1 and a second PMOS transistor P2.
  • One end of the first resistor R1 is connected to one end of the second resistor R2, the other end of the first resistor R1 is connected to the drain of the first PMOS transistor P1, and the other end of the second resistor R2 is grounded.
  • the positive input terminal of the operational amplifier OPAMP is connected to the electrical connection point between the first resistor R1 and the second resistor R2, the negative input terminal of the operational amplifier OPAMP is connected to the reference voltage, and the output terminal of the operational amplifier OPAMP is connected to the first PMOS
  • the gate of the transistor P1 the power supply terminal of the operational amplifier OPAMP is connected to the first voltage Vext input from outside, the source of the first PMOS transistor P1 is connected to the first voltage Vext input from outside, and the first PMOS transistor P1
  • the electrical connection point between the drain of the first transistor and the first resistor R1 outputs a second voltage Vpp (connected to the word line drive circuit), and one end of the capacitor C is connected between the drain of the first transistor and the first resistor R1
  • the other end of the capacitor C is grounded, the source of the second PMOS transistor P2 is connected to the first voltage Vext input from outside, and the gate of the second PMOS transistor P2 is connected to the op amp OPAMP
  • the output end is connected,
  • the voltage regulation unit 204 adopts this circuit, which has a simple structure and occupies a small area of the memory chip, and has high voltage conversion efficiency and low power consumption. At the same time, PMOS transistors are used as the mirror current source, and the structure is simple and economical. Occupy area.
  • the capacitance C value of the capacitor C is 5 picofarads to 30 picofarads.

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Abstract

一种半导体存储器，包括：存储器芯片，所述存储器芯片中至少包括存储阵列；电压调节单元，所述电压调节单元用于将外部输入的第一电压转换为第二电压，以供所述存储阵列中的字线驱动电路使用，其中所述第一电压大于第二电压。本发明的半导体存储器减小了存储器芯片(或者半导体存储器)的功耗，同时电压被寄生电阻的消耗也较小，使得字线驱动电路上施加的第二电压大小达到预定值。

Description

半导体存储器
相关申请引用说明
本申请要求于2020年03月31日递交的中国专利申请号202010243119.7，申请名为“半导体存储器”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及存储器领域，尤其涉及一种半导体存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，其存储阵列区由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线驱动电路上的电压信号输出到字线上后能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
现有为了提高对存储器的写入速度，通常需要对外部输入的电压进行升压提供给字线驱动电路，使得存储器的功耗较大，特别是对于多层堆叠的存储器，存储器消耗的功耗更大、效率不高，并且字线驱动电路上施加的电压可能会小于预定值。
发明内容
本发明所要解决的技术问题是怎样减小存储器的功耗、提高效率以及避免字线驱动电路上施加的电压可能会小于预定值。
为此，本发明提供了一种半导体存储器，包括：
存储器芯片，所述存储器芯片中至少包括存储阵列；
电压调节单元，所述电压调节单元用于将外部输入的第一电压转换为第二电压，以供所述存储阵列中的字线驱动电路使用，其中所述第一电压大于第二电压。
可选的，所述存储器芯片的数量为1个或者大于等于2个，所述存储器芯片的数量大于等于2个时，若干存储器芯片依次向上堆叠或者若干存储器芯片呈平面排布。
可选的，所述电压调节单元的数量为1个，所述1个电压调节单元将转换 后的第二电压输出给所述1个存储器芯片中的字线驱动电路或者分别输出给所述大于等于2个的存储器芯片中的字线驱动电路。
可选的，所述电压调节单元的数量为大于等于2个，所述存储器芯片的数量大于等于2个，且所述电压调节单元的数量等于存储器芯片的数量，每一个电压调节单元将转换后的第二电压对应输出给相应的一个存储器芯片中的字线驱动电路。
可选的，所述电压调节单元数量为大于等于2个，所述存储器芯片的数量为大于等于1个，所述1个存储器芯片中的字线驱动电路与至少2个电压调节单元连接，所述至少2个电压调节单元将转换后的第二电压对应输出给相应的一个存储器芯片中的字线驱动电路，且所述至少两个电压调节单元集成在对应的存储器芯片中。
可选的，所述存储器芯片的数量为1个时，且所述电压调节单元的数量为1个时，所述1个电压调节单元集成在所述1个存储器芯片中。
可选的，所述存储器芯片的数量大于等于2个时，且所述电压调节单元的数量为1个时，所述1个电压调节单元集成在所述其中一个存储器芯片中。
可选的，所述电压调节单元为独立的电压调节芯片，所述半导体存储器还包括线路基板，所述线路上具有连接线路，所述存储器芯片和电压调节芯片位于基板上，所述电压调节芯片通过连接线路与存储器芯片连接，电压调节芯片输出的第二电压通过线路基板上的连接线路施加到存储器芯片的字线驱动电路。
可选的，所述存储器芯片为DRAM存储器芯片。
如权利要求9所述的半导体存储器，其特征在于，所述第一电压为3V-4V，所述第二电压为2.5-2.9V。
可选的，所述电压调节单元包括运算放大器、第一电阻和第二电阻，所述第一电阻的一端连接外部输入的第一电压，所述第一电阻的另一端与第二电阻的一端连接，所述第二电阻的另一端接地，所述第一电阻与第二电阻之间的电连接点连接所述运算放大器的正输入端，所述运算放大器的负输入端与运算放大器的输出端相连接并输出第二电压，所述运算放大器的电源供应端连接外部输入的第一电压。
可选的，所述第一电阻的阻值与第二电阻的阻值之比为3/2.9到4/2.5。
可选的，所述电压调节单元包括运算放大器、第一电阻、第二电阻和PMOS晶体管，所述第一电阻的一端与第二电阻的一端连接，所述第一电阻的另一端与PMOS晶体管的漏极连接，所述第二电阻的另一端接地，所述运算放大器的正输入端与第一电阻和第二电阻之间的电连接点连接，所述运算放大器的负输入端连接参考电压，所述运算放大器的输出端连接PMOS晶体管的栅极，所述运算放大器的电源供应端连接外部输入的第一电压，所述PMOS晶体管的源极连接外部输入的第一电压，所述PMOS晶体管的漏极与第一电阻之间的电连接点输出第二电压。
可选的，所述电压调节单元还包括电容，所述电容一端连接所述PMOS晶体管的漏极与第一电阻之间的电连接点，另一端接地，所述电容的电容值为5皮法～30皮法，所述运算放大器的偏置电流固定，所述偏置电流为5微安～50微安。
可选的，所述电压调节单元包括运算放大器、第一电阻、第二电阻和PMOS晶体管，所述第一电阻的一端与第二电阻的一端连接，所述第一电阻的另一端与PMOS晶体管的漏极连接，所述第二电阻的另一端接地，所述运算放大器的正输入端与第一电阻和第二电阻之间的电连接点连接，所述运算放大器的负输入端连接参考电压，所述运算放大器的输出端连接PMOS晶体管的栅极，所述运算放大器的电源供应端连接外部输入的第一电压，所述运算放大器的使能端连接使能信号，所述PMOS晶体管的源极连接外部输入的第一电压，所述PMOS晶体管的漏极与第一电阻之间的电连接点输出第二电压。
可选的，所述电压调节单元还包括电容，述电容一端连接所述PMOS晶体管的漏极与第一电阻之间的电连接点，所述电容的另一端接地，所述电容的电容值为5皮法～30皮法，通过所述使能信号控制所述运算放大器工作在正常工作模式或睡眠模式，所述运算放大器正常工作模式时偏置电流为10～100微安，睡眠模式时偏置电流为0.5～3微安。
可选的，所述电压调节单元包括运算放大器、第一电阻、第二电阻、PMOS晶体管和镜像电流源，所述第一电阻的一端与第二电阻的一端连接，所述第一电阻的另一端与PMOS晶体管的漏极连接，所述第二电阻的另一端接地，所述 运算放大器的正输入端与第一电阻和第二电阻之间的电连接点连接，所述运算放大器的负输入端连接参考电压，所述运算放大器的输出端连接PMOS晶体管的栅极，所述运算放大器的电源供应端连接外部输入的第一电压，所述镜像电流源的第一输入端连接外部输入的第一电压，所述镜像电流源的第二输入端连接所述运算放大器的输出端，所述镜像电流源的输出端产生输出电流以调整运算放大器的偏置电流，所述PMOS晶体管的源极连接外部输入的第一电压，所述PMOS晶体管的漏极与第一电阻之间的电连接点输出第二电压。
可选的，所述电压调节单元还包括电容，所述电容一端连接所述PMOS晶体管的漏极与第一电阻之间的电连接点，所述电容的另一端接地，所述电容的电容值为5皮法～30皮法，所述镜像电流源中输出电流与所述PMOS晶体管的工作电流比例为1:1000～1:100。
可选的，所述电压调节单元包括运算放大器、第一电阻、第二电阻、第一PMOS晶体管和第二PMOS晶体管，所述第一电阻的一端与第二电阻的一端连接，所述第一电阻的另一端与第一PMOS晶体管的漏极连接，所述第二电阻的另一端接地，所述运算放大器的正输入端与第一电阻和第二电阻之间的电连接点连接，所述运算放大器的负输入端连接参考电压，所述运算放大器的输出端连接第一PMOS晶体管的栅极，所述运算放大器的电源供应端连接外部输入的第一电压，所述第一PMOS晶体管的源极连接外部输入的第一电压，所述第一PMOS晶体管的漏极与第一电阻之间的电连接点输出第二电压，所述第二PMOS晶体管的源极连接外部输入的第一电压，所述第二PMOS晶体管的栅极与所述运算放大器的输出端连接，所述第二PMOS晶体管的漏极与运算放大器的偏置电流调节端连接以调整运算放大器的偏置电流。
可选的，所述电压调节单元还包括电容，所述电容的一端连接所述第一晶体管的漏极与第一电阻之间的电连接点，所述电容的另一端接地，所述电容的电容值为5皮法～30皮法。
与现有技术相比，本发明技术方案具有以下优点：
本发明的半导体存储器，包括：存储器芯片，所述存储器芯片中至少包括存储阵列；电压调节单元，所述电压调节单元用于将外部输入的第一电压转换为第二电压，以供所述存储阵列中的字线驱动电路使用，其中所述第一电压大 于第二电压。即本申请中供给存储器芯片中字线驱动电路(或者字线上)的电压是通过电压调节单元将外部输入的较高第一电压(比如3V-4V)转换为第二电压(所述第二电压等于现有进行读写时字线驱动电路上施加的电压，第二电压比如可以为2.9V)输出给字线驱动电路的，因而在与现有的存储器在进行读写时采用同样的功率的情况下，本申请在进行读写时外部输入的电流可以更小(同样功率下，电压增大时，电流相应会减小)，因而各种金属连线或者导电结构以及寄生电阻消耗的能量会减小，从而减小了存储器芯片(或者半导体存储器)的功耗、提高了效率，同时电压被寄生电阻的消耗也较小，使得字线驱动电路上实际可获得的电压大小达到预定值。
进一步，当所述存储器芯片的数量大于等于2个，相应的所述电压调节单元的数量为大于等于2个，且所述电压调节单元的数量与存储器芯片的数量，使得电压调节单元的负担可以较小，可避免由于过长的导电路径带来的电压损失(IR drop)，使得调节后的第二电压的精度较高，并能提高半导体存储器的集成度。
附图说明
图1-4为本发明实施例中半导体存储器的结构示意图；
图5为本发明一实施例电压调节单元的示意图；
图6为本发明一实施例字线驱动电路电路的示意图；
图7为本发明另一实施例电压调节单元的示意图；
图8为本发明又一实施例电压调节单元的示意图；
图9为本发明又一实施例电压调节单元的示意图；
图10为本发明又一实施例电压调节单元的示意图。
具体实施方式
如背景技术所言，现有为了提高对存储器的写入速度，通常需要对外部输入的电压进行升压提供给字线驱动电路，使得存储器的功耗较大，特别是对于多层堆叠的存储器，存储器消耗的功耗更大，并且字线驱动电路上实际可获得的电压可能会小于预定值。
研究发现，现有通常采用电荷泵电路对外部输入的电压(比如2.5V)进行升压后(升压后为2.9V)提供给字线驱动电路，通过字线驱动电路提供给相应 的字线，电荷泵电路转换效率较低，功耗较大，并且电荷泵电路会占据较大的芯片面积。此外，为了提高存储容量，会将多存储芯片封装到一起，例如HMC、HBM等，而这种情况下，这种多层封装结构会导致需求功耗进一步增加，并且封装在一起的存储芯片数量或者层数越多，相应的功耗也会越大，并且由于外部输入的电压一般是恒定的(2.5V)，堆叠的层数增多，相应的供给电流需要增大，存储器中各金属连接线的电阻一定，电流增大使得功耗会增大，加上寄生电容的影响，使得字线驱动电路实际可获得的电压可能会小于预定值，同时大量功耗消耗在寄生电阻上会极大降低效率。
为此，本发明提供了一种存储器，包括：存储器芯片，所述存储器芯片中至少包括存储阵列；电压调节单元，所述电压调节单元用于将外部输入的第一电压转换为第二电压，以供所述存储阵列中的字线驱动电路使用，其中所述第一电压大于第二电压。即本申请中供给存储器芯片中字线驱动电路(或者字线上)的电压是通过电压调节单元将外部输入的较高第一电压(比如3V-4V)转换为第二电压(所述第二电压等于现有进行读写时施加到字线上的电压，第二电压比如可以为2.9V)输出给字线驱动电路的，因而在与现有的存储器在进行读写时采用同样的功率的情况下，本申请的在进行读写时外部输入的电流的大小可以更小(同样功率下，电压增大时，电流相应会减小)，因而各种金属连线或者导电结构以及寄生电阻消耗的能量会减小，从而减小了存储器芯片(或者半导体存储器)的功耗，同时电压被寄生电阻的消耗也较小，使得字线驱动电路上实际可获得的第二电压大小达到预定值。
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在详述本发明实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
参考图1，本发明实施例提供了一种半导体存储器，包括：
存储器芯片201，所述存储器芯片201中至少包括存储阵列(图中未示出)；
电压调节单元204，所述电压调节单元204用于将外部输入的第一电压Vext转换为第二电压，以供所述存储阵列中的字线驱动电路206使用，其中， 所述第一电压Vext大于第二电压。
具体的，所述存储器芯片201为能进行数据写入、数据读取和/或数据擦除的存储器，所述存储器芯片201通过半导体集成制作工艺形成，具体的所述存储器芯片201可以包括存储阵列和与存储阵列连接的外围电路，所述存储阵列包括若干存储单元、与存储单元连接的位线、字线、与字线连接的字线驱动电路、以及金属连线(金属接触部)，所述存储单元用于存储数据，所述外围电路为在对存储阵列进行操作时的相关电路。本实施例中，所述存储器芯片201为DRAM存储器芯片，所述DRAM存储器芯片中包括若干存储单元，每一个所述存储单元通常包括电容器和晶体管，所述晶体管的栅极与字线相连、所述晶体管的漏极与位线相连、所述晶体管的源极与电容器相连，所述字线与字线驱动电路206连接。在其他实施例中所述存储器芯片201可以为其他类型的存储器芯片。
所述存储器芯片201的数量至少为一个，具体的，所述存储器芯片201的数量可以为1个或者大于等于2个。当所述存储器芯片201的数量大于等于2个时，若干存储器芯片依次向上或向下堆叠形成存储器芯片堆叠结构。本实施例中，请参考图1，以所述存储器芯片201的数量为4个作为示例，所述4个存储器芯片201从下向上依次堆叠形成存储器芯片堆叠结构，相邻存储器芯片201通过键合工艺或者粘合工艺贴合在一起。在一实施例中，所述存储器芯片201中形成有硅通孔互连结构(TSV)203，通过硅通孔互连结构(TSV)203将存储器芯片201中的电连接点引出。当存在多个存储器芯片201堆叠时，每一个存储器芯片201可以通过不同的硅通孔互连结构(TSV)203将电连接点引出。
在其他实施例中，当所述存储器芯片201的数量大于等于2个时，若干存储器芯片呈平面排布。具体的若干存储器芯片可以呈平面排布的分布在一个线路基(比如PCB基板)板上。
在一实施例中，当多个存储器芯片201堆叠时，上下相邻的两个存储器芯片201通过现有的键合工艺键合在一起形成存储器芯片堆叠结构，所述键合工艺可以为金属键合工艺、直接键合工艺或其他键合工艺。在进行键合时，相邻存储器芯片201之间具有隔离层202进行隔离。
在一实施例中，在所述存储器芯片堆叠结构背面或者单个存储器芯片的背面可以形成线路基板(或者线路层)301，所述线路基板(或者线路层)301与存储器芯片堆叠结构的背面之间通过隔离层202进行隔离，所述线路基板(或者线路层)301中具有再布线层(或者金属线路层)302，所述再布线层(或者金属线路层)302与硅通孔互连结构(TSV)203连接，所述线路基板(或者线路层)301远离存储器芯片堆叠结构背面的表面具有与再布线层(或者金属线路层)302连接的凸起或者焊球303。在其他实施例中，请参考图2，当存在多个存储器芯片201堆叠时，每一个存储器芯片201上的连接焊盘208通过金属引线209与线路基板(或者线路层)301中的再布线层(或者金属线路层)302连接。具体的，所述金属引线209可以通过引线键合工艺形成。
继续参考图1，所述半导体存储器中还包括电压调节单元204，所述电压调节单元204用于将外部输入的第一电压Vext转换为第二电压输出给字线驱动电路206，进而通过字线驱动电流206提供给对应的字线，所述第一电压Vext大于第二电压。即本申请中供给存储器芯片201中字线驱动电路206的电压是通过电压调节单元将外部输入的较高第一电压(比如3V-4V)转换为第二电压(所述第二电压等于现有进行读写时字线驱动电路上施加的电压，第二电压比如可以为2.9V)输出给字线驱动电路206，因而在与现有的存储器在进行读写时同样的功率的情况下，本申请的在进行读写时外部输入的电流的大小可以更小，因而各种金属连线或者导电结构以及寄生电阻消耗的能量会减小，从而减小了存储器芯片(或者半导体存储器)的功耗，同时电压被寄生电阻的消耗也较小，使得字线驱动电路上实际可获得的第二电压大小达到预定值。
所述电压调节单元204的数量至少为一个，具体的，所述电压调节单元204的数量可以为1个或者大于等于2个。
在一实施例中，当所述存储器芯片201的数量大于等于2个，相应的所述电压调节单元204的数量为大于等于2个，且所述电压调节单元204的数量与存储器芯片201的数量相等，每一个电压调节单元204将转换后的第二电压对应输出给相应的存储器芯片201中字线驱动电路206。具体的，请参考图1或者图2，所述存储器芯片201的数量为4个，相应的电压调节单元204的数量也为4个，即每一个存储器芯片201对应具有一个电压调节单元204，并且每 一个电压调节单元204可以集成制作在相应的存储器芯片201中。前述设置方式，使得电压调节单元204的负担可以较小，可避免由于过长的导电路径带来的电压损失(IR drop)，使得调节后的第二电压的精度较高，并能提高半导体存储器的集成度。
在一实施例中，请参考图1，所述外部输入的第一电压Vext具体可以通过线路基板301上焊球302和线路基板301中的再布线层302以及存储器芯片201中硅通孔互连结构(TSV)205输送给电压调节单元204，所述电压调节单元204通过存储器芯片201中形成的部分金属连线将第二电压输送给字线驱动电路206。在另一实施例中，请参考图2，所述外部输入的第一电压Vext具体可以通过线路基板301上焊球302、线路基板301中的再布线层302、引线208、焊盘208以及位于存储芯片中的金属连线215输送给电压调节单元204。
在另一实施例中，当所述电压调节单元204的数量为1个时，所述1个电压调节单元204将转换后的第二电压输出给所述1个存储器芯片201中的字线驱动电路或者分别输出给所述大于等于2个的存储器芯片201中的字线驱动电路。即所述1个电压调节单元204可以将外部输入的第一电压Vext转换为第二电压后输送给1个存储器芯片201中字线驱动电路或者同时输送给多个存储器芯片201中的字线驱动电路。具体的，请参考图3，所述半导体存储器中有4个存储器芯片201和一个电压调节单元204，所述1个电压调节单元204集成在其中一个存储器芯片201，较优的，所述1个电压调节单元204集成在存储器堆叠结构最底层的一个存储器芯片201中，所述1个电压调节单元204在接收外部输入的第一电压，将第一电压转换为第二电压，并将第二电压分别输出给4个存储器芯片中对应的字线驱动电路206上。
在又一实施例中，所述电压调节单元数量为大于等于2个，所述存储器芯片的数量为大于等于1个，所述1个存储器芯片中的字线驱动电路与至少2个电压调节单元连接(具体的一个存储器芯片中可以具有多个针对字线的驱动电路，每一个驱动电路可以驱动一个或若干字线，本发明所述的字线驱动电路可以指存储器芯片中针对所有字线的驱动电路的集合，或者仅指针对其中一个字线的驱动电路)，所述至少2个电压调节单元将转换后的第二电压对应输出给相应的一个存储器芯片中的字线驱动电路，且所述至少2个电压调节单元集成 在相应的存储器芯片中。
除了将电压调节单元集成在相应的存储器芯片中，在其他实施例中，所述电压调节单元204可以为独立的电压调节芯片，具体请参考图4，所述电压调节单元(电压调节芯片)204位于线路基板301上，所述电压调节单元204通过线路基板301上的连接线路与存储器芯片201连接。具体的，外部输入的第一电压Vext通过焊球303和再布线层302输送给电压调节单元(电压调节芯片)204，电压调节单元(电压调节芯片)204将第一电压Vext转换为第二电压，所述第二电压通过线路基板301上部分连接线路(或者金属布线层)以及存储器芯片201中的连接结构(比如硅通孔互连结构(TSV)205)施加到存储器芯片中的字线驱动电路206上。所述电压调节单元(电压调节芯片)204数量可以为1个或者多个(大于等于2个)。当电压调节单元(电压调节芯片)204数量为1个时，所述1个电压调节单元(电压调节芯片)204向1个存储器芯片201或者同时向多个存储器芯片201输送第二电压。当电压调节单元(电压调节芯片)204数量为多个时，相应的所述存储器芯片201的数量也为多个，每一个电压调节单元(电压调节芯片)204可以向对应存储器芯片201输送第二电压，或者多个电压调节单元(电压调节芯片)204向一个存储器芯片输送第二电压。
本实施例中，所述存储器芯片为DRAM存储器芯片。所述外部输入的第一电压Vext为3V-4V，具体可以为3V、3.1V、3.2V、3.3V、3.4V、3.5V、3.6V、3.7V、3.8V、3.9V、4V，通过电压调节单元204降压后得到的所述第二电压为2.5V-2.9V，具体可以为2.5V、2.6V、2.7V、2.8V、2.9V。下面将对电压调节单元204的具体的电路结构进行详细的说明。
在一具体的实施例中，请参考图5，所述电压调节单元204包括运算放大器OPAMP、第一电阻R1和第二电阻R2，所述第一电阻R1的一端连接外部输入的第一电压Vext，所述第一电阻R1的另一端与第二电阻R2的一端连接，所述第二电阻R2的另一端接地，所述第一电阻R1与第二电阻R2之间的电连接点连接所述运算放大器OPAMP的正输入端，所述运算放大器OPAMP的负输入端与运算放大器OPAMP的输出端相连接并输出第二电压Vpp，所述运算放大器OPAMP的电源供应端与外部输入的第一电压Vext连接。所述电压调节 单元204采用该电路相比于现有的电荷泵电路结构简单、占据存储器芯片的面积小，并且电压转化效率高，功耗低。
在一实施例中，所述外部输入的第一电压Vext为3V-4V时，具体可以为3.3V，所述第一电阻R1的阻值与第二电阻R2的阻值之比为3/2.9到4/2.5，具体可以为3.3/2.9，相应的运算放大器OPAMP输出端输出的第二电压Vpp为2.9V。
所述电压调节单元204输出的第二电压Vpp提供给字线驱动电路，参考图6，图6为一实施例中一种字线驱动电路线路的结构示意图，所述字线驱动电路206包括第一PMOS晶体管P1、第一NMOS晶体管N1、第二NMOS晶体管N2以及字线，所述字线为若干字线的一条，用WLxy表示，所述第一PMOS晶体管P1的源极与电压调节单元204的运算放大器OPAMP输出端连接(即运算放大器OPAMP输出端输出的第二电压Vpp(参考图5)施加在第一PMOS晶体管P1的源极)，第一PMOS晶体管P1的漏极与第一NMOS晶体管N1的漏极连接，所述第一PMOS晶体管P1的栅极与第一NMOS晶体管N1的栅极连接在一起并与行控制电压Rowx连接，所述第一NMOS晶体管N1的源极与阱电压Vnwl连接或接地，附图中展示的仅是与阱电压Vnwl连接的情形，为了在不打开时能够让存储单元的晶体管完全关闭，阱电压Vnwl可能会设置成负电压，所述第二NMOS晶体管N2的漏极与第一PMOS晶体管P1的漏极以及第一NMOS晶体管N1的漏极连接，所述第二NMOS晶体管N2的栅极与行控制电压Rowy连接，所述第二NMOS晶体管N2的源极与阱电压Vnwl连接，所述第一PMOS晶体管P1的漏极以及第一NMOS晶体管N1的漏极连接在一起与字线WLxy连接。通过第一PMOS晶体管P1、第一NMOS晶体管N1、第二NMOS晶体管N2的打开或关闭，可以将第二电压Vpp施加在某一根选中的字线WLxy上，该字线WLxy由于与DRAM存储器的某一个存储单元中的晶体管连接(一个存储单元通常包括电容器和晶体管，所述晶体管的栅极与字线相连、所述晶体管的漏极与位线相连、所述晶体管的源极与电容器相连)，字线上施加的第二电压Vpp控制所述晶体管打开，使得与晶体管漏极连接的位线可以从电容器中读取数据或者向电容器中写入数据。
在另一具体的实施例中，请参考图7，所述电压调节单元204包括运算放 大器OPAMP、第一电阻R1、第二电阻R2、电容C和PMOS晶体管，所述第一电阻R1的一端与第二电阻R2的一端连接，所述第一电阻R1的另一端与PMOS晶体管P的漏极连接，所述第二电阻R2的另一端接地，所述运算放大器OPAMP的正输入端与第一电阻R1和第二电阻R2之间的电连接点连接，所述运算放大器OPAMP的负输入端连接参考电压Vref，所述运算放大器OPAMP的输出端连接PMOS晶体管P的栅极，所述运算放大器OPAMP的电源供应端连接外部输入的第一电压Vext，所述PMOS晶体管的源极N连接外部输入的第一电压Vext，所述PMOS晶体管P的漏极与第一电阻R1之间的电连接点输出第二电压Vpp(与字线驱动电路连接)，所述电容C一端连接所述PMOS晶体管P的漏极与第一电阻R1之间的电连接点，所述电容C的另一端接地。所述电压调节单元204采用该电路相比于现有的电荷泵电路结构简单、占据存储器芯片的面积小，并且电压转化效率高，功耗低，输出电压噪声小。
在一实施例中，所述第一电阻R1的阻值与第二电阻R2的阻值之比与所选用的参考电压Vref相关，本领域内普通技术人员可以根据需求自行设计调整，所述电容C的电容值为5皮法～30皮法，所述运算放大器的偏置电流固定，偏置电流过大会导致功耗大，偏置电流小会导致响应慢从而影响电压稳定性，所述偏置电流为5微安～50微安，可以为5微安、10微安、15微安、20微安、25微安、30微安、35微安、40微安、45微安、50微安。
在另一具体的实施例中，请参考图8，所述电压调节单元204所述电压调节单元包括运算放大器OPAMP、第一电阻R1、第二电阻R2、电容C和PMOS晶体管P，所述第一电阻R1的一端与第二电阻R2的一端连接，所述第一电阻R1的另一端与PMOS晶体管P的漏极连接，所述第二电阻R2的另一端接地，所述运算放大器OPAMP的正输入端与第一电阻R1和第二电阻R2之间的电连接点连接，所述运算放大器OPAMP的负输入端连接参考电压，所述运算放大器OPAMP的输出端连接PMOS晶体管P的栅极，所述运算放大器OPAMP的电源供应端连接外部输入的第一电压Vext，所述运算放大器OPAMP的使能端连接使能信号En，所述PMOS晶体管P的源极连接外部输入的第一电压Vext，所述PMOS晶体管P的漏极与第一电阻R1之间的电连接点输出第二电压Vpp(与字线驱动电路连接)，所述电容C一端连接所述PMOS晶体管P的漏极与 第一电阻R1之间的电连接点，所述电容C的另一端接地。所述电压调节单元204采用该电路相比于现有的电荷泵电路结构简单占据存储器芯片的面积小，并且电压转化效率高，功耗低，同时具备使能信号，可以根据存储器的工作模式调整偏置电流，从而可以降低综合功耗。
在一实施例中，所述电容C的电容C值为5皮法～30皮法，通过所述使能信号控制所述运算放大器OPAMP工作在正常工作模式或睡眠模式，所述运算放大器OPAMP正常工作模式时偏置电流为10～100微安，保证存储器正常读取时对电压稳定性的需求，睡眠模式时偏置电流为0.5～3微安，大幅减小睡眠模式的功耗。
在另一具体的实施例中，参考图9，所述电压调节单元204包括运算放大器OPAMP、第一电阻R1、第二电阻R2、电容C、PMOS晶体管P和镜像电流源Ie，所述第一电阻R1的一端与第二电阻R2的一端连接，所述第一电阻R1的另一端与PMOS晶体管P的漏极连接，所述第二电阻R2的另一端接地，所述运算放大器OPAMP的正输入端与第一电阻R1和第二电阻R2之间的电连接点连接，所述运算放大器OPAMP的负输入端连接参考电压Vref，所述运算放大器OPAMP的输出端连接PMOS晶体管P的栅极，所述运算放大器OPAMP的电源供应端连接外部输入的第一电压Vext，所述运算放大器OPAMP的负电压输入端接地，所述镜像电流源Ie的第一输入端连接外部输入的第一电压Vext，所述镜像电流源Ie的第二输入端连接所述运算放大器OPAMP的输出端，所述镜像电流源Ie的输出端产生输出电流以调整运算放大器OPAMP的偏置电流PMOS晶体管P，所述PMOS晶体管P的源极连接外部输入的第一电压Vext，所述PMOS晶体管P的漏极与第一电阻R1之间的电连接点输出第二电压Vpp(与字线驱动电路连接)，所述电容C一端连接所述PMOS晶体管P的漏极与第一电阻R1之间的电连接点，所述电容C的另一端接地。所述电压调节单元204采用该电路相比于现有的电荷泵电路结构简单占据存储器芯片的面积小，并且电压转化效率高，功耗低，输出电压噪声小，同时因为镜相电流的控制，可以根据输出电流的大小而实时调整偏置电流，进一步提高电压稳定性且降低功耗。
在一实施例中，所述电容C的电容值为5皮法～30皮法，所述镜像电流源 Ie中输出电流与所述PMOS晶体管的工作电流比例为1:1000～1:100，比例太小可以降低功耗但也降低了电压稳定性，比例太大会提高电压稳定性但也增加了电路功耗。
在另一具体的实施例中，请参考图10，所述电压调节单元204包括运算放大器OPAMP、第一电阻R1、第二电阻R2、电容C、第一PMOS晶体管P1和第二PMOS晶体管P2，所述第一电阻R1的一端与第二电阻R2的一端连接，所述第一电阻R1的另一端与第一PMOS晶体管P1的漏极连接，所述第二电阻R2的另一端接地，所述运算放大器OPAMP的正输入端与第一电阻R1和第二电阻R2之间的电连接点连接，所述运算放大器OPAMP的负输入端连接参考电压，所述运算放大器OPAMP的输出端连接第一PMOS晶体管P1的栅极，所述运算放大器OPAMP的电源供应端连接外部输入的第一电压Vext，所述第一PMOS晶体管P1的源极连接外部输入的第一电压Vext，所述第一PMOS晶体管P1的漏极与第一电阻R1之间的电连接点输出第二电压Vpp(与字线驱动电路连接)，所述电容C的一端连接所述第一晶体管的漏极与第一电阻R1之间的电连接点，所述电容C的另一端接地，所述第二PMOS晶体管P2的源极连接外部输入的第一电压Vext，所述第二PMOS晶体管P2的栅极与所述运算放大器OPAMP的输出端连接，所述第二PMOS晶体管P2的漏极与运算放大器OPAMP偏置电流调节端连接以调整运算放大器的偏置电流。所述电压调节单元204采用该电路相比于现有的电荷泵电路结构简单占据存储器芯片的面积小，并且电压转化效率高，功耗低，同时采用PMOS晶体管作为镜像电流源，结构简单，节省占用面积。
在一实施例中，所述电容C的电容C值为5皮法～30皮法。
本发明虽然已以较佳实施例公开如上，但其并不是用来限定本发明，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。

Claims (20)

  1. 一种半导体存储器，其特征在于，包括：
    存储器芯片，所述存储器芯片中至少包括存储阵列；
    电压调节单元，所述电压调节单元用于将外部输入的第一电压转换为第二电压，以供所述存储阵列中的字线驱动电路使用，其中所述第一电压大于第二电压。
  2. 如权利要求1所述的半导体存储器，其特征在于，所述存储器芯片的数量为1个或者大于等于2个，所述存储器芯片的数量大于等于2个时，若干存储器芯片依次向上堆叠或者若干存储器芯片呈平面排布。
  3. 如权利要求2所述的半导体存储器，其特征在于，所述电压调节单元的数量为1个，所述1个电压调节单元将转换后的第二电压输出给所述1个存储器芯片中的字线驱动电路或者分别输出给所述大于等于2个的存储器芯片中的字线驱动电路。
  4. 如权利要求2所述的半导体存储器，其特征在于，所述电压调节单元的数量为大于等于2个，所述存储器芯片的数量大于等于2个，且所述电压调节单元的数量等于存储器芯片的数量，每一个电压调节单元将转换后的第二电压对应输出给相应的一个存储器芯片中的字线驱动电路。
  5. 如权利要求2所述的半导体存储器，其特征在于，所述电压调节单元数量为大于等于2个，所述存储器芯片的数量为大于等于1个，所述1个存储器芯片中的字线驱动电路与至少2个电压调节单元连接，所述至少2个电压调节单元将转换后的第二电压对应输出给相应的一个存储器芯片中的字线驱动电路，且所述至少两个电压调节单元集成在对应的存储器芯片中。
  6. 如权利要求2所述的半导体存储器，其特征在于，所述存储器芯片的数量为1个时，且所述电压调节单元的数量为1个时，所述1个电压调节单元集成在所述1个存储器芯片中。
  7. 如权利要求2所述的半导体存储器，其特征在于，所述存储器芯片的数量大于等于2个时，且所述电压调节单元的数量为1个时，所述1个电压调节单元集成在所述其中一个存储器芯片中。
  8. 如权利要求2所述的半导体存储器，其特征在于，所述电压调节单元为独 立的电压调节芯片，所述半导体存储器还包括线路基板，所述线路上具有连接线路，所述存储器芯片和电压调节芯片位于基板上，所述电压调节芯片通过连接线路与存储器芯片连接，电压调节芯片输出的第二电压通过线路基板上的连接线路施加到存储器芯片的字线驱动电路。
  9. 如权利要求1所述的半导体存储器，其特征在于，所述存储器芯片为DRAM存储器芯片。
  10. 如权利要求9所述的半导体存储器，其特征在于，所述第一电压为3V-4V，所述第二电压为2.5-2.9V。
  11. 如权利要求1所述的半导体存储器，其特征在于，所述电压调节单元包括运算放大器、第一电阻和第二电阻，所述第一电阻的一端连接外部输入的第一电压，所述第一电阻的另一端与第二电阻的一端连接，所述第二电阻的另一端接地，所述第一电阻与第二电阻之间的电连接点连接所述运算放大器的正输入端，所述运算放大器的负输入端与运算放大器的输出端相连接并输出第二电压，所述运算放大器的电源供应端连接外部输入的第一电压。
  12. 如权利要求11所述的半导体存储器，其特征在于，所述第一电阻的阻值与第二电阻的阻值之比为3/2.9到4/2.5。
  13. 如权利要求1所述的半导体存储器，其特征在于，所述电压调节单元包括运算放大器、第一电阻、第二电阻和PMOS晶体管，所述第一电阻的一端与第二电阻的一端连接，所述第一电阻的另一端与PMOS晶体管的漏极连接，所述第二电阻的另一端接地，所述运算放大器的正输入端与第一电阻和第二电阻之间的电连接点连接，所述运算放大器的负输入端连接参考电压，所述运算放大器的输出端连接PMOS晶体管的栅极，所述运算放大器的电源供应端连接外部输入的第一电压，所述PMOS晶体管的源极连接外部输入的第一电压，所述PMOS晶体管的漏极与第一电阻之间的电连接点输出第二电压。
  14. 如权利要求13所述的半导体存储器，其特征在于，所述电压调节单元还包 括电容，所述电容一端连接所述PMOS晶体管的漏极与第一电阻之间的电连接点，另一端接地，所述电容的电容值为5皮法～30皮法，所述运算放大器的偏置电流固定，所述偏置电流为5微安～50微安。
  15. 如权利要求1所述的半导体存储器，其特征在于，所述电压调节单元包括运算放大器、第一电阻、第二电阻和PMOS晶体管，所述第一电阻的一端与第二电阻的一端连接，所述第一电阻的另一端与PMOS晶体管的漏极连接，所述第二电阻的另一端接地，所述运算放大器的正输入端与第一电阻和第二电阻之间的电连接点连接，所述运算放大器的负输入端连接参考电压，所述运算放大器的输出端连接PMOS晶体管的栅极，所述运算放大器的电源供应端连接外部输入的第一电压，所述运算放大器的使能端连接使能信号，所述PMOS晶体管的源极连接外部输入的第一电压，所述PMOS晶体管的漏极与第一电阻之间的电连接点输出第二电压。
  16. 如权利要求15所述的半导体存储器，其特征在于，所述电压调节单元还包括电容，述电容一端连接所述PMOS晶体管的漏极与第一电阻之间的电连接点，所述电容的另一端接地，所述电容的电容值为5皮法～30皮法，通过所述使能信号控制所述运算放大器工作在正常工作模式或睡眠模式，所述运算放大器正常工作模式时偏置电流为10～100微安，睡眠模式时偏置电流为0.5～3微安。
  17. 如权利要求1所述的半导体存储器，其特征在于，所述电压调节单元包括运算放大器、第一电阻、第二电阻、PMOS晶体管和镜像电流源，所述第一电阻的一端与第二电阻的一端连接，所述第一电阻的另一端与PMOS晶体管的漏极连接，所述第二电阻的另一端接地，所述运算放大器的正输入端与第一电阻和第二电阻之间的电连接点连接，所述运算放大器的负输入端连接参考电压，所述运算放大器的输出端连接PMOS晶体管的栅极，所述运算放大器的电源供应端连接外部输入的第一电压，所述镜像电流源的第一输入端连接外部输入的第一电压，所述镜像电流源的第二输入端连接所述运算放大器的输出端，所述镜像电流源的输出端产生输出电流以调整 运算放大器的偏置电流，所述PMOS晶体管的源极连接外部输入的第一电压，所述PMOS晶体管的漏极与第一电阻之间的电连接点输出第二电压。
  18. 如权利要求17所述的半导体存储器，其特征在于，所述电压调节单元还包括电容，所述电容一端连接所述PMOS晶体管的漏极与第一电阻之间的电连接点，所述电容的另一端接地，所述电容的电容值为5皮法～30皮法，所述镜像电流源中输出电流与所述PMOS晶体管的工作电流比例为1:1000～1:100。
  19. 如权利要求1所述的半导体存储器，其特征在于，所述电压调节单元包括运算放大器、第一电阻、第二电阻、第一PMOS晶体管和第二PMOS晶体管，所述第一电阻的一端与第二电阻的一端连接，所述第一电阻的另一端与第一PMOS晶体管的漏极连接，所述第二电阻的另一端接地，所述运算放大器的正输入端与第一电阻和第二电阻之间的电连接点连接，所述运算放大器的负输入端连接参考电压，所述运算放大器的输出端连接第一PMOS晶体管的栅极，所述运算放大器的电源供应端连接外部输入的第一电压，所述第一PMOS晶体管的源极连接外部输入的第一电压，所述第一PMOS晶体管的漏极与第一电阻之间的电连接点输出第二电压，所述第二PMOS晶体管的源极连接外部输入的第一电压，所述第二PMOS晶体管的栅极与所述运算放大器的输出端连接，所述第二PMOS晶体管的漏极与运算放大器的偏置电流调节端连接以调整运算放大器的偏置电流。
  20. 如权利要求19所述的半导体存储器，其特征在于，所述电压调节单元还包括电容，所述电容的一端连接所述第一晶体管的漏极与第一电阻之间的电连接点，所述电容的另一端接地，所述电容的电容值为5皮法～30皮法。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060273771A1 (en) * 2005-06-03 2006-12-07 Micrel, Incorporated Creating additional phase margin in the open loop gain of a negative feedback amplifier system
CN103814628A (zh) * 2011-09-19 2014-05-21 莫塞德技术公司 用于3d封装的电压调节以及制造其的方法
CN104102261A (zh) * 2013-04-03 2014-10-15 盛群半导体股份有限公司 低压降线性稳压器
CN105810247A (zh) * 2016-04-19 2016-07-27 北京兆易创新科技股份有限公司 一种字线驱动电路
CN106782643A (zh) * 2015-11-23 2017-05-31 南亚科技股份有限公司 动态随机存取存储器电路及其电压控制方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3667787B2 (ja) * 1994-05-11 2005-07-06 株式会社ルネサステクノロジ 半導体記憶装置
CN1867068A (zh) * 1998-07-14 2006-11-22 联合视频制品公司 交互式电视节目导视系统及其方法
JP3886669B2 (ja) * 1999-06-10 2007-02-28 株式会社東芝 半導体記憶装置
TW527601B (en) * 2000-01-31 2003-04-11 Fujitsu Ltd Internal supply voltage generating circuit in a semiconductor memory device and method for controlling the same
JP2002083942A (ja) * 2000-09-06 2002-03-22 Matsushita Electric Ind Co Ltd 半導体集積回路装置
KR100460459B1 (ko) * 2002-07-30 2004-12-08 삼성전자주식회사 향상된 테스트 모드를 갖는 반도체 메모리 장치
US6898104B2 (en) * 2002-11-12 2005-05-24 Kabushiki Kaisha Toshiba Semiconductor device having semiconductor memory with sense amplifier
KR100575882B1 (ko) * 2003-11-26 2006-05-03 주식회사 하이닉스반도체 번인 테스트용 내부 전압 발생 장치
JP4426361B2 (ja) * 2004-03-31 2010-03-03 パナソニック株式会社 不揮発性半導体記憶装置
KR100562654B1 (ko) * 2004-04-20 2006-03-20 주식회사 하이닉스반도체 균등화신호(ｂｌｅｑ) 구동회로 및 이를 사용한 반도체메모리 소자
US7352609B2 (en) * 2005-08-15 2008-04-01 International Business Machines Corporation Voltage controlled static random access memory
JP5134208B2 (ja) * 2006-03-20 2013-01-30 株式会社東芝 半導体記憶装置
JP5158624B2 (ja) 2006-08-10 2013-03-06 ルネサスエレクトロニクス株式会社 半導体記憶装置
JP4946260B2 (ja) * 2006-08-16 2012-06-06 富士通セミコンダクター株式会社 アンチヒューズ書込電圧発生回路を内蔵する半導体メモリ装置
US7692978B2 (en) * 2007-05-25 2010-04-06 Nec Electronics Corporation Semiconductor device that uses a plurality of source voltages
US7764563B2 (en) * 2008-11-26 2010-07-27 Micron Technology, Inc. Adjustable voltage regulator for providing a regulated output voltage
US7859917B2 (en) * 2009-01-08 2010-12-28 Macronix International Co., Ltd. Voltage regulation method and memory applying thereof
CN102487240B (zh) * 2010-12-01 2014-02-05 中芯国际集成电路制造(上海)有限公司 电压转换速率控制电路和输出电路
IT1404186B1 (it) * 2011-02-28 2013-11-15 St Microelectronics Srl Regolatore di tensione
JP2012203673A (ja) * 2011-03-25 2012-10-22 Seiko Instruments Inc ボルテージレギュレータ
US9305604B2 (en) * 2011-09-01 2016-04-05 HangZhou HaiCun Information Technology Co., Ltd. Discrete three-dimensional vertical memory comprising off-die address/data-translator
US9311980B1 (en) * 2012-10-11 2016-04-12 Everspin Technologies, Inc. Word line supply voltage generator for a memory device and method therefore
KR102204678B1 (ko) * 2014-12-11 2021-01-20 삼성전자주식회사 인버터 증폭기 기반의 이중 루프 레귤레이터 및 그에 따른 전압 레귤레이팅 방법
US10395723B2 (en) * 2017-03-07 2019-08-27 Toshiba Memory Corporation Memory system that differentiates voltages applied to word lines
KR102392665B1 (ko) * 2017-11-29 2022-04-29 삼성전자주식회사 메모리 장치, 이를 포함하는 시스템 온 칩 및 메모리 장치의 동작 방법
CN109147834B (zh) * 2018-09-27 2024-02-13 长鑫存储技术有限公司 电源系统及半导体封装集合体
US11342031B2 (en) * 2020-08-28 2022-05-24 Stmicroelectronics S.R.L. Circuit and method for process and temperature compensated read voltage for non-volatile memory

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060273771A1 (en) * 2005-06-03 2006-12-07 Micrel, Incorporated Creating additional phase margin in the open loop gain of a negative feedback amplifier system
CN103814628A (zh) * 2011-09-19 2014-05-21 莫塞德技术公司 用于3d封装的电压调节以及制造其的方法
CN104102261A (zh) * 2013-04-03 2014-10-15 盛群半导体股份有限公司 低压降线性稳压器
CN106782643A (zh) * 2015-11-23 2017-05-31 南亚科技股份有限公司 动态随机存取存储器电路及其电压控制方法
CN105810247A (zh) * 2016-04-19 2016-07-27 北京兆易创新科技股份有限公司 一种字线驱动电路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3920186A4 *

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US11869573B2 (en) 2024-01-09

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