WO2021196619A1 - 读写方法及存储器装置 - Google Patents

读写方法及存储器装置 Download PDF

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Publication number
WO2021196619A1
WO2021196619A1 PCT/CN2020/127508 CN2020127508W WO2021196619A1 WO 2021196619 A1 WO2021196619 A1 WO 2021196619A1 CN 2020127508 W CN2020127508 W CN 2020127508W WO 2021196619 A1 WO2021196619 A1 WO 2021196619A1
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Prior art keywords
address information
read
command
pointed
data
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PCT/CN2020/127508
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English (en)
French (fr)
Inventor
寗树梁
何军
刘杰
应战
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长鑫存储技术有限公司
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Priority to EP20926358.1A priority Critical patent/EP4131009A4/en
Priority to US17/310,495 priority patent/US11922023B2/en
Publication of WO2021196619A1 publication Critical patent/WO2021196619A1/zh

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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
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    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
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    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair

Definitions

  • the present invention relates to the field of semiconductor storage, in particular to a reading and writing method and a memory device.
  • Semiconductor memory is a memory component used to store various data and information. With the increase in circuit complexity, various forms of memory are inevitably prone to produce defective or damaged memory cells in the manufacturing or use process, resulting in a decrease in the reliability of the semiconductor memory.
  • the technical problem to be solved by the present invention is to provide a reading and writing method and a memory device, which can greatly improve the reliability and life of the memory device.
  • the present invention provides a read and write method, which applies a read command to a memory device, the read command points to address information, and reads the to-be-read from the memory cell corresponding to the address information pointed to by the read command. If an error occurs in the data to be read, the address information pointed to by the read command is stored in the preset storage space.
  • the address information pointed to by the read command is not stored in the preset storage space.
  • the step of reading the data to be read from the storage unit corresponding to the address information pointed to by the read command further includes: reading the data to be read from the storage unit corresponding to the address information pointed to by the read command.
  • the first ECC code corresponding to the read data; the method for judging whether the data to be read has an error includes: decoding the first ECC code to determine whether the data to be read has an error.
  • a write command is applied to the memory device, and the address information pointed to by the write command is compared with the address information stored in the preset storage space. If the address information pointed to by the write command is compared with the stored address information If the address information in the preset storage space is not the same, a write operation is performed on the storage unit corresponding to the address information pointed to by the write command. If the address information pointed to by the write command is different from the address information stored in the preset If the address information in the storage space is the same, the writing operation to the storage unit corresponding to the address information pointed to by the write command is stopped.
  • the method further includes the following step: changing the address information pointed to by the write command to another address information.
  • the method further includes the following step: comparing the another address information with the address information stored in the preset storage space, if If the another address information is the same as the address information stored in the preset storage space, the writing operation to the storage unit corresponding to the another address information is stopped, and if the another address information is the same as that stored in the If the address information in the preset storage space is not the same, a write operation is performed on the storage unit corresponding to the other address information.
  • the step of performing a write operation on the storage unit corresponding to the address information pointed to by the write command further includes: forming a second ECC code corresponding to the data to be written in the write operation, and combining it with the to-be-written data The written data is also written into the storage unit corresponding to the address information pointed to by the write command.
  • the method further includes: The address information is compared with the address information stored in the preset storage space, and if the address information pointed to by the read command is not the same as the address information stored in the preset storage space, the read The memory cell corresponding to the address information pointed to by the command performs a read operation.
  • the address information pointed to by the read command is the same as the address information stored in the preset storage space, it is determined whether the address information pointed to by the read command is stored in the preset storage space.
  • the address information pointed to by the read command has executed a write command, and if so, the read command points to the address information pointed to by the write command to perform a read operation on the corresponding storage unit.
  • the present invention also provides a memory device, which includes: a command receiving unit for receiving a read command or a write command; a storage unit corresponding to the address information pointed to by the read command or a write command; The storage unit performs a read operation or a write operation; the preset storage space is used to store the address information corresponding to the storage unit where the data error occurs.
  • the memory device further includes an ECC encoding and decoding unit for decoding the first ECC encoding corresponding to the data to be read in the read operation and forming the second ECC encoding corresponding to the data to be written in the writing operation.
  • ECC code for decoding the first ECC encoding corresponding to the data to be read in the read operation and forming the second ECC encoding corresponding to the data to be written in the writing operation.
  • the memory device further includes a comparing unit connected to the command receiving unit and the preset storage space, and configured to compare the address information pointed to by the read command or the write command with the preset storage space. The address information in the storage space is compared.
  • the execution unit is also connected to the comparison unit, and is configured to perform a read operation or a write operation on the storage unit corresponding to the address information pointed to by the read command or the write command according to the result output by the comparison unit, or stop the The storage unit corresponding to the address information pointed to by the read command or the write command performs a read operation or a write operation.
  • the memory device further includes a judging unit, which is connected to the command receiving unit and the execution unit, and is configured to judge whether the address information pointed to by the read command is stored in the preset storage space.
  • the address information pointed to by the read command has executed a write command.
  • the memory device further includes a conversion unit, which is used to change the address pointed to by the read command or the write command after the read operation or the write operation on the storage unit corresponding to the address information pointed by the read command or the write command is stopped. The information is changed to another address information.
  • the memory device includes a logic layer and at least one storage layer, the command receiving unit and the execution unit are arranged in the logic layer, the storage unit is arranged in the storage layer, and the preset storage space is arranged At the storage layer or the logic layer.
  • the advantage of the present invention is that the address information corresponding to the storage unit where the data error occurs is stored in the preset storage space when the user performs the read/write operation on the memory device, so as to distinguish the effective storage unit from the failed storage unit in real time. That is, every time a read operation is performed, the corresponding address information of the failed storage unit will be stored in the preset storage space, so that when the user performs a read operation or write operation on the storage device, it is not stored in the preset storage space.
  • the address information can be read and written to avoid data errors or data loss, which greatly improves the reliability and life of the memory device.
  • FIG. 1 is a schematic flowchart of the first specific implementation of the reading and writing method of the present invention
  • FIG. 2 is a schematic flowchart of a second specific embodiment of the reading and writing method of the present invention.
  • FIG. 3 is a schematic flowchart of a third specific implementation of the reading and writing method of the present invention.
  • FIG. 4 is a schematic diagram of the framework of the first specific embodiment of the memory device of the present invention.
  • FIG. 5 is a schematic diagram of the framework of the second specific embodiment of the memory device of the present invention.
  • FIG. 6 is a schematic diagram of the framework of the third specific embodiment of the memory device of the present invention.
  • FIG. 7 is a schematic diagram of a framework of a fourth specific embodiment of the memory device of the present invention.
  • FIG. 8 is a schematic diagram of a framework of a fifth specific embodiment of the memory device of the present invention.
  • FIG. 9 is a schematic diagram of the framework of the sixth specific embodiment of the memory device of the present invention.
  • a common method to improve the reliability of a memory device is to encode the data as an Error Correction Code (ECC) before writing the data into the memory device, and store the data and the error correction code in the memory device at the same time.
  • ECC Error Correction Code
  • the error correction code can only correct the data when the data is read, and the storage unit where the data error occurred in the memory still exists. If in the subsequent data storage process, at least one storage unit with data error occurs in the storage segment corresponding to the storage unit where the data error occurs, there will be at least two storage units with data error in the storage segment. The error correction code will not be able to correct the error, causing the storage segment to be unusable, or even causing the memory device to be unusable, thereby affecting the reliability and life of the memory device.
  • the present invention provides a method for reading and writing, which can distinguish the storage units where data errors have occurred in real time.
  • the address information corresponding to the storage unit where the data to be read has an error is stored in the preset storage space, so as to make the data to be read have an error.
  • the storage unit of is distinguished from the storage unit of the data to be read without error.
  • FIG. 1 is a schematic flowchart of the first specific implementation of the reading and writing method of the present invention.
  • the reading and writing method includes the following steps:
  • Step S10 applying a read command to the memory device, the read command pointing to address information.
  • the address information pointed to by the read command is A0.
  • Step S11 Read the data to be read from the storage unit corresponding to the address information pointed to by the read command.
  • the data to be read is read from the storage unit corresponding to the address information A0.
  • step S12 it is judged whether an error occurs in the data to be read.
  • the address information A0 pointed to by the read command is stored in the preset storage space 10; If an error occurs in the data to be read read in the storage unit corresponding to the address information A4 pointed to by the read command, the address information A4 pointed to by the read command is stored in the preset storage space 10.
  • the preset storage space 10 may be a structure with storage function known to those skilled in the art, such as static random access memory (SRAM), dynamic random access memory (DRAM), magnetic memory (MRAM), registers, latches, or flip-flops. If there is no error in the data to be read, it means that the storage unit is valid, and the address information pointed to by the read command is not stored in the preset storage space 10.
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • MRAM magnetic memory
  • the address information A1 pointed to by the read command is not stored in the preset storage space 10; If there is no error in the data to be read read from the storage unit corresponding to the address information A2 pointed to by the read command, the address information A2 pointed to by the read command is not stored in the preset storage space 10.
  • the present invention also provides a method for judging whether the data to be read out has an error.
  • the step of reading the data to be read from the storage unit corresponding to the address information pointed to by the read command further includes: reading the data to be read from the storage unit corresponding to the address information pointed to by the read command.
  • the first ECC code corresponding to the data to be read For example, the number of bits of data read from the storage unit corresponding to the address information pointed to by the read command is 64b+8b, where 64b is the number of bits of data to be read, and 8b is the first ECC code. Number of digits.
  • the first ECC code can be decoded to restore the data that may have errors. The algorithm is the prior art and will not be repeated. Therefore, it can be determined whether an error occurs in the data to be read based on the decoding of the first ECC code.
  • the present invention lists a method for judging whether the data to be read out has an error based on decoding the first ECC code: re-encoding the data to be read out to form a new ECC code, and encoding the new ECC code Perform a bit-wise XOR comparison with the first ECC code. If each bit is consistent, it means that there is no error in the data to be read and the storage unit is valid. Then the address information corresponding to the storage unit is not stored In the preset storage space 10; if there is an inconsistency between the new ECC code and the first ECC code, it indicates that an error has occurred in the data to be read, and the storage unit is invalid, then the address corresponding to the storage unit The information is stored in the preset storage space 10.
  • the data to be read is used as the output data of the memory device, and if an error occurs in the data to be read, the first ECC encoding can be used to perform Restore the data, and use the restored data as the output data of the memory device.
  • the reading and writing method of the present invention uses the preset storage space 10 to distinguish the address information corresponding to the storage unit where the data error has occurred and the address information corresponding to the storage unit where the data does not have an error, so that in the subsequent reading and writing operations, it can be based on the read command or the write command. Whether the address information pointed to by the command is located in the preset storage space 10 to determine whether to perform a read operation or a write operation on the address information, avoiding data errors or data loss, greatly improving the reliability of the memory device and extending the memory device’s performance life.
  • the reading and writing method of the present invention also provides a second specific implementation manner. After the read command is applied to the memory device, before the data to be read is read from the storage unit corresponding to the address information pointed to by the read command, a comparison step is further included. Specifically, please refer to FIG. 2, which is a schematic flowchart of the second embodiment of the reading and writing method of the present invention.
  • Step S20 Apply a read command to the memory device, where the read command points to address information.
  • Step S21 comparing the address information pointed to by the read command with the address information stored in the preset storage space 20. That is, it is determined whether the address information pointed to by the read command is the same as the address information stored in the preset storage space 20.
  • step S22 If the address information pointed to by the read command is different from the address information stored in the preset storage space 20, it means that the address information pointed to by the read command is not stored in the preset storage space 20. Then the storage unit corresponding to the address information pointed to by the read command is a valid storage unit, and a read operation is performed on the storage unit corresponding to the address information pointed to by the read command, that is, step S22 is executed.
  • the address information pointed to by the read command is A1
  • the address information pointed to by the read command is A1 and the address information stored in the preset storage space 20 is compared. If the address information pointed to by the read command is Since A1 is different from any address information stored in the preset storage space 20, it means that the address information A1 pointed to by the read command is not stored in the preset storage space 20, then the read command is not stored in the preset storage space 20.
  • the storage unit corresponding to the pointed address information A1 performs a read operation, that is, step S22 is executed. Then, in step S22, the address information pointed to by the read command is A1.
  • the address information pointed to by the read command is the same as the address information stored in the preset storage space 20, it means that the address information pointed to by the read command is stored in the preset storage space 20, then the The storage unit corresponding to the address information pointed to by the read command is a failed storage unit. Then proceed as follows: determine whether the address information pointed to by the read command is stored in the preset storage space 20 in the operation before the current read operation, whether a write command has been executed on the address information pointed to by the read command . If so, the read command is directed to the address information pointed to by the write command, that is, the address information pointed to by the write command is used as the new address information pointed to by the read command, and step S22 is performed on the new address information. If not, there are two processing methods. One processing method is to stop the read operation as shown in FIG. 2 in this specific embodiment; the other processing method is to continue the read operation and use the first ECC code The restored data is used as the output data of the memory device.
  • the address information A4 pointed to by the read command is the same as the address information stored in the preset storage space 20, that is, the address information A4 pointed to by the read command is stored in the preset storage space 20, and it is determined that In the operation before the current read operation, after storing the address information A4 pointed to by the read command in the preset storage space 20, whether a write command has been executed on the address information A4 pointed to by the read command. If yes, and the write command points to another address information A5, then the read command points to the address information A5 pointed to by the write command to perform a read operation on the corresponding storage unit, that is, step S22, step S22
  • the address information pointed to by the read command is address information A5.
  • the specific implementation of the write command please refer to the third specific implementation manner. If not, stop the read operation.
  • Step S22 Read the data to be read from the storage unit corresponding to the address information pointed to by the read command.
  • the data to be read is read from the storage unit corresponding to the address information A1 pointed to by the read command. This step is the same as step S11 in the first specific embodiment.
  • Step S23 It is judged whether an error occurs in the data to be read. This step is the same as step S12 in the first specific embodiment. If an error occurs in the data to be read, it indicates that the storage unit is invalid, and the address information pointed to by the read command is stored in the preset storage space 20. If there is no error in the data to be read, it indicates that the storage If the unit is valid, the address information pointed to by the read command is not stored in the preset storage space 20.
  • Step S24 output data.
  • the address information pointed to by the read command is compared with the address information stored in the preset storage space 20 to determine Whether the address information pointed to by the read command is located in the preset storage space 20, so that the read command can be selectively executed on the address information pointed to by the read command, thereby improving the reliability of the memory device.
  • the reading and writing method of the present invention also provides a third specific implementation manner.
  • the third specific embodiment is a write operation to a memory device.
  • FIG. 3 is a schematic flowchart of a third specific embodiment of the reading and writing method of the present invention.
  • Step S30 applying a write command to the memory device, the write command pointing to address information. For example, a write command is applied to the memory device, and the write command points to address information A0.
  • Step S31 Compare the address information pointed to by the write command with the address information stored in the preset storage space 30, that is, determine whether the address information pointed to by the write command is stored in the preset storage space 30 .
  • the address information pointed to by the write command is different from the address information stored in the preset storage space 30, that is, the address information pointed to by the write command is not stored in the preset storage space 30,
  • the write operation is performed on the storage unit corresponding to the address information pointed to by the write command. If the address information pointed to by the write command is the same as the address information stored in the preset storage space 30, that is, the write command
  • the pointed address information is stored in the preset storage space 30, and then the writing operation to the storage unit corresponding to the address information pointed to by the write command is stopped.
  • the address information pointed to by the write command is address information A1, and the address information A1 is compared with the address information stored in the preset storage space 30.
  • the address information A1 is different from any address information stored in the preset storage space 30, indicating that the address information A1 pointed to by the write command is not stored in the preset storage space 30.
  • the storage unit corresponding to the address information A1 pointed to by the write command performs the write operation.
  • the address information pointed to by the write command is address information A4, and the address information A4 is compared with the address information stored in the preset storage space 30.
  • the address information A4 is the same as an address information stored in the preset storage space 30, which means that the address information A4 pointed to by the write command is stored in the preset storage space 30, and then the write command is stopped.
  • the storage unit corresponding to the pointed address information A4 performs a write operation.
  • the method further includes the following step: changing the address information pointed to by the write command to Another address information.
  • the other address information can also be compared with the address information stored in the preset storage space 30.
  • the comparison method is the same as step S31. If the another address information is the same as the address information stored in the preset storage space 30, stop writing to the storage unit corresponding to the another address information, if the other address information is the same as that stored in the If the address information in the preset storage space 30 is different, a write operation is performed on the storage unit corresponding to the other address information.
  • the address information A0 pointed to by the write command is changed to another address information A1, that is, the step is described after this step.
  • the write command points to address information A1.
  • the address information A1 pointed to by the write command is further compared with the address information stored in the preset storage space 30, that is, it is determined whether the address information A1 is stored in the preset storage space 30.
  • the address information A1 is different from any address information stored in the preset storage space 30, that is, the address information A1 is not stored in the preset storage space 30.
  • the storage unit corresponding to the address information A1 performs a write operation.
  • the address information A1 is the same as a certain address information stored in the preset storage space 30, that is, the address information A1 is stored in the preset storage space 30, then Stop writing to the storage unit corresponding to the address information A1, and change the address information of the write command to A2, and compare the address information A2 with the address information stored in the preset storage space 30 That is, it is determined whether the address information A2 is stored in the preset storage space 30, and so on, until the address information pointed to by the write command is different from the address information stored in the preset storage space 30, it stops.
  • the read and write method further includes the following steps: forming a second ECC code corresponding to the data to be written in the write operation, and combining it with the data to be written And write it into the storage unit corresponding to the address information pointed to by the write command.
  • the data in the storage unit is read, the data and the second ECC code are read at the same time, and the second ECC code is decoded to restore the data that may have errors.
  • the reading and writing method of the present invention compares the address pointed to by the write command with the address information stored in the preset storage space 30 after applying the write command to the memory device, as The basis of whether to perform a write operation on a storage unit can avoid performing a write operation on a failed storage unit, thereby improving the reliability of the memory device and prolonging the life of the memory device.
  • the present invention also provides a memory device capable of realizing the above-mentioned reading and writing method.
  • the memory device includes, but is not limited to, volatile memory such as DRAM and SRAM, and non-volatile memory such as NAND, NOR, FeRAM, RRAM, MRAM, and PCRAM.
  • FIG. 4 is a schematic diagram of the framework of the first embodiment of the memory device of the present invention.
  • the memory device includes a command receiving unit 40, a storage unit 41, a preset storage space 42 and an execution unit 43.
  • the command receiving unit 40 is configured to receive address information pointed to by a read command, a write command, or a read/write command applied to the memory device.
  • the storage unit 41 corresponds to the address information corresponding to the read command or the write command, and is used to store data.
  • the storage unit 41 may be a storage unit well-known to those skilled in the art, such as a basic cell, a segment, a page, and a block. No restrictions.
  • the preset storage space 42 is used to store the address information corresponding to the storage unit where the data error occurs.
  • the preset storage space 42 may be a structure with storage function known to those skilled in the art, such as static random access memory (SRAM), dynamic random access memory (DRAM), magnetic memory (MRAM), registers, latches, or flip-flops.
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • MRAM magnetic memory
  • the execution unit 43 is configured to control the execution of a read operation or a write operation on the storage unit 41.
  • the execution unit 43 is also connected to the preset storage space 42, and is configured to perform a read operation on the storage unit corresponding to the address information pointed to by the read command or the write command according to the address information stored in the preset storage space 42, or Write operation, or stop reading or writing the memory cell corresponding to the address information pointed to by the read command or the write command.
  • the execution unit 43 executes the storage unit corresponding to the address information For a read operation or a write operation, if the address information pointed to by the read command or the write command is the same as a certain address information stored in the preset storage space 42, the execution unit 43 stops processing the storage unit corresponding to the address information Perform a read operation or a write operation.
  • execution unit 43 can also be directly connected to the command receiving unit 40, which is not limited in the present invention, and those skilled in the art can choose the connection mode according to their needs.
  • the memory device of the present invention also provides a second specific embodiment. Please refer to FIG. 5, which is a schematic diagram of the framework of the second embodiment of the memory device of the present invention.
  • the difference between the second embodiment and the first embodiment is that the memory device further includes an ECC encoding and decoding unit. 44.
  • the ECC encoding and decoding unit 44 is connected to the execution unit 43, the storage unit 41, and the preset storage space 42.
  • the ECC encoding and decoding unit 44 is used to decode the first ECC encoding corresponding to the data to be read in the read operation to restore the data that may be erroneous, and can be used to restore the data according to whether the ECC encoding and decoding unit 44 restores the data. It is determined whether the address information needs to be stored in the preset storage space 42.
  • the ECC encoding and decoding unit 44 is also used to form a second ECC encoding corresponding to the data to be written in the write operation.
  • the command receiving unit receives a write command, and when a write operation is performed on the storage unit corresponding to the address information pointed to by the write command, the ECC encoding and decoding unit 44 is formed and the write operation is in progress.
  • the ECC code corresponding to the data to be written is simultaneously stored in the storage unit 41 corresponding to the address information pointed to by the write command.
  • the ECC encoding and decoding unit 44 decodes the ECC encoding.
  • the decoding of the ECC encoding and decoding unit 44 can be used to determine whether an error occurs in the data to be read read by the read operation, and then to determine whether the address information needs to be stored in the preset storage space 42.
  • the address information needs to be stored in the preset storage space 42 according to whether the ECC encoding and decoding unit 44 restores the data. Specifically, if the ECC encoding and decoding unit 44 decodes the ECC encoding and restores the data, indicating that an error occurs in the data to be read read by the read operation, the address information of the storage unit is stored in the preview. Assuming that in the storage space 42, if the ECC encoding and decoding unit 44 decodes the ECC encoding, but does not restore the data, indicating that the data to be read read by the read operation has no error, then the address information is not Stored in the preset storage space 42.
  • the ECC encoding and decoding unit 44 decodes the ECC encoding. Although the data is not restored, according to the decoding of the ECC encoding and decoding unit 44, it can be determined that the read operation is read. If an error occurs in the data to be read, the address information of the storage unit is stored in the preset storage space 42.
  • the memory device further includes a conversion unit 45.
  • the conversion unit 45 may be connected to the execution unit 43. After stopping the read operation or write operation on the storage unit corresponding to the address information, the conversion unit 45 changes the address information pointed to by the read command or the write command to another address information.
  • the execution unit 43 reads or writes another address information according to the marking information of the marking unit.
  • the execution unit 43 is not only connected to the ECC encoding and decoding unit 44, but also connected to the storage unit 41.
  • FIG. 6 is the memory
  • the execution unit 43 is connected to the ECC encoding and decoding unit 44, and the ECC encoding and decoding unit 44 is then connected to the storage unit 41. It is understandable that different connection relationships can be selected according to different needs.
  • the memory device of the present invention also provides a fourth specific embodiment. Please refer to FIG. 7, which is a schematic diagram of the frame of the fourth embodiment of the memory device.
  • the memory device includes the memory device and further includes a comparison unit 46.
  • the comparison unit 46 is connected to the command receiving unit 40 and the preset storage space 42, and is used to compare the address information pointed to by the read command or the write command with the address information in the preset storage space 42 Compare.
  • the execution unit 43 is also connected to the comparison unit 46, and is configured to perform a read operation or a write operation on the storage unit corresponding to the address information pointed to by the read command or the write command according to the result output by the comparison unit 46, or stop Perform a read operation or a write operation on the storage unit corresponding to the address information pointed to by the read command or the write command.
  • the comparison unit 46 compares the address information pointed to by the read command or the write command with the address information in the preset storage space 42, if the address information pointed to by the read command or write command is compared with the address information pointed to by the read command or write command.
  • the comparison unit 46 outputs a signal that can identify the difference to the execution unit 43, and the execution unit 43 responds to the read command or The storage unit corresponding to the address information pointed to by the write command performs a read operation or a write operation; if the address information pointed to by the read command or write command is the same as a certain address information in the preset storage space 42, the comparison The unit 46 outputs a signal capable of identifying the same to the execution unit 43, and the execution unit 43 stops performing a read operation or a write operation on the storage unit corresponding to the address information pointed to by the read command or the write command according to the signal.
  • the memory device further includes a judging unit 47, which is connected to the command receiving unit 40 and the execution unit 43, and is used to judge whether the read command is directed to After the address information of is stored in the preset storage space 42, whether a write command has been performed on the address information pointed to by the read command.
  • the execution unit 43 can perform a write operation on the corresponding storage unit according to the output result of the judgment unit 47.
  • the memory device of the present invention also provides a fifth specific embodiment.
  • FIG. 8 is a schematic diagram of the framework of the fifth embodiment of the memory device.
  • the memory device includes a logic layer 100 and a plurality of storage layers 200 (only A case of a storage layer is shown), the storage layer 200 may be a DRAM chip, and the logic layer 100 may be a layer provided with logic circuits such as a control chip or an interposer.
  • Several storage layers 200 can be vertically stacked above or below the logic layer 100, but the present invention is not limited to this, and other packaging methods can also be used to integrate them.
  • the command receiving unit 40, the preset storage space 42, the execution unit 43, the ECC encoding and decoding unit 44, and the conversion unit 45 can all be set in the logic layer 100, and the storage The unit 41 is provided in the storage layer 200.
  • the preset storage space 42 and the ECC encoding and decoding unit 44 may also be provided in the storage layer 200.
  • the logic layer 100 has at least one first data transmission port 48
  • the storage layer 200 has at least one second data transmission port 49. Instructions and data are transmitted between the logic layer 100 and the storage layer 200 through the first data transmission port 48 and the second data transmission port 49.
  • the execution unit 43 is not only connected to the ECC encoding and decoding unit 44, but also connected to the storage unit 41 through the first data transmission port 48 and the second data transmission port 49, and
  • FIG. 9 is a schematic diagram of the framework of the fifth embodiment of the memory device.
  • the execution unit 43 is connected to the ECC encoding and decoding unit 44, and the ECC encoding and decoding unit 44 is then connected to the storage unit 41 through the first data transmission port 48 and the second data transmission port 49. It is understandable that different connection relationships can be selected according to different needs.
  • the comparison unit 46 and the judgment unit 47 may also be provided in the logic layer 100.
  • the memory device of the present invention can use the preset storage space to distinguish the address information of the invalid storage unit from the address information of the valid storage unit during the user's use, and then selectively perform read and write operations on the storage unit, which greatly improves The reliability and longevity of the memory device.

Abstract

一种读写方法及存储器装置，所述读写方法为：对存储器装置施加读命令，所述读命令指向地址信息（S10），从所述读命令所指向的地址信息对应的存储单元（41）中读取待读出的数据（S11），若所述待读出的数据发生错误，则将所述读命令所指向的地址信息存储在预设存储空间（42）中（S12）。从而在用户对存储器装置执行读写操作时将数据发生错误的存储单元（41）对应的地址信息存储在预设存储空间（42）中，以将有效的存储单元（41）与失效的存储单元（41）进行实时区分，以在用户对所述存储器装置执行读操作或者写操作时，不对存储在预设存储空间（42）中的地址信息进行读写操作，避免数据错误或者数据丢失，大大提高了存储器装置的可靠性及寿命。

Description

读写方法及存储器装置
相关申请引用说明
本申请要求于2020年04月01日递交的中国专利申请号202010250011.0，申请名为“读写方法及存储器装置”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及半导体存储领域，尤其涉及一种读写方法及存储器装置。
背景技术
半导体存储器是用来存储各种数据信息的记忆部件。随着电路复杂度的提升，各种形式的存储器在制造上或者使用过程中无可避免地容易产生不良或受损的存储单元，导致半导体存储器可靠度降低。
因此，如何避免上述情况发生，成为目前亟需解决的问题。
发明内容
本发明所要解决的技术问题是，提供一种读写方法及存储器装置，其能够大大提高存储器装置的可靠性及寿命。
为了解决上述问题，本发明提供了一种读写方法，对存储器装置施加读命令，所述读命令指向地址信息，从所述读命令所指向的地址信息对应的存储单元中读取待读出的数据，若所述待读出的数据发生错误，则将所述读命令所指向的地址信息存储在预设存储空间中。
进一步，若所述待读出的数据没有发生错误，则不将所述读命令所指向的地址信息存储在所述预设存储空间中。
进一步，从所述读命令所指向的地址信息对应的存储单元中读取待读出的数据的步骤还包括：从所述读命令所指向的地址信息对应的存储单元中读取与所述待读出的数据对应的第一ECC编码；判断所述待读出的数据是否发生错误的方法包括：对所述第一ECC编码进行解码，以判断所述待读出的数据是否发生错误。
进一步，对所述存储器装置施加写命令，并将所述写命令所指向的地址信息与存储在所述预设存储空间内的地址信息进行比较，若所述写命令所指向的地址信息与存储在所述预设存储空间内的地址信息不相同，则对所述写命令所指向的地址信息对应的存储单元执行写操作，若所述写命令所指向的地址信息与存储在所述预设存储空间内的地址信息相同，则停止对所述写命令所指向的地址信息对应的存储单元执行写操作。
进一步，在停止对所述写命令所指向的地址信息对应的存储单元执行写操作的步骤之后还包括如下步骤：将所述写命令所指向的地址信息改变为另一地址信息。
进一步，将所述写命令所指向的地址信息改变为另一地址信息的步骤之后 还包括如下步骤：将所述另一地址信息与存储在所述预设存储空间内的地址信息进行比较，若所述另一地址信息与存储在所述预设存储空间内的地址信息相同，则停止对所述另一地址信息对应的存储单元执行写操作，若所述另一地址信息与存储在所述预设存储空间内的地址信息不相同，则对所述另一地址信息对应的存储单元执行写操作。
进一步，对所述写命令所指向的地址信息对应的存储单元执行写操作的步骤进一步包括：形成与所述写操作中待写入的数据对应的第二ECC编码，并将其与所述待写入的数据一并写入所述写命令所指向的地址信息对应的存储单元中。
进一步，在所述对存储器装置施加读命令之后，在所述从所述读命令所指向的地址信息对应的存储单元中读取待读出的数据之前，还包括：将所述读命令所指向的地址信息与存储在所述预设存储空间内的地址信息进行比较，若所述读命令所指向的地址信息与存储在所述预设存储空间内的地址信息不相同，则对所述读命令所指向的地址信息对应的存储单元执行读操作。
进一步，若所述读命令所指向的地址信息与存储在所述预设存储空间内的地址信息相同，则判断将所述读命令所指向的地址信息存储在所述预设存储空间之后是否对所述读命令所指向的地址信息执行过写命令，若是，则将该读命令指向所述写命令指向的地址信息，以对其对应的存储单元执行读操作。
本发明还提供一种存储器装置，其包括：命令接收单元，用于接收读命令或写命令；存储单元，与所述读命令或写命令所指向的地址信息对应；执行单元，用于对所述存储单元执行读操作或写操作；预设存储空间，用于存储数据发生错误的存储单元对应的地址信息。
进一步，所述存储器装置还包括所述存储器装置还包括ECC编码解码单元，用于解码读操作中与待读出数据对应的第一ECC编码及形成写操作中与待写入数据对应的第二ECC编码。
进一步，所述存储器装置还包括比较单元，所述比较单元与所述命令接收单元及所述预设存储空间连接，用于将所述读命令或写命令所指向的地址信息与所述预设存储空间内的地址信息进行比较。
进一步，所述执行单元还与所述比较单元连接，用于根据所述比较单元输出的结果对所述读命令或者写命令指向的地址信息对应的存储单元执行读操作或者写操作，或停止对所述读命令或者写命令指向的地址信息对应的存储单元执行读操作或写操作。
进一步，所述存储器装置还包括判断单元，所述判断单元与所述命令接收单元及所述执行单元连接，用于判断将读命令所指向的地址信息存储在所述预设存储空间之后是否对所述读命令所指向的地址信息执行过写命令。
进一步，所述存储器装置还包括转换单元，用于在停止对所述读命令或者 写命令指向的地址信息对应的存储单元执行读操作或写操作后，将所述读命令或写命令指向的地址信息改变为另一地址信息。
进一步，所述存储器装置包括逻辑层及至少一存储层，所述命令接收单元及所述执行单元设置在所述逻辑层，所述存储单元设置在所述存储层，所述预设存储空间设置在所述存储层或所述逻辑层。
本发明的优点在于，在用户对存储器装置执行读写操作时将数据发生错误的存储单元对应的地址信息存储在预设存储空间中，以将有效的存储单元与失效的存储单元进行实时区分。即每进行一次读操作，都会将失效的存储单元的对应的地址信息存储在预设存储空间中，以在用户对所述存储器装置执行读操作或者写操作时，不对存储在预设存储空间中的地址信息进行读写操作，避免数据错误或者数据丢失，大大提高了存储器装置的可靠性及寿命。
附图说明
图1是本发明读写方法的第一具体实施方式的流程示意图；
图2是本发明读写方法的第二具体实施方式的流程示意图；
图3是本发明读写方法的第三具体实施方式的流程示意图；
图4是本发明存储器装置的第一具体实施方式的框架示意图；
图5是本发明存储器装置的第二具体实施方式的框架示意图；
图6是本发明存储器装置的第三具体实施方式的框架示意图；
图7是本发明存储器装置的第四具体实施方式的框架示意图；
图8是本发明存储器装置的第五具体实施方式的框架示意图；
图9是本发明存储器装置的第六具体实施方式的框架示意图。
具体实施方式
下面结合附图对本发明提供的读写方法及存储器装置的具体实施方式做详细说明。
一种常见的改善存储器装置可靠度的方法是在数据写入存储器装置之前事先将数据编码为错误修正码(Error Correction Code，ECC)，同时将数据和错误修正码储存于存储器装置中。当读出时，同时读取数据和错误修正码，解码错误修正码以还原可能发生错误的数据。
但是，发明人发现，错误修正码仅能够在数据被读出时修正数据，存储器中发生数据错误的存储单元依然存在。若在后续的数据存储过程中，该发生数据错误的存储单元对应的存储段再出现至少一个发生数据错误的存储单元，则该存储段会存在至少两个数据错误的存储单元。而错误修正码将无法对该错误进行修正，导致该存储段不能使用，甚至会导致存储器装置不能使用，从而影响存储器装置的可靠性及寿命。
发明人研究发现，在用户使用存储器装置时，若是能够实时地将发生数据错误的存储单元区分出来，则可为后续的读写操作提供执行的依据，进而能够 大大提高存储器装置的可靠性。因此，本发明提供一种读写方法，其能够实时地将发生数据错误的存储单元区分出来。
在本发明读写方法的第一具体实施方式中，在执行读操作时，将待读出数据发生错误的存储单元对应的地址信息存储在预设存储空间中，以将待读出数据发生错误的存储单元与待读出数据未发生错误的存储单元区分。具体地说，请参阅图1，其为本发明读写方法的第一具体实施方式的流程示意图，所述读写方法包括如下步骤：
步骤S10，向存储器装置施加读命令，所述读命令指向地址信息。例如，所述读命令指向的地址信息为A0。
步骤S11，从所述读命令所指向的地址信息对应的存储单元中读取待读出数据。例如，从所述地址信息A0对应的存储单元中读取待读出数据。
步骤S12，判断所述待读出数据是否发生错误。
若所述待读出数据发生错误，说明该存储单元失效，则将所述读命令所指向的地址信息存储在预设存储空间10中。
例如，若从读命令所指向的地址信息A0对应的存储单元中读取的待读出数据发生错误，则将所述读命令所指向的地址信息A0存储在预设存储空间10中；若从读命令所指向的地址信息A4对应的存储单元中读取的待读出数据发生错误，则将所述读命令所指向的地址信息A4存储在预设存储空间10中。
所述预设存储空间10可为静态随机存储器(SRAM)、动态随机存储器(DRAM)、磁存储器(MRAM)、寄存器、锁存器或触发器等本领域技术人员熟知的具备存储功能的结构。若所述待读出数据没有发生错误，说明该存储单元有效，则不将所述读命令所指向的地址信息存储在所述预设存储空间10中。
例如，若从读命令所指向的地址信息A1对应的存储单元中读取的待读出数据没有发生错误，则不将所述读命令所指向的地址信息A1存储在预设存储空间10中；若从读命令所指向的地址信息A2对应的存储单元中读取的待读出数据没有发生错误，则不将所述读命令所指向的地址信息A2存储在预设存储空间10中。
进一步，本发明还提供一种判断所述待读出数据是否发生错误的方法。具体地说，在从所述读命令所指向的地址信息对应的存储单元中读取待读出数据的步骤还包括：从所述读命令所指向的地址信息对应的存储单元中读取与所述待读出数据对应的第一ECC编码。例如，从所述读命令所指向的地址信息对应的存储单元中读取的数据的位数为64b+8b，其中64b为所述待读出数据位数，8b为所述第一ECC编码的位数。根据相应的算法，对所述第一ECC编码进行解码，可还原可能发生错误的数据，所述算法为现有技术，不再赘述。因此，可依据对所述第一ECC编码进行解码判断所述待读出数据是否发生错误。
本发明列举一种依据对所述第一ECC编码进行解码判断所述待读出数据 是否发生错误的方法：将待读出数据重新编码，形成一个新的ECC编码，将所述新的ECC编码与所述第一ECC编码进行每位异或比对，若每位均一致，说明所述待读出数据没有发生错误，所述存储单元有效，则不将所述存储单元对应的地址信息存储在预设存储空间10中；若所述新的ECC编码与所述第一ECC编码存在不一致的情况，说明待读出数据发生错误，所述存储单元失效，则将所述存储单元对应的地址信息存储在预设存储空间10中。
其中，若所述待读出数据没有发生错误，则将所述待读出数据作为所述存储器装置的输出数据，若所述待读出数据发生错误，则可利用所述第一ECC编码进行还原数据，并将还原的数据作为所述存储器装置的输出数据。
本发明读写方法利用预设存储空间10将数据发生错误的存储单元对应的地址信息与数据没有发生错误的存储单元对应的地址信息区分，以在后续读写操作中，可根据读命令或者写命令所指向的地址信息是否位于预设存储空间10中而确定是否对所述地址信息执行读操作或者写操作，避免数据错误或者数据丢失，大大提高了存储器装置的可靠性及延长了存储器装置的寿命。
本发明读写方法还提供第二具体实施方式。在所述对存储器装置施加读命令之后，在所述从所述读命令所指向的地址信息对应的存储单元中读取待读出的数据之前，还包括比较步骤。具体地说，请参阅图2，其为本发明读写方法的第二具体实施方式的流程示意图。
步骤S20，向存储器装置施加读命令，所述读命令指向地址信息。
步骤S21，将所述读命令所指向的地址信息与存储在所述预设存储空间20内的地址信息进行比较。即判断所述读命令所指向的地址信息与存储在所述预设存储空间20内的地址信息是否相同。
若所述读命令所指向的地址信息与存储在所述预设存储空间20内的地址信息不相同，说明所述读命令所指向的地址信息并未存储在所述预设存储空间20中，则所述读命令所指向的地址信息对应的存储单元为有效存储单元，对所述读命令所指向的地址信息对应的存储单元执行读操作，即执行步骤S22。
例如，所述读命令所指向的地址信息为A1，将所述读命令所指向的地址信息为A1与预设存储空间20内存储的地址信息进行比较，若所述读命令所指向的地址信息为A1与存储在预设存储空间20中的任何地址信息均不相同，说明所述读命令所指向的地址信息A1并未存储在所述预设存储空间20中，则对所述读命令所指向的地址信息A1对应的存储单元执行读操作，即执行步骤S22，则在步骤S22中，所述读命令所指向的地址信息为A1。
若所述读命令所指向的地址信息与存储在所述预设存储空间20内的地址信息相同，说明所述读命令所指向的地址信息存储在所述预设存储空间20中，则所述读命令所指向的地址信息对应的存储单元为失效存储单元。则进行如下步骤：判断在当前读操作之前的操作中，将所述读命令所指向的地址信息存储 在所述预设存储空间20之后是否对所述读命令所指向的地址信息执行过写命令。若是，则将该读命令指向所述写命令指向的地址信息，即将所述写命令所指向的地址信息作为所述读命令所指向的新的地址信息，并对新的地址信息执行步骤S22。若否，则存在两种处理方式，一种处理方式如本具体实施方式中附图2所示，停止读操作；另一种处理方式是继续进行读操作，并将利用所述第一ECC编码还原的数据作为所述存储器装置的输出数据。
例如，所述读命令所指向的地址信息A4与存储在所述预设存储空间20内的地址信息相同，即所述读命令所指向的地址信息A4存储在预设存储空间20中，判断在当前读操作之前的操作中，将所述读命令所指向的地址信息A4存储在所述预设存储空间20之后是否对所述读命令所指向的地址信息A4执行过写命令。若是，且所述写命令指向另一地址信息A5，则将该读命令指向所述写命令指向的地址信息A5，以对其对应的存储单元执行读操作，即执行步骤S22，步骤S22中的所述读命令所指向的地址信息为地址信息A5。其中写命令的具体实现请参见第三具体实施方式。若否，则停止读操作。
步骤S22，从所述读命令所指向的地址信息对应的存储单元中读取待读出数据。例如，从所述读命令所指向的地址信息A1对应的存储单元中读取待读出数据。该步骤与第一具体实施方式中的步骤S11相同。
步骤S23，判断所述待读出数据是否发生错误。该步骤与第一具体实施方式中的步骤S12相同。若所述待读出数据发生错误，说明该存储单元失效，则将所述读命令所指向的地址信息存储在预设存储空间20中，若所述待读出数据未发生错误，说明该存储单元有效，则不将所述读命令所指向的地址信息存储在所述预设存储空间20中。
步骤S24，输出数据。
在所述第二具体实施方式中，在对所述存储器装置施加读命令后，将所述读命令所指向的地址信息与存储在所述预设存储空间20内的地址信息进行比较，以判断所述读命令所指向的地址信息是否位于预设存储空间20中，以可选择性地对所述读命令所指向的地址信息执行读命令，从而可提高存储器装置的可靠性。另外，在读出待读出数据后，还可根据所述待读出数据是否发生错误而选择是否将该存储单元的地址信息存储在预设存储空间20中，以为后续的读写操作提供判断依据。
本发明读写方法还提供第三具体实施方式。该第三具体实施方式为对存储器装置的写操作。具体地说，请参阅图3，其为本发明读写方法的第三具体实施方式的流程示意图。
步骤S30，对所述存储器装置施加写命令，所述写命令指向地址信息。例如，对所述存储器装置施加写命令，所述写命令指向地址信息A0。
步骤S31，将所述写命令所指向的地址信息与存储在所述预设存储空间30 内的地址信息进行比较，即判断所述写命令所指向的地址信息是否存储在预设存储空间30内。
若所述写命令所指向的地址信息与存储在所述预设存储空间30内的地址信息不相同，即所述写命令所指向的地址信息并未存储在所述预设存储空间30中，则对所述写命令所指向的地址信息对应的存储单元执行写操作，若所述写命令所指向的地址信息与存储在所述预设存储空间30内的地址信息相同，即所述写命令所指向的地址信息存储在所述预设存储空间30中，则停止对所述写命令所指向的地址信息对应的存储单元执行写操作。
例如，所述写命令所指向的地址信息为地址信息A1，将所述地址信息A1与存储在所述预设存储空间30内的地址信息进行比较。所述地址信息A1与存储在预设存储空间30中的任何地址信息均不相同，说明所述写命令所指向的地址信息A1并未存储在所述预设存储空间30中，则对所述写命令所指向的地址信息A1对应的存储单元执行写操作。
再例如，所述写命令所指向的地址信息为地址信息A4，将所述地址信息A4与存储在所述预设存储空间30内的地址信息进行比较。所述地址信息A4与存储在预设存储空间30中的一个地址信息相同，说明所述写命令所指向的地址信息A4存储在所述预设存储空间30中，则停止对所述写命令所指向的地址信息A4对应的存储单元执行写操作。
进一步，在本第三具体实施方式中，在停止对所述写命令所指向的地址信息对应的存储单元执行写操作的步骤之后还包括如下步骤：将所述写命令所指向的地址信息改变为另一地址信息。在该步骤之后，还可将所述另一地址信息与存储在所述预设存储空间30内的地址信息进行比较。该比较方法与步骤S31相同。若所述另一地址信息与存储在所述预设存储空间30内的地址信息相同，则停止对所述另一地址信息对应的存储单元执行写操作，若所述另一地址信息与存储在所述预设存储空间30内的地址信息不相同，则对所述另一地址信息对应的存储单元执行写操作。
例如，在停止对所述写命令所指向的地址信息A0对应的存储单元执行写操作后，将所述写命令所指向的地址信息A0改变为另一地址信息A1，即在该步骤之后所述写命令指向地址信息A1。进一步将所述写命令所指向的地址信息A1与存储在所述预设存储空间30内的地址信息进行比较，即判断所述地址信息A1是否存储在预设存储空间30内。例如，在本具体实施方式中，所述地址信息A1与存储在预设存储空间30中的任何地址信息均不相同，即所述地址信息A1并未存储在预设存储空间30中，则对所述地址信息A1对应的存储单元执行写操作。例如，在其他具体实施方式中，所述地址信息A1与存储在所述预设存储空间30中的某一地址信息相同，即所述地址信息A1存储在所述预设存储空间30中，则停止对所述地址信息A1对应的存储单元执行写操作，并 改变所述写命令的地址信息为A2，并将所述地址信息A2与存储在所述预设存储空间30内的地址信息进行比较，即判断所述地址信息A2是否存储在预设存储空间30内，以此类推，直至所述写命令指向的地址信息与存储在预设存储空间30中的地址信息均不相同时停止。
进一步，在本第三具体实施方式中，所述读写方法还包括如下步骤：形成与所述写操作中待写入数据对应的第二ECC编码，并将其与所述待写入数据一并写入所述写命令所指向的地址信息对应的存储单元中。当读出该存储单元中的数据时，同时读取数据和第二ECC编码，解码所述第二ECC编码以还原可能发生错误的数据。
在本第三具体实施方式中，本发明读写方法在对存储器装置施加写命令之后将所述写命令所指向的地址与存储在所述预设存储空间30内的地址信息进行比较，以作为是否对存储单元执行写操作的依据，进而可避免对失效的存储单元执行写操作，从而提高存储器装置的可靠性，并延长存储器装置的寿命。
本发明还提供一种能够实现上述读写方法的存储器装置。所述存储器装置包括但不限于DRAM、SRAM等易失性存储器，以及NAND、NOR、FeRAM、RRAM、MRAM、PCRAM等非易失存储器。
请参阅图4，其为本发明存储器装置的第一具体实施方式的框架示意图。所述存储器装置包括命令接收单元40、存储单元41、预设存储空间42及执行单元43。
所述命令接收单元40用于接收施加在存储器装置的读命令、写命令或者读/写命令所指向的地址信息。
所述存储单元41与所述读命令或写命令对应的地址信息对应，并用于存储数据。在本发明中，所述存储单元41可为存储基本单元(cell)、存储段(segment)、存储页(pages)、存储块(blocks)等本领域技术人员熟知的存储单位，本发明对此不进行限制。
所述预设存储空间42用于存储数据发生错误的存储单元对应的地址信息。所述预设存储空间42可为静态随机存储器(SRAM)、动态随机存储器(DRAM)、磁存储器(MRAM)、寄存器、锁存器或触发器等本领域技术人员熟知的具备存储功能的结构。
所述执行单元43用于控制对所述存储单元41执行读操作或写操作。所述执行单元43还与所述预设存储空间42连接，用于根据所述预设存储空间42内存储的地址信息对读命令或者写命令所指向的地址信息对应的存储单元执行读操作或者写操作，或停止对读命令或者写命令所指向的地址信息对应的存储单元执行读操作或写操作。
具体地说，若所述读命令或者写命令所指向的地址信息与预设存储空间42中存储的任一地址信息均不相同，则所述执行单元43对所述地址信息对应的 存储单元执行读操作或写操作，若所述读命令或写命令所指向的地址信息与预设存储空间42中存储的某一地址信息相同，则所述执行单元43停止对所述地址信息对应的存储单元执行读操作或写操作。
需要说明的是，执行单元43也可直接与命令接收单元40直接连接，本发明对此不做限定，本领域内技术人员可根据需求自行选择连接方式。
进一步，本发明存储器装置还提供一第二具体实施方式。请参阅图5，其为本发明存储器装置的第二具体实施方式的框架示意图，所述第二具体实施方式相较于第一具体实施方式的区别在于，所述存储器装置还包括ECC编码解码单元44。
所述ECC编码解码单元44与执行单元43、存储单元41及预设存储空间42连接。
所述ECC编码解码单元44用于解码读操作中与待读出数据对应的第一ECC编码，以还原有可能发生错误的数据，并可根据所述ECC编码解码单元44是否对数据进行还原来判断是否需要将所述地址信息存储在所述预设存储空间42中。所述ECC编码解码单元44还用于形成写操作中与待写入数据对应的第二ECC编码。
具体地说，在本具体实施方式中，所述命令接收单元接收写命令，在对写命令所指向的地址信息对应的存储单元执行写操作时，所述ECC编码解码单元44形成与写操作中待写入数据对应的ECC编码，并同时存储在所述写命令所指向的地址信息对应的存储单元41中。在该写操作完成后，在后续对该地址信息对应的存储单元执行读操作时，所述ECC编码解码单元44解码所述ECC编码。其中，可根据所述ECC编码解码单元44的解码来判断所述读操作读取的待读出数据是否发生错误，进而判断是否需要将所述地址信息存储在所述预设存储空间42中。
进一步，在本具体实施方式中，可根据所述ECC编码解码单元44是否对数据进行还原来判断是否需要将所述地址信息存储在所述预设存储空间42中。具体地说，若所述ECC编码解码单元44解码所述ECC编码，并对数据进行还原，说明所述读操作读取的待读出数据发生错误，则将该存储单元的地址信息存储在预设存储空间42中，若所述ECC编码解码单元44解码所述ECC编码，但未对数据进行还原，说明所述读操作读取的待读出数据未发生错误，则不将所述地址信息存储在预设存储空间42。
在本发明其他具体实施方式中，所述ECC编码解码单元44解码所述ECC编码，虽然未对数据进行还原，但根据所述ECC编码解码单元44的解码可判断出所述读操作读取的待读出数据发生了错误，则将该存储单元的地址信息存储在预设存储空间42中。
进一步，在所述存储器装置的第二具体实施方式中，所述存储器装置还包 括转换单元45。所述转换单元45可与所述执行单元43连接。在停止对所述地址信息对应的存储单元执行读操作或写操作后，所述转换单元45将所述读命令或写命令所指向的所述地址信息改变为另一地址信息。所述执行单元43根据所述标记单元的标记信息再对另一地址信息进行读操作或者写操作。
在第二具体实施方式中，所述执行单元43不仅与ECC编码解码单元44连接，还与存储单元41连接，而在本发明第三具体实施方式中，请参阅图6，其为所述存储器装置的第三具体实施方式的框架示意图，所述执行单元43与所述ECC编码解码单元44连接，所述ECC编码解码单元44再与存储单元41连接。可以理解的是，可根据不同的需求选择不同的连接关系。
本发明存储器装置还提供第四具体实施方式。请参阅图7，其为所述存储器装置的第四具体实施方式的框架示意图，相较于存储器装置的第一具体实施方式，所述存储器装置包括所述存储器装置还包括比较单元46。所述比较单元46与所述命令接收单元40及所述预设存储空间42连接，用于将所述读命令或写命令所指向的地址信息与所述预设存储空间42内的地址信息进行比较。
所述执行单元43还与所述比较单元46连接，用于根据所述比较单元46输出的结果对所述读命令或者写命令指向的地址信息对应的存储单元执行读操作或者写操作，或停止对所述读命令或者写命令指向的地址信息对应的存储单元执行读操作或写操作。
例如，所述比较单元46将所述读命令或写命令所指向的地址信息与所述预设存储空间42内的地址信息进行比较，若所述读命令或写命令所指向的地址信息与所述预设存储空间42内的任一地址信息均不相同，则所述比较单元46输出能够标识不相同的信号至所述执行单元43，所述执行单元43根据该信号对所述读命令或者写命令指向的地址信息对应的存储单元执行读操作或者写操作；若所述读命令或写命令所指向的地址信息与所述预设存储空间42内的某一地址信息相同，则所述比较单元46输出能够标识相同的信号至所述执行单元43，所述执行单元43根据该信号停止对所述读命令或者写命令指向的地址信息对应的存储单元执行读操作或者写操作。
需要说明的是，虽然附图中给出了具体连接关系的实施例，但本发明对此具体连接方式不做特殊限定，可以理解的是，本领域技术人员可根据不同的需求选择不同的连接关系。
进一步，在所述第四具体实施方式中，所述存储器装置还包括判断单元47，所述判断单元47与所述命令接收单元40及所述执行单元43连接，用于判断将读命令所指向的地址信息存储在所述预设存储空间42之后是否对所述读命令所指向的地址信息执行过写命令。所述执行单元43能够根据所述判断单元47的输出结果对对应的存储单元执行写操作。
本发明存储器装置还提供第五具体实施方式。请参阅图8，其为所述存储 器装置的第五具体实施方式的框架示意图，相较于存储器装置的第二具体实施方式，所述存储器装置包括逻辑层100及若干存储层200(图中仅示出一个存储层情形)，所述存储层200可为DRAM芯片，所述逻辑层100可以为控制芯片或中介层等具备逻辑电路的层。若干所述存储层200可以垂直堆叠于所述逻辑层100之上或之下，但本发明不限定于此，也可用其他封装方式将其集成在一起。
其中，所述命令接收单元40、所述预设存储空间42、所述执行单元43、所述ECC编码解码单元44及所述转换单元45均可设置在所述逻辑层100，而所述存储单元41设置在所述存储层200。在本发明另一具体实施方式中，所述预设存储空间42、所述ECC编码解码单元44也可设置在所述存储层200。
在本具体实施方式中，所述逻辑层100具有至少一第一数据传输端口48，所述存储层200具有至少一第二数据传输端口49。所述逻辑层100与所述存储层200之间通过所述第一数据传输端口48及所述第二数据传输端口49传输指令及数据。
进一步，在第五具体实施方式中，所述执行单元43不仅与ECC编码解码单元44连接，还通过所述第一数据传输端口48及所述第二数据传输端口49与存储单元41连接，而在本发明第六具体实施方式中，请参阅图9，其为所述存储器装置的第五具体实施方式的框架示意图，所述执行单元43与ECC编码解码单元44连接，所述ECC编码解码单元44再通过所述第一数据传输端口48及所述第二数据传输端口49与存储单元41连接。可以理解的是，可根据不同的需求选择不同的连接关系。
进一步，在本发明其他具体实施方式中，比较单元46及判断单元47也可设置在所述逻辑层100。
本发明存储器装置能够在用户使用的过程中利用预设存储空间将失效的存储单元的地址信息与有效的存储单元的地址信息区分开，进而可选择地对存储单元进行读写操作，大大提高了存储器装置的可靠性及寿命。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (16)

  1. 一种读写方法，其特征在于，对存储器装置施加读命令，所述读命令指向地址信息，从所述读命令所指向的地址信息对应的存储单元中读取待读出的数据，若所述待读出的数据发生错误，则将所述读命令所指向的地址信息存储在预设存储空间中。
  2. 根据权利要求1所述的读写方法，其特征在于，若所述待读出的数据没有发生错误，则不将所述读命令所指向的地址信息存储在所述预设存储空间中。
  3. 根据权利要求1所述的读写方法，其特征在于，从所述读命令所指向的地址信息对应的存储单元中读取待读出的数据的步骤还包括：从所述读命令所指向的地址信息对应的存储单元中读取与所述待读出的数据对应的第一ECC编码；
    判断所述待读出的数据是否发生错误的方法包括：对所述第一ECC编码进行解码，以判断所述待读出的数据是否发生错误。
  4. 根据权利要求1所述的读写方法，其特征在于，对所述存储器装置施加写命令，并将所述写命令所指向的地址信息与存储在所述预设存储空间内的地址信息进行比较，若所述写命令所指向的地址信息与存储在所述预设存储空间内的地址信息不相同，则对所述写命令所指向的地址信息对应的存储单元执行写操作，若所述写命令所指向的地址信息与存储在所述预设存储空间内的地址信息相同，则停止对所述写命令所指向的地址信息对应的存储单元执行写操作。
  5. 根据权利要求4所述的读写方法，其特征在于，在停止对所述写命令所指向的地址信息对应的存储单元执行写操作的步骤之后还包括如下步骤：
    将所述写命令所指向的地址信息改变为另一地址信息。
  6. 根据权利要求5所述的读写方法，其特征在于，将所述写命令所指向的地址信息改变为另一地址信息的步骤之后还包括如下步骤：将所述另一地址信息与存储在所述预设存储空间内的地址信息进行比较，若所述另一地址信息与存储在所述预设存储空间内的地址信息相同，则停止对所述另一地址信息对应的存储单元执行写操作，若所述另一地址信息与存储在所述预设存储空间内的地址信息不相同，则对所述另一地址信息对应的存储单元执行写操作。
  7. 根据权利要求4所述的读写方法，其特征在于，对所述写命令所指向的地址信息对应的存储单元执行写操作的步骤进一步包括：
    形成与所述写操作中待写入的数据对应的第二ECC编码，并将其与所述待写入的数据一并写入所述写命令所指向的地址信息对应的存储单元中。
  8. 根据权利要求1所述的读写方法，其特征在于，在所述对存储器装置施加读命令之后，在所述从所述读命令所指向的地址信息对应的存储单元中读 取待读出的数据之前，还包括：将所述读命令所指向的地址信息与存储在所述预设存储空间内的地址信息进行比较，若所述读命令所指向的地址信息与存储在所述预设存储空间内的地址信息不相同，则对所述读命令所指向的地址信息对应的存储单元执行读操作。
  9. 根据权利要求8所述的读写方法，其特征在于，若所述读命令所指向的地址信息与存储在所述预设存储空间内的地址信息相同，则判断将所述读命令所指向的地址信息存储在所述预设存储空间之后是否对所述读命令所指向的地址信息执行过写命令，若是，则将该读命令指向所述写命令指向的地址信息，以对其对应的存储单元执行读操作。
  10. 一种存储器装置，其特征在于，包括：
    命令接收单元，用于接收读命令或写命令；
    存储单元，与所述读命令或写命令所指向的地址信息对应；
    执行单元，用于对所述存储单元执行读操作或写操作；
    预设存储空间，用于存储数据发生错误的存储单元对应的地址信息。
  11. 根据权利要求10所述的存储器装置，其特征在于，所述存储器装置还包括所述存储器装置还包括ECC编码解码单元，用于解码读操作中与待读出数据对应的第一ECC编码及形成写操作中与待写入数据对应的第二ECC编码。
  12. 根据权利要求10所述的存储器装置，其特征在于，所述存储器装置还包括比较单元，所述比较单元与所述命令接收单元及所述预设存储空间连接，用于将所述读命令或写命令所指向的地址信息与所述预设存储空间内的地址信息进行比较。
  13. 根据权利要求12所述的存储器装置，其特征在于，所述执行单元还与所述比较单元连接，用于根据所述比较单元输出的结果对所述读命令或者写命令指向的地址信息对应的存储单元执行读操作或者写操作，或停止对所述读命令或者写命令指向的地址信息对应的存储单元执行读操作或写操作。
  14. 根据权利要求10所述的存储器装置，其特征在于，所述存储器装置还包括判断单元，所述判断单元与所述命令接收单元及所述执行单元连接，用于判断将读命令所指向的地址信息存储在所述预设存储空间之后是否对所述读命令所指向的地址信息执行过写命令。
  15. 根据权利要求10所述的存储器装置，其特征在于，所述存储器装置还包括转换单元，用于在停止对所述读命令或者写命令指向的地址信息对应的存储单元执行读操作或写操作后，将所述读命令或写命令指向的地址信息改变为另一地址信息。
  16. 根据权利要求10所述的存储器装置，其特征在于，所述存储器装置包括逻辑层及至少一存储层，所述命令接收单元及所述执行单元设置在所述逻辑 层，所述存储单元设置在所述存储层，所述预设存储空间设置在所述存储层或者所述逻辑层。
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