WO2021189860A1 - 叠层光伏器件及生产方法 - Google Patents

叠层光伏器件及生产方法 Download PDF

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WO2021189860A1
WO2021189860A1 PCT/CN2020/126078 CN2020126078W WO2021189860A1 WO 2021189860 A1 WO2021189860 A1 WO 2021189860A1 CN 2020126078 W CN2020126078 W CN 2020126078W WO 2021189860 A1 WO2021189860 A1 WO 2021189860A1
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layer
crystalline silicon
silicon layer
photovoltaic device
transition
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PCT/CN2020/126078
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English (en)
French (fr)
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吴兆
徐琛
李子峰
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隆基绿能科技股份有限公司
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Priority to US17/912,869 priority Critical patent/US20230144354A1/en
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Priority to EP20927947.0A priority patent/EP4106018A4/en
Priority to AU2020437211A priority patent/AU2020437211B2/en
Publication of WO2021189860A1 publication Critical patent/WO2021189860A1/zh

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    • Y02E10/544—Solar cells from Group III-V materials
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Definitions

  • the invention relates to the field of photovoltaic technology, in particular to a laminated photovoltaic device and a production method.
  • Laminated photovoltaic devices can divide sunlight into multiple bands. From the front to the back, solar cells with gradually reduced band gaps are used to absorb sunlight of different energy in order to broaden the spectral response bands to sunlight and reduce energy loss. Therefore, stacked photovoltaic devices have broad application prospects.
  • the laminated photovoltaic device with crystalline silicon cell as the lower cell unit has a larger mass production space.
  • the tunnel junction has strong transmission and recombination capabilities, and the thickness required to achieve a higher recombination rate is thin. Therefore, a tunnel junction is usually used to connect individual battery cells in series in stacked photovoltaic devices.
  • the tunnel junction tunneling efficiency of the stacked photovoltaic device in which the lower battery unit is a crystalline silicon battery is low, and the overall series resistance of the device is relatively high.
  • the invention provides a laminated photovoltaic device and a production method, which aims to solve the problems of low tunnel junction tunneling efficiency and high overall series resistance of the laminated photovoltaic device whose lower battery unit is a crystalline silicon battery.
  • a stacked photovoltaic device comprising: an upper battery cell and a lower battery cell, and a tunnel located between the upper battery cell and the lower battery cell Junction;
  • the lower battery cell is a crystalline silicon battery;
  • the tunnel junction includes: an upper crystalline silicon layer, a lower crystalline silicon layer, and an intermediate layer located between the upper crystalline silicon layer and the lower crystalline silicon layer;
  • the upper crystalline silicon layer, the lower crystalline silicon layer, and the intermediate layer are in direct contact, and the doping types of the upper crystalline silicon layer and the lower crystalline silicon layer are opposite; the upper crystalline silicon layer is in contact with the The doping concentration at the interface of the intermediate layer and the doping concentration at the interface of the lower crystalline silicon layer and the intermediate layer are both greater than or equal to 10 18 cm -3 ;
  • the intermediate layer includes: at least one dielectric layer; the band gap width of the dielectric layer is greater than or equal to 3 eV.
  • the dielectric strength of the dielectric layer is greater than or equal to 3MV/cm.
  • the material of the dielectric layer is selected from: silicon oxide, silicon nitride, silicon oxynitride, silicon halide, silicon oxyfluoride, silicon oxycarbide, alkali metal Oxide, alkali metal nitride, alkali metal oxynitride, alkali metal halide, alkali metal oxyfluoride, transition metal oxide, transition metal nitride, transition metal oxynitride, transition metal Halides, transition metal oxyfluorides, group III metal oxides, group III metal nitrides, group III metal oxynitrides, group III metal halides, group III metal oxyfluorides, group IV At least one of metal nitride, group IV metal oxynitride, group IV metal halide, or group IV metal oxyfluoride.
  • the material of the dielectric layer is selected from at least one of silicon oxide, silicon nitride, silicon fluoride, silicon oxyfluoride, silicon oxycarbide, aluminum oxide, aluminum fluoride, or aluminum oxynitride.
  • the thickness of the upper crystalline silicon layer and the lower crystalline silicon layer are both 2-100 nm;
  • the thickness of the intermediate layer is 0.1-5 nm.
  • the intermediate layer further includes: a first transition layer located between the dielectric layer and the upper crystalline silicon layer and in direct contact with the upper crystalline silicon layer, and/or, located in the intermediate layer A second transition layer between the electrical layer and the lower crystalline silicon layer and in direct contact with the lower crystalline silicon layer;
  • the material of the first transition layer is selected from at least one product of the interface reaction between the dielectric layer and the upper crystalline silicon layer;
  • the material of the second transition layer is selected from at least one product of the interface reaction between the dielectric layer and the lower crystalline silicon layer.
  • the upper crystalline silicon layer has a doping concentration gradient
  • the lower crystalline silicon layer has a doping concentration gradient
  • the light-facing surface of the lower battery unit is provided with a light trapping structure; the backlight surface of the tunnel junction is adapted to the shape of the light-facing surface of the lower battery unit.
  • a production method of a stacked photovoltaic device including:
  • the lower battery cell being a crystalline silicon battery
  • a tunnel junction is prepared; wherein, the tunnel junction includes: an upper crystalline silicon layer, a lower crystalline silicon layer, and an intermediate layer located between the upper crystalline silicon layer and the lower crystalline silicon layer; the upper crystalline silicon layer, the The lower crystalline silicon layer and the intermediate layer are in direct contact, and the doping types of the upper crystalline silicon layer and the lower crystalline silicon layer are opposite; the doping of the upper crystalline silicon layer at the interface with the intermediate layer
  • the doping concentration of the lower crystalline silicon layer at the interface with the intermediate layer is greater than or equal to 10 18 cm -3 ; the intermediate layer includes: at least one dielectric layer; Band gap width is greater than or equal to 3eV;
  • the step of preparing the lower crystalline silicon layer includes one of the following processes:
  • the step of preparing the intermediate layer includes one of the following processes:
  • the step of preparing the upper crystalline silicon layer includes one of the following processes:
  • the intermediate layer further includes: a first transition layer located between the dielectric layer and the upper crystalline silicon layer and in direct contact with the upper crystalline silicon layer, and/or, located in the intermediate layer
  • the second transition layer between the electrical layer and the lower crystalline silicon layer and in direct contact with the lower crystalline silicon layer includes:
  • the first transition layer is formed between the dielectric layer and the upper crystalline silicon layer; the material of the first transition layer is selected from the interface reaction between the dielectric layer and the upper crystalline silicon layer At least one of the products;
  • the second transition layer is formed between the dielectric layer and the lower crystalline silicon layer; the material of the second transition layer is selected from the interface reaction between the dielectric layer and the lower crystalline silicon layer At least one of the products.
  • an intermediate layer including a dielectric layer is introduced between the upper crystalline silicon layer and the lower crystalline silicon layer.
  • the doping concentration of the upper crystalline silicon layer at the interface with the intermediate layer and the doping concentration of the lower crystalline silicon layer at the interface with the intermediate layer are greater than or equal to 10 18 cm -3 , the band gap width of the dielectric layer Greater than or equal to 3eV, is conducive to achieving energy level degeneration on both sides, which can effectively improve the tunneling efficiency of the tunnel junction, increase the peak tunnel current, and reduce the overall series resistance of the device.
  • Fig. 1 shows a schematic structural diagram of a first type of stacked photovoltaic device in an embodiment of the present invention
  • Figure 2 shows a schematic structural diagram of a second type of stacked photovoltaic device in an embodiment of the present invention
  • FIG. 3 shows a schematic structural diagram of a third type of laminated photovoltaic device in an embodiment of the present invention
  • Fig. 4 shows a schematic structural diagram of a fourth type of stacked photovoltaic device in an embodiment of the present invention
  • Fig. 5 shows a schematic structural diagram of a fifth type of stacked photovoltaic device in an embodiment of the present invention
  • Fig. 6 shows a schematic structural diagram of a sixth type of stacked photovoltaic device in an embodiment of the present invention.
  • the effective doping concentration on both sides of the junction interface expands the tunneling distance.
  • FIG. 1 shows a schematic structural diagram of the first type of stacked photovoltaic device in the embodiment of the present invention.
  • the laminated photovoltaic device includes: an upper battery cell 1 and a lower battery cell 2, and a tunnel junction 3 located between the upper battery cell 1 and the lower battery cell 2, and the tunnel junction 3 is used to connect the upper battery cell 1 and the lower battery in series.
  • Unit 2 to form a stacked photovoltaic device.
  • the upper battery cell 1 and the lower battery cell 2 have different band gaps, and the band gap of the upper battery cell 1 is larger than the band gap of the lower battery cell 2.
  • the lower battery cell is a crystalline silicon battery.
  • the number of upper battery cells, lower battery cells, and tunnel junctions included in the stacked photovoltaic device is not specifically limited.
  • 4 is the top electrode and 5 is the bottom electrode.
  • the tunnel junction 3 is light-transmissive and is used to pass through the upper battery cell to absorb the remaining wavelength band.
  • the light-transmitting wavelength band can be determined according to the wavelength band remaining after the upper-layer battery cell adjacent to it absorbs the wavelength band.
  • the light-transmitting light-transmitting waveband can be the waveband remaining after the upper-layer battery cell adjacent to it absorbs the waveband.
  • the tunnel junction 3 includes: an upper crystalline silicon layer 31, a lower crystalline silicon layer 32, and an intermediate layer 33 located between the upper crystalline silicon layer 31 and the lower crystalline silicon layer 32.
  • the upper crystalline silicon layer 31, the lower crystalline silicon layer 32, and the intermediate layer 33 are in direct contact.
  • the upper crystalline silicon layer 31 has a first doping type
  • the lower crystalline silicon layer 32 has a second doping type, and the first doping type is opposite to the second doping type.
  • the upper crystalline silicon layer 31 is of an n-type doping type
  • the lower crystalline silicon layer 32 is of a p-type doping type.
  • the upper crystalline silicon layer 31 is in contact with the upper battery cell 1
  • the lower crystalline silicon layer 32 is in contact with the lower battery cell 2.
  • the first doping type of the upper crystalline silicon layer 31 is the same as the doping type of the backlight surface of the upper battery unit 1.
  • the second doping type of the lower crystalline silicon layer 32 is the same as the doping type of the light-facing surface of the lower battery cell 2. For example, if the lower battery cell 2 uses a p-type silicon wafer, and if the light-surface diffusion of the lower battery cell 2 is n-type, the second doping type of the lower crystalline silicon layer 32 is n-type.
  • the intermediate layer includes at least one dielectric layer.
  • the number of dielectric layers is not specifically limited.
  • the doping concentration of the upper crystalline silicon layer 31 at the interface in contact with the intermediate layer 33 and the doping concentration of the lower crystalline silicon layer 32 at the interface in contact with the intermediate layer 33 are both greater than or equal to 10 18 cm -3 .
  • the doping concentration of the rest of the upper crystalline silicon layer 31 can be set according to actual needs.
  • the doping concentration of the rest of the lower crystalline silicon layer 32 can also be set according to actual needs.
  • the band gap width of the dielectric layer is greater than or equal to 3 eV, which is beneficial to prevent ineffective tunneling.
  • the doping concentration at the interface of the upper crystalline silicon layer 31 and the interface of the lower crystalline silicon layer 32 that are in contact with the interfaces on both sides of the intermediate layer 33 is higher.
  • the upper crystalline silicon layer 31 has a doping concentration gradient
  • the lower crystalline silicon layer 32 has a doping concentration gradient.
  • the doping concentration gradient of the upper crystalline silicon layer 31 may increase or decrease
  • the doping concentration gradient of the lower crystalline silicon layer 32 may also increase or decrease.
  • the doping concentration of the upper crystalline silicon layer 31 at the contact interface of the intermediate layer 33 is greater than or equal to 10 18 cm -3
  • the doping concentration of the remaining positions in the upper crystalline silicon layer 31 is set according to actual needs.
  • the doping concentration in the lower crystalline silicon layer 32 at the contact interface of the intermediate layer 33 is greater than or equal to 10 18 cm ⁇ 3 , and the doping concentration in the remaining positions in the lower crystalline silicon layer 32 can also be set according to actual needs.
  • the peak doping concentration of the upper crystalline silicon layer 31 may not necessarily be located on the surface thereof, and may be located in a region outside the surface of the upper crystalline silicon layer 31.
  • the peak doping concentration of the lower crystalline silicon layer 32 may not necessarily be located on the surface thereof, and may be located in a region outside the surface of the lower crystalline silicon layer 32.
  • the crystal structure of the upper crystalline silicon layer 31 and the lower crystalline silicon layer 32 may be single crystal or polycrystalline, so that there are many types of choices and the choices are more flexible.
  • the dielectric strength of the dielectric layer is greater than or equal to 3MV/cm, which is beneficial to suppress invalid tunneling, thereby effectively improving tunneling efficiency, reducing tunnel junction series resistance, and increasing peak tunneling current.
  • the material of the dielectric layer can be selected from: silicon oxide, silicon nitride, silicon oxynitride, silicon halide, silicon oxyfluoride, silicon oxycarbide, alkali metal oxide Compounds, alkali metal nitrides, alkali metal oxynitrides, alkali metal halides, alkali metal oxyfluorides, transition metal oxides, transition metal nitrides, transition metal oxynitrides, transition metal Halides, transition metal oxyfluorides, group III metal oxides, group III metal nitrides, group III metal oxynitrides, group III metal halides, group III metal oxyfluorides, group IV metals At least one of the nitride, the oxynitride of the group IV metal, the halide of the group IV metal, and the oxyfluoride of the group IV metal.
  • the dielectric layer of the above material has a relatively high band gap width, which is beneficial to suppress ineffective tunneling,
  • the material of the dielectric layer can also be selected from: silicon oxide (e.g., SiO x , e.g., SiO 2 ), silicon nitride (SiN x ), silicon fluoride (e.g., SiF 4 ), fluorine oxide At least one of silicon (SiOF), silicon oxycarbide (SiOC), aluminum oxide (eg, Al 2 O 3 ), aluminum fluoride (AlF x ), and aluminum oxynitride (AlON).
  • the conductive materials of the above-mentioned materials have relatively large dielectric strength and band gap width, which are beneficial to suppress ineffective tunneling, thereby effectively improving tunneling efficiency, reducing tunnel junction series resistance, and increasing peak tunneling current.
  • the intermediate layer 33 also includes: a first transition layer located between the dielectric layer and the upper crystalline silicon layer 31 and in direct contact with the upper crystalline silicon layer 31, and/ Or, a second transition layer located between the dielectric layer and the lower crystalline silicon layer 32 and in direct contact with the lower crystalline silicon layer 32.
  • the material of the first transition layer which is located between the dielectric layer and the upper crystalline silicon layer 31 and is in direct contact with the upper crystalline silicon layer 31 is selected from the interface reaction between the dielectric layer and the upper crystalline silicon layer 31 (doping and migration are not limited). Etc.) at least one of the products.
  • the material of the second transition layer that is located between the dielectric layer and the lower crystalline silicon layer 32 and is in direct contact with the lower crystalline silicon layer 32 is selected from at least one of the products of the interface reaction between the dielectric layer and the lower crystalline silicon layer 32 kind. Both the first transition layer and the second transition layer can play a good role in surface chemical passivation.
  • the first transition layer located between the dielectric layer and the upper crystalline silicon layer 31 and in direct contact with the upper crystalline silicon layer 31 can be reacted by the interface between the dielectric layer and the lower crystalline silicon layer 31 (without limitation of doping, migration, etc.) ) Generated, or, formed independently.
  • the second transition layer located between the dielectric layer and the lower crystalline silicon layer 32 and in direct contact with the lower crystalline silicon layer 32 can be reacted by the interface between the dielectric layer and the lower crystalline silicon layer 32 (without limitation of doping, migration, etc.) ) Generated or formed independently.
  • the thickness of the upper crystalline silicon layer 31 and the lower crystalline silicon layer 32 are both 2-100 nm, and further, the thickness of the upper crystalline silicon layer 31 and the lower crystalline silicon layer 32 are both 2-10 nm.
  • the thickness of the intermediate layer 33 is 0.1-5 nm, and further, the thickness of the intermediate layer 33 may be 0.5-1 nm.
  • the thickness of the tunnel junction thus formed is small, which is beneficial to reduce the tunneling distance and improve the tunneling efficiency. At the same time, the thickness of the tunnel junction is small, which will not cause more optical shielding to the lower battery cells.
  • the light-facing surface of the lower battery unit is provided with a light trapping structure
  • the light-facing surface of the lower battery unit is the surface of the lower battery unit in contact with the lower crystalline silicon layer or the surface in contact with the tunnel junction.
  • the backlight surface of the tunnel junction is adapted to the shape of the light-facing surface of the lower battery cell.
  • the backlight surface of the tunnel junction is the surface in contact with the light-facing surface of the lower battery cell.
  • the light trapping structure can be a nano-optical structure, a suede structure, or the like.
  • the nano optical structure is a regular nano light trapping structure.
  • the suede structure is pyramid, inverted pyramid and other structures.
  • the light-trapping structure is provided on the light-facing surface of the lower battery unit, and the backlight surface of the tunnel junction is adapted to the shape of the light-facing surface of the lower battery unit. Then, the backlight surface of the tunnel junction is also provided with a light-trapping structure to increase the optical path. At the same time, the structure and material of the tunnel junction are beneficial to obtain a tunnel junction with uniform thickness and uniform function on the light-trapping structure of the light-facing surface of the lower battery unit.
  • FIG. 2 shows a schematic structural diagram of a second type of stacked photovoltaic device in an embodiment of the present invention.
  • the light-facing surface of the lower battery cell 2 has a light-trapping structure
  • the backlight surface of the tunnel junction 3 is a light-trapping structure adapted to the shape of the light-facing surface of the lower battery cell 2.
  • the light-facing surface of the tunnel junction 3 is a light-trapping structure
  • the backlight surface of the upper battery unit 1 is a light-trapping structure adapted to the shape of the light-facing surface of the tunnel junction 3.
  • the light-facing surface of the upper battery unit 1 has a light-trapping structure.
  • the lower battery unit is a crystalline silicon battery, and the doping type of the substrate silicon material of the lower battery unit is not limited.
  • the bottom electrode can be an integral metal back field or a local grid line.
  • the light facing surface of the lower battery unit may be a planar structure or have a light trapping structure. It is understandable that the top of the light-facing surface of the lower battery cell cannot be covered with an insulating material or a dielectric material (such as a conventional passivation layer or an anti-reflection layer) to facilitate electrical contact with the tunnel junction.
  • the backlight surface of the lower battery unit can directly cover the electrodes.
  • any structure can be designed on the backlight surface of the lower battery unit, for example: passivation layer and open hole electrical export structure (PERC (Passivated Emitter and Rear Contact)), or further adopt comprehensive Or local heavy doping (PERT (Passivated Emitter and Rear Totally-diffused), PERL (Passivated Emitter and Rear Locally-diffused)), or can adopt oxide tunneling passivation layer and polycrystalline transmission layer structure (TOPCon (Tunnel Oxide) Passivated Contact)).
  • PERC Passivated Emitter and Rear Contact
  • PERT Passivated Emitter and Rear Totally-diffused
  • PERL Passivated Emitter and Rear Locally-diffused
  • TOPCon Tel Oxide
  • the lower battery cell can use homojunction or single-sided heterojunction technology, and the contact area with the lower crystalline silicon layer of the tunnel junction is crystalline, and the front or back pn junction process can be used.
  • the doping elements in the lower crystalline silicon layer of the lower battery cell facing the smooth surface may partially diffuse into the lower battery cell during the high temperature process. Since the lower crystalline silicon layer usually has a relatively low minority carrier life, the front pn junction process is adopted. A deeper pn junction depth is preferred, that is, the pn junction is set farther from the lower crystalline silicon layer, and the high-temperature process time is minimized to reduce the influence of doping element diffusion on the pn junction.
  • the band gap width of the upper battery cell is wider than the band gap width of the lower battery cell.
  • the specific type of the upper battery cell is not limited.
  • the band gap of the upper battery cell can be 1.5eV-2.3eV.
  • the band gap of the upper battery cell can be 1.7eV-1.8eV.
  • the upper battery unit can be: perovskite thin film solar cells, organic thin film solar cells, quantum dot thin film solar cells, amorphous silicon thin film solar cells, amorphous silicon carbide thin film solar cells, copper indium gallium selenium thin film solar cells, tellurium Cadmium thin film solar cells, gallium arsenide thin film solar cells, etc.
  • the upper battery cell may include one or more buffer layers or matching layers required to contact the upper crystalline silicon layer in the tunnel junction to reduce the resistance or recombination between the tunnel junction and the upper battery cell.
  • the buffer layer or matching layer plays the role of contacting the crystalline silicon layer on the tunnel junction, collecting and transporting the upper battery cell carriers, and at the same time, the layer can also play a role in energy band buffering, energy band matching, lattice matching, and contact reduction. The role of resistance, etc., to further reduce the series resistance of the overall device.
  • the top of the uppermost battery cell and the bottom of the lowermost battery cell may have electrodes. As shown in FIG. 1 or FIG. 2, the top electrode 4 is provided on the top of the uppermost battery cell.
  • the bottom of the lowermost battery cell has a bottom electrode 5.
  • the top of the uppermost battery cell may also have one or more anti-reflection films.
  • the bottom electrode of the lowermost battery cell can be an integral metal back field (single-sided battery) or a grid line (double-sided battery).
  • the upper and lower battery cells require electrical and optical adaptation.
  • the laminated photovoltaic device where the lower battery unit is a crystalline silicon battery
  • the lower battery unit is a crystalline silicon battery
  • an intermediate layer including a dielectric layer between the upper crystalline silicon layer and the lower crystalline silicon layer under the barrier effect of the dielectric layer, It can effectively alleviate the mutual diffusion of doped elements in the upper crystalline silicon layer and the lower crystalline silicon layer with opposite doping types, thereby forming a sudden doped interface structure at the interface, and is beneficial to increase the effective doping concentration on both sides, which can Effectively improve the tunneling efficiency, reduce the series resistance of the tunnel junction, and increase the peak tunnel current.
  • the doping concentration of the upper crystalline silicon layer at the interface with the intermediate layer and the doping concentration of the lower crystalline silicon layer at the interface with the intermediate layer are greater than or equal to 10 18 cm -3 , the band gap width of the dielectric layer Greater than or equal to 3eV, is conducive to achieving energy level degeneration on both sides, which can effectively improve the tunneling efficiency, reduce the tunnel junction series resistance, and increase the peak tunnel current.
  • the embodiment of the present invention also provides a method for producing a stacked photovoltaic device.
  • the method includes the following steps:
  • step S1 a lower battery cell is prepared, and the lower battery cell is a crystalline silicon battery.
  • Step S2 preparing a tunnel junction; wherein, the tunnel junction includes: an upper crystalline silicon layer, a lower crystalline silicon layer, and an intermediate layer located between the upper crystalline silicon layer and the lower crystalline silicon layer; the upper crystalline silicon layer Layer, the lower crystalline silicon layer, and the intermediate layer are in direct contact, and the upper crystalline silicon layer and the lower crystalline silicon layer have opposite doping types; the upper crystalline silicon layer is at the interface with the intermediate layer The doping concentration of the lower crystalline silicon layer at the interface with the intermediate layer is greater than or equal to 10 18 cm -3 ; the intermediate layer includes: at least one dielectric layer; The band gap width of the electrical layer is greater than or equal to 3 eV.
  • step S3 the upper battery cell is prepared.
  • the lower battery in the case that some layers of the lower battery unit cannot withstand high temperatures, the lower battery can be prepared after the tunnel junction or other parts of the laminated photovoltaic device have been prepared. The layer in the unit that cannot withstand high temperatures.
  • the step of preparing the lower crystalline silicon layer may include one of the following processes: deposition, doping, and growth.
  • the deposition process may include: depositing a lower crystalline silicon layer of amorphous or nanocrystalline silicon with a corresponding doping concentration on the light-facing surface of the lower battery unit by PVD, CVD, etc., and performing fast or slow annealing for crystallization.
  • the growth process may include: vapor phase growth methods such as CVD, PVD, and ALD, or epitaxial growth methods such as molecular beam epitaxy (MBE). After growth, fast or slow annealing can be used to further improve the performance of the layer. Or through thermal diffusion, particle injection, laser doping and other methods to further dope the light-facing surface of the lower battery cell.
  • the step of preparing the intermediate layer may include one of the following processes: deposition, water bath, coating, surface in-situ compounding, wet thermal oxygen, dry thermal oxygen, plasma oxidation, plasma enhanced assisted oxidation.
  • deposition processes such as PVD, CVD, and ALD can be used, or chemical processes such as water bath methods and coating methods can be used, or surface in-situ compounding processes such as oxidation and nitridation can be used.
  • silicon oxide can use wet thermal oxygen (HNO 3 ), O 3 , UV/O 3 , dry thermal oxygen, plasma oxidation, plasma enhanced assisted oxidation (PECVD-assisted) N 2 O-oxidized SiO x , CVD And other processes.
  • the intermediate layer 33 further includes: a first transition layer located between the dielectric layer and the upper crystalline silicon layer 31 and in direct contact with the upper crystalline silicon layer 31, and/or, located between the dielectric layer and the lower crystalline silicon layer 31 A second transition layer between the layers 32 and in direct contact with the lower crystalline silicon layer 32.
  • the first transition layer located between the dielectric layer and the upper crystalline silicon layer 31 and directly in contact with the upper crystalline silicon layer 31 may be formed by an interface reaction between the dielectric layer and the upper crystalline silicon layer 31, or independently.
  • the second transition layer located between the dielectric layer and the lower crystalline silicon layer 32 and directly in contact with the lower crystalline silicon layer 32 may be formed by an interface reaction between the dielectric layer and the lower crystalline silicon layer 32 or independently.
  • the ALD method For example, first use the ALD method to deposit 0.5nm silicon oxide, then deposit 1nm aluminum oxide, and then deposit 0.5nm silicon oxide.
  • the aluminum oxide may be a dielectric layer, and the silicon oxide located on both sides of the dielectric layer may be a first transition layer and a second transition layer formed independently.
  • the step of preparing the upper crystalline silicon layer includes one of the following processes: deposition and growth.
  • the deposition process includes depositing amorphous or nanocrystalline silicon thin films with corresponding doping concentrations by PVD, CVD and other methods and performing fast or slow annealing.
  • the growth process includes CVD, PVD, ALD and other vapor phase growth methods, or MBE and other epitaxial growth methods. After growth, fast or slow annealing can be used to further improve the performance of the layer.
  • FIG. 3 shows a schematic structural diagram of a third type of laminated photovoltaic device in an embodiment of the present invention.
  • the lower battery unit 2 uses n-type silicon wafers 21, and the backlight surface of the lower battery unit 2 uses amorphous silicon for passivation and deposits n-type amorphous silicon 22 for electron transmission.
  • the temperature tolerance of crystalline silicon is poor, so the deposition of amorphous silicon can be carried out after the tunnel junction or other parts of the laminated photovoltaic device have been prepared.
  • the light-facing surface of the lower battery cell 2 may have a pyramid suede structure.
  • the upper battery cell 1 uses a wide band gap perovskite as the absorption layer, and the band gap width of the absorption layer is 1.6-1.8 eV.
  • the absorption layer has a morphology that is bonded to the light-facing surface of the lower battery cell 2.
  • the intermediate layer shown in FIG. 3 includes a dielectric layer, that is, the SiO 2 dielectric layer 331.
  • the silicon wafer is cleaned and the upper and lower surfaces are textured.
  • the p-type layer is made to form a pn junction by diffusion or crystallization after deposition on the smooth surface, and the p-type layer is crystallized by thermal diffusion or deposition on the smooth surface.
  • a lower crystalline silicon layer is fabricated, and the lower crystalline silicon layer 32 is heavily doped with p++, and the doping concentration is 10 20 cm -3 .
  • the p-type layer and the lower crystalline silicon layer p++ layer 321 can be produced by a one-step diffusion or post-deposition crystallization method, and a transition p+ layer 23 is formed in the middle.
  • the thickness of the lower crystalline silicon layer p++ layer 321 is calculated from the doping concentration of 10 20 cm -3 , and the thickness of the layer is 5 nm.
  • a SiO 2 dielectric layer 331 is fabricated on the light-facing surface of the lower crystalline silicon layer p++ layer 321, with a thickness of 1 nm, which can be fabricated by surface oxidation (thermal oxidation, chemical oxidation) or ALD deposition.
  • the upper crystalline silicon layer 31 can be made by over-depositing amorphous silicon and then crystallization, or by growth methods such as CVD, PVD, etc.
  • the upper crystalline silicon layer 31 is doped
  • the impurity concentration is 10 20 cm -3 and the thickness is 5 nm.
  • the TiO 2 coating 11 is deposited on the smooth surface of the upper n++ layer 311 of the upper crystalline silicon layer, which can be produced by a chemical method or a vacuum deposition method.
  • the above layers can allow high-temperature processes.
  • Intrinsic amorphous silicon 24 and n-type amorphous silicon 22 are deposited on the backlight surface of the above structure.
  • the perovskite coating layer 12 and the hole transport layer 13 are deposited on the smooth surface of the above structure.
  • ITO14 is deposited on both sides of the above structure, and electrodes are deposited to complete the overall structure.
  • FIG. 4 shows a schematic structural diagram of a fourth type of stacked photovoltaic device in an embodiment of the present invention.
  • the lower battery cell 2 uses n-type silicon wafers 21, and the backlight surface of the lower battery cell 2 uses amorphous silicon for passivation and deposits n-type amorphous silicon 22 for electron transmission.
  • the temperature tolerance of crystalline silicon is poor, so the deposition of amorphous silicon can be carried out after the tunnel junction or other parts of the laminated photovoltaic device have been prepared.
  • the light-facing surface of the lower battery cell 2 may have a pyramid suede structure.
  • the upper cell unit 1 adopts the top solar cell and uses wide band gap amorphous silicon as the absorption layer, and the band gap width of the absorption layer is 1.7 eV.
  • the absorption layer has a morphology that is bonded to the light-facing surface of the lower battery cell 2.
  • the intermediate layer shown in FIG. 4 includes a dielectric layer, that is, the SiO 2 dielectric layer 331.
  • the silicon wafer is cleaned and the upper and lower surfaces are textured.
  • the p-type layer is made to form a pn junction by diffusion or crystallization after deposition on the smooth surface, and the p-type layer is crystallized by thermal diffusion or deposition on the smooth surface.
  • a lower crystalline silicon layer is fabricated, and the lower crystalline silicon layer 32 is a heavily doped p++ layer with a doping concentration of 10 20 cm -3 .
  • the p-type layer and the lower crystalline silicon layer p++ layer 321 can be produced by a one-step diffusion or post-deposition crystallization method, and a transition p+ layer 23 is formed in the middle.
  • the thickness of the lower crystalline silicon layer p++ layer 321 is calculated from the doping concentration of 10 20 cm -3 , and the thickness of the layer is 5 nm.
  • a SiO 2 dielectric layer 331 is fabricated on the light-facing surface of the lower crystalline silicon layer p++ layer 321, with a thickness of 1 nm, which can be fabricated by surface oxidation (thermal oxidation, chemical oxidation) or ALD deposition.
  • the n++ heavy doping is made on the smooth surface of the SiO 2 dielectric layer 331, that is, the upper crystalline silicon layer 31, which can be made by over-depositing amorphous silicon and then crystallization or CVD, PVD and other growth methods.
  • This layer is doped
  • the concentration is 10 20 cm -3 and the thickness is 5 nm.
  • Intrinsic amorphous silicon films are deposited on both sides of the above structure.
  • An n-type amorphous silicon film 22 is deposited on the backlight surface of the above structure.
  • a p-type amorphous silicon thin film 15 is deposited on the smooth surface of the above structure.
  • ITO14 and metal electrodes are deposited on both sides of the above structure to complete the device.
  • FIG. 5 shows a schematic structural diagram of a fifth type of stacked photovoltaic device in an embodiment of the present invention.
  • the lower battery cell 2 uses p-type silicon wafers 25
  • the backlight of the lower battery cell 2 uses PERx (PERC, PERT, PERL) passivation technology, and double-sided texturing , Can receive light on both sides.
  • the upper battery cell 1 uses a wide band gap perovskite as the absorption layer, and the band gap width of the absorption layer is 1.6-1.8 eV.
  • the absorption layer has a morphology that is bonded to the light-facing surface of the lower battery cell 2.
  • the intermediate layer shown in FIG. 5 includes a dielectric layer, that is, the SiO 2 dielectric layer 331.
  • the silicon wafer is cleaned and the upper and lower surfaces are textured.
  • the n-type layer is formed on the backlight surface by diffusion or crystallization after deposition to form a pn junction, and the n+ layer is made by thermal diffusion or crystallization after deposition on the light surface.
  • a PERx structure 27 is fabricated on the back of the above structure for back passivation.
  • the lower crystalline silicon layer 32 is formed by thermal diffusion or crystallization after deposition toward the smooth surface.
  • the lower crystalline silicon layer is a p++ layer 321 with a doping concentration of 10 19 cm -3 .
  • the thickness of the lower crystalline silicon layer p++ layer 321 is from doped When the impurity concentration reaches the order of 10 19 cm -3 , the thickness of the layer is 8 nm.
  • a SiO 2 dielectric layer 331 is formed on the p++ layer 321 of the lower crystalline silicon layer facing the smooth surface.
  • the thickness of this layer is 0.8 nm, which can be formed by surface oxidation (thermal oxidation, chemical oxidation) or ALD deposition.
  • the SiO 2 dielectric layer 331 is heavily doped with n++, that is, the upper crystalline silicon layer 31, which can be produced by over-depositing amorphous silicon and then crystallization or CVD, PVD and other growth methods.
  • the layer is from a doping concentration of 10 From 19 cm -3 to the order of magnitude, the thickness is 5nm.
  • the TiO 2 coating 11 is deposited on the smooth surface of the upper n++ layer 311 of the upper crystalline silicon layer, which can be produced by a chemical method or a vacuum deposition method.
  • the perovskite coating layer 12 and the hole transport layer 13 are deposited on the smooth surface of the above structure.
  • ITO14 is deposited on both sides of the above structure, and electrodes are deposited to complete the overall structure.
  • FIG. 6 shows a schematic structural diagram of a sixth type of stacked photovoltaic device in an embodiment of the present invention.
  • the lower battery unit 2 uses p-type silicon wafers 25, and the backlight of the lower battery unit 2 uses PERx (PERC, PERT, PERL) passivation technology, and double-sided texturing , Can receive light on both sides.
  • the light-facing surface of the lower battery unit 2 is an inverted pyramid suede.
  • the upper battery cell 1 uses wide band gap gallium arsenide as the absorption layer, and the band gap width of the absorption layer is 1.6-1.8 eV.
  • the absorption layer has a morphology that is bonded to the light-facing surface of the lower battery cell 2.
  • the intermediate layer shown in FIG. 6 includes a dielectric layer, that is, the Al 2 O 3 dielectric layer 332.
  • the silicon wafer is cleaned and the upper and lower surfaces are textured.
  • the p-type layer is made to form a pn junction by diffusion or crystallization after deposition to the smooth surface.
  • the upper surface of the p-type layer is made by thermal diffusion or crystallization after deposition.
  • the lower crystalline silicon layer, the lower crystalline silicon layer 32 is a heavily doped p++ layer 321 with a doping concentration of 10 20 cm -3 , and the thickness of the lower crystalline silicon layer p++ layer 321 is calculated from the doping concentration reaching the order of 10 20 cm -3 ,
  • the thickness of the layer is 8nm.
  • the p-type layer and the lower crystalline silicon layer p++ layer 321 can be produced by a one-step diffusion or post-deposition crystallization method, and a transition p+ layer 23 is formed in the middle.
  • a PERx passivation structure 27 is made on the back side.
  • An Al 2 O 3 dielectric layer 332 is formed on the smooth surface of the lower crystalline silicon layer p++ layer 321, with a thickness of 0.8 nm, which can be formed by surface oxidation (thermal oxidation, chemical oxidation) or ALD deposition;
  • the n++ heavy doping is made on the Al 2 O 3 dielectric layer 332, that is, the upper crystalline silicon layer 31, which can be made by over-depositing amorphous silicon followed by crystallization or CVD, PVD and other growth methods.
  • the doping concentration of this layer is 10 20 cm -3 reaches the order of magnitude, with a thickness of 5nm.
  • the silicon-germanium mixed buffer layer 16 is fabricated on the light-facing surface of the upper crystalline silicon layer n++ layer 311, and CVD or epitaxial processes can be used.
  • a gallium arsenide absorption layer 17 is grown on the buffer layer, and the thickness of the absorption layer is about 1.5 ⁇ m.
  • a window layer 18 of gallium indium phosphate is grown on the absorber layer.
  • An anti-reflection film 19 is deposited on the window layer.
  • Electrodes are deposited or printed on both sides of the above structure to complete the structure.
  • each step of the above method can refer to the relevant description in the foregoing embodiment, and can achieve the same or similar beneficial effects. In order to avoid repetition, it will not be repeated here.
  • each device and the like can be referred to each other.

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Abstract

一种叠层光伏器件及生产方法，涉及光伏技术领域。叠层光伏器件包括：上层电池单元（1）和下层电池单元（2），以及位于上层电池单元（1）和下层电池单元（2）之间的隧道结（3）；下层电池单元（2）为晶体硅电池；隧道结（3）包括：上晶体硅层（31）、下晶体硅层（32）以及位于上晶体硅层（31）和下晶体硅层（32）之间的中间层（33）；所述上晶体硅层（31）、所述下晶体硅层（32）、所述中间层（33）直接接触，所述上晶体硅层（31）和所述下晶体硅层（32）的掺杂类型相反；所述上晶体硅层（31）在与所述中间层（33）的界面处的掺杂浓度、所述下晶体硅层（32）在与所述中间层（33）的界面处的掺杂浓度均大于或等于10 18cm -3；所述中间层（33）包括：至少一层介电层；所述介电层的带隙宽度大于或等于3eV。该技术方案提高了叠层光伏器件效率，降低了串联电阻，提升了峰值隧道电流。

Description

叠层光伏器件及生产方法
本申请要求在2020年3月27日提交中国专利局、申请号为202010231541.0、发明名称为“叠层光伏器件及生产方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及光伏技术领域，特别是涉及一种叠层光伏器件及生产方法。
背景技术
叠层光伏器件可以将太阳光分成多个波段，从正面到背面，依次采用带隙逐渐减小的太阳能电池单元吸收不同能量的太阳光，以拓宽对太阳光的光谱响应波段，减少能量损失，因此，叠层光伏器件具有广泛的应用前景。以晶体硅电池为下层电池单元的叠层光伏器件具有较大的量产空间。
隧道结具有较强的传输与复合能力，实现较高的复合速率所需的厚度较薄，因此，叠层光伏器件中通常采用隧道结串联各个电池单元。
但是，现有技术中，下层电池单元为晶体硅电池的叠层光伏器件的隧道结隧穿效率低、器件整体串联电阻偏高。
发明内容
本发明提供一种叠层光伏器件及生产方法，旨在解决下层电池单元为晶体硅电池的叠层光伏器件的隧道结隧穿效率低、器件整体串联电阻偏高的问题。
根据本发明的第一方面，提供了一种叠层光伏器件，所述叠层光伏器件包括：上层电池单元和下层电池单元，以及位于所述上层电池单元和所述下层电池单元之间的隧道结；所述下层电池单元为晶体硅电池；
所述隧道结包括：上晶体硅层、下晶体硅层以及位于所述上晶体硅层和所述下晶体硅层之间的中间层；
所述上晶体硅层、所述下晶体硅层、所述中间层直接接触，所述上晶体硅层和所述下晶体硅层的掺杂类型相反；所述上晶体硅层在与所述中间层的界面处的掺杂浓度、所述下晶体硅层在与所述中间层的界面处的掺杂浓度均 大于或等于10 18cm -3；
所述中间层包括：至少一层介电层；所述介电层的带隙宽度大于或等于3eV。
可选的，所述介电层的介电强度大于或等于3MV/cm。
可选的，所述介电层的材料选自：硅的氧化物、硅的氮化物、硅的氮氧化物、硅的卤化物、硅的氟氧化物、硅的碳氧化物、碱金属的氧化物、碱金属的氮化物、碱金属的氮氧化物、碱金属的卤化物、碱金属的氟氧化物、过渡金属的氧化物、过渡金属的氮化物、过渡金属的氮氧化物、过渡金属的卤化物、过渡金属的氟氧化物、III族金属的氧化物、III族金属的氮化物、III族金属的氮氧化物、III族金属的卤化物、III族金属的氟氧化物、IV族金属的氮化物、IV族金属的氮氧化物、IV族金属的卤化物或IV族金属的氟氧化物中的至少一种。
可选的，所述介电层的材料选自：氧化硅、氮化硅、氟化硅、氟氧化硅、碳氧化硅、氧化铝、氟化铝或氮氧化铝中的至少一种。
可选的，所述上晶体硅层、所述下晶体硅层的厚度均为2-100nm；
所述中间层的厚度为0.1-5nm。
可选的，所述中间层还包括：位于所述介电层和所述上晶体硅层之间且与所述上晶体硅层直接接触的第一过渡层，和/或，位于所述介电层和所述下晶体硅层之间且与所述下晶体硅层直接接触的第二过渡层；
所述第一过渡层的材料选自所述介电层与所述上晶体硅层的界面反应的生成物中的至少一种；
所述第二过渡层的材料选自所述介电层与所述下晶体硅层的界面反应的生成物中的至少一种。
可选的，在所述叠层光伏器件的堆叠方向上，所述上晶体硅层具有掺杂浓度梯度，和/或，所述下晶体硅层具有掺杂浓度梯度。
可选的，所述下层电池单元的向光面设置有陷光结构；所述隧道结的背光面与所述下层电池单元的向光面形状适配。
根据本发明的第二方面，提供了一种叠层光伏器件的生产方法，包括：
制备下层电池单元，所述下层电池单元为晶体硅电池；
制备隧道结；其中，所述隧道结包括：上晶体硅层、下晶体硅层以及位于所述上晶体硅层和所述下晶体硅层之间的中间层；所述上晶体硅层、所述下晶体硅层、所述中间层直接接触，所述上晶体硅层和所述下晶体硅层的掺 杂类型相反；所述上晶体硅层在与所述中间层的界面处的掺杂浓度、所述下晶体硅层在与所述中间层的界面处的掺杂浓度均大于或等于10 18cm -3；所述中间层包括：至少一层介电层；所述介电层的带隙宽度大于或等于3eV；
制备上层电池单元。
可选的，制备所述下晶体硅层步骤包括下述工艺中的一种：
沉积、掺杂、生长；
制备所述中间层的步骤包括下述工艺中的一种：
沉积、水浴、涂覆、表面原位化合、湿法热氧、干法热氧、等离子氧化、等离子增强辅助氧化；
制备所述上晶体硅层的步骤包括下述工艺中的一种：
沉积、生长。
可选的，所述中间层还包括：位于所述介电层和所述上晶体硅层之间且与所述上晶体硅层直接接触的第一过渡层，和/或，位于所述介电层和所述下晶体硅层之间且与所述下晶体硅层直接接触的第二过渡层；所述制备隧道结的步骤包括：
在所述介电层和所述上晶体硅层之间，形成所述第一过渡层；所述第一过渡层的材料选自所述介电层和所述上晶体硅层的界面反应的生成物中的至少一种；
在所述介电层和所述下晶体硅层之间，形成所述第二过渡层；所述第二过渡层的材料选自所述介电层和所述下晶体硅层的界面反应的生成物中的至少一种。
本发明实施方式中，针对下层电池单元为晶体硅电池的叠层光伏器件，通过在上晶体硅层和下晶体硅层之间引入包括介电层的中间层，在介电层的阻隔作用下，可以有效缓解掺杂类型相反的上晶体硅层和下晶体硅层中的掺杂元素互相扩散，进而在界面形成突变的掺杂界面结构，且有利于两侧有效掺杂浓度的提高，从而可以有效地提高隧穿效率，降低隧道结串联电阻，提升峰值隧道电流。同时，上晶体硅层在与中间层的界面处的掺杂浓度、下晶体硅层在与中间层的界面处的掺杂浓度均大于或等于10 18cm -3，介电层的带隙宽度大于或等于3eV，有利于实现两侧的能级简并，从而可以有效地提高隧道结隧穿效率，提升峰值隧道电流，降低器件整体串联电阻。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其它 目的、特征和优点能够更明显易懂，以下特举本发明的具体实施方式。
附图说明
为了更清楚地说明本发明实施方式的技术方案，下面将对本发明实施方式的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1示出了本发明实施方式中的第一种叠层光伏器件的结构示意图；
图2示出了本发明实施方式中的第二种叠层光伏器件的结构示意图；
图3示出了本发明实施方式中的第三种叠层光伏器件的结构示意图；
图4示出了本发明实施方式中的第四种叠层光伏器件的结构示意图；
图5示出了本发明实施方式中的第五种叠层光伏器件的结构示意图；
图6示出了本发明实施方式中的第六种叠层光伏器件的结构示意图。
附图编号说明：
1-上层电池单元，11-TiO 2涂层，12-钙钛矿涂层，13-空穴传输层，14-ITO，15-p型非晶硅薄膜，16-硅锗混合缓冲层，17-砷化镓吸收层，18-磷镓铟窗口层，19-减反射薄膜，2-下层电池单元，21-n型硅片，22-n型非晶硅，23-p+层，24-本征非晶硅，25-p型硅片，26-n+层，27-PERx，3-隧道结，4-顶部电极，5-底部电极，31-上晶体硅层，311-n++层，32-下晶体硅层，321-p++层，33-中间层，331-SiO 2介电层，332-Al 2O 3介电层。
具体实施例
下面将结合本发明实施方式中的附图，对本发明实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式是本发明一部分实施方式，而不是全部的实施方式。基于本发明中的实施方式，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施方式，都属于本发明保护的范围。
发明人在研究中发现：现有技术中针对下层电池单元为晶体硅电池的叠层光伏器件中隧道结隧穿效率低、整体串联电阻偏高的主要原因在于：缓慢变化的扩散界面降低了隧道结界面处两侧的有效掺杂浓度，并扩宽了隧穿距离。
在本发明实施方式中，参照图1所示，图1示出了本发明实施方式中的 第一种叠层光伏器件的结构示意图。该叠层光伏器件包括：上层电池单元1和下层电池单元2，以及位于上层电池单元1和下层电池单元2之间的隧道结3，该隧道结3用于串联上述上层电池单元1和下层电池单元2以形成叠层光伏器件。可以理解的是，上层电池单元1和下层电池单元2具有不同的带隙，且上层电池单元1的带隙大于下层电池单元2的带隙。该下层电池单元为晶体硅电池。在本发明实施方式中，对叠层光伏器件包括的上层电池单元、下层电池单元、隧道结的数量均不作具体限定。在图1中，4为顶部电极，5为底部电极。
可以理解的是，隧道结3具有透光性，用于透过上层电池单元吸收之后剩余的波段。该透光性的透光波段可以根据与其相邻的上层电池单元吸收波段之后剩余的波段确定。如，该透光性的透光波段即可以为与其相邻的上层电池单元吸收波段之后剩余的波段。
参照图1所示，该隧道结3包括：上晶体硅层31、下晶体硅层32以及位于上晶体硅层31和下晶体硅层32之间的中间层33。上晶体硅层31、下晶体硅层32、中间层33直接接触。上晶体硅层31具有第一掺杂类型，下晶体硅层32具有第二掺杂类型，第一掺杂类型和第二掺杂类型相反。例如，上晶体硅层31为n型掺杂类型，则下晶体硅层32为p型掺杂类型。上晶体硅层31与上层电池单元1接触，下晶体硅层32与下层电池单元2接触。可以理解的是，上晶体硅层31的第一掺杂类型与上层电池单元1的背光面的掺杂类型相同。下晶体硅层32的第二掺杂类型与下层电池单元2的向光面的掺杂类型相同。例如，下层电池单元2若采用p型硅片，若下层电池单元2的向光面扩散为n型，则，下晶体硅层32的第二掺杂类型为n型。
该中间层包括至少一层介电层。本发明实施方式中，对介电层的数量不作具体限定。通过在上晶体硅层31和下晶体硅层32之间引入包括介电层的中间层33，在介电层的阻隔作用下，可以有效缓解掺杂类型相反的上晶体硅层31和下晶体硅层32中掺杂元素互相扩散，进而在界面形成突变的掺杂界面结构，且有利于两侧有效掺杂浓度的提高，从而可以有效地提高隧道结隧穿效率，提升峰值隧道电流，降低器件整体串联电阻。
上晶体硅层31在与中间层33接触的界面处的掺杂浓度、下晶体硅层32在中间层33接触的界面处的掺杂浓度均大于或等于10 18cm -3。上晶体硅层31其余处的掺杂浓度可以根据实际需要进行设定。下晶体硅层32其余处的掺杂浓度也可以根据实际需要进行设定。介电层的带隙宽度大于或等于3eV， 从而有利于阻挡无效隧穿，与中间层33两侧界面接触的上晶体硅层31界面处以及下晶体硅层32界面处的掺杂浓度较高，实现了导带底与价带顶的对位，有利于实现中间层33两侧的界面能级简并，从而可以有效地提高隧道结隧穿效率，提升峰值隧道电流，降低器件整体串联电阻。
可选的，在叠层光伏器件的堆叠方向上，上晶体硅层31具有掺杂浓度梯度，和/或，下晶体硅层32具有掺杂浓度梯度。具体的，在叠层光伏器件的堆叠方向上，上晶体硅层31的掺杂浓度梯度可以是增大或减小，下晶体硅层32的掺杂浓度梯度也可以是增大或减小，以进一步提升隧穿效率。需要说明的是，上晶体硅层31中在于中间层33的接触的界面处的掺杂浓度大于或等于10 18cm -3，上晶体硅层31中其余位置的掺杂浓度根据实际需要进行设定。下晶体硅层32中在于中间层33的接触的界面处的掺杂浓度大于或等于10 18cm -3，下晶体硅层32中其余位置的掺杂浓度也可以根据实际需要进行设定。上晶体硅层31掺杂浓度的峰值可能不一定位于其表面，可以位于上晶体硅层31的表面之外的区域。下晶体硅层32掺杂浓度的峰值也可能不一定位于其表面，可以位于下晶体硅层32的表面之外的区域。
可选的，上晶体硅层31、下晶体硅层32的晶体结构可以为单晶或多晶，这样选择类型多，选择更加灵活。
可选的，介电层的介电强度大于或等于3MV/cm，利于抑制无效隧穿，从而可以有效地提高隧穿效率，降低隧道结串联电阻，提升峰值隧道电流。
可选的，介电层的材料可以选自：硅的氧化物、硅的氮化物、硅的氮氧化物、硅的卤化物、硅的氟氧化物、硅的碳氧化物、碱金属的氧化物、碱金属的氮化物、碱金属的氮氧化物、碱金属的卤化物、碱金属的氟氧化物、过渡金属的氧化物、过渡金属的氮化物、过渡金属的氮氧化物、过渡金属的卤化物、过渡金属的氟氧化物、III族金属的氧化物、III族金属的氮化物、III族金属的氮氧化物、III族金属的卤化物、III族金属的氟氧化物、IV族金属的氮化物、IV族金属的氮氧化物、IV族金属的卤化物、IV族金属的氟氧化物中的至少一种。上述材料的介电层具有较高的带隙宽度，利于抑制无效隧穿，从而可以有效地提高隧道结隧穿效率，提升峰值隧道电流，降低器件整体串联电阻。
可选的，介电层的材料还可以选自：氧化硅(如，可以为SiO x，如，SiO 2)、氮化硅(SiN x)、氟化硅(如，SiF 4)、氟氧化硅(SiOF)、碳氧化硅(SiOC)、氧化铝(如，Al 2O 3)、氟化铝(AlF x)、氮氧化铝(AlON)中的至少一种。 上述材料的导电材料介电强度、带隙宽度均较大，利于抑制无效隧穿，从而可以有效地提高隧穿效率，降低隧道结串联电阻，提升峰值隧道电流。
可选的，中间层33除了包括至少一层介电层之外，还包括：位于介电层与上晶体硅层31之间且与上晶体硅层31直接接触的第一过渡层，和/或，位于介电层和下晶体硅层32之间且与下晶体硅层32直接接触的第二过渡层。位于介电层与上晶体硅层31之间，且与上晶体硅层31直接接触的第一过渡层的材料选自介电层与上晶体硅层31的界面反应(不局限掺杂、迁移等手段)的生成物中的至少一种。位于介电层与下晶体硅层32之间，且与下晶体硅层32直接接触的第二过渡层的材料选自介电层与下晶体硅层32的界面反应的生成物中的至少一种。上述第一过渡层、第二过渡层均可以起到良好的表面化学钝化的作用。
位于介电层与上晶体硅层31之间，且与上晶体硅层31直接接触的第一过渡层可以由介电层和下晶体硅层31通过界面反应(不局限掺杂、迁移等手段)生成，或，独立形成。位于介电层与下晶体硅层32之间，且与下晶体硅层32直接接触的第二过渡层可以由介电层与下晶体硅层32通过界面反应(不局限掺杂、迁移等手段)生成或独立形成。
可选的，上晶体硅层31、下晶体硅层32的厚度均为2-100nm，更进一步的，上晶体硅层31、下晶体硅层32的厚度均为2-10nm。中间层33的厚度为0.1-5nm，更进一步的，中间层33的厚度可以为0.5-1nm。由此形成的隧道结的厚度较小，利于减小隧穿距离，提升隧穿效率。同时，隧道结的厚度较小，不会对下层电池单元造成较多的光学遮挡。
可选的，下层电池单元的向光面设置有陷光结构，下层电池单元的向光面为下层电池单元与下晶体硅层接触的表面或与隧道结接触的表面。隧道结的背光面与下层电池单元的向光面形状适配。隧道结的背光面为与下层电池单元的向光面接触的表面。该陷光结构可以为纳米光学结构、绒面结构等。纳米光学结构为规则的纳米陷光结构。绒面结构为金字塔、倒金字塔等结构等。下层电池单元的向光面设置陷光结构，隧道结的背光面与下层电池单元的向光面形状适配，则，隧道结的背光面同样设置有陷光结构利于增加光程。同时，该隧道结的结构和材料，利于在下层电池单元的向光面的陷光结构上获得厚度均匀、功能均一的隧道结。
例如，参照图2所示，图2示出了本发明实施方式中的第二种叠层光伏器件的结构示意图。该叠层光伏器件中，下层电池单元2的向光面为陷光结 构，隧道结3的背光面为与下层电池单元2的向光面形状适配的陷光结构。隧道结3的向光面为陷光结构，上层电池单元1的背光面为隧道结3的向光面形状适配的陷光结构。上层电池单元1的向光面为陷光结构。
在本发明实施方式中，下层电池单元为晶体硅电池，下层电池单元的衬底硅材料掺杂类型不限，可为正面pn结或背面pn结结构，可为单面或双面结构，即底部电极可以是整体金属背场或局部栅线。下层电池单元的向光面可为平面结构或具有陷光结构。可以理解的是，下层电池单元的向光面顶部不能覆盖有绝缘材料或电介质材料(如常规的钝化层或减反层)，以便于与隧道结进行电学接触。下层电池单元的背光面可以直接覆盖电极。为了提高下层电池单元的光电转换效率，可在下层电池单元的背光面设计任何结构，例如：制作钝化层及开孔的电学导出结构(PERC(Passivated Emitter and Rear Contact))，或进一步采用全面或局域重掺(PERT(Passivated Emitter and Rear Totally-diffused)、PERL(Passivated Emitter and Rear Locally-diffused))，或者可以采用氧化物隧穿钝化层和多晶传输层结构(TOPCon(Tunnel Oxide Passivated Contact))。
下层电池单元可采用同质结或单面异质结技术，与隧道结的下晶体硅层接触区域为晶体，可采用正面或背面pn结工艺。特别地，位于下层电池单元向光面的下晶体硅层的掺杂元素在高温过程中可能会部分向下层电池单元内部扩散，由于下晶体硅层少子寿命通常较低，因此采用正面pn结工艺时优选较深的pn结深度，即，将pn结设置的距离下晶体硅层较远，且高温过程时间尽量缩减，以减少掺杂元素扩散对pn结的影响。
在本发明实施方式中，上层电池单元的带隙宽度比下层电池单元的带隙宽度更宽。对上层电池单元具体类型不作限定。如，上层电池单元的带隙可以为1.5eV-2.3eV。如，上层电池单元的带隙可以为1.7eV-1.8eV。如，上层电池单元可以为：钙钛矿薄膜太阳电池、有机物薄膜太阳电池、量子点薄膜太阳电池、非晶硅薄膜太阳电池、非晶碳化硅薄膜太阳电池、铜铟镓硒薄膜太阳电池、碲化镉薄膜太阳电池、砷化镓薄膜太阳电池等。上层电池单元可以包含一层或多层与隧道结中上晶体硅层接触所需缓冲层或匹配层，以减少隧道结与上层电池单元间电阻或复合。该缓冲层或匹配层起到与隧道结上晶体硅层接触、收集并传输上层电池单元载流子的作用，同时该层还可以起到能带缓冲、能带匹配、晶格匹配、降低接触电阻等作用，以进一步降低整体器件的串联电阻。
在本发明实施方式中，最上层电池单元的顶部和最下电池单元底部可以具有电极。如图1或图2所示，最上层电池单元的顶部具有顶部电极4。最下电池单元底部具有底部电极5。最上层电池单元的顶部还可以具有一层或多层减反射薄膜。最下电池单元底部电极可以是整体金属背场(单面电池)，也可以是栅线(双面电池)。上下层电池单元需要进行电学与光学适配。
本发明实施方式中针对下层电池单元为晶体硅电池的叠层光伏器件，通过在上晶体硅层和下晶体硅层之间引入包括介电层的中间层，在介电层的阻隔作用下，可以有效缓解掺杂类型相反的上晶体硅层和下晶体硅层中的掺杂元素互相扩散，进而在界面形成突变的掺杂界面结构，且有利于两侧有效掺杂浓度的提高，从而可以有效地提高隧穿效率，降低隧道结串联电阻，提升峰值隧道电流。同时，上晶体硅层在与中间层的界面处的掺杂浓度、下晶体硅层在与中间层的界面处的掺杂浓度均大于或等于10 18cm -3，介电层的带隙宽度大于或等于3eV，有利于实现两侧的能级简并，从而可以有效地提高隧穿效率，降低隧道结串联电阻，提升峰值隧道电流。
本发明实施方式中还提供一种叠层光伏器件的生产方法。该方法包括如下步骤：
步骤S1，制备下层电池单元，所述下层电池单元为晶体硅电池。
步骤S2，制备隧道结；其中，所述隧道结包括：上晶体硅层、下晶体硅层以及位于所述上晶体硅层和所述下晶体硅层之间的中间层；所述上晶体硅层、所述下晶体硅层、所述中间层直接接触，所述上晶体硅层和所述下晶体硅层的掺杂类型相反；所述上晶体硅层在与所述中间层的界面处的掺杂浓度、所述下晶体硅层在与所述中间层的界面处的掺杂浓度均大于或等于10 18cm -3；所述中间层包括：至少一层介电层；所述介电层的带隙宽度大于或等于3eV。
步骤S3，制备上层电池单元。
上述步骤S1至步骤S3中有关下层电池单元、上层电池单元、隧道结的描述可以参照前述实施方式中的记载，且能够达到相同或类似的有益效果，为了避免重复，此处不再赘述。
在本发明实施方式中，对步骤S1-S3的先后顺序没有特殊限制。例如在制备下层电池单元的过程中，针对该下层电池单元的某些层不能承受高温的情况下，可以在隧道结或该叠层光伏器件其他部分已经制备完毕的情况下，再制备该下层电池单元中不能承受高温的层。
可选的，制备上述下晶体硅层的步骤可以包括下述工艺中的一种：沉积、掺杂、生长。沉积工艺可以包括：在下层电池单元的向光面通过PVD、CVD等方法沉积对应掺杂浓度的非晶、纳晶硅的下晶体硅层，并进行快速或慢速退火以进行晶化。生长工艺可以包括：CVD、PVD、ALD等气相生长方法，或分子束外延MBE(Molecular beam epitaxy)等外延生长方法，生长后可通过快速或慢速退火进一步改善该层的性能。或通过热扩散、粒子注入、激光掺杂等方法对下层电池单元的向光面进行进一步掺杂。
可选的，制备中间层的步骤可以包括下述工艺中的一种：沉积、水浴、涂覆、表面原位化合、湿法热氧、干法热氧、等离子氧化、等离子增强辅助氧化。具体的，可采用PVD、CVD、ALD等沉积工艺，或，可采用水浴法、涂敷法等化学工艺，或者，可采用氧化、氮化等表面原位化合工艺。特别地，氧化硅可采用湿法热氧(HNO 3)、O 3、UV/O 3，干法热氧，等离子氧化、等离子增强辅助氧化(PECVD-assisted)N 2O-oxidized SiO x，CVD等工艺。
可选的，中间层33还包括：位于介电层和上晶体硅层31之间，且与上晶体硅层31直接接触的第一过渡层，和/或，位于介电层和下晶体硅层32之间，且与下晶体硅层32直接接触的第二过渡层。位于介电层和上晶体硅层31之间，和上晶体硅层31直接接触的第一过渡层可以由介电层和上晶体硅层31的界面反应形成，或，独立形成。位于介电层与下晶体硅层32之间，且与下晶体硅层32直接接触的第二过渡层可以由介电层与下晶体硅层32的界面反应形成或独立形成。
如，先采用ALD法沉积0.5nm的氧化硅，再沉积1nm氧化铝，再沉积0.5nm氧化硅。其中，氧化铝可以为介电层，位于其两侧的氧化硅可以为独立形成的第一过渡层和第二过渡层。
可选的，制备上晶体硅层的步骤包括下述工艺中的一种：沉积、生长。具体的，沉积工艺包括通过PVD、CVD等方法沉积对应掺杂浓度的非晶、纳晶硅薄膜并进行快速或慢速退火。生长工艺包括CVD、PVD、ALD等气相生长方法，或MBE等外延生长方法，生长后可通过快速或慢速退火进一步改善该层的性能。
下面列举几种叠层光伏器件，及其生产过程：
参照图3所示，图3示出了本发明实施方式中的第三种叠层光伏器件的结构示意图。图3所示的叠层光伏器件中：下层电池单元2采用n型硅片21，下层电池单元2的背光面采用非晶硅进行钝化并沉积n型非晶硅22进行电 子传输，因非晶硅温度耐受性差，因此非晶硅的沉积可以在隧道结或该叠层光伏器件其他部分已经制备完毕之后再进行。下层电池单元2的向光面可以具有金字塔绒面结构。上层电池单元1采用宽带隙钙钛矿作为吸收层，吸收层带隙宽度为1.6-1.8eV。吸收层具备与下层电池单元2的向光面贴合的形貌。图3所示的中间层包括一层介电层，即为SiO 2介电层331。
该图3所示的叠层光伏器件的生产过程如下：
首先清洗硅片并进行上下表面制绒，在向光面通过扩散或沉积后晶化的方式制作p型层形成pn结，在p型层的向光面通过热扩散或沉积后晶化的方式制作下晶体硅层，下晶体硅层32为重掺杂p++，掺杂浓度为10 20cm -3。p型层与下晶体硅层p++层321可通过一步扩散或沉积后晶化法制作，中间形成过渡p+层23。下晶体硅层p++层321厚度从掺杂浓度达到10 20cm -3算起，该层厚度5nm。
在下晶体硅层p++层321的向光面制作SiO 2介电层331，该层厚度1nm，可以通过表面氧化(热氧化、化学氧化)或ALD沉积等方法制作。
在SiO 2介电层上制作n++重掺杂，即上晶体硅层31，可以用过沉积非晶硅后晶化的方法，或CVD、PVD等生长方法来制作，该上晶体硅层31掺杂浓度为10 20cm -3，厚度为5nm。
在上晶体硅层n++层311的向光面沉积TiO 2涂层11，可通过化学法或真空沉积方法制作。
从清洗硅片开始至TiO 2涂层11完毕，以上各层可以允许高温工艺。
在上述结构的背光面沉积本征非晶硅24及n型非晶硅22。在上述结构的向光面沉积钙钛矿涂层12、空穴传输层13。在上述结构两面沉积ITO14，并沉积电极，完成整体结构。
参照图4所示，图4示出了本发明实施方式中的第四种叠层光伏器件的结构示意图。图4所示的叠层光伏器件中：下层电池单元2采用n型硅片21，下层电池单元2的背光面采用非晶硅进行钝化并沉积n型非晶硅22进行电子传输，因非晶硅温度耐受性差，因此非晶硅的沉积可以在隧道结或该叠层光伏器件其他部分已经制备完毕之后再进行。下层电池单元2的向光面可以具有金字塔绒面结构。上层电池单元1采用顶部太阳电池采用宽带隙非晶硅作为吸收层，吸收层带隙宽度为1.7eV。吸收层具备与下层电池单元2的向光面贴合的形貌。图4所示的中间层包括一层介电层，即为SiO 2介电层331。
该图4所示的叠层光伏器件的生产过程如下：
首先清洗硅片并进行上下表面制绒，在向光面通过扩散或沉积后晶化的方式制作p型层形成pn结，在p型层的向光面通过热扩散或沉积后晶化的方式制作下晶体硅层，下晶体硅层32为重掺杂p++层，掺杂浓度为10 20cm -3。p型层与下晶体硅层p++层321可通过一步扩散或沉积后晶化法制作，中间形成过渡p+层23。下晶体硅层p++层321厚度从掺杂浓度达到10 20cm -3算起，该层厚度5nm。
在下晶体硅层p++层321的向光面制作SiO 2介电层331，该层厚度1nm，可以通过表面氧化(热氧化、化学氧化)或ALD沉积等方法制作。
在SiO 2介电层331的向光面制作n++重掺杂，即上晶体硅层31，可以用过沉积非晶硅后晶化的方法或CVD、PVD等生长方法来制作，该层掺杂浓度为10 20cm -3，厚度为5nm。
在上述结构两面沉积本征非晶硅薄膜。在上述结构的背光面沉积n型非晶硅薄膜22。在上述结构的向光面沉积p型非晶硅薄膜15。在上述结构两面沉积ITO14及金属电极，完成器件。
参照图5所示，图5示出了本发明实施方式中的第五种叠层光伏器件的结构示意图。图5所示的叠层光伏器件中：下层电池单元2采用p型硅片25，下层电池单元2的背光面采用背光面采用PERx(PERC、PERT、PERL)类钝化技术，双面制绒，可双面受光。上层电池单元1采用宽带隙钙钛矿作为吸收层，吸收层带隙宽度为1.6-1.8eV。吸收层具备与下层电池单元2的向光面贴合的形貌。图5所示的中间层包括一层介电层，即为SiO 2介电层331。
该图5所示的叠层光伏器件的生产过程如下：
首先清洗硅片并进行上下表面制绒，在背光面通过扩散或沉积后晶化的方式制作n型层形成pn结，在n型层向光面通过热扩散或沉积后晶化的方式制作n+层26，形成背场。在上述结构背面制作PERx结构27进行背钝化。在向光面通过热扩散或沉积后晶化的方式形成下晶体硅层32，下晶体硅层为p++层321，掺杂浓度为10 19cm -3，下晶体硅层p++层321厚度从掺杂浓度达到10 19cm -3量级算起，该层厚度8nm。
在下晶体硅层p++层321向光面制作SiO 2介电层331，该层厚度0.8nm，可以通过表面氧化(热氧化、化学氧化)或ALD沉积等方法制作。
在SiO 2介电层331上制作n++重掺杂，即上晶体硅层31，可以用过沉积非晶硅后晶化的方法或CVD、PVD等生长方法来制作，该层从掺杂浓度10 19cm -3达到量级算起，厚度5nm。
在上晶体硅层n++层311的向光面沉积TiO 2涂层11，可通过化学法或真空沉积方法制作。
在上述结构的向光面沉积钙钛矿涂层12、空穴传输层13。在上述结构两面沉积ITO14，并沉积电极，完成整体结构。
参照图6所示，图6示出了本发明实施方式中的第六种叠层光伏器件的结构示意图。图6所示的叠层光伏器件中：下层电池单元2采用p型硅片25，下层电池单元2的背光面采用背光面采用PERx(PERC、PERT、PERL)类钝化技术，双面制绒，可双面受光。下层电池单元2的向光面为倒金字塔绒面。上层电池单元1采用宽带隙砷化镓作为吸收层，吸收层带隙宽度为1.6-1.8eV。吸收层具备与下层电池单元2的向光面贴合的形貌。图6所示的中间层包括一层介电层，即为Al 2O 3介电层332。
该图6所示的叠层光伏器件的生产过程如下：
首先清洗硅片并进行上下表面制绒，在向光面通过扩散或沉积后晶化的方式制作p型层形成pn结，在p型层上表面通过热扩散或沉积后晶化的方式制作形成下晶体硅层，下晶体硅层32为重掺杂p++层321，掺杂浓度为10 20cm -3，下晶体硅层p++层321厚度从掺杂浓度达到10 20cm -3量级算起，该层厚度8nm。p型层与下晶体硅层p++层321可通过一步扩散或沉积后晶化法制作，中间形成过渡p+层23。在背面制作PERx钝化结构27。
在下晶体硅层p++层321的向光面制作Al 2O 3介电层332，该层厚度0.8nm，可以通过表面氧化(热氧化、化学氧化)或ALD沉积等方法制作；
在Al 2O 3介电层332上制作n++重掺杂，即上晶体硅层31，可以用过沉积非晶硅后晶化的方法或CVD、PVD等生长方法来制作，该层掺杂浓度10 20cm -3达到量级，厚度5nm。
在上述上晶体硅层n++层311的向光面制作硅锗混合缓冲层16，可以采用CVD或外延工艺。缓冲层上生长砷化镓吸收层17，吸收层厚度约1.5μm。吸收层上生长磷镓铟窗口层18。窗口层上沉积减反射薄膜19。
上述结构正面两面沉积或印刷电极，完成结构。
在本发明实施方式中，上述方法的各个步骤可以参照前述实施方式中的有关记载，且能达到相同或类似的有益效果，为了避免重复，此处不再赘述。
需要说明的是，对于方法实施方式，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本发明实施方式并不受所描述的动作顺序的限制，因为依据本发明实施方式，某些步骤可以采用其他 顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施方式均属于优选实施方式，所涉及的动作并不一定都是本发明实施方式所必须的。
本发明实施方式中，关于叠层光伏器件及其生产方法，各个器件等可以相互参照。
上面结合附图对本发明的实施方式进行了描述，但是本发明并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本发明的启示下，在不脱离本发明宗旨和权利要求所保护的范围情况下，还可做出很多形式，这些均属于本发明的保护之内。

Claims (11)

  1. 一种叠层光伏器件，其特征在于，所述叠层光伏器件包括：上层电池单元和下层电池单元，以及位于所述上层电池单元和所述下层电池单元之间的隧道结；所述下层电池单元为晶体硅电池；
    所述隧道结包括：上晶体硅层、下晶体硅层以及位于所述上晶体硅层和所述下晶体硅层之间的中间层；
    所述上晶体硅层、所述下晶体硅层、所述中间层直接接触，所述上晶体硅层和所述下晶体硅层的掺杂类型相反；所述上晶体硅层在与所述中间层的界面处的掺杂浓度、所述下晶体硅层在与所述中间层的界面处的掺杂浓度均大于或等于10 18cm -3；
    所述中间层包括：至少一层介电层；所述介电层的带隙宽度大于或等于3eV。
  2. 根据权利要求1所述的叠层光伏器件，其特征在于，所述介电层的介电强度大于或等于3MV/cm。
  3. 根据权利要求1所述的叠层光伏器件，其特征在于，所述介电层的材料选自：硅的氧化物、硅的氮化物、硅的氮氧化物、硅的卤化物、硅的氟氧化物、硅的碳氧化物、碱金属的氧化物、碱金属的氮化物、碱金属的氮氧化物、碱金属的卤化物、碱金属的氟氧化物、过渡金属的氧化物、过渡金属的氮化物、过渡金属的氮氧化物、过渡金属的卤化物、过渡金属的氟氧化物、III族金属的氧化物、III族金属的氮化物、III族金属的氮氧化物、III族金属的卤化物、III族金属的氟氧化物、IV族金属的氮化物、IV族金属的氮氧化物、IV族金属的卤化物或IV族金属的氟氧化物中的至少一种。
  4. 根据权利要求3所述的叠层光伏器件，其特征在于，所述介电层的材料选自：氧化硅、氮化硅、氟化硅、氟氧化硅、碳氧化硅、氧化铝、氟化铝或氮氧化铝中的至少一种。
  5. 根据权利要求1至4中任一所述的叠层光伏器件，其特征在于，所述上晶体硅层、所述下晶体硅层的厚度均为2-100nm；
    所述中间层的厚度为0.1-5nm。
  6. 根据权利要求1所述的叠层光伏器件，其特征在于，所述中间层还包括：位于所述介电层和所述上晶体硅层之间且与所述上晶体硅层直接接触的第一过渡层，和/或，位于所述介电层和所述下晶体硅层之间且与所述下晶体硅层直接接触的第二过渡层；
    所述第一过渡层的材料选自所述介电层与所述上晶体硅层的界面反应的生成物中的至少一种；
    所述第二过渡层的材料选自所述介电层与所述下晶体硅层的界面反应的生成物中的至少一种。
  7. 根据权利要求1所述的叠层光伏器件，其特征在于，在所述叠层光伏器件的堆叠方向上，所述上晶体硅层具有掺杂浓度梯度，和/或，所述下晶体硅层具有掺杂浓度梯度。
  8. 根据权利要求1所述的叠层光伏器件，其特征在于，所述下层电池单元的向光面设置有陷光结构；所述隧道结的背光面与所述下层电池单元的向光面形状适配。
  9. 一种叠层光伏器件的生产方法，其特征在于，包括：
    制备下层电池单元，所述下层电池单元为晶体硅电池；
    制备隧道结；其中，所述隧道结包括：上晶体硅层、下晶体硅层以及位于所述上晶体硅层和所述下晶体硅层之间的中间层；所述上晶体硅层、所述下晶体硅层、所述中间层直接接触，所述上晶体硅层和所述下晶体硅层的掺杂类型相反；所述上晶体硅层在与所述中间层的界面处的掺杂浓度、所述下晶体硅层在与所述中间层的界面处的掺杂浓度均大于或等于10 18cm -3；所述中间层包括：至少一层介电层；所述介电层的带隙宽度大于或等于3eV；
    制备上层电池单元。
  10. 根据权利要求9所述的方法，其特征在于，制备所述下晶体硅层步骤包括下述工艺中的一种：
    沉积、掺杂、生长；
    制备所述中间层的步骤包括下述工艺中的一种：
    沉积、水浴、涂覆、表面原位化合、湿法热氧、干法热氧、等离子氧化、等离子增强辅助氧化；
    制备所述上晶体硅层的步骤包括下述工艺中的一种：
    沉积、生长。
  11. 根据权利要求9或10所述的方法，其特征在于，所述中间层还包括：位于所述介电层和所述上晶体硅层之间且与所述上晶体硅层直接接触的第一过渡层，和/或，位于所述介电层和所述下晶体硅层之间且与所述下晶体硅层直接接触的第二过渡层；所述制备隧道结的步骤包括：
    在所述介电层和所述上晶体硅层之间，形成所述第一过渡层；所述第一 过渡层的材料选自所述介电层和所述上晶体硅层的界面反应的生成物中的至少一种；
    在所述介电层和所述下晶体硅层之间，形成所述第二过渡层；所述第二过渡层的材料选自所述介电层和所述下晶体硅层的界面反应的生成物中的至少一种。
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