WO2024060933A1 - 太阳电池及其制备方法 - Google Patents

太阳电池及其制备方法 Download PDF

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WO2024060933A1
WO2024060933A1 PCT/CN2023/115160 CN2023115160W WO2024060933A1 WO 2024060933 A1 WO2024060933 A1 WO 2024060933A1 CN 2023115160 W CN2023115160 W CN 2023115160W WO 2024060933 A1 WO2024060933 A1 WO 2024060933A1
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solar cell
cell according
silicon
type
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PCT/CN2023/115160
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French (fr)
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陈浩
邢国强
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通威太阳能(眉山)有限公司
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Priority to AU2023343930A priority Critical patent/AU2023343930A1/en
Publication of WO2024060933A1 publication Critical patent/WO2024060933A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
    • H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation

Definitions

  • the present application relates to the field of solar cells, specifically, to a solar cell and a preparation method thereof.
  • TOPCon cells tunnel oxide passivated contact cells
  • the front side of the TOPCon battery usually uses a full-coverage boron diffusion process. The purpose is to form a PN junction on the front side, adapt to the high-temperature metallization process, reduce the metal composite protection opening voltage, form a contact, and also provide lateral transmission, which is beneficial to current collection. .
  • the carrier recombination on the front-side fully covered boron diffused emitter interface is relatively high, usually 20-40fAcm -2 , which limits the passivation performance and open circuit voltage of the cell. This further leads to low cell efficiency, so interface carrier recombination becomes an important factor limiting the development of solar cell efficiency.
  • the industry generally adopts the solution of preparing a fully covered boron diffused emitter to prepare the front structure of the N-type TOPCon battery.
  • a tubular device is used for boron diffusion. After vacuuming and heating to high temperature, an inert gas is used to carry a certain flow of oxygen into the tube for the pre-oxidation process, and then a boron source is carried for the diffusion process. Then, a post-oxidation process is performed at high temperature, and finally the temperature is lowered, the vacuum is broken, and the boat is taken out.
  • the Auger recombination in the silicon substrate under the non-metallic contact area increases, the passivation performance of the front is weakened, and the interface recombination current is high, usually 20-40fAcm -2 ; 2.
  • the boron diffusion process usually takes 2-4 hours, which is time-consuming and is a limiting factor in the production capacity of TOPCon batteries.
  • the purpose of the embodiments of the present application is to provide a solar cell and a preparation method thereof.
  • the cell structure is simple, the process time is short, the production capacity is high, and the conversion efficiency of the cell is high.
  • a solar cell which includes:
  • the P-type heavily doped layer, the front passivation layer, the front anti-reflection layer, and the front metal gate lines are arranged on the front side of the P-type silicon wafer in sequence.
  • the P-type heavily doped layer is arranged in regions corresponding to the front metal gate lines.
  • the front metal gate The line passes through the front anti-reflection layer and the front passivation layer in sequence, and forms contact with the corresponding P-type heavily doped layer;
  • a doped oxide layer, a back crystalline silicon layer, a back anti-reflection layer and a back metal electrode layer are arranged in sequence on the back of the P-type silicon wafer.
  • the front side of the TOPCon battery adopts a no-front-field solution, that is, P-type silicon wafers are used to prepare the battery, and no full-coverage boron diffusion is prepared on the front side of the battery. Boron is only heavily doped under the front metal grid line in a targeted manner. area to reduce surface recombination and form good metal contact.
  • the solar cell of this application has at least three advantages compared to the traditional N-type full-coverage boron-expanded (locally heavily doped under the metal gate line, that is, superimposed selective emitter) TOPCon cell:
  • the battery opening voltage is greatly increased (above 5mV).
  • the P-type front-field-less structure of the present application lacks the low-doped boron expanded layer and the lateral carrier transport effect compared to the N-type full-coverage boron expanded structure, the filling factor of the battery of the present application (FF) is higher (1% higher under the same silicon wafer resistivity of 1 ⁇ cm). The reason is that the front passivation layer performs better than the low boron expanded N-type silicon wafer when passivating the P-type silicon substrate (P-type silicon wafer).
  • the passivation performance is better, which is conducive to the improvement of iFF, and the FF value after metallization is increased accordingly;
  • the P-type silicon matrix has a high hole conductivity, and holes are conducted from the back PN junction through the silicon matrix to the front highly doped
  • the resistance loss during the hybrid contact area is much smaller than the transmission in boron-diffused N-type silicon, so the FF value is higher.
  • the resistance loss increases with the increase in the resistivity of the silicon substrate, and the resistivity should be controlled at about 1 ⁇ cm.
  • the battery cost per watt of this application is lower, and the cost of P-type silicon wafers is much lower than that of N-type silicon wafers.
  • the no-front-field solution eliminates the entire surface boron expansion process, and the total process time is shorter and the production capacity is greater.
  • the battery of this application has a simple structure and short process time. Since the front side does not fully cover the emitter, the passivation performance and corresponding open circuit voltage are greatly improved. The quantum efficiency and short-circuit current at short wavelengths are reduced, and the battery conversion efficiency is high. Compared with traditional N-type TOPCon batteries, it has the advantages of higher battery efficiency, lower battery cost, higher production capacity and cost-effectiveness, which is conducive to promoting the industrialization process of high-efficiency double-sided TOPCon batteries.
  • the back metal electrode layer is a back metal gate line, and the back metal gate line passes through the back anti-reflection layer, the back crystal silicon layer, and the doped oxide layer in order, and forms contact with the P-type silicon wafer.
  • the resistivity of the P-type silicon wafer is 0.5-10 ⁇ cm
  • the square resistance of the P-type heavily doped layer is 1-120 ⁇ /sq.
  • the front anti-reflection layer is composed of at least one of silicon nitride, silicon oxynitride, and silicon oxide, and has a thickness of 1-150 nm;
  • the component of the back anti-reflection layer includes at least one of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness is 1-100 nm.
  • the front passivation layer is composed of at least one of aluminum oxide and silicon oxide, and has a thickness of 1-40 nm.
  • the doped oxide layer includes silicon oxide and has a thickness of 1-2 nm.
  • the back crystalline silicon layer includes polycrystalline silicon or amorphous silicon, and has a thickness of 1-200 nm.
  • embodiments of the present application provide a method for preparing the solar cell provided in the first aspect, which includes the following steps:
  • a P-type heavily doped layer On the front side of the P-type silicon wafer, a P-type heavily doped layer, a front passivation layer, a front anti-reflection layer, and a front metal gate line are formed in sequence.
  • a doped oxide layer On the back side of the P-type silicon wafer, a doped oxide layer, a back crystalline silicon layer, and Back antireflection layer and back metal electrode layer.
  • P-type silicon wafers are used to replace N-type silicon wafers to prepare TOPCon cells.
  • the price of silicon wafers is lower and the cost per watt is reduced; one step of boron diffusion process is eliminated in the process, and the battery preparation process time is reduced by 2 hours, reducing the cost of corresponding auxiliary materials and equipment.
  • the P-type heavily doped layer is formed by boron laser doping, boron paste printing doping or laser film opening boron diffusion doping.
  • the front metal grid lines are formed using a local burn-through contact method
  • the back metal electrode layer is formed by a local burn-through contact method or a full coverage method.
  • Figure 1 is a schematic structural diagram of a P-type TOPCon battery provided by an embodiment of the present application.
  • the current TOPCon cells dope P-type compounds (boron sources) into the silicon wafer at high temperatures and form a boron concentration; the boron concentration in the silicon wafer changes with the depth of the silicon wafer, usually as follows: The surface area is the highest, forming a peak. As the depth of advancement increases, the boron concentration decreases.
  • parameters such as boron source amount, temperature and time, a doping curve suitable for preparing solar cells can be obtained.
  • the doped silicon wafer is on the front side
  • the interface between P-type doped silicon and the silicon matrix forms a PN junction, and the built-in electric field direction is from the inside to the outside;
  • the boron expanded emitter responds better to the short-wavelength light than the bare silicon wafer, making the battery's quantum conversion efficiency higher in the short-wavelength band.
  • the short-circuit current is higher; TOPCon batteries usually use a high-temperature sintering metallization process.
  • the printed silver grid lines will ablate into the battery during the sintering process, penetrate the aluminum oxide layer or reach near the aluminum oxide layer, and interact with the battery at high temperatures.
  • high-concentration boron doping is conducive to forming good contact between the emitter and silver particles, leading to current, and reducing the loss of open voltage due to carrier recombination.
  • the higher the boron doping concentration the lower the metal recombination;
  • the contact resistance between silver paste and bare silicon is large, and a certain concentration of boron doping is beneficial to reducing the contact resistance to the normal range; before the carriers on the front of the battery are collected by the metal electrode, their conduction path includes the silicon matrix and boron expanded emission Lateral transmission within the electrode, when the doping concentration of the boron expanded emitter is lower, the sheet resistance is higher, the resistance loss suffered by carrier transmission is higher, the corresponding series resistance of the battery is higher, and the filling factor is and the lower the conversion efficiency.
  • the applicant has explored solving the above technical problems by changing the boron expanded emitter in the TOPCon battery.
  • This embodiment provides a P-type TOPCon battery, which includes: a P-type silicon wafer 5, a P-type heavily doped layer 4 and a front-side passivation layer 3 arranged on the front side of the P-type silicon wafer 5 in sequence.
  • the front anti-reflection layer 2, the front metal gate line 1, the doped oxide layer 6, the back crystal silicon layer 7, the back anti-reflection layer 8 and the back metal gate line 9 are arranged on the back side of the P-type silicon wafer 5 in sequence.
  • the P-type heavily doped layer 4 is arranged in regions corresponding to the front metal gate lines.
  • the front metal gate lines 1 pass through the front anti-reflection layer 2 and the front passivation layer 3 in sequence, and form contact with the corresponding P-type heavily doped layer 4;
  • the back metal gate line 9 passes through the back anti-reflection layer 8, the back crystalline silicon layer 7, and the doped oxide layer 6 in sequence, and forms contact with the P-type silicon wafer 5.
  • the PN junction of the battery is located between the doped oxide layer 6 on the back and the doped oxide layer 6 on the back. between 5 P-type silicon wafers.
  • the back metal grid line 9 may also be a back metal electrode layer that fully covers the back anti-reflection layer 8 .
  • the resistivity of the P-type silicon wafer 5 can be selected arbitrarily in the range of 0.5-10 ⁇ cm.
  • the front side morphology of the P-type silicon wafer 5 is a velvet surface, without a fully covered emitter, and only a boron-expanded heavily doped region (P++), i.e., a P-type heavily doped layer 4, is locally arranged below the metal contact region.
  • P++ boron-expanded heavily doped region
  • the square resistance of the P-type heavily doped layer 4 can be arbitrarily selected within the range of 1-120 ⁇ /sq, and the square resistance of the non-contact region is the square resistance of the P-type silicon wafer 5 ;
  • the components of the front anti-reflection layer 2 include, but are not limited to, any one of silicon nitride ( SiNx ), silicon oxynitride ( SiOxNy ), and silicon oxide ( SiOx ), or a combination of any two or three thereof, and the thickness is arbitrarily selected within the range of 1-150nm;
  • the components of the front passivation layer 3 include, but are not limited to, aluminum oxide ( AlOx ), silicon oxide ( SiOx ), or a combination thereof, and the thickness is arbitrarily selected within the range of 1-40nm.
  • the components of the doped oxide layer 6 include but are not limited to silicon oxide (SiO x ), and the thickness can be arbitrarily selected within 1-2 nm;
  • the back crystalline silicon layer 7 can be a polycrystalline silicon layer or an amorphous silicon layer, and the components include but are not limited to Si, and the thickness can be arbitrarily selected within 1-200 nm;
  • the components of the back anti-reflection layer 8 include but are not limited to any one of silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), and silicon oxide (SiO x ), or a combination of any two or three thereof, and the thickness can be arbitrarily selected within 1-100 nm.
  • the front-side structure involved in this application can reduce the recombination current in the front-side non-metal contact area from 20-40fA/cm 2 to less than 8fA/cm 2 , corresponding to an increase in the battery open circuit voltage of more than 5mV; the carrier between the P-type silicon matrix and the P++ area
  • the flow adaptability is better than that of the N-type silicon matrix, and the filling factor gain of the corresponding battery is more than 1%; since there is no low-concentration boron diffusion on the front of this solution, the corresponding The quantum efficiency of the battery at short wavelengths is low and the current is low; the final efficiency gain of the battery is more than 0.5%.
  • This embodiment also provides a method for preparing the above-mentioned P-type TOPCon battery, which includes the following steps:
  • a P-type heavily doped layer 4, a front passivation layer 3, a front anti-reflection layer 2, and a front metal gate line 1 are formed on the front side of the P-type silicon wafer 5, and a doped oxide layer is formed on the back side of the P-type silicon wafer 5.
  • the solution for preparing the P++ region can be all current mainstream SE heavily doped region preparation solutions, including but not limited to, the P-type heavily doped layer 4 is doped by boron laser doping, boron paste printing doping or laser film opening boron Formed by diffusion doping.
  • the front side of the battery adopts a local burn-through contact scheme, and only metal contacts are formed in the P++ area to derive current; the metallization scheme on the back of the battery can be all current mainstream schemes, including but not limited to the local burn-through contact scheme (as shown in the above battery structure diagram ) and a full-coverage metal electrode solution on the back.
  • the sintering temperature can be selected arbitrarily between 600-1000°C.
  • the front metal grid line 1 is formed using a local burn-through contact method; the back metal grid line 9 is formed using a local burn-through contact method.
  • the back metal electrode layer can also be formed in a full coverage manner to replace the back metal gate line 9 .
  • the preparation method of P-type TOPCon battery includes the following steps:
  • the boron-containing compound is locally diffused on the front side of the silicon wafer to form a localized P Type heavily doped layer (P++ layer); form a doped silicon oxide layer and a doped amorphous silicon layer on the back of the silicon wafer; prepare an anti-reflection layer containing silicon nitride on the amorphous silicon layer; Prepare an aluminum oxide passivation layer on the front side; prepare an anti-reflection layer containing silicon nitride on the aluminum oxide passivation layer; print silver aluminum paste on the front anti-reflection layer to form a front electrode, and passivate the anti-reflection layer on the back side. Silver paste is printed on it to form the back electrode.
  • the form and shape of the equipment such as tubular or plate equipment, is not limited, nor is it limited to the equipment manufacturer and the environmental conditions used; the geometric size and specification shape of the silicon wafer are not limited; The material and shape of the silicon wafer carrying device are not limited, such as the shape and size of the graphite boat.
  • Etching Use a chain HF machine to remove the SiO2 protective layer on the back and side that is wound by PECVD, and then clean it with hydrogen peroxide and alkali solution;
  • Preparation of the backside PN junction Use tubular PECVD to prepare a doped oxide layer and a phosphorus-doped amorphous silicon layer on the back of the battery.
  • the thickness of the oxide layer is 1-2nm and the thickness of the amorphous silicon layer is 80nm;
  • Annealing Use a tubular annealing furnace to anneal the battery.
  • the annealing gas atmosphere is nitrogen (N2), the temperature is 900°C, and the time is 20 minutes, so that the deposited amorphous silicon layer crystallizes to form a polycrystalline silicon film poly-Si;
  • RCA cleaning first use chain hydrofluoric acid (HF) to remove the oxide layer that was deposited on the front side during the deposition in step 4 and the oxide layer generated during the annealing process, and then transferred to an alkali bath to remove the front poly coating layer ;
  • HF hydrofluoric acid
  • Preparation of front-side passivation and anti-reflection film Use ALD water process to deposit front-side aluminum oxide (AlO x ) passivation layer with a thickness of 4-6nm, use PECVD to deposit anti-reflection silicon nitride (SiN x ) layer, film The thickness is 85-90nm, and the cell front reflectivity is 0.9%;
  • PECVD is used to deposit a SiN x film with a thickness of about 70nm to improve the hydrogen passivation performance of the battery;
  • the above preparation method selects a silicon wafer with a resistivity of 0.5-1 ⁇ cm, uses boron paste printing to prepare the P++ heavily doped region, and uses the conventional front and back film layer preparation scheme and the local burn-through contact metallization scheme to prepare the P-type
  • the photoelectric conversion efficiency of TOPCon cells reaches more than 25.5% ("above” means close)
  • the open circuit voltage Voc can reach more than 732mV
  • the fill factor FF value can reach more than 84%.
  • This comparative example provides an N-type TOPCon battery.
  • the difference from the first embodiment is that this comparative example uses an N-type silicon wafer as the silicon substrate, and a fully covered P++ heavily doped region is prepared during the preparation process.
  • the photoelectric conversion efficiency of the N-type TOPCon cell reaches more than 24.5%, the open circuit voltage Voc can reach more than 714mV, and the fill factor FF value can reach more than 82%.
  • This comparative example provides an N-type TOPCon battery, which is different from the first embodiment in that this comparative example uses an N-type silicon wafer as the silicon substrate.
  • the photoelectric conversion efficiency of the N-type TOPCon cell reaches over 25.2%, the open circuit voltage Voc can reach over 725mV, and the fill factor FF value can reach over 83%.
  • the solar cells and their preparation methods in the embodiments of the present application have simple cell structures, short process time, high production capacity, and high cell conversion efficiency.

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Abstract

本申请实施例提供一种太阳电池及其制备方法，涉及太阳能电池领域。太阳电池包括：P型硅片，依次设置于P型硅片正面上的P型重掺杂层、正面钝化层、正面减反射层、正面金属栅线，依次设置于P型硅片背面上的掺杂氧化层、背面晶硅层、背面减反射层和背面金属电极层；P型重掺杂层对应正面金属栅线分区域设置，正面金属栅线依次穿过正面减反射层、正面钝化层，并与对应的P型重掺杂层形成接触；本申请实施例的太阳电池的结构简单，工艺时间短，产能高，电池的转换效率高。

Description

太阳电池及其制备方法
本申请要求于2022年09月23日提交中国专利局、申请号为202211170399.9、申请名称为“一种太阳电池及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及太阳能电池领域，具体而言，涉及一种太阳电池及其制备方法。
背景技术
TOPCon电池(隧穿氧化层钝化接触电池)具有很高的效率极限，接近晶硅太阳电池的理论极限效率。TOPCon电池的正面通常采用全覆盖的硼扩散工艺，其目的是为了在正面形成PN结，适配高温金属化工艺，降低金属复合保护开压，形成接触，还提供横向传输的作用，利于电流收集。另外，在诸如TOPCon电池的单晶硅太阳能电池中，正面全覆盖硼扩散发射极界面上的载流子复合较高，通常为20-40fAcm-2，限制了电池的钝化性能和开路电压，进一步导致电池效率偏低，因此界面载流子复合成为限制太阳电池效率发展的重要因素。
当前行业内普遍选用制备全覆盖硼扩散发射极的方案制备N型TOPCon电池的正面结构，通常使用管式设备进行硼扩散，先在抽真空并升至高温后，用惰性气体携一定流量的氧气进管做前氧化工艺，再携硼源做扩散工艺，接着在高温下做后氧化工艺，最后降温、破真空并出舟。这种制备全覆盖硼扩散发射极存在一些问题：1、在非金属接触区(占电池面积95％以上)下方的硅基体内的俄歇复合增加，正面的钝化性能被削弱，界面的复合电流高，通常为20-40fAcm-2；2、硼扩散工艺通常需要2-4小时，耗时长，是TOPCon电池产能的限制因素。
发明内容
本申请实施例的目的在于提供一种太阳电池及其制备方法，电池结构简单，工艺时间短，产能高，电池的转换效率高。
第一方面，本申请实施例提供了一种太阳电池，其包括：
P型硅片；
依次设置于P型硅片正面上的P型重掺杂层、正面钝化层、正面减反射层、正面金属栅线，P型重掺杂层对应正面金属栅线分区域设置，正面金属栅线依次穿过正面减反射层、正面钝化层，并与对应的P型重掺杂层形成接触；
依次设置于P型硅片背面上的掺杂氧化层、背面晶硅层、背面减反射层和背面金属电极层。
在上述技术方案中，TOPCon电池正面采用无前场方案，即选用P型硅片制备电池，在电池正面不制备全覆盖的硼扩散，仅在正面金属栅线下方针对性地设置硼重掺杂区，用于减少表面复合和形成良好金属接触。本申请的太阳电池相比于传统的N型全覆盖硼扩(金属栅线下局域重掺杂，即叠加选择性发射极)TOPCon电池至少具备三点优势：
1、由于非金属接触区界面的复合和硅基体的俄歇复合降低，电池开压大幅提升(5mV以上)。
2、虽然本申请的P型无前场结构相比于N型全覆盖硼扩结构缺少了低掺杂的硼扩层及其带来的载流子横向传输作用，但是本申请电池的填充系数(FF)更高(同等硅片电阻率1Ωcm条件下高1％)，其原因在于：正面钝化层在钝化P型硅基体(P型硅片)时比低硼扩N型硅片表现出钝化性能更好，这有利于iFF的提高，金属化后的FF值相应提高；P型硅基体有很高的空穴传导能力，空穴从背面PN结经过硅基体传导到正面高掺杂接触区过程中的电阻损耗远小于在硼扩散N型硅中传输的情况，所以FF值更高，电阻损耗随硅基体电阻率提高而增大，应控制电阻率在1Ωcm左右。
3、本申请的电池每瓦成本更低，P型硅片成本远低于N型硅片，无前场方案去除了整面硼扩的工艺，总工艺耗时更短，产能更大。
因此，本申请的电池结构简单，工艺时间短，由于正面无全覆盖发射极，钝化性能和相应开路电压大幅提升，短波上量子效率和短路电流有所下降，电池转换效率高。相比传统N型TOPCon电池，具有更高电池效率，更低电池成本，更高产能和性价比的优势，有利于推进高效双面TOPCon电池的产业化进程。
在一种可能的实现方式中，背面金属电极层为背面金属栅线，背面金属栅线依次穿过背面减反射层、背面晶硅层、掺杂氧化层，并与P型硅片形成接触。
在一种可能的实现方式中，P型硅片的电阻率为0.5-10Ωcm；
和/或，P型重掺杂层的方阻为1-120Ω/sq。
在一种可能的实现方式中，正面减反射层的组分包括氮化硅、氮氧化硅、氧化硅中的至少一种，厚度为1-150nm；
和/或，背面减反射层的组分包括氮化硅、氮氧化硅、氧化硅中的至少一种，厚度为1-100nm。
在一种可能的实现方式中，正面钝化层的组分包括氧化铝、氧化硅中的至少一种，厚度为1-40nm。
在一种可能的实现方式中，掺杂氧化层的组分包括氧化硅，厚度为1-2nm。
在一种可能的实现方式中，背面晶硅层的组分包括多晶硅或非晶硅，厚度为1-200nm。
第二方面，本申请实施例提供了一种第一方面提供的太阳电池的制备方法，其包括以下步骤：
在P型硅片的正面依次形成P型重掺杂层、正面钝化层、正面减反射层、正面金属栅线，在P型硅片的背面依次形成掺杂氧化层、背面晶硅层、背面减反射层和背面金属电极层。
在上述技术方案中，本申请中制备TOPCon电池采用P型硅片取代N型硅片，硅片价格更低，每瓦成本减少；工艺工序中减少了一步硼扩散工序，减少电池制备工艺时长2小时以上，降低了对应辅料和设备成本。
在一种可能的实现方式中，P型重掺杂层是采用硼激光掺杂、硼浆印刷掺杂或激光开膜硼扩散掺杂形成。
在一种可能的实现方式中，正面金属栅线采用局域烧穿接触方式形成；
和/或，背面金属电极层采用局域烧穿接触方式形成或全覆盖方式形成。
附图说明
为了更清楚地说明本申请的技术方案，下面将对本申请中所使用的附图作简单介绍。显 而易见地，下面所描述的附图仅仅是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据附图获得其他的附图。
图1为本申请实施例提供的一种P型TOPCon电池的结构示意图。
附图说明：1-正面金属栅线；2-正面减反射层；3-正面钝化层；4-P型重掺杂层；5-P型硅片；6-掺杂氧化层；7-背面晶硅层；8-背面减反射层；9-背面金属栅线。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
申请人发现，目前的TOPCon电池是通过高温将P型化合物(硼源)掺杂进硅片，并形成硼的浓度；在硅片中硼浓度随着进入硅片的深度而改变，通常表现为表面区域最高，形成峰值，随着推进的深度越高，硼浓度越低；通过控制硼源量、温度和时间等参数可以得到适合制备太阳能电池的掺杂曲线，掺杂后的硅片在正面P型掺杂硅和硅基体的界面形成PN结，内建电场方向由内指向外部；硼扩发射极对光照的短波相应优于裸硅片，使得电池在短波段的量子转换效率更高，短路电流更高；TOPCon电池通常使用高温烧结的金属化工艺，印刷后的银栅线在烧结过程中会烧蚀进入电池内部，穿透氧化铝层或达到氧化铝层附近，在高温下与电池形成接触结构，高浓度的硼掺杂有利于发射极与银颗粒形成良好的接触，导出电流，减少载流子的复合对开压的损失，通常硼掺杂浓度越高，金属复合越低；银浆与裸硅的接触电阻较大，一定浓度的硼掺杂有利于把接触电阻降至正常范围；在电池正面载流子被金属电极收集前，其传导路径包括硅基体内和硼扩发射极内的横向传输，当硼扩发射极的掺杂浓度越低，其方阻越高，载流子传输受到的电阻损耗越高，对应电池的串联电阻越高，填充系数 和转换效率越低。
申请人探索出通过改变TOPCon电池中硼扩发射极以解决上述技术问题。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。
第一实施例
请参看图1，本实施例提供的一种P型TOPCon电池，其包括：P型硅片5，依次设置于P型硅片5正面上的P型重掺杂层4、正面钝化层3、正面减反射层2、正面金属栅线1，依次设置于P型硅片5背面上的掺杂氧化层6、背面晶硅层7、背面减反射层8和背面金属栅线9。P型重掺杂层4对应正面金属栅线分区域设置，正面金属栅线1依次穿过正面减反射层2、正面钝化层3，并与对应的P型重掺杂层4形成接触；背面金属栅线9依次穿过背面减反射层8、背面晶硅层7、掺杂氧化层6，并与P型硅片5形成接触，该电池的PN结位于背面的掺杂氧化层6和P型硅片5之间。在其他实施例中，背面金属栅线9还可以是全覆盖于背面减反射层8的背面金属电极层。
本申请实施例中，P型硅片5的电阻率可以在0.5-10Ωcm范围内可任意选择。
从P型硅片5正面看，P型硅片5的正面形貌为绒面，无全覆盖发射极，仅在金属接触区下方局域设置有硼扩重掺杂区(P++)，即P型重掺杂层4，P型重掺杂层4(金属接触区)的方阻可以在1-120Ω/sq范围内任意选择，非接触区方阻即为P型硅片5方阻；正面减反射层2的组分包括但不限于氮化硅(SiNx)、氮氧化硅(SiOxNy)、氧化硅(SiOx)中的任意一种或任意2种或3种的组合，厚度在1-150nm内任意选择；正面钝化层3的组分包括但不限于氧化铝(AlOx)、氧化硅(SiOx)或它们的组合，厚度在1-40nm内任意选择。
从P型硅片5背面看，掺杂氧化层6的组分包括但不限于氧化硅(SiOx)，厚度可以为1-2nm内任意选择；背面晶硅层7可以为多晶硅层或非晶硅层，组分包括但不限于Si，厚度在1-200nm内任意选择；背面减反射层8的组分包括但不限于氮化硅(SiNx)、氮氧化硅(SiOxNy)、氧化硅(SiOx)中的任意一种或任意2种或3种的组合，厚度在1-100nm内任意选择。
本申请中涉及的正面结构，可以把正面非金属接触区的复合电流从20-40fA/cm2降至8fA/cm2以下，对应电池开路电压提高5mV以上；P型硅基体与P++区域的载流子适配性优于N型硅基体，对应电池的填充系数增益1％以上；由于本方案正面没有低浓度的硼扩散，对应 电池在短波长的量子效率较低，电流偏低；最终电池的效率增益为0.5％以上。
本实施例还提供一种上述的P型TOPCon电池的制备方法，其包括以下步骤：
在P型硅片5的正面依次形成P型重掺杂层4、正面钝化层3、正面减反射层2、正面金属栅线1，在P型硅片5的背面依次形成掺杂氧化层6、背面晶硅层7、背面减反射层8和背面金属栅线9。其中，制备P++区的方案可以为当前所有主流的SE重掺杂区制备方案，包括但不限于，P型重掺杂层4是采用硼激光掺杂、硼浆印刷掺杂或激光开膜硼扩散掺杂形成。电池正面采用局域烧穿接触方案，仅在P++区域形成金属接触导出电流；电池背面金属化方案可以为当前所有主流方案，包括但不限于局域烧穿接触方案(如上述电池结构图所示)和背面全覆盖金属电极方案，烧结温度在600-1000℃内可任意选择，正面金属栅线1采用局域烧穿接触方式形成；背面金属栅线9采用局域烧穿接触方式形成。在其他实施例中，还可以采用全覆盖方式形成背面金属电极层以替代背面金属栅线9。
作为一种示例，P型TOPCon电池的制备方法包括以下步骤：
在P型硅片的正面制绒；通过印刷硼化合物浆料并激光推进掺杂(或其他常规制备P型重掺杂层)的方式，对硅片正面局部扩散含硼的化合物形成局域P型重掺杂层(P++层)；在硅片的背面形成掺杂氧化硅层和掺杂非晶硅层；在非晶硅层上面制备一层含氮化硅的减反射层；在硅片的正面制备氧化铝钝化层；在氧化铝钝化层的上面制备一层含氮化硅的减反射层；在正面减反射层上面印刷银铝浆形成正面电极，在背面钝化减反射层上面印刷银浆形成背面电极。
在本申请的P型TOPCon电池的制备方法中，不限定设备形式何形状，如管式或者板式设备，也不限定于设备厂家和使用的环境条件；不限定硅片的几何尺寸和规格形状；不限定硅片承载装置的材质和形状，比如石墨舟的形状和大小。
本实施例中，P型TOPCon电池的制备方法具体过程如下：
(1)制绒：选用电阻率0.5-1Ωcm的P型硅片，采用1％的KOH碱液进行制绒，使用双氧水和碱液清洗硅片；
(2)制备P++重掺杂区：使用PECVD管式设备在硅片表面生长100nm SiO2保护层，印刷硼浆料(与金属化图形一致)，使用激光轰击硼浆区进行局域重掺杂，掺杂后P++区方阻 为40Ω/sq；
(3)刻蚀：采用链式HF机去除背面和侧面受PECVD绕度的SiO2保护层，再过双氧水和碱液进行清洗；
(4)制备背面PN结：采用管式PECVD在电池背面制备掺杂氧化层和磷掺杂非晶硅层，氧化层厚度为1-2nm，非晶硅层厚度为80nm；
(5)退火：采用管式退火炉，对电池进行退火，退火气体氛围为氮气(N2)，温度为900℃，时间为20分钟，使得沉积的非晶硅层结晶形成多晶硅薄膜poly-Si；
(6)RCA清洗：先经过链式氢氟酸(HF)，去除步骤4步中沉积时绕镀到正面的氧化层以及退火过程中生成的氧化层，随后转入碱槽去除正面poly绕镀层；
(7)正面钝化和减反射膜制备：采用ALD水工艺方式沉积正面氧化铝(AlOx)钝化层，厚度为4-6nm，使用PECVD沉积减反射氮化硅(SiNx)层，膜厚度为85-90nm，电池正面反射率为0.9％；
(8)背膜制备：采用PECVD沉积SiNx薄膜，厚度为70nm左右，提高电池氢钝化性能；
(9)金属化：采用丝网印刷和高温(830℃)烧结工艺制备正背面银电极；
(10)进行光注入、效率测试和分选包装。
上述制备方法选取电阻率0.5-1Ωcm的硅片，采用硼浆印刷的方式制备P++重掺杂区，使用常规的正背面膜层制备方案和局域烧穿接触的金属化方案，制备的P型TOPCon电池光电转换效率达到25.5％以上(“以上”表示接近的意思)，开路电压Voc可达732mV以上，填充系数FF值可达84％以上。
第一对比例
本对比例提供一种N型TOPCon电池，其与第一实施例的不同之处在于：本对比例采用N型硅片作为硅基底，制备过程中制备全覆盖的P++重掺杂区。
该N型TOPCon电池的光电转换效率达到24.5％以上，开路电压Voc可达714mV以上，填充系数FF值可达82％以上。
第二对比例
本对比例提供一种N型TOPCon电池，其与第一实施例的不同之处在于：本对比例采用N型硅片作为硅基底。
该N型TOPCon电池的光电转换效率达到25.2％以上，开路电压Voc可达725mV以上，填充系数FF值可达83％以上。
综上所述，本申请实施例的太阳电池及其制备方法的电池结构简单，工艺时间短，产能高，电池的转换效率高。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (18)

  1. 一种太阳电池，其特征在于，其包括：
    P型硅片；
    依次设置于所述P型硅片正面上的P型重掺杂层、正面钝化层、正面减反射层、正面金属栅线，所述P型重掺杂层对应所述正面金属栅线分区域设置，所述正面金属栅线依次穿过所述正面减反射层、所述正面钝化层，并与对应的所述P型重掺杂层形成接触；
    依次设置于所述P型硅片背面上的掺杂氧化层、背面晶硅层、背面减反射层和背面金属电极层。
  2. 根据权利要求1所述的太阳电池，其特征在于，所述背面金属电极层为背面金属栅线，所述背面金属栅线依次穿过背面减反射层、背面晶硅层、掺杂氧化层，并与所述P型硅片形成接触。
  3. 根据权利要求1或2所述的太阳电池，其特征在于，所述P型硅片的电阻率为0.5-10Ωcm。
  4. 根据权利要求1至3中任一项所述的太阳电池，其特征在于，所述P型重掺杂层的方阻为1-120Ω/sq。
  5. 根据权利要求1至4中任一项所述的太阳电池，其特征在于，所述正面减反射层的组分包括氮化硅、氮氧化硅、氧化硅中的至少一种。
  6. 根据权利要求1至5中任一项所述的太阳电池，其特征在于，所述正面减反射层的厚度为1-150nm。
  7. 根据权利要求1至6中任一项所述的太阳电池，其特征在于，所述背面减反射层的组分包括氮化硅、氮氧化硅、氧化硅中的至少一种。
  8. 根据权利要求1至7中任一项所述的太阳电池，其特征在于，所述背面减反射层的厚度为1-100nm。
  9. 根据权利要求1至8中任一项所述的太阳电池，其特征在于，所述正面钝化层的组分包括氧化铝、氧化硅中的至少一种。
  10. 根据权利要求1至9中任一项所述的太阳电池，其特征在于，所述正面钝化层的厚度为1-40nm。
  11. 根据权利要求1至10中任一项所述的太阳电池，其特征在于，所述掺杂氧化层的组分包括氧化硅。
  12. 根据权利要求1至11中任一项所述的太阳电池，其特征在于，所述掺杂氧化层的厚度为1-2nm。
  13. 根据权利要求1至12中任一项所述的太阳电池，其特征在于，所述背面晶硅层的组分包括多晶硅或非晶硅。
  14. 根据权利要求1至13中任一项所述的太阳电池，其特征在于，所述背面晶硅层的厚度为1-200nm。
  15. 一种如权利要求1至14中任一项所述的太阳电池的制备方法，其特征在于，其包括以下步骤：
    在所述P型硅片的正面依次形成所述P型重掺杂层、所述正面钝化层、所述正面减反射层、所述正面金属栅线，在所述P型硅片的背面依次形成所述掺杂氧化层、所述背面晶硅层、所述背面减反射层和所述背面金属电极层。
  16. 根据权利要求15所述的太阳电池的制备方法，其特征在于，所述P型重掺杂层是采用硼激光掺杂、硼浆印刷掺杂或激光开膜硼扩散掺杂形成。
  17. 根据权利要求15或16所述的太阳电池的制备方法，其特征在于，所述正面金属栅线采用局域烧穿接触方式形成。
  18. 根据权利要求15至17中任一项所述的太阳电池的制备方法，其特征在于，所述背面金属电极层采用局域烧穿接触方式形成或全覆盖方式形成。
PCT/CN2023/115160 2022-09-23 2023-08-28 太阳电池及其制备方法 WO2024060933A1 (zh)

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