WO2023050822A1 - 一种背接触电池的制作方法 - Google Patents

一种背接触电池的制作方法 Download PDF

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WO2023050822A1
WO2023050822A1 PCT/CN2022/092268 CN2022092268W WO2023050822A1 WO 2023050822 A1 WO2023050822 A1 WO 2023050822A1 CN 2022092268 W CN2022092268 W CN 2022092268W WO 2023050822 A1 WO2023050822 A1 WO 2023050822A1
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layer
doped
doped layer
region
electrode
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PCT/CN2022/092268
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English (en)
French (fr)
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李中兰
鲁伟明
李华
靳玉鹏
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泰州隆基乐叶光伏科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
    • H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the field of photovoltaic technology, in particular to a method for manufacturing a back contact battery.
  • a back contact battery refers to a battery in which the emitter and metal contacts are on the back of the battery, and the front is not blocked by a metal electrode. Compared with cells with a shielded front, back-contact cells have higher short-circuit current and photoelectric conversion efficiency, and are currently one of the technical directions for realizing high-efficiency crystalline silicon cells.
  • the object of the present invention is to provide a method for manufacturing a back contact battery, so as to simplify the manufacturing process of the back contact battery.
  • the present invention provides a method for manufacturing a back contact battery, comprising:
  • a substrate is provided, the substrate has opposite first surface and second surface, first surface has first doped region and second doped region alternately arranged, and is used for spacing the first doped region and second doped region the third area of the District;
  • a second interface passivation layer and a second doped layer are sequentially formed on the first mask layer, the second doped region and the third region at the same time, and the conductive layer between the second doped layer and the first doped layer is type opposite;
  • a first electrode is formed on the first doped layer, and a second electrode is formed on the second doped layer.
  • the mask layer can be formed only in the required area, avoiding the formation of unnecessary mask layer in other areas, Reduce the number of steps to remove masking layers in unnecessary areas.
  • the patterning of the second doped layer that is, the process of removing the second doped layer in the area outside the second mask layer
  • the formation of the third area are completed in the same step, which simplifies the steps.
  • the first mask layer remains on the first doped layer. Therefore, in the process of patterning the second doped layer, due to the first mask layer
  • the protective effect of the film layer on the first doped layer reduces damage to the first doped layer and ensures the conductivity of the first doped layer.
  • the first mask layer is a first oxide mask layer; and/or, the second mask layer is a second oxide mask layer.
  • Both the first mask layer and the second mask layer use an oxide mask layer, and the oxide mask layer can be directly formed by oxidation on the first doped layer and the second doped layer, and the oxide mask layer is relatively Compared with other additionally prepared mask layers, such as printing masks, the oxide mask layer has high cleanliness, does not introduce other elements, and will not cause other pollution or influence on the first doped layer and the second doped layer.
  • the oxide mask is easy to clean.
  • the method for forming the first oxide mask layer is: in an oxygen-containing atmosphere, only performing laser irradiation oxidation on the surface of the first doped layer located in the first doped region; And/or, the method for forming the second oxide mask layer is: in an oxygen-containing atmosphere, only the surface of the second doped layer located in the second doped region is oxidized by laser irradiation.
  • the oxide mask layer is directly formed on the first doped layer and the second doped layer by laser irradiation, so that the formation precision of the oxide mask layer is high, compared with that formed by external heating oxidation or PECVD method
  • the heat in the laser irradiation process is small, which reduces the damage to the first doped layer and the second doped layer.
  • the gas in the oxygen-containing atmosphere environment is: one or more of oxygen, ozone, air, CO 2 , and N 2 O.
  • the first doped layer and the second doped layer can undergo an oxidation reaction with the gas by laser irradiation, and an oxide mask layer is formed on the surface.
  • an alkaline solution is used to remove the second doped layer and the second interface passivation layer located on the first mask layer and the third region, and the same alkaline solution is used to continue the third layer on the first surface.
  • the region and the second surface simultaneously form a textured structure.
  • the multiple processes of patterning the second doped layer, patterning the third region and texturing the second surface of the substrate can be completed simultaneously in the same step using the same alkaline solution.
  • the process steps are greatly reduced.
  • the suede structure in the third area increases the level of light trapping on the back of the back-contact battery and improves the power generation.
  • the process of texturing the second surface is placed after the formation of the first doped layer and the second doped layer, so as to ensure the integrity of the textured structure of the second surface and its light-trapping performance.
  • an alkaline solution of KOH, NaOH or tetramethylammonium hydroxide with a mass percentage of 1wt% to 5wt% is used to remove the The second doped layer and the second interface passivation layer on the upper surface, and use the same alkaline solution to continue to form a textured structure on the third region of the first surface and the second surface at the same time.
  • the first electrode is formed on the first doped layer
  • the second electrode is formed on the second doped layer, which specifically includes the steps of:
  • a first electrode is formed on the first surface passivation layer located on the first doped layer, a second electrode is formed on the first surface passivation layer located on the second doped layer, and the first electrode is electrically connected to the first doped layer. In contact, the second electrode is in electrical contact with the second doped layer.
  • the first mask layer and the second mask layer can be removed to improve the Conductive contact performance between a doped layer and the first electrode, and between the second doped layer and the second electrode.
  • the first surface passivation layer can passivate the surface of the back contact cell, passivate the dangling bonds at the first doped layer, the second doped layer and the third region, and reduce the carrier recombination speed of the first surface, Improve photoelectric conversion efficiency.
  • the first electrode and the second electrode are in electrical contact with the first doped layer and the second doped layer through the first opening and the second opening respectively, forming a local ohmic contact between the metal and the semiconductor, reducing the contact between the metal electrode and the first doped layer.
  • the contact area between the impurity layer and the second doped layer reduces the contact resistance, further reduces the recombination rate of carriers at the electrode surface, and increases the open circuit voltage.
  • the first mask layer and the second mask layer are removed using an etching solution containing fluorine.
  • the mask layer, especially the oxide mask layer, can be easily removed by an etching solution containing fluorine; and/or
  • the step of simultaneously forming a first surface passivation layer on the first doped layer, the second doped layer and the third region it also includes forming a second surface passivation layer on the second surface.
  • the formation of the second surface passivation layer and the formation of the first surface passivation layer are in the same step, which simplifies the steps, and the second surface passivation layer has the effect of reducing incident light reflection and passivation.
  • the formation method of the first doped layer and the second doped layer is an in-situ doping method or an ex-situ doping method.
  • a step is further included: performing a heat treatment process, the heat treatment process combines the first doped layer and the second electrode /or at least a portion of the second doped layer is crystallized.
  • the heat treatment makes the first interface passivation layer and the second interface passivation layer more conducive to carrier selectivity and transport; Heating can make the dopant element enter into the first interface passivation layer and the second interface passivation layer and the substrate, thereby reducing the transmission resistance.
  • FIG. 1 is a schematic structural diagram of a back contact battery provided by an embodiment of the present invention
  • FIGS. 2 to 10 are schematic diagrams of the states of each stage of the manufacturing process of the back contact battery provided by the embodiment of the present invention.
  • Fig. 11 is a schematic diagram of the principle of laser irradiation used in a manufacturing method of a back contact battery provided by an embodiment of the present invention.
  • FIG. 12 is a schematic flowchart of a method for manufacturing a back contact battery provided by an embodiment of the present invention.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • plurality means two or more, unless otherwise specifically defined. "Several” means one or more than one, unless otherwise clearly and specifically defined.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it may be mechanical connection or electrical connection; it may be direct connection or indirect connection through an intermediary, and it may be the internal communication of two elements or the interaction relationship between two elements. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.
  • a solar cell is a device that converts the sun's light energy into electrical energy.
  • Solar cells use the principle of photovoltaics to generate carriers, and then use electrodes to extract the carriers, which is beneficial to the effective use of electrical energy.
  • Interdigitated back contact battery also known as IBC battery.
  • IBC Interdigitated back contact
  • the biggest feature of the IBC battery is that the emitter and the metal contact are on the back of the battery, and the front is not affected by the shielding of the metal electrode, so it has a higher short-circuit current Isc, and the back can allow wider metal grid lines to reduce the series resistance Rs. Improve the fill factor FF; and this kind of battery with no shielding on the front not only has high conversion efficiency, but also looks more beautiful, and at the same time, the assembly of the full back electrode is easier to assemble.
  • IBC battery is one of the technical directions to realize high-efficiency crystalline silicon battery at present.
  • the embodiment of the present invention provides a manufacturing method of the back contact battery, including the following steps:
  • Step S100 providing a substrate 10, the substrate 10 has a first surface and a second surface opposite to each other, the first surface has first doped regions 101 and second doped regions 102 arranged alternately, and is used to space the first doped regions the third region 103 of the impurity region 101 and the second doped region 102;
  • Step S200 sequentially forming a first interface passivation layer 14 and a first doped layer 11 on the first surface of the substrate 10;
  • Step S300 as shown in FIG. 3 , forming a first mask layer 16 only on the surface of the first doped layer 11 located in the first doped region 101 ;
  • Step S400 removes the first doped layer 11 and the first interface passivation layer 14 located in the second doped region 102 and the third region 103;
  • the first doped layer 11 is removed by a wet etching method, and the wet etching method includes: an alkaline solution or an acidic solution etching method.
  • Dry etching methods include: plasma etching methods.
  • the speed of removing the second doped region 102 and the third region 103 of the first doped layer 11 and the first interface passivation layer 14 is faster than the speed of removing the first mask layer 16 .
  • etching by using a method with different etching speeds can well realize the masking function of the first mask layer 16 .
  • step S500 as shown in FIG. 5, the second interface passivation layer 15 and the second doped layer 12 are sequentially formed on the first mask layer 16, the second doped region 102 and the third region 103 simultaneously, and the second doped
  • the conductivity type of the impurity layer 12 is opposite to that of the first doped layer 11;
  • Step S600 as shown in FIG. 6, forming a second mask layer 17 only on the surface of the second doped layer 12 located in the second doped region 102;
  • step S700 as shown in FIG. 7, the second doped layer 12 and the second interface passivation layer 15 located on the first mask layer 16 and the third region 103 are removed, and only the second doped layer 15 located on the second doped region 102 remains.
  • step S800 as shown in FIG. 10 , a first electrode 20 is formed on the first doped layer 11 , and a second electrode 21 is formed on the second doped layer 12 .
  • the alkali solution is blocked by the first mask layer 16, so the alkali solution cannot damage the first doped layer 11 of the first doped region 101, and due to the protective effect of the first mask layer 16 on the first doped layer 11, the completion
  • the patterned preparation of the first doped region 101 and the second doped region 102 is improved, the damage to the first doped layer 11 is reduced, and the conductivity of the first doped layer 11 is ensured.
  • the substrate 10 is a semiconductor substrate 10 .
  • the material of the substrate 10 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs).
  • the substrate 10 can be an intrinsically conductive substrate, an n-type conductive substrate or a p-type conductive substrate. type conductive substrate.
  • the substrate 10 is a p-type conductive substrate or an n-type conductive substrate. Compared with the intrinsically conductive substrate, the p-type conductive substrate or the n-type conductive substrate has better conductivity, so that the final back-contact battery has lower volume resistivity, thereby improving the efficiency of the back-contact battery.
  • the first doped layer 11 and the second doped layer 12 are also semiconductor doped layers.
  • the first doped layer 11 and the second doped layer 12 may be amorphous, microcrystalline, single crystal, nanocrystalline or polycrystalline.
  • the materials of the first doped layer 11 and the second doped layer 12 may be silicon (Si), germanium (Ge), silicon carbide (SiC x ) or gallium arsenide (GaAs) and the like.
  • the first doped layer 11 and the second doped layer 12 may be n-type doped layers or p-type doped layers.
  • the first doped layer 11 when the substrate 10 is an n-type substrate, the first doped layer 11 can be a p-type doped layer, and the second doped layer 12 can be an n-type doped layer; or, when the substrate 10 is a p-type When forming a substrate, the first doped layer 11 may be an n-type doped layer, and the second doped layer 12 may be a p-type doped layer.
  • the first interface passivation layer 14 and the second interface passivation layer 15 are tunnel oxide layers.
  • the tunneling oxide layer allows many carriers to tunnel into the semiconductor doped layer while blocking minority carriers from passing through, and then many carriers are transported laterally in the semiconductor doped layer and collected by electrodes, reducing the recombination of carriers and improving the open circuit voltage of the back contact cell and short circuit current.
  • the tunnel oxide layer and the semiconductor doped layer form a passivation contact structure of the tunnel oxide layer, which can achieve excellent interface passivation and selective collection of carriers, and improve the photoelectric conversion efficiency of the back contact cell.
  • the tunnel oxide layer can also be replaced by other interface passivation layers.
  • the first interface passivation layer 14 and the second interface passivation layer 15 can be one or more of oxide, nitride, carbide, hydrogenated amorphous silicon; wherein, the oxide can be silicon oxide, nitride A mixture of one or more of silicon oxide, aluminum oxide, titanium oxide, HfO 2 , Ga 2 O 3 , Ta 2 O 5 , Nb 2 O 5 ; wherein, the nitride can be silicon nitride, aluminum nitride, One or more of TiN and TiCN; wherein, the carbide can be SiC, SiCN, etc.
  • the thickness ranges of the first doped layer 11 and the second doped layer 12 are both 50 nm ⁇ 500 nm.
  • the process of forming the first interface passivation layer 14 and the first doped layer 11 on the substrate 10 and the process of forming the second doped layer 12 on the first mask layer 16, the second doped region 102 and the third region 103 The process may be a plasma chemical vapor deposition (PECVD) process, a hot wire chemical vapor deposition process, a physical vapor deposition (PVD) process, a low pressure chemical vapor deposition (LPCVD) process or a catalytic chemical vapor deposition process.
  • PECVD plasma chemical vapor deposition
  • PVD physical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • the layer 12 can be laser etching process, ion milling etching process, plasma etching process, reactive ion etching process, alkali etching process and acid etching process, etc.
  • the passivation film can be coated directly with fire-through slurry, and then heat-treated so that the electrode slurry passes through the passivation film to form contact. It is also possible to form a passivation film opening on a small part of the area to be contacted, and then use electrode paste, laser transfer method, electroplating, electroless plating, light-induced electroplating, or physical vapor deposition such as evaporation and sputtering and other methods to form electrodes.
  • one or a combination of the above methods can also be used to form electrodes.
  • the method of using PVD seed layer with printing electrodes or the method of screen printing electrode paste with electroplating, or the combination of laser transfer printing method and screen printing sintering method, etc.
  • a passivation film is used to form a contact region, a P-type contact region is formed on the patterned first doped layer 11, and an N-type contact region is formed on the patterned second doped layer 12. type contact area.
  • a conductive paste is printed on the contact area or rear passivation film and sintered to form metallized contacts.
  • a P-type metal region is formed on the P-type contact region, and an N-type metal region is formed on the N-type contact region.
  • the electrodes may be formed, there may be other steps, such as light injection or electrical injection of carriers or other heat treatment processes, as well as steps of efficiency binning or slicing.
  • the IBC battery with passivation contact structure prepared by this method has good passivation effect, small metal area recombination, simple process flow, no mask layer formed by external heating oxidation or PECVD method, and the mask layer formation process and patterning process are combined. Combine.
  • a two-step laser oxidation process is used to form a rear PN passivation contact intersection structure with isolation regions, which greatly reduces the recombination of the PN direct junction region, thereby improving the efficiency of the battery.
  • the first mask layer 16 is a first oxide mask layer; and/or, the second mask layer 17 is a second oxide mask layer. Since the first mask layer 16 and the second mask layer 17 both use an oxide mask layer, the oxide mask layer can be directly formed by oxidation on the first doped layer 11 and the second doped layer 12, and the oxidation Compared with other additionally prepared mask layers, such as printing masks, the oxide mask layer has high cleanliness and does not introduce other elements, which will not bring other elements to the first doped layer and the second doped layer. pollution or impact. The oxide mask is easy to clean.
  • the oxide mask is specifically: when the first doped layer 11 and the second doped layer 12 are SiC and Si, the formed oxide mask is a SiO x layer, and the first doped layer 11 and the second doped layer When the doped layer 12 is germanium, the formed oxide mask layer is GeO x .
  • the formation method of the first oxide mask layer is: in an atmosphere containing oxygen, only on the surface of the first doped layer 11 located in the first doped region 101 Oxidation formation by laser irradiation; and/or, the formation method of the second oxide mask layer is: in an oxygen-containing atmosphere environment, laser irradiation is only performed on the surface of the second doped layer 12 located in the second doped region 102 Formed according to oxidation.
  • the oxide mask layer is directly formed on the first doped layer 11 and the second doped layer 12 by laser irradiation, the formation precision of the oxide mask layer is high, compared with the method formed by external heating oxidation or PECVD For the mask layer, the heat in the laser irradiation process is small, which reduces the damage to the first doped layer 11 and the second doped layer 12 .
  • the oxygen-containing atmosphere gas in the oxygen-containing atmosphere environment is: one or more of oxygen, ozone, air, CO 2 , and N 2 O.
  • Other ambient gases or carrier gases, such as nitrogen, may also be included.
  • the first doped layer 11 and the second doped layer 12 can undergo an oxidation reaction with the gas through laser irradiation to form an oxide mask layer on the surface.
  • the wavelength range of the laser is 190nm-545nm.
  • step S700 the second doped layer 12 and the second interface passivation located on the first mask layer 16 and the third region 103 are specifically removed by using an alkaline solution.
  • layer 5 and in this step, use the same alkaline solution to continue to form the textured structure on the third region 103 of the first surface and the second surface of the substrate 10 at the same time.
  • the patterning of the second doped layer 12 the patterning of the third region 103 and the texturing of the second surface of the substrate 10 can be performed simultaneously in the same step using the same alkaline solution.
  • the process steps are greatly reduced.
  • the suede structure of the third region 103 increases the light trapping level on the back of the back contact cell, for example, when the back contact cell is applied to a bifacial module, it increases the power generation.
  • the second surface texturing is usually performed before the formation of the doped semiconductor layer, and it is easy to cause damage to the second surface texturing during the patterning or cleaning process of the doped semiconductor layer.
  • the process of texturing the second surface in the present invention is placed after the formation of the first doped layer 11 and the second doped layer 12 to ensure the integrity of the textured structure of the second surface and its light-trapping performance.
  • the textured structure of the second surface is a nano-textured structure
  • various cleaning processes and patterning processes will almost certainly destroy the textured structure of the nano-textured surface.
  • the textured structure of the light-receiving surface using nano-microstructures has become more and more widely used, so the advantages of post-texturing methods have become more prominent.
  • the nano-textured textured structure has a better light trapping effect, and since the light-receiving surface of the back-contact cell has no electrodes, the color of the second surface will be more beautiful after applying the nano-textured textured structure on the back-contact cell . Therefore, the nano-textured textured structure is more suitable for back contact batteries.
  • an alkaline solution of KOH, NaOH or tetramethylammonium hydroxide with a mass percentage of 1 wt % to 5 wt % is used to remove the first mask layer 16 and the second mask layer 16 .
  • forming the first electrode 20 on the first doped layer 11 in step S800 and forming the second electrode 21 on the second doped layer 12 specifically includes the steps :
  • Step S801 removing the first mask layer 16 on the first doped layer 11 and the second mask layer 17 on the second doped layer 12 .
  • step S700 since the first mask layer 16 remains on the first doped layer 11 and the second mask layer 17 remains on the second doped layer 12, the first mask layer 16 and the After the second mask layer 17 finishes protecting the first doped layer 11 and the second doped layer 12 , the first mask layer 16 and the second mask layer 17 can be removed first, and subsequent electrode fabrication is performed.
  • Step S802 forming a first surface passivation layer 13 on the first doped layer 11 , the second doped layer 12 and the third region 103 at the same time.
  • Step S803 forming the first electrode 20 on the first surface passivation layer 13 located in the first doped layer 11, forming the second electrode 21 on the first surface passivation layer 13 located in the second doped layer 12, the second An electrode 20 is in electrical contact with the first doped layer 11 , and a second electrode 21 is in electrical contact with the second doped layer 12 .
  • the first mask layer 16 and the second mask layer 17 can be removed to improve the first doped layer.
  • the first surface passivation layer 13 can passivate the surface of the back contact cell, passivate the dangling bonds at the first doped layer 11, the second doped layer 12 and the third region 103, and reduce the current carrying capacity of the first surface Sub-recombination speed, improve photoelectric conversion efficiency.
  • the first electrode 20 and the second electrode 21 are in electrical contact with the first doped layer 11 and the second doped layer 12 respectively through the first opening 130 and the second opening 131 to form a local ohmic contact between the metal and the semiconductor, reducing the The contact area between the metal electrode and the first doped layer 11 and the second doped layer 12 reduces the contact resistance, further reduces the recombination rate of carriers at the electrode surface, and increases the open circuit voltage.
  • the process for forming the first surface passivation layer 13 may be a plasma chemical vapor deposition (PECVD) process, a hot wire chemical vapor deposition process, a physical vapor deposition (PVD) process, a low pressure chemical vapor deposition (LPCVD) process or catalytic chemical vapor deposition process, etc.
  • PECVD plasma chemical vapor deposition
  • PVD physical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • catalytic chemical vapor deposition process etc.
  • the back contact cell has a first surface passivation layer 13
  • the method for forming the first electrode 20 and the second electrode 21 can also be coating the electrode slurry on The first surface passivation layer 13 is then sintered, so that the electrode paste passes through the first surface passivation layer 13 to form electrical contact with the second doped layer 12 respectively.
  • the method for forming the first electrode 20 and the second electrode 21 can also be to first passivate the first surface
  • the first opening 130 and the second opening 131 are opened on the layer 13, and then physical vapor deposition such as printing paste, laser transfer method, electroplating, electroless plating, light-induced electroplating, or vacuum evaporation, magnetron sputtering, etc.
  • the method forms the first electrode 20 and the second electrode 21 in partial contact.
  • the hole opening method may include laser film opening, or using an etching slurry that can react with the first surface passivation layer 13 to open a film.
  • the method of making electrical contact through openings can enable the back contact cell to obtain lower metal region recombination, ensuring high conversion efficiency of the back contact cell.
  • the first electrode 20 and the second electrode 21 can also be formed by using one or a combination of the above methods.
  • the first electrode 20 is formed on the first doped layer 11, and the second electrode 21 is formed on the second doped layer 12, specifically: on the first doped layer 11.
  • the first electrode 20 is in electrical contact with the second doped layer 121 through the first opening 130, and the second electrode 21 is in electrical contact with the third doped layer 121 through the second opening 131.
  • the doped layer 122 is in electrical contact.
  • first electrode 20 and the second electrode 21 there may be other steps.
  • light injection or electric carrier injection or other heat treatment processes as well as steps such as efficiency binning or slicing.
  • the step of forming the third region 103 may be performed before the formation of the first surface passivation layer 13 .
  • the step of forming the third region 103 can also be arranged after the preparation of the outer back contact cell, but this will sacrifice the partial passivation of the third region 103 .
  • the first mask layer 16 and the second mask layer 17 may be removed using an etching solution containing fluorine.
  • a solution containing HF or NH 4 F can be used to remove the silicon oxide layer, which can be easily removed by an etching solution containing fluorine.
  • the second doped layer 12 and the third region 103 in step S802 in the step of simultaneously forming the first surface passivation layer 13 on the first doped layer 11, the second doped layer 12 and the third region 103 in step S802, it also includes forming The second surface passivation layer 18 .
  • the formation of the second surface passivation layer 18 and the formation of the first surface passivation layer 13 are in the same step, which simplifies the steps, and the second surface passivation layer 18 has the effect of reducing incident light reflection and passivation.
  • the process for forming the second surface passivation layer 18 may be a plasma chemical vapor deposition (PECVD) process, a hot wire chemical vapor deposition process, a physical vapor deposition (PVD) process, a low pressure chemical vapor deposition (LPCVD) process or a catalytic chemical vapor deposition process, etc.
  • PECVD plasma chemical vapor deposition
  • PVD physical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • catalytic chemical vapor deposition process etc.
  • an anti-reflection layer may also be formed on the second surface passivation layer 18 .
  • the anti-reflection layer can reduce the reflection of the light incident on the second surface, increase the refraction of the light, increase the utilization rate of the light incident on the second surface, and then improve the photoelectric conversion efficiency of the back contact cell.
  • the surface passivation layer and the antireflection layer can be composed of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon.
  • the formation method of the first doped layer 11 and the second doped layer 12 is an in-situ doping method or an ex-situ doping method. That is, the first doped layer 11 and the doped film layer 12 can be directly formed, or the intrinsic semiconductor layer and the intrinsic semiconductor film layer can be formed first, and then doped to form the first doped layer 11 and the doped film layer 12 respectively.
  • a step is further included: performing a heat treatment process, the heat treatment process will At least a part of the first doped layer 11 and/or the second doped layer 12 is crystallized. Specifically, heat treatment can be performed on the p-type or n-type semiconductor layer, so that the dopant is further distributed, or the structure of the semiconductor layer is changed, which is more conducive to the improvement of battery performance.
  • heating and annealing can crystallize at least a part of the first doped layer 11 and/or the second doped layer 12 , improving the electrical conductivity of the first doped layer 11 and the second doped layer 12 .
  • heating and annealing can also make the first interface passivation layer 14 and the second interface passivation layer 15 (such as the tunneling oxide layer) more conducive to the selective transport of carriers; heating can also make doping elements enter the tunneling layer. Through the oxide layer and the substrate 10, thereby reducing the transfer resistance.
  • this embodiment provides a specific manufacturing process of the n-type back-contact battery:
  • Step 1 provide an n-type silicon substrate 10, and then perform polishing, cleaning and other damage removal treatments on the n-type silicon substrate 10 in sequence.
  • a PECVD device is used to deposit a layer of silicon oxide tunneling oxide layer and a boron-doped p-type polysilicon layer, and the silicon oxide tunneling oxide layer serves as The first interface passivation layer 14 and the boron-doped p-type polysilicon layer serve as the first doped layer 11 .
  • the fourth step is to remove the p-type polysilicon layer and the silicon oxide tunnel oxide layer located in the second doped region 102 and the third region 103 by using an alkali etching process, only on the first doped region 101 Forming a first doped layer 11 and a first interface passivation layer 14, the thickness of the first doped layer 11 is 200nm;
  • the fifth step is to deposit a layer of silicon oxide tunnel oxide layer and phosphorus-doped n-type polysilicon layer, the silicon oxide tunneling oxide layer is used as the second interface passivation layer 15, and the phosphorus-doped n-type polysilicon layer is used as the second doped layer 12;
  • the second doped layer 12 located on the third region 103 and the first oxide mask layer is removed by an alkali etching process, and only the second doped layer 12 located on the second doped region 102 remains.
  • Two interface passivation layer 15 and the second doped layer 12 the thickness of the second doped layer 12 is 200nm; at the same time, use the same alkaline solution to texture the third region 103 and the second surface to form a textured structure .
  • the first oxide mask layer and the second oxide mask layer are removed using a fluorine-containing solution.
  • a layer of silicon nitride is deposited on the first doped layer 11, the third region 103 and the second doped layer 12 as the first surface passivation layer 13 by using PECVD equipment, and at the same time A layer of silicon nitride is deposited on the textured structure of the second surface as the second surface passivation layer 18 .
  • the tenth step is to open a first opening 130 with a laser on the first surface passivation layer 13 at the first doped region 101, and then form a first electrode 20 by printing a conductive paste,
  • the first electrode 20 is in electrical contact with the first doped layer 11 through the first opening 130; on the first surface passivation layer 13 at the second doped region 102, a second opening 131 is opened by laser, and then printed conductive
  • the second electrode 21 is formed by using a paste method, and the second electrode 21 is in electrical contact with the second doped layer 12 through the second opening 131 to form a back contact cell as shown in FIG. 1 .
  • Both the first electrode 20 and the second electrode 21 are local contact electrodes with a width of 50 ⁇ m.
  • the width of the first doped regions 101 is greater than the width of the second doped regions 102 .
  • the width of the first doped region 101 is 600 ⁇ m ⁇ 2000 ⁇ m.
  • the width of the second doped region 102 is 200 ⁇ m ⁇ 1000 ⁇ m.
  • the width of the first doped layer 11 on the first doped region 101 is larger than the width of the second doped layer 12 on the second doped region 102, and the width range of the formed pn junction is also larger, that is, the carrier
  • the separation area is relatively large, which is conducive to the separation of carriers, thereby improving the photoelectric conversion efficiency of the battery.
  • the width of the first doped region 101 is between 600 ⁇ m and 1500 ⁇ m
  • the width of the second doped region 102 is between 200 ⁇ m and 800 ⁇ m.
  • the width of the first doped region 101 may be 600 ⁇ m, and the width of the second doped region may be 500 ⁇ m; or, the width of the first doped region 101 may be 2000 ⁇ m, and the width of the second doped region may be 200 ⁇ m; or, the width of the first doped region 101 may be 1400 ⁇ m, and the width of the second doped region may be 1000 ⁇ m.
  • the width of the third region 103 ranges from 10 ⁇ m to 100 ⁇ m. If the third region 103 is too wide, the effective area of the back contact cell may be wasted, and the effective carriers are difficult to be collected, thereby reducing the performance of the cell.
  • the third region 103 is arranged between the first doped region 101 and the second doped region 102, so that the first doped region 101 and the second doped region 102 are separated from each other at the boundary, canceling the conventional
  • the design of the insulator between the electrode and the negative electrode can reduce the production process and also reduce the space complexity. Such a structure does not have the coexistence of positive and negative electrodes in the vertical direction, avoiding the leakage of back-contact batteries; and can improve the reliability performance of batteries in later products and reduce the difficulty of the production process of back-contact batteries.
  • the width of the third region may be 10 ⁇ m, or 100 ⁇ m, or 60 ⁇ m.
  • the surface of the first doped region 101 and/or the surface of the second doped region 102 is a polished surface.
  • the surfaces of the first doped region 101 and the second doped region 102 can be polished surfaces, so that the light incident from the second surface and passing through the back-contact cell is re-reflected, so that the light has a chance to be back-contacted.
  • the battery is reused, thereby improving the photoelectric conversion efficiency of the back contact cell.
  • the polished surface has better flatness, and the effect of forming other layers on the polished surface will be better, which is beneficial to reduce the generation of interface defects, thereby reducing the recombination of carriers caused by defects, which is beneficial to the background
  • the improvement of the passivation performance of the contact cell improves the photoelectric conversion efficiency of the back contact cell.
  • the IBC battery with passivation contact structure prepared by this method has good passivation effect, small metal area recombination, simple process flow, no mask layer formed by external heating oxidation or PECVD method, and the mask layer formation process and patterning process are combined. Combine.
  • a laser oxidation process is used to form a rear PN passivation contact intersection structure with a third region, which greatly reduces the recombination of the PN direct junction region, thereby improving the efficiency of the battery.
  • specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in an appropriate manner.

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Abstract

本发明公开一种背接触电池的制作方法，涉及光伏技术领域，用于简化制作工艺。制作方法包括：提供一基底；在基底的第一表面上依次形成第一界面钝化层和第一掺杂层；仅在位于第一掺杂区的第一掺杂层的表面形成第一掩膜层；去除位于第二掺杂区和第三区域上的第一掺杂层和第一界面钝化层；在第一掩膜层、第二掺杂区和第三区域上同时依次形成第二界面钝化层和第二掺杂层，第二掺杂层与第一掺杂层的导电类型相反；仅在位于第二掺杂区的第二掺杂层的表面形成第二掩膜层；去除位于第一掩膜层和第三区域上的第二掺杂层和第二界面钝化层，只保留位于第二掺杂区的第二界面钝化层和第二掺杂层；在第一掺杂层上形成第一电极，在第二掺杂层上形成第二电极。

Description

一种背接触电池的制作方法
相关申请的交叉引用
本公开要求在2021年9月30日提交中国专利局、申请号为202111165394.2、名称为“一种背接触电池的制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本发明涉及光伏技术领域，尤其涉及一种背接触电池的制作方法。
背景技术
背接触电池指发射极和金属接触都处于电池的背面，正面没有金属电极遮挡的电池。与正面有遮挡的电池相比，背接触电池具有更高的短路电流和光电转换效率，是目前实现高效晶体硅电池的技术方向之一。
现有的背接触电池的制备方法较为复杂，步骤繁琐，因此需要一种简单并且保证高效率的太阳电池的制备方法。
发明内容
本发明的目的在于提供一种背接触电池的制作方法，以简化背接触电池的制作工艺。
第一方面，本发明提供一种背接触电池的制作方法，包括：
提供一基底，基底具有相对的第一表面和第二表面，第一表面上具有交错排列的第一掺杂区和第二掺杂区，以及用于间隔第一掺杂区和第二掺杂区的第三区域；
在基底的第一表面上依次形成第一界面钝化层和第一掺杂层；
仅在位于第一掺杂区的第一掺杂层的表面形成第一掩膜层；
去除位于第二掺杂区和第三区域上的第一掺杂层和第一界面钝化层；
在第一掩膜层、第二掺杂区和第三区域上同时依次形成第二界面钝化层和第二掺杂层，所述第二掺杂层与所述第一掺杂层的导电类型相反；
仅在位于第二掺杂区的第二掺杂层的表面形成第二掩膜层；
去除位于第一掩膜层和第三区域上的第二掺杂层和第二界面钝化层，只保留位于第二掺杂区的第二界面钝化层和第二掺杂层；
在第一掺杂层上形成第一电极，在第二掺杂层上形成第二电极。
采用上述技术方案的情况下，第一掺杂层和第二掺杂层在进行图形化的过程中，可以仅在需要的区域形成掩膜层，避免在其他区域形成不必要的掩膜层，减少去除非必要区域掩膜层的步骤。且在第二掺杂层的图形化(即去除第二掩膜层之外区域的第二掺杂层的过程)和第三区域的形成在同一个步骤中完成，减化了步骤。此外，在制作第二掺杂层以及第二掺杂层图形化时，第一掺杂层上始终保留第一掩膜层，因此，第二掺杂层图形化的过程中，由于第一掩膜层对第一掺杂层的保护作用，减少了对第一掺杂层的损伤，确保了第一掺杂层的导电性能。
在一些可能的实现方式中，第一掩膜层为第一氧化物掩膜层；和/或，第二掩膜层为第二氧化物掩膜层。第一掩膜层和第二掩膜层均采用氧化物掩膜层，氧化物掩膜层可以直接在第一掺杂层和第二掺杂层上通过氧化形成，且氧化物掩膜层相对于其他另外制备的掩膜层，如印刷掩膜，氧化物掩膜层清洁度高，未引入其他元素，不会对第一掺杂层和第二掺杂层带来其他的污染或者影响。氧化物掩膜易于清洗。
在一些可能的实现方式中，第一氧化物掩膜层的形成方法为：在含氧气氛环境下，仅在位于第一掺杂区的第一掺杂层的表面进行激光辐照氧化形成；和/或，第二氧化物掩膜层的形成方法为：在含氧气氛环境下，仅在位于第二掺杂区的第二掺杂层的表面进行激光辐照氧化形成。如此设置，通过激光辐照直接在第一掺杂层和第二掺杂层上形成氧化物掩膜层，使得氧化物掩膜层的形成精度高，相较于外加热氧化或者PECVD方法形成的掩膜层，激光辐照过程的热量小，减小了对第一掺杂层和第二掺杂层的损伤。
在一些可能的实现方式中，含氧气氛环境下的气体为：氧气、臭氧、空气、CO 2、N 2O中的一种或多种。在此含氧气氛环境下，通过激光辐照，使得第一掺杂层和第二掺杂层能够与气体发生氧化反应，在表面形成氧化物掩膜层。
在一些可能的实现方式中，使用碱溶液去除位于第一掩膜层和第三区域上的第二掺杂层和第二界面钝化层，并使用同一碱溶液继续在第一表面的第 三区域和第二表面同时形成绒面结构。如此设置，第二掺杂层的图形化、第三区域的图形化和基底的第二表面的织构化多个工序可以使用同一碱溶液在同一步骤中同时完成。极大地减少了工艺步骤。第三区域的绒面结构，增加了背接触电池背面的陷光水平，提高发电量。第二表面织构化的工序，置于了形成第一掺杂成和第二掺杂层之后，保证了第二表面的绒面结构的完整性和其陷光性能。
在一些可能的实现方式中，在70℃～90℃下，使用质量百分比为1wt％～5wt％的KOH、NaOH或者四甲基氢氧化铵的碱溶液去除位于第一掩膜层和第三区域上的第二掺杂层和第二界面钝化层，并使用同一碱溶液继续在所述第一表面的第三区域和所述第二表面同时形成绒面结构。
在一些可能的实现方式中，在第一掺杂层上形成第一电极，在第二掺杂层上形成第二电极，具体包括步骤：
去除位于第一掺杂层上的第一掩膜层和位于第二掺杂层上的第二掩膜层；
在第一掺杂层、第二掺杂层和第三区域同时形成第一表面钝化层；
在位于第一掺杂层的第一表面钝化层上形成第一电极，在位于第二掺杂层的第一表面钝化层上形成第二电极，第一电极与第一掺杂层电接触，第二电极与第二掺杂层电接触。
采用上述技术方案的情况下，在完成第一掺杂层和第二掺杂层的图形化以及第三区域的形成后，可以将第一掩膜层和第二掩膜层去除，以提高第一掺杂层与第一电极，以及第二掺杂层与第二电极的导电接触性能。且第一表面钝化层可以对背接触电池进行表面钝化，钝化第一掺杂层、第二掺杂层和第三区域处的悬挂键，降低第一表面的载流子复合速度，提高光电转换效率。第一电极和第二电极分别通过第一开孔和第二开孔与第一掺杂层和第二掺杂层电接触，形成金属和半导体的局部欧姆接触，减少了金属电极与第一掺杂层和第二掺杂层的接触面积，降低了接触电阻，进一步降低了载流子在电极表面处的复合速率，提高了开路电压。
在一些可能的实现方式中，使用含氟元素的刻蚀溶液去除第一掩膜层和第二掩膜层。通过含氟元素的刻蚀溶液能够较为容易地去除掩膜层，特别是氧化物掩膜层；和/或
在第一掺杂层、第二掺杂层和第三区域同时形成第一表面钝化层的步骤 中，还包括在第二表面形成第二表面钝化层。如此设置，第二表面钝化层的形成与第一表面钝化层的形成在同一步骤中，简化了步骤，且第二表面钝化层具有减少入光反射和钝化的效果。
在一些可能的实现方式中，第一掺杂层和第二掺杂层的形成方法为原位掺杂方法或者非原位掺杂方法。
在一些可能的实现方式中，在第一掺杂层上形成第一电极和在第二掺杂层上形成第二电极之前，还包括步骤：进行热处理过程，热处理过程将第一掺杂层和/或第二掺杂层的至少一部分晶化。如此设置，提高了第一掺杂层和/或第二掺杂层的电导率，热处理使得第一界面钝化层和第二界面钝化层更有利于进行载流子选择性和传输性；加热可以使得掺杂元素进入第一界面钝化层和第二界面钝化层和基底中，从而减少传输电阻。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
此处所说明的附图用来提供对本发明的进一步理解，构成本发明的一部分，本发明的示意性实施例及其说明用于解释本发明，并不构成对本发明的不当限定。在附图中：
图1为本发明实施例提供的一种背接触电池的结构示意图；
图2～图10为本发明实施例提供的背接触电池制作流程的各个阶段状态示意图；
图11为本发明实施例提供的一种背接触电池的制作方法中使用的激光辐照原理示意图；
图12为本发明实施例提供的一种背接触电池的制作方法的流程示意图。
附图标记：
10-基底，                         101-第一掺杂区，
102-第二掺杂区，                  103-第三区域，
11-第一掺杂层，                   12-第二掺杂层，
13-第一表面钝化层，               131-第一开孔，
132-第二开孔，                    14-第一界面钝化层，
15-第二界面钝化层，               16-第一掩膜层，
17-第二掩膜层，                   18-第二表面钝化层，
20-第一电极，                     21-第二电极，
30-第一电极，                     301-进气口，
302-排气口
具体实施例
为了使本发明所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
需要说明的是，当元件被称为“固定于”或“设置于”另一个元件，它可以直接在另一个元件上或者间接在该另一个元件上。当一个元件被称为是“连接于”另一个元件，它可以是直接连接到另一个元件或间接连接至该另一个元件上。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。“若干”的含义是一个或一个以上，除非另有明确具体的限定。
在本发明的描述中，需要理解的是，术语“上”、“下”、“前”、“后”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相 连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
目前太阳电池作为新的能源替代方案，使用越来越广泛。太阳电池是将太阳的光能转换为电能的装置。太阳电池利用光生伏特原理产生载流子，然后使用电极将载流子引出，从而利于将电能有效利用。
指状交叉背接触电池，又称为IBC电池。其中IBC是指Interdigitated back contact(中文名称：指状交叉背接触)。IBC电池最大的特点是发射极和金属接触都处于电池的背面，正面没有金属电极遮挡的影响，因此具有更高的短路电流Isc，同时背面可以容许较宽的金属栅线来降低串联电阻Rs从而提高填充因子FF；并且这种正面无遮挡的电池不仅转换效率高，而且看上去更美观，同时，全背电极的组件更易于装配。IBC电池是目前实现高效晶体硅电池的技术方向之一。
但由于IBC电池的制备方法较为复杂，步骤繁琐。需要一种简单并且保证高效率的太阳电池的制备方法。
为了解决上述技术问题，请参考图1-图12，在保证高的光电转换效率的情况下简化背接触电池的制作工艺，本发明实施例提供一种背接触电池的制作方法，包括以下步骤：
步骤S100，提供一基底10，基底10具有相对的第一表面和第二表面，第一表面上具有交错排列的第一掺杂区101和第二掺杂区102，以及用于间隔第一掺杂区101和第二掺杂区102的第三区域103；
步骤S200，如图2所示，在基底10的第一表面上依次形成第一界面钝化层14和第一掺杂层11；
步骤S300，如图3所示，仅在位于第一掺杂区101的第一掺杂层11的表面形成第一掩膜层16；
步骤S400，如图4所示，去除位于第二掺杂区102和第三区域103的第一掺杂层11和第一界面钝化层14；具体的，可通过干法刻蚀方法或者湿法刻蚀方法去除第一掺杂层11，湿法刻蚀方法包括：碱性溶液或酸性溶液刻蚀方法。干法刻蚀方法包括：等离子刻蚀方法。其中，去除第二掺杂区102和第三区域103第一掺杂层11和第一界面钝化层14的的速度大于去除第一掩膜 层16的速度。一般来说，使用刻蚀速度有差异的方法来刻蚀，即可以很好的实现第一掩膜层16的掩膜作用。
步骤S500，如图5所示，在第一掩膜层16、第二掺杂区102和第三区域103上同时依次形成第二界面钝化层15和第二掺杂层12，第二掺杂层12与第一掺杂层11的导电类型相反；
步骤S600，如图6所示，仅在位于第二掺杂区102的第二掺杂层12的表面形成第二掩膜层17；
步骤S700，如图7所示，去除位于第一掩膜层16和第三区域103上的第二掺杂层12和第二界面钝化层15，只保留位于第二掺杂区102的第二界面钝化层15和第二掺杂层12；
步骤S800，如图10所示，在第一掺杂层11上形成第一电极20，在第二掺杂层12上形成第二电极21。
采用上述技术方案的情况下，与现有技术相比，第一掺杂层11和第二掺杂层12分别在进行图形化的过程中，仅在第一掺杂层11或第二掺杂层12需要的区域形成掩膜层，避免在其他区域形成不必要的掩膜层，减少去除非必要区域掩膜层的步骤。且在第二掺杂层12的图形化(即去除第二掩膜层12之外区域的第二掺杂层12的过程)和第三区域103的形成在同一个步骤中完成，减化了步骤。此外，在制作第二掺杂层12以及第二掺杂层12图形化时，第一掺杂层11上始终保留第一掩膜层16，因此，第二掺杂层12图形化的过程中，碱溶液被第一掩膜层16阻挡，因此碱液无法破坏第一掺杂区101的第一掺杂层11，由于第一掩膜层16对第一掺杂层11的保护作用，完成了第一掺杂区101和第二掺杂区102的图形化制备，减少了对第一掺杂层11的损伤，确保了第一掺杂层11的导电性能。
其中，在实际应用中，基底10为半导体基底10。基底10的材料可以选择硅(Si)或者锗(Ge)等材料或者砷化镓(GaAs)等材料，显然的，在导电类型方面，基底10可以为本征导电基底、n型导电基底或者p型导电基底。优选的，基底10为p型导电基底或n型导电基底。与本征导电基底相比，p型导电基底或n型导电基底具有更好的导电率，从而使得最终制得的背接触电池具有更低的体电阻率，从而提高背接触电池的效率。
第一掺杂层11、第二掺杂层12也均为半导体掺杂层。在物质的内部排列 形式方面，第一掺杂层11、第二掺杂层12可以为非晶、微晶、单晶、纳米晶或多晶等。在具体材料方面，第一掺杂层11、第二掺杂层12的材料可以为硅(Si)、锗(Ge)、碳化硅(SiC x)或砷化镓(GaAs)等。在导电类型方面，第一掺杂层11、第二掺杂层12可以为n型掺杂层或p型掺杂层。
在一些示例中，当基底10为n型基底时，第一掺杂层11可以为p型掺杂层，第二掺杂层12可以为n型掺杂层；或，当基底10为p型基底时，第一掺杂层11为可以n型掺杂层，第二掺杂层12可以为p型掺杂层。
第一界面钝化层14和第二界面钝化层15为遂穿氧化层。隧穿氧化层允许多子隧穿进入半导体掺杂层同时阻挡少子通过，进而多子在半导体掺杂层内横向运输被电极收集，减少了载流子的复合，提高了背接触电池的开路电压和短路电流。此时，隧穿氧化层与半导体掺杂层构成隧穿氧化层钝化接触结构，可以实现优异的界面钝化和载流子的选择性收集，提高了背接触电池的光电转换效率。显然地，隧穿氧化层也可以替换为其他的界面钝化层。其中，第一界面钝化层14和第二界面钝化层15可以为氧化物、氮化物、碳化物、氢化非晶硅中的一种或多种；其中，氧化物可以为氧化硅、氮氧化硅、氧化铝、氧化钛、HfO 2、Ga 2O 3、Ta 2O 5、Nb 2O 5中的一种或多种的混合物；其中，氮化物可以为氮化硅、氮化铝、TiN、TiCN中的一种或多种；其中，碳化物可以为SiC、SiCN等。
第一掺杂层11、第二掺杂层12的厚度范围均为50nm～500nm。在基底10上形成第一界面钝化层14和第一掺杂层11的工艺以及在第一掩膜层16、第二掺杂区102和第三区域103上形成第二掺杂层12的工艺可以为等离子体化学气相沉积(PECVD)工艺、热丝化学气相沉积工艺、物理气相沉积(PVD)工艺、低压化学气相沉积(LPCVD)工艺或催化化学气相沉积工艺等。去除位于第二掺杂区102和第三区域103的第一界面钝化层14和第一掺杂层11的工艺以及去除位于第三区域103和第一掩膜层16上的第二掺杂层12，可以为激光刻蚀工艺、离子铣刻蚀工艺、等离子刻蚀工艺、反应离子刻蚀工艺、碱刻蚀工艺和酸刻蚀工艺等。
实际应用中，形成电极的方法包括多种，可以直接使用烧穿型浆料涂覆在钝化膜上，然后经过热处理使得电极浆料穿过钝化膜形成接触。也可以先在待接触区域的少部分区域上形成钝化膜开孔，然后使用电极浆料、激光转 印法、电镀、化学镀、光诱导电镀等方法，或者蒸发、溅射等物理气相沉积等方法形成电极。
显然地，也可以使用以上方法中的一种或者多种方法的结合来形成电极。例如，使用PVD种子层配合印刷电极的方法，亦或是丝网印刷电极浆料配合电镀方法，或是激光转印方法和丝网印刷烧结方法的结合等。
例如，其中开膜形成电极的方法中，使用开钝化膜形成接触区，在图形化的第一掺杂层11上形成P型接触区，在图形化的第二掺杂层12上形成N型接触区。
在接触区或背面钝化膜上印刷导电浆料并烧结形成金属化接触。其中P型接触区上形成P型金属区，N型接触区上形成N型金属区。或直接在图形化第一掺杂区和第二掺杂区上的钝化膜上直接印刷烧穿型浆料，形成对应的P型金属区和N型金属区。
进一步的，在形成电极后，还可以有其他的步骤，例如光注入或者电注入载流子或者其他热处理的过程等，以及效率分档或者切片等的步骤。
该方法制备的具有钝化接触结构的IBC电池，钝化效果好，金属区复合小，工艺流程简单，无外加热氧化或者PECVD方法形成的掩膜层，将掩膜层形成工艺与图形化工艺相结合。采用了两步激光氧化工艺，形成具有隔离区域的背面PN钝化接触交叉结构，大大地降低了PN直接交接区域的复合，从而提升了电池的效率。
进一步地，在本实施例中，第一掩膜层16为第一氧化物掩膜层；和/或，第二掩膜层17为第二氧化物掩膜层。由于第一掩膜层16和第二掩膜层17均采用氧化物掩膜层，氧化物掩膜层可以直接在第一掺杂层11和第二掺杂层12上通过氧化形成，且氧化物掩膜层相对于其他另外制备的掩膜层，如印刷掩膜，氧化物掩膜层清洁度高，未引入其他元素，不会对第一掺杂层和第二掺杂层带来其他的污染或者影响。氧化物掩膜易于清洗。
氧化物掩膜具体为：在第一掺杂层11和第二掺杂层12为SiC和Si的情况下，形成的氧化物掩膜为SiO x层，在第一掺杂层11和第二掺杂层12为锗的情况下，形成的氧化物掩膜层为GeO x。
如图11所示，在本实施例中，第一氧化物掩膜层的形成方法为：在含氧气氛环境下，仅在位于第一掺杂区101的第一掺杂层11的表面进行激光辐照 氧化形成；和/或，第二氧化物掩膜层的形成方法为：在含氧气氛环境下，仅在位于第二掺杂区102的第二掺杂层12的表面进行激光辐照氧化形成。
具体实施时，使用如图11所示的装置，在密闭的箱体30内，通过进气口301向箱体30中持续通入含氧气氛气体，通过排气口302将含氧气氛气体排出箱体。激光在箱体30中对放入的含硅的半导体基底的特定区域进行激光辐照，从而在激光扫过的区域形成氧化物掩膜层。
由于通过激光辐照直接在第一掺杂层11和第二掺杂层12上形成氧化物掩膜层，使得氧化物掩膜层的形成精度高，相较于外加热氧化或者PECVD方法形成的掩膜层，激光辐照过程的热量小，减小了对第一掺杂层11和第二掺杂层12的损伤。
在本实施例中，含氧气氛环境下的含氧气氛气体为：氧气、臭氧、空气、CO 2、N 2O中的一种或多种。也可以包括其他的氛围气体或者载气，如氮气等。在此含氧气氛环境下，通过激光辐照，使得第一掺杂层11和第二掺杂层12能够与气体发生氧化反应，在表面形成氧化物掩膜层。
进一步地，激光的波长范围为190nm-545nm。
如图7所示，进一步地，在本实施例中，步骤S700中，具体使用碱溶液去除位于第一掩膜层16和第三区域103上的第二掺杂层12和第二界面钝化层5，且在该步骤中，使用同一碱溶液继续在第一表面的第三区域103和基底10的第二表面同时形成绒面结构。
由于第二掺杂层12的图形化、第三区域103的图形化和基底10的第二表面的织构化多个工序可以使用同一碱溶液在同一步骤中同时完成。极大地减少了工艺步骤。第三区域103的绒面结构，增加了背接触电池背面的陷光水平，如背接触电池应用于双面组件时，提高发电量。相较于常规技术中第二表面织构化通常在掺杂半导体层形成之前进行，很容易造成第二表面的织构化在掺杂半导体层图形化过程或者清洗过程中损坏。本发明中的第二表面织构化的工序，置于了形成第一掺杂层11和第二掺杂层12之后，保证了第二表面的绒面结构的完整性和其陷光性能。尤其是第二表面的织构化结构是纳米绒面结构时，各类清洗过程和图形化过程，几乎必定会破坏纳米绒面织构化结构。近年来，受光面的织构化结构使用纳米微结构越来越广泛使用，因此织构化后置的方法的优势越发凸显。纳米绒面织构化结构具有更好的陷 光效果，并且由于背接触电池的受光面没有电极，因此在背接触电池上应用纳米绒面织构化结构后，第二表面的颜色会更加美观。因此，纳米绒面织构化结构更加适用于背接触电池。
具体地，在本实施例中，在70℃～90℃下，使用质量百分比为1wt％～5wt％的KOH、NaOH或者四甲基氢氧化铵的碱溶液去除位于第一掩膜层16和第三区域103上的第二掺杂层12和第二界面钝化层15，并使用同一碱溶液继续在第一表面的第三区域103和第二表面同时形成绒面结构。在此条件下，能够实现更好地刻蚀效果，并形成均匀纳米微绒面结构。
如图8-图10所示，在本实施例中，步骤S800中的在第一掺杂层11上形成第一电极20，在第二掺杂层12上形成第二电极21，具体包括步骤：
步骤S801，去除位于第一掺杂层11上的第一掩膜层16和位于第二掺杂层12上的第二掩膜层17。在完成步骤S700之后，由于第一掺杂层11上还保留第一掩膜层16，第二掺杂层12上还保留有第二掩膜层17，因此，在第一掩膜层16和第二掩膜层17完成了对第一掺杂层11和第二掺杂层12的保护作用后，可以先去除第一掩膜层16和第二掩膜层17，在进行后续电极制作。
步骤S802，在第一掺杂层11、第二掺杂层12和第三区域103同时形成第一表面钝化层13。
步骤S803，在位于第一掺杂层11的第一表面钝化层13上形成第一电极20，在位于第二掺杂层12的第一表面钝化层13上形成第二电极21，第一电极20与第一掺杂层11电接触，第二电极21与第二掺杂层12电接触。
由于在完成第一掺杂层11和第二掺杂层12的图形化以及第三区域103的形成后，可以将第一掩膜层16和第二掩膜层17去除，以提高第一掺杂层11与第一电极20，以及第二掺杂层12与第二电极21的导电接触性能。且第一表面钝化层13可以对背接触电池进行表面钝化，钝化第一掺杂层11、第二掺杂层12和第三区域103处的悬挂键，降低第一表面的载流子复合速度，提高光电转换效率。第一电极20和第二电极21分别通过第一开孔130和第二开孔131与第一掺杂层11和第二掺杂层12电接触，形成金属和半导体的局部欧姆接触，减少了金属电极与第一掺杂层11和第二掺杂层12的接触面积，降低了接触电阻，进一步降低了载流子在电极表面处的复合速率，提高了开路电压。
具体地，在实际应用中，形成第一表面钝化层13的工艺可以为等离子体化学气相沉积(PECVD)工艺、热丝化学气相沉积工艺、物理气相沉积(PVD)工艺、低压化学气相沉积(LPCVD)工艺或催化化学气相沉积工艺等。当背接触电池具有第一表面钝化层13，第一电极20和第二电极21为连续接触电极时，形成第一电极20和第二电极21的方法还可以为将电极浆料涂覆在第一表面钝化层13上，然后经过烧结，使得电极浆料穿过第一表面钝化层13，分别与第二掺杂层12形成电接触。当背接触电池具有第一表面钝化层13，第一电极20和第二电极21为局部接触电极时，形成第一电极20和第二电极21的方法还可以为先在第一表面钝化层13上开设第一开孔130和第二开孔131，然后采用印刷浆料、激光转印法、电镀、化学镀、光诱导电镀、或者真空蒸镀、磁控溅射等物理气相沉积等方法形成局部接触的第一电极20和第二电极21。开孔方法可以包括激光开膜，或者使用可以和第一表面钝化层13反应的刻蚀浆料开膜。通过开孔进行电接触的方式可以使得背接触电池获得较低的金属区复合，保证了背接触电池的高转换效率。显然的，也可以使用以上方法中的一种或者多种方法的结合来形成第一电极20和第二电极21。例如，使用物理气相沉积(PVD)的种子层配合印刷电极的方法，亦或是丝网印刷电极浆料配合电镀方法，或是激光转印方法和丝网印刷烧结方法的结合等。
示例性的，如图8～图10所示，在第一掺杂层11上形成第一电极20，在第二掺杂层12上形成第二电极21，具体为：在第一掺杂层11、第二掺杂层12和第三区域103上采用PECVD工艺沉积一层氮化硅作为第一表面钝化层13；在位于第一掺杂层11的第一表面钝化层13上利用激光开膜，开设第一开孔130，然后采用印刷导电浆料的方法形成第一电极20，在第二掺杂层12的第一表面钝化层13上利用激光开膜，开设第二开孔131，然后采用印刷导电浆料的方法形成第二电极21，第一电极20通过第一开孔130与第二掺杂层121电接触，第二电极21通过第二开孔131与第三掺杂层122电接触。
示例性的，在形成第一电极20和第二电极21后，还可以有其他的步骤。例如光注入或者电注入载流子或者其他热处理的过程等，以及效率分档或者切片等步骤。
在一些示例中，形成第三区域103的步骤可以设在第一表面钝化层13形成前。形成第三区域103的步骤也可以设在外城背接触电池的制备之后，但 这样会会牺牲第三区域103的部分钝化。
进一步地，在本实施例中，步骤S801中，可使用含氟元素的刻蚀溶液去除第一掩膜层16和第二掩膜层17。第一掩膜层16和第二掩膜层17为氧化硅层时，具体可以使用含HF或者NH 4F等的溶液等去除氧化硅层，通过含氟元素的刻蚀溶液能够较为容易地去除掩膜层，特别是氧化物掩膜层。
在本实施例中，在步骤S802中的在第一掺杂层11、第二掺杂层12和第三区域103同时形成第一表面钝化层13的步骤中，还包括在第二表面形成第二表面钝化层18。如此设置，第二表面钝化层18的形成与第一表面钝化层13的形成在同一步骤中，简化了步骤，且第二表面钝化层18具有减少入光反射和钝化的效果。
具体地，形成第二表面钝化层18的工艺可以为等离子体化学气相沉积(PECVD)工艺、热丝化学气相沉积工艺、物理气相沉积(PVD)工艺、低压化学气相沉积(LPCVD)工艺或催化化学气相沉积工艺等。
在一些示例中，在形成第二表面钝化层18后，还可以在第二表面钝化层18上形成一层减反射层。减反射层可以减少对入射到第二表面的光线的反射，提高对光线的折射，增加对入射到第二表面的光线的利用率，进而提高了背接触电池的光电转换效率。表面钝化层和减反射层可以采用氮化硅、氧化硅、氮氧化硅、氧化铝、碳化硅、非晶硅中的一种或多种组成。
在本实施例中，第一掺杂层11和第二掺杂层12的形成方法为原位掺杂方法或者非原位掺杂方法。即可以直接形成第一掺杂层11和掺杂膜层12，也可以先形成本征半导体层和本征半导体膜层，再分别掺杂形成第一掺杂层11和掺杂膜层12。
进一步地，在本实施例中，在第一掺杂层11上形成第一电极20和在第二掺杂层12上形成第二电极21之前，还包括步骤：进行热处理过程，热处理过程将第一掺杂层11和/或第二掺杂层12的至少一部分晶化。具体可以对p型或n型半导体层进行热处理，使得掺杂剂进一步分布，或者使得半导体层的结构发生变化，更有利于电池性能的提升。例如，当第一掺杂层11、第二掺杂层12为非晶半导体或微晶半导体时，加热退火可以使得第一掺杂层11和/或第二掺杂层12的至少一部分晶化，提高了第一掺杂层11、第二掺杂层12的电导率。此外，加热退火还可以使得第一界面钝化层14和第二界面钝化 层15(如隧穿氧化层)更有利于进行载流子的选择性传输；加热还可以使得掺杂元素进入隧穿氧化层和基底10中，从而减少传输电阻。
以制作图1所示的n型背接触电池为例，本实施例提供了一种具体的n型背接触电池的制作过程：
第一步：提供一n型硅基底10，然后对n型硅基底10依次进行抛光、清洗等去损伤处理。
第二步，如图2所示，在n型硅基底10的第一表面上利用PECVD设备沉积一层氧化硅遂穿氧化层和硼掺杂的p型多晶硅层，氧化硅遂穿氧化层作为第一界面钝化层14，硼掺杂的p型多晶硅层作为第一掺杂层11。
第三步，如3所示，在含氧气氛环境下，仅对位于第一掺杂区101的p型多晶硅层的表面进行激光辐照形成第一氧化物掩膜层。
第四步，如图4所示，采用碱刻蚀工艺去除位于第二掺杂区102和第三区域103的p型多晶硅层和氧化硅遂穿氧化层，仅在第一掺杂区101上形成第一掺杂层11和第一界面钝化层14，第一掺杂层11的厚度为200nm；
第五步，如图5所示，在第一氧化物掩膜层和裸露的第二掺杂区102和第三区域103上利用PECVD设备沉积一层氧化硅隧穿氧化层和磷掺杂的n型多晶硅层，氧化硅遂穿氧化层作为第二界面钝化层15，磷掺杂的n型多晶硅层作为第二掺杂层12；
第六步，如图6所示，在含氧气氛环境下，仅对位于第二掺杂区102的n型多晶硅层的表面进行激光辐照形成第二氧化物掩膜层。
第七步，如图7所示，采用碱刻蚀工艺去除位于第三区域103、第一氧化物掩膜层上的第二掺杂层12，只保留位于第二掺杂区102上的第二界面钝化层15和第二掺杂层12，第二掺杂层12的厚度为200nm；同时，使用同一碱溶液对第三区域103和第二表面进行织构化处理，形成绒面结构。
第八步，如图8所示，使用含氟溶液去除第一氧化物掩膜层和第二氧化物掩膜层。
第九步，如图9所示，利用PECVD设备在第一掺杂层11、第三区域103和第二掺杂层12上沉积一层氮化硅作为第一表面钝化层13，同时在第二表面的绒面结构上沉积一层氮化硅作为第二表面钝化层18。
第十步，如图10所示，在第一掺杂区101处的第一表面钝化层13上利 用激光开设第一开孔130，然后采用印刷导电浆料的方法形成第一电极20，第一电极20通过第一开孔130与第一掺杂层11电接触；在第二掺杂区102处的第一表面钝化层13上利用激光开设第二开孔131，然后采用印刷导电浆料的方法形成第二电极21，第二电极21通过第二开孔131与第二掺杂层12电接触，形成如图1所示的背接触电池。第一电极20与第二电极21均为局部接触电极，宽度均为50μm。
在本实施例中，沿着第一掺杂区101和第二掺杂区102交错排列的方向，第一掺杂区101的宽度大于第二掺杂区102的宽度。第一掺杂区101的宽度为600μm～2000μm。第二掺杂区102的宽度200μm～1000μm。基于此，第一掺杂区101上第一掺杂层11的宽度大于第二掺杂区102上第二掺杂层12的宽度，形成的pn结的宽度范围也较大，即载流子分离的面积比较大，有利于载流子的分离，进而提高了电池的光电转换效率。优选地，第一掺杂区101的宽范围在600μm～1500μm之间，第二掺杂区102的宽度范围在200μm～800μm之间。
示例性的，第一掺杂区101的宽度可以为600μm，第二掺杂区的宽度可以为500μm；或者，第一掺杂区101的宽度可以为2000μm，第二掺杂区的宽度可以为200μm；或者，第一掺杂区101的宽度可以为1400μm，第二掺杂区的宽度可以为1000μm。
在一些示例中，沿着第一掺杂区和第二掺杂区交错排列的方向，第三区域103的宽度范围为10μm～100μm。第三区域103太宽可能会导致背接触电池的有效面积被浪费，有效载流子也难以被收集，从而降低了电池性能。设置在第一掺杂区101和第二掺杂区102之间的第三区域103，使得第一掺杂区101和第二掺杂区102在边界处彼此隔开，取消了现有技术中正电极和负电极之间的绝缘体设计，可以减少生产工艺流程，还可以减少空间复杂度。这样的结构在垂直方向上不会有正负极共存的现象，避免了背接触电池漏电现象的产生；并且可以提高电池在后期产品的可靠性表现，减少背接触电池的生产工艺难度。
示例性的，第三区域的宽度可以为10μm，也可以为100μm，还可以为60μm。
作为一些可能的实现方式，如图1所示，第一掺杂区101的表面和/或第二掺杂区102的表面为抛光面。
基于此，第一掺杂区101和第二掺杂区102的表面均可以为抛光面，使得从第二表面入射并穿过背接触电池的光线进行再反射，从而使得光线有机会被背接触电池再次利用，从而提高了背接触电池的光电转换效率。此外，抛光后的表面具有更好的平整度，后续在抛光面上形成其他层的效果会更好，有利于减少界面缺陷的产生，进而减少由于缺陷导致的载流子的复合，有利于背接触电池钝化性能的提升，从而提高了背接触电池的光电转换效率。
该方法制备的具有钝化接触结构的IBC电池，钝化效果好，金属区复合小，工艺流程简单，无外加热氧化或者PECVD方法形成的掩膜层，将掩膜层形成工艺与图形化工艺相结合。采用激光氧化工艺，形成具有第三区域的背面PN钝化接触交叉结构，大大地降低了PN直接交接区域的复合，从而提升了电池的效率。在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种背接触电池的制作方法，其特征在于，包括：
    提供一基底，所述基底具有相对的第一表面和第二表面，所述第一表面上具有交错排列的第一掺杂区和第二掺杂区，以及用于间隔所述第一掺杂区和所述第二掺杂区的第三区域；
    在基底的所述第一表面上依次形成第一界面钝化层和第一掺杂层；
    仅在位于所述第一掺杂区的所述第一掺杂层的表面形成第一掩膜层；
    去除位于所述第二掺杂区和所述第三区域上的所述第一掺杂层和所述第一界面钝化层；
    在所述第一掩膜层、所述第二掺杂区和所述第三区域上同时依次形成第二界面钝化层和第二掺杂层，所述第二掺杂层与所述第一掺杂层的导电类型相反；
    仅在位于所述第二掺杂区的所述第二掺杂层的表面形成第二掩膜层；
    去除位于所述第一掩膜层和所述第三区域上的所述第二掺杂层和所述第二界面钝化层，只保留位于所述第二掺杂区的所述第二界面钝化层和所述第二掺杂层；
    在所述第一掺杂层上形成第一电极，在所述第二掺杂层上形成第二电极。
  2. 根据权利要求1所述的背接触电池的制作方法，其特征在于，所述第一掩膜层为第一氧化物掩膜层；和/或，所述第二掩膜层为第二氧化物掩膜层。
  3. 根据权利要求2所述的背接触电池的制作方法，其特征在于，所述第一氧化物掩膜层的形成方法为：在含氧气氛环境下，仅在位于所述第一掺杂区的第一掺杂层的表面进行激光辐照氧化形成；和/或，
    所述第二氧化物掩膜层的形成方法为：在含氧气氛环境下，仅在位于第二掺杂区的第二掺杂层的表面进行激光辐照氧化形成。
  4. 根据权利要求3所述的背接触电池的制作方法，其特征在于，所述含氧气氛环境下的气体为：氧气、臭氧、空气、CO 2、N 2O中的一种或多种。
  5. 根据权利要求1所述的背接触电池的制作方法，其特征在于，使用碱溶液去除位于所述第一掩膜层和所述第三区域上的所述第二掺杂层和所述第二界面钝化层，并使用同一所述碱溶液继续在所述第一表面的第三区域和所述第二表面同时形成绒面结构。
  6. 根据权利要求5所述的背接触电池的制作方法，其特征在于，在70℃～90℃下，使用质量百分比为1％～5wt％的KOH、NaOH或者四甲基氢氧化铵的碱溶液去除位于所述第一掩膜层和所述第三区域上的第二掺杂层和第二界面钝化层，并使用同一所述碱溶液继续在所述第一表面的第三区域和所述第二表面同时形成绒面结构。
  7. 根据权利要求1所述的背接触电池的制作方法，其特征在于，所述在所述第一掺杂层上形成所述第一电极，在所述第二掺杂层上形成所述第二电极的步骤，具体包括步骤：
    去除位于所述第一掺杂层上的所述第一掩膜层和位于所述第二掺杂层上的所述第二掩膜层；
    在所述第一掺杂层、所述第二掺杂层和所述第三区域同时形成第一表面钝化层；
    在位于所述第一掺杂层的所述第一表面钝化层上形成第一电极，在位于所述第二掺杂层的所述第一表面钝化层上形成第二电极，所述第一电极与所述第一掺杂层电接触，所述第二电极与所述第二掺杂层电接触。
  8. 根据权利要求6所述的背接触电池的制作方法，其特征在于，使用含氟元素的刻蚀溶液去除所述第一掩膜层和所述第二掩膜层；和/或，
    所述在所述第一掺杂层、所述第二掺杂层和所述第三区域同时形成所述第一表面钝化层的步骤中，还包括在所述第二表面形成第二表面钝化层。
  9. 根据权利要求1所述的背接触电池的制作方法，其特征在于，所述第一掺杂层和所述第二掺杂层的形成方法为原位掺杂方法或者非原位掺杂方法。
  10. 根据权利要求1所述的背接触电池的制作方法，其特征在于，在所述在所述第一掺杂层上形成所述第一电极，在所述第二掺杂层上形成所述第二电极的步骤之前，还包括步骤：进行热处理过程，所述热处理过程将所述第一掺杂层和/或所述第二掺杂层的至少一部分晶化。
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