WO2023050824A1 - 一种背接触电池及其制作方法 - Google Patents

一种背接触电池及其制作方法 Download PDF

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WO2023050824A1
WO2023050824A1 PCT/CN2022/092271 CN2022092271W WO2023050824A1 WO 2023050824 A1 WO2023050824 A1 WO 2023050824A1 CN 2022092271 W CN2022092271 W CN 2022092271W WO 2023050824 A1 WO2023050824 A1 WO 2023050824A1
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layer
doped
region
doped layer
electrode
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PCT/CN2022/092271
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French (fr)
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李中兰
鲁伟明
李华
靳玉鹏
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泰州隆基乐叶光伏科技有限公司
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Publication of WO2023050824A1 publication Critical patent/WO2023050824A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table
    • H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic Table characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present application relates to the field of photovoltaic technology, in particular to a back contact cell and a manufacturing method thereof.
  • a back contact battery refers to a battery in which the emitter and metal contacts are on the back of the battery, and the front is not blocked by a metal electrode. Compared with cells with a shielded front, back-contact cells have higher short-circuit current and photoelectric conversion efficiency, and are currently one of the technical directions for realizing high-efficiency crystalline silicon cells.
  • the existing method for manufacturing back-contact cells is relatively complicated, so a method for manufacturing solar cells that is simple and ensures high efficiency is required.
  • the purpose of the present application is to provide a back contact cell and its manufacturing method, which are used to simplify the manufacturing process of the back contact cell while ensuring high photoelectric conversion efficiency.
  • the invention provides a back contact battery, comprising: a substrate having opposite first and second surfaces. There are first doped regions and second doped regions alternately arranged on the first surface, and a laminated layer region and a third region between the first doped regions and the second doped regions.
  • the stacked region is close to the first doped region.
  • the first doped layer is formed on the first doped region and the laminated layer region.
  • the second doped layer is formed on the first doped layer.
  • the second doped layer is only located above the stacked layer region.
  • the conductivity type of the first doped layer is opposite to that of the second doped layer.
  • the third doped layer is formed on the second doped region, and the conductivity type of the third doped layer is opposite to that of the first doped layer.
  • a first electrode and a second electrode The first electrode is in electrical contact with the first doped layer.
  • the second electrode is in electrical contact with the third doped layer.
  • the first surface of the substrate has a laminated region located between the first doped region and the second doped region and is close to the first doped region, and the laminated region has a sequentially formed second doped region.
  • the first doped layer and the second doped layer have opposite conductivity types.
  • the second doped layer covers the first doped layer below it, which protects part of the surface of the first doped layer, and prevents the first doped layer at the lamination region from being destroyed in the subsequent process. Destruction or introduction of impurities improves the yield and production efficiency of the back contact cell, and at the same time ensures the collection of the first electrical carriers.
  • the retained second doped layer reduces the processing area and difficulty in the patterning process, reduces production costs, and improves the production capacity and production efficiency during mass production.
  • the third region can separate the first doped layer on the first doped region from the third doped layer on the second doped region, which is beneficial to ensure the excellent positive and negative electrode insulation properties of the battery .
  • it further includes a first protection layer located above the stack region and located between the first doped layer and the second doped layer.
  • the formed first protective layer can protect the first doped layer in the subsequent patterning treatment, surface texturing treatment and cleaning process , so that the first doped layer will not be corroded or damaged.
  • the first protection layer can completely separate the first doped layer and the second doped layer, thereby reducing the adverse effect of the second doped layer on the first doped layer in subsequent processes.
  • the crystallization for a long time will make the crystallization in the second doped layer Doping elements enter the first doped layer, causing damage to the first doped layer, and may even change the conductivity type of the first doped layer, resulting in the failure of the battery to generate electricity normally.
  • the first protection layer includes at least one of a dielectric layer and a mask layer.
  • the dielectric layer and/or mask layer used in the first protection layer has obvious differences in physical or chemical properties from the first doped layer, so as to ensure that the second doped layer is removed by etching or etching.
  • the first protective layer can be effectively retained.
  • the first protective layer includes one of a borosilicate glass layer and a phosphosilicate glass layer. At this time, the first protective layer may be formed by doping together with the first doped layer.
  • the surface of the third region has a suede structure.
  • No electrode is provided on the third area, and the third area may be textured so that the third area has a suede structure. Because the suede structure has good light trapping effect and anti-reflection effect, the light incident on the first surface can also be used, which increases the light absorption effect of the back contact cell on the first surface, so that the back contact cell can absorb light on both sides energy, realizing the further utilization of light energy and improving the power generation efficiency of the back contact cell.
  • the surface of the first doped region and/or the surface of the second doped region and/or the surface of the stacked layer region are polished surfaces.
  • the surfaces of the first doped region, the second doped region and the stacked layer region can all be polished surfaces, so that the light incident from the second surface and passing through the back contact cell is re-reflected, thereby The light has the opportunity to be reused by the back contact cell, thereby improving the photoelectric conversion efficiency of the back contact cell.
  • the polished surface has better flatness, and the effect of forming other layers on the polished surface will be better, which is beneficial to reduce the generation of interface defects, thereby reducing the recombination of carriers caused by defects, which is beneficial to the background
  • the improvement of the passivation performance of the contact cell improves the photoelectric conversion efficiency of the back contact cell.
  • a first interface passivation layer, a second interface passivation layer and a third interface passivation layer are also included.
  • the first interface passivation layer is located between the base and the first doped layer.
  • the second interface passivation layer is located between the second doped layer and the first protective layer.
  • the third interface passivation layer is located between the base and the third doped layer.
  • the first interface passivation layer, the second interface passivation layer and the third interface passivation layer passivate the substrate, the first protective layer and the first doped layer respectively to reduce the recombination of carriers at the interface, ensuring Carrier transport efficiency.
  • the substrate is an n-type substrate, the first doped layer is a p-type doped layer, the second doped layer and the third doped layer are n-type doped layers; or, the substrate is a p-type
  • the substrate, the first doped layer is an n-type doped layer, and the second doped layer and the third doped layer are p-type doped layers.
  • the first doped layer is a p-type doped layer, and both the second doped layer and the third doped layer can be phosphorus-doped n-type doped layers.
  • the doped region has greater solubility for metal impurities, and the phosphorus contained in the second doped layer can provide phosphorus gettering and passivation for the first doped layer, thereby improving battery efficiency.
  • a first surface passivation layer is also included.
  • the first surface passivation layer covers the first doped layer, the second doped layer, the third doped layer and the third region.
  • the first electrode is in electrical contact with the first doped layer through the first opening.
  • the second electrode is in electrical contact with the third doped layer through the second opening.
  • a first surface passivation layer is formed outside the first doped layer, the second doped layer, the third doped layer and the third region.
  • the first surface passivation layer can passivate the surface of the back contact battery, passivate the dangling bonds at the first doped layer, the second doped layer, the third doped layer and the third region, and reduce the load on the first surface.
  • the recombination speed of flow electrons improves the photoelectric conversion efficiency.
  • the first electrode and the second electrode are in electrical contact with the first doped layer and the third doped layer through the first opening and the second opening respectively, forming a local ohmic contact between the metal and the semiconductor, reducing the contact between the metal electrode and the first doped layer.
  • the contact area between the impurity layer and the third doped layer reduces the contact resistance, further reduces the recombination rate of carriers at the electrode surface, and increases the open circuit voltage.
  • the area of the stacked layer accounts for 5%-95% of the area of the first doped layer.
  • the area of the stacked layer accounts for 20% to 95% of the area of the first doped layer.
  • the larger the area of the stacked layer the larger the area of the first doped layer covered by the second doped layer, that is, the protected
  • the larger the area of the first doped layer the better the protection of the first doped layer from being corroded or damaged in subsequent processes.
  • the area of the stacked layer accounts for 40% to 75% of the area of the first doped layer, and the first protective layer and the second doped layer above the stacked area should avoid contact with the electrodes.
  • the stacked area If the area is too large, there is a risk of electric leakage.
  • the present application also provides a method for manufacturing a back contact battery, including:
  • a substrate is provided, the substrate has a first surface and a second surface opposite to each other, the first surface has first doped regions and second doped regions alternately arranged, and Between the laminated region and the third region, the laminated region is close to the first doped region;
  • a first electrode is formed on the first doped layer, and a second electrode is formed on the third doped layer.
  • beneficial effects of the manufacturing method of the back contact battery provided by the second aspect or any possible implementation of the second aspect can refer to the beneficial effects of the back contact battery described in the first aspect or any possible implementation of the first aspect , which will not be described here.
  • removing the first doped layer located in the second doped region and the third region specifically includes: forming a first protective layer on the first doped region and the first doped layer in the stacked region layer. The first doped layer and the first protection layer on the second doped region and the third region are removed.
  • removing the doped film layer located on the third region and the first doped region is specifically: forming a second protective layer on the doped film layer located on the stack region and the second doped region .
  • the doped film layer located on the third region and the first doped region is removed. Remove the second protective layer.
  • a further step is included: forming an interface passivation on the first protective layer and the first surface film layer; in the step of removing the doped film layer located in the third region and the first doped region, further comprising the step of: removing the interface passivation film layer located in the third region and the first doped region, so that the layer located in the stack
  • the interface passivation film layer on the first protective layer in the region is the second interface passivation layer, and the interface passivation film layer
  • the formation method of the first doped layer and the doped film layer is an in-situ doping method or an ex-situ doping method.
  • a step is further included: performing texturing treatment on the third region.
  • the first electrode is formed on the first doped layer, and the second electrode is formed on the third doped layer, specifically: the first doped layer, the second doped layer, the third A first surface passivation layer is formed on the doped layer and the third region.
  • a first electrode is formed on the first surface passivation layer located on the first doped layer.
  • a second electrode is formed on the first surface passivation layer located on the third doped layer. The first electrode is in electrical contact with the first doped layer. The second electrode is in electrical contact with the third doped layer.
  • the step of: performing a heat treatment process heat treatment The process crystallizes at least a portion of the first doped layer and/or the second doped layer and/or the third doped layer.
  • the method of removing the first doped layer located in the second doped region and the third region and/or removing the doped film layer located on the third region and the first doped region is alkali etching eclipse.
  • FIG. 1 to 3 are schematic structural views of the back contact battery provided in the embodiment of the present application.
  • Figures 4 to 13 are schematic diagrams of the states of each stage of the manufacturing process of the back contact battery provided by the embodiment of the present application.
  • Figure 14 is a schematic diagram of the first surface of the back contact battery provided by the embodiment of the present application.
  • Figure 15 is a partially enlarged view of Figure 14;
  • Fig. 16 is a schematic diagram of the first surface of a back contact battery with a continuous contact electrode provided in an embodiment of the present application;
  • FIG. 17 is a partial schematic view of the first surface of a back contact battery with partial contact electrodes provided in an embodiment of the present application.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as “first” and “second” may explicitly or implicitly include one or more of these features.
  • plurality means two or more, unless otherwise specifically defined. "Several” means one or more than one, unless otherwise clearly and specifically defined.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it may be mechanical connection or electrical connection; it may be direct connection or indirect connection through an intermediary, and it may be the internal communication of two elements or the interaction relationship between two elements. Those of ordinary skill in the art can understand the specific meanings of the above terms in this application according to specific situations.
  • a solar cell is a device that converts the sun's light energy into electricity.
  • Solar cells use the principle of photovoltaics to generate carriers, and then use electrodes to extract the carriers, which is beneficial to the effective use of electrical energy.
  • Interdigitated back contact battery also known as IBC battery.
  • IBC Interdigitated back contact
  • the biggest feature of the IBC battery is that the emitter and the metal contact are on the back of the battery, and the front is not affected by the shielding of the metal electrode, so it has a higher short-circuit current Isc, and the back can allow wider metal grid lines to reduce the series resistance Rs. Improve the fill factor FF; and this kind of battery with no shielding on the front not only has high conversion efficiency, but also looks more beautiful, and at the same time, the assembly of the full back electrode is easier to assemble.
  • IBC battery is one of the technical directions to realize high-efficiency crystalline silicon battery at present.
  • the embodiment of the present application provides a back contact battery.
  • the back contact battery provided by the embodiment of the present application includes: a substrate 10 having opposite first and second surfaces. There are first doped regions 101 and second doped regions 102 arranged alternately on the first surface, and a laminated region 104 and a third region 103 between the first doped regions 101 and the second doped regions 102 .
  • the stacked region 104 is close to the first doped region 101 .
  • the first doped layer 11 is formed on the first doped region 101 and the stacked layer region 104 .
  • the second doped layer 121 is formed on the first doped layer 11 .
  • the second doped layer 121 is only located above the stack region 104 .
  • the conductivity type of the first doped layer 11 is opposite to that of the second doped layer 121 .
  • the third doped layer 122 is formed on the second doped region 102 , and the conductivity type of the third doped layer 122 is opposite to that of the first doped layer 11 .
  • the first electrode 20 and the second electrode 21 are in electrical contact with the first doped layer 11 .
  • the second electrode 21 is in electrical contact with the third doped layer 122 .
  • the first surface of the substrate 10 has a laminated region 104 located between the first doped region 101 and the second doped region 102 and close to the first doped region 101, the laminated region 104 has a first doped layer 11 and a second doped layer 121 formed in sequence, and the conductivity types of the first doped layer 11 and the second doped layer 121 are opposite.
  • the second doped layer 121 covers the first doped layer 11 below it, which protects part of the surface of the first doped layer 11 and prevents the first doped layer 11 at the stack region 104 from Impurities are destroyed or introduced during the process, which improves the yield and production efficiency of the back contact battery, and at the same time ensures the collection of the first electrical carriers.
  • the remaining second doped layer 121 reduces the processing area and difficulty in the patterning process, reduces the production cost, and improves the production capacity and production efficiency during mass production.
  • the third region 103 can separate the first doped layer 11 on the first doped region 101 from the third doped layer 122 on the second doped region 102, which is beneficial to ensure the excellent performance of the battery. Positive and negative insulation properties.
  • the width of the third region 103 ranges from 10 ⁇ m to 100 ⁇ m. If the third region 103 is too wide, the effective area of the back contact cell may be wasted, and the effective carriers are difficult to be collected, thereby reducing the performance of the cell.
  • the third region 103 is arranged between the first doped region 101 and the second doped region 102, so that the first doped region 101 and the second doped region 102 are separated from each other at the boundary, canceling the conventional
  • the design of the insulator between the electrode and the negative electrode can reduce the production process and also reduce the space complexity. Such a structure will not have the coexistence of positive and negative electrodes in the vertical direction, avoiding the leakage of back-contact batteries; it can also improve the reliability performance of batteries in later products and reduce the difficulty of the production process of back-contact batteries.
  • the width of the third region 103 may be 10 ⁇ m, or 100 ⁇ m, or 60 ⁇ m.
  • the substrate 10 is a semiconductor substrate 10 .
  • the material of the substrate 10 can be selected from materials such as silicon (Si) or germanium (Ge), or materials such as gallium arsenide (GaAs).
  • the substrate 10 can be an intrinsically conductive substrate 10 or an n-type conductive substrate 10. Or a p-type conductive substrate 10 .
  • the substrate 10 is a p-type conductive substrate 10 or an n-type conductive substrate 10 .
  • the p-type conductive substrate 10 or the n-type conductive substrate 10 has better conductivity, so that the final back contact battery has a lower volume resistivity, thereby improving the performance of the back contact battery. efficiency.
  • the substrate 10 is an n-type silicon substrate 10 .
  • the n-type conductive substrate 10 has the advantages of high minority carrier lifetime, no light decay, and good weak light performance.
  • the first doped layer 11 , the second doped layer 121 and the third doped layer 122 are also semiconductor doped layers.
  • the first doped layer 11 , the second doped layer 121 and the third doped layer 122 may be amorphous, microcrystalline, single crystal, nanocrystalline or polycrystalline.
  • the materials of the first doped layer 11, the second doped layer 121 and the third doped layer 122 can be silicon (Si), germanium (Ge), silicon carbide (SiC x ) or gallium arsenide ( GaAs) and so on.
  • the first doped layer 11 , the second doped layer 121 and the third doped layer 122 may be n-type doped layers or p-type doped layers.
  • the first doped layer 11 when the substrate 10 is an n-type substrate 10, the first doped layer 11 may be a p-type doped layer, and the second doped layer 121 and the third doped layer 122 may be n-type doped layers; Or, when the substrate 10 is a p-type substrate 10, the first doped layer 11 may be an n-type doped layer, and the second doped layer 121 and the third doped layer 122 may be p-type doped layers.
  • the substrate 10 is an n-type silicon substrate 10
  • the first doped layer 11 is a boron-doped p-type doped layer
  • the second doped layer 121 and the third doped layer Layers 122 are both phosphorus-doped n-type doped layers.
  • the heavily doped phosphorus region has greater solubility to metal impurities, the phosphorus contained in the second doped layer 121 can provide phosphorus gettering and passivation for the first doped layer 11 , improving battery efficiency.
  • the entire stacked layer on the stacked layer region 104 actually also functions as a p-type doped layer, that is,
  • the second doped layer 121 above the first doped layer 11 on the laminated region 104 is not conductive, and only the first doped region 101 and the first doped layer 11 on the laminated region 104 play the role of transporting carriers , after that, the carriers on the first doped layer 11 are drawn out through the first electrode 20 in electrical contact with the first doped layer 11 .
  • the p-type region on the entire cell is a collection of the first doped region 101 and the stacked region 104 .
  • a first protective layer 16 located above the layer stack region 104 and located between the first doped layer 11 and the second doped layer 121 is further included.
  • the formed first protective layer 16 can protect the first doped layer 11 in the subsequent patterning treatment, surface texturing treatment and cleaning process, so that the first A doped layer 11 will not be corroded or damaged.
  • the first protective layer 16 can completely separate the first doped layer 11 and the second doped layer 121, thereby reducing the impact of the second doped layer 121 on the first doped layer 11 in subsequent processes. Negative Effects.
  • the first doped layer 11 is in direct contact with the second doped layer 121, when at least one of the first doped layer 11 and the second doped layer 121 is the required crystal
  • the doped amorphous silicon layer is transformed into a doped polysilicon layer, because the crystallization time is relatively long, and the conductivity types of the second doped layer 121 and the first doped layer 11 are opposite, long-term crystallization will make
  • the doping elements in the second doped layer 121 enter the first doped layer 11 , causing damage to the first doped layer 11 , and may even change the conductivity type of the first doped layer 11 , causing the battery to fail to generate electricity normally.
  • the first doped layer 11 is in direct contact with the second doped layer 121, when the first doped layer 11 is a boron-doped P-type polysilicon layer, the second When the doped layer 121 is an N-type amorphous silicon layer doped with phosphorus, and the second doped layer 121 needs to be transformed into an N-type polysilicon layer through crystallization, during the crystallization process, the phosphorus element contained in the second doped layer 121 It may enter the first doped layer 11 and cause damage to the first doped layer 11; too much phosphorus element entering may also cause the first doped layer 11 to change from P-type to N-type, which is different from the conductivity type of the substrate 10. The same, causing the battery to fail to generate electricity.
  • the first passivation layer 16 includes at least one of a dielectric layer and a mask layer.
  • the dielectric layer and/or mask layer used in the first protective layer 16 has obvious differences in physical or chemical properties from the first doped layer 11, so as to ensure that the first protective layer 16 is removed by an etching process or an etching process.
  • the first protection layer 16 can be effectively retained.
  • the material of the first protective layer 16 may be one or more of oxides, nitrides, carbides, and hydrogenated amorphous silicon, wherein the oxides include silicon oxide, silicon oxynitride, aluminum oxide, One or more of titanium oxide, hafnium dioxide (HfO 2 ), gallium oxide (Ga 2 O 3 ), tantalum pentoxide (Ta 2 O 5 ), and niobium pentoxide (Nb 2 O 5 );
  • the nitride includes one or more of silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride (TiN), titanium nitride carbide (TiCN) and the like; the carbide includes silicon carbide (SiC).
  • a dielectric layer that does not react with the used alkali can be selected as the first protective layer. 16.
  • the first doped layer 11 will react with the selected alkali.
  • a dielectric material such as silicon oxide, silicon nitride or silicon carbide (SiC x ) can be selected as the dielectric layer.
  • a thermal growth process can be used to form the dielectric layer, that is, under the condition of an oxidizing atmosphere (such as air, oxygen, etc.), heating is used to form a oxide dielectric layer.
  • a mask layer resistant to laser ablation can be selected as the first protective layer 16, on the contrary Yes, the first doped layer 11 will be ablated by laser. Based on this, in the process of patterning the first doped layer 11, the first doped layer 11 located in the second doped region 102 and the third region 103 is removed, and the first doped layer covered by the first protective layer 16 The impurity layer 11 is completely preserved.
  • the mask layer used can be photolithographic development or laser patterned mask, colloidal mask that can be printed, silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon carbide (SiC ) and other materials.
  • the dielectric layer should be close to the first doped layer 11, so as to ensure the passivation effect of the first doped layer 11; Since the mask layer has more impurities, it should be kept away from the first doped layer 11 to prevent the first doped layer 11 from being polluted.
  • the first protective layer 16 includes one of a borosilicate glass (BSG) layer and a phosphosilicate glass (PSG) layer.
  • BSG borosilicate glass
  • PSG phosphosilicate glass
  • the first protective layer 16 can be formed by doping together with the first doped layer 11 , which saves the process of forming the first protective layer 16 separately.
  • the BSG or PSG between the first doped layer 11 and the second doped layer 121 can block phosphorus or boron Diffusion plays an isolation role and better protects the first doped layer 11.
  • the material of the first protection layer 16 may be silicon oxide. Since silicon oxide does not react with alkali, silicon oxide can better protect the integrity of the first doped layer 11 when alkali is used for etching in a subsequent process. In addition, silicon oxide has a good interface passivation effect, can passivate the dangling bonds on the surface of the first doped layer 11, and inhibit the recombination of carriers on the surface of the first doped layer 11, thereby improving the photoelectric conversion efficiency of the battery.
  • the thickness of the first protection layer 16 ranges from 20 nm to 100 nm. In order to better protect the first doped layer 11 during etching or cleaning, the first protection layer 16 can be thicker.
  • the surface of the third region 103 has a textured structure.
  • the third region 103 is not provided with electrodes, and the third region 103 may be textured so that the third region 103 has a textured structure.
  • the suede structure has good light trapping effect and anti-reflection effect, the light incident on the first surface can also be used, which increases the light absorption effect of the back contact cell on the first surface, so that the back contact cell can absorb light on both sides energy, realizing the further utilization of light energy and improving the power generation efficiency of the back contact cell.
  • the surface of the first doped region 101 and/or the surface of the second doped region 102 and/or the surface of the stacked layer region 104 are polished surfaces.
  • the surfaces of the first doped region 101, the second doped region 102, and the stacked layer region 104 can all be polished surfaces, so that the light incident from the second surface and passing through the back-contact cell is re-reflected, so that the light There is an opportunity to be reused by the back contact cell, thereby improving the photoelectric conversion efficiency of the back contact cell.
  • the polished surface has better flatness, and the effect of forming other layers on the polished surface will be better, which is beneficial to reduce the generation of interface defects, thereby reducing the recombination of carriers caused by defects, which is beneficial to the background
  • the improvement of the passivation performance of the contact cell improves the photoelectric conversion efficiency of the back contact cell.
  • the back contact cell further includes a first interface passivation layer 14 , a second interface passivation layer 151 and a third interface passivation layer 152 .
  • the first interface passivation layer 14 is located between the substrate 10 and the first doped layer 11 .
  • the second interface passivation layer 151 is located between the second doped layer 121 and the first passivation layer 16 .
  • the third interface passivation layer 152 is located between the substrate 10 and the third doped layer 122 .
  • the first interface passivation layer 14, the second interface passivation layer 151 and the third interface passivation layer 152 perform interface passivation on the substrate 10, the first protective layer 16 and the first doped layer 11 respectively, reducing the current carrying capacity at the interface. The recombination of carriers ensures the transfer efficiency of carriers.
  • the first interface passivation layer 14, the second interface passivation layer 151 and the third interface passivation layer 152 may be one or more of oxide, nitride, carbide, hydrogenated amorphous silicon .
  • oxides include silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, hafnium dioxide (HfO 2 ), gallium oxide (Ga 2 O 3 ), tantalum pentoxide (Ta 2 O 5 ), niobium pentoxide ( One or more of Nb 2 O 5 ) and other substances;
  • nitrides include one of silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride (TiN), titanium nitride carbide (TiCN) and other substances or more;
  • carbides include silicon carbide (SiC).
  • the triple interface passivation layer 152 may be a tunnel oxide layer.
  • the tunneling oxide layer allows many carriers to tunnel into the semiconductor doped layer while blocking minority carriers from passing through, and then many carriers are transported laterally in the semiconductor doped layer and collected by electrodes, reducing the recombination of carriers and improving the open circuit voltage of the back contact cell and short circuit current.
  • the tunnel oxide layer and the semiconductor doped layer form a passivation contact structure of the tunnel oxide layer, which can achieve excellent interface passivation and selective collection of carriers, and improve the photoelectric conversion efficiency of the back contact cell.
  • the first interface passivation layer 14 , the second interface passivation layer 151 and the third interface passivation layer 152 can all be silicon oxide interface passivation layers. Compared with the amorphous silicon interface passivation layer which will crystallize and transform into polysilicon at high temperature, the interface passivation layer of silicon oxide is more resistant to high temperature.
  • the back contact cell further includes a first surface passivation layer 13 .
  • the first surface passivation layer 13 covers the first doped layer 11 , the second doped layer 121 , the third doped layer 122 and the third region 103 .
  • a first opening 130 is formed at a contact surface of the first surface passivation layer 13 and the first doped layer 11 .
  • the first electrode 20 is in electrical contact with the first doped layer 11 through the first opening 130 .
  • the contact surface of the first surface passivation layer 13 and the third doped layer 122 has a second opening 131 .
  • the second electrode 21 is in electrical contact with the third doped layer 122 through the second opening 131 .
  • a first surface passivation layer 13 is formed outside the first doped layer 11 , the second doped layer 121 , the third doped layer 122 and the third region 103 .
  • the first surface passivation layer 13 can passivate the surface of the back contact cell, passivate the dangling bonds at the first doped layer 11, the second doped layer 121, the third doped layer 122 and the third region 103, and reduce the The carrier recombination speed on the first surface improves the photoelectric conversion efficiency.
  • the first electrode 20 and the second electrode 21 are in electrical contact with the first doped layer 11 and the third doped layer 122 respectively through the first opening 130 and the second opening 131 to form a local ohmic contact between the metal and the semiconductor, reducing the The contact area between the metal electrode and the first doped layer 11 and the third doped layer 122 reduces the contact resistance, further reduces the recombination rate of carriers at the electrode surface, and increases the open circuit voltage.
  • the first surface passivation layer 13 located in the third region 103 also functions to isolate the second doped layer 121 from the third doped layer 122 .
  • the material of the first surface passivation layer 13 may be one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon.
  • the second surface has a textured structure.
  • the suede structure on the second surface has a good light-trapping effect, which can reduce the reflection of light incident on the second surface and improve the utilization rate of light.
  • the second surface passivation layer 18 provides the function of passivating the interface of the substrate 10 for the second surface, reduces the recombination of carriers at the interface, improves the transport efficiency of carriers, and further improves the photoelectric conversion efficiency of the back contact cell.
  • the material of the second surface passivation layer 18 may be one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon.
  • the second surface of the back contact cell further includes an anti-reflection layer.
  • An anti-reflection layer may be formed on the second surface passivation layer 18 .
  • the anti-reflection layer can reduce the reflection of the light incident on the second surface, increase the refraction of the light, increase the utilization rate of the light incident on the second surface, and then improve the photoelectric conversion efficiency of the back contact cell.
  • the first surface passivation layer 13 and the second surface passivation layer 18 also have the function of anti-reflection. It is also possible to stack the passivation layer and the anti-reflection layer so that the whole plays an anti-reflection role.
  • the anti-reflection layer may be magnesium fluoride (MgF 2 ), silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), zinc sulfide (ZnS), silicon nitride (SiN), titanium dioxide ( One or more of substances such as TiO 2 ).
  • MgF 2 magnesium fluoride
  • SiO 2 silicon dioxide
  • Al 2 O 3 aluminum oxide
  • ZnS zinc sulfide
  • SiN silicon nitride
  • TiO 2 titanium dioxide
  • the anti-reflection layer may be an aluminum oxide anti-reflection layer, and may also be an anti-reflection layer composed of a stack of silicon nitride and silicon oxide.
  • the area of the stacked layer region 104 accounts for 5%-95% of the area of the first doped layer 11 .
  • the area of the stacked layer 104 accounts for 20% to 95% of the area of the first doped layer 11, the larger the area of the stacked area 104, the larger the area of the first doped layer 11 covered by the second doped layer 121 , that is, the larger the area of the first doped layer 11 to be protected, the better the protection of the first doped layer 11 from being corroded or damaged in subsequent processes.
  • the area of the stacked layer 104 accounts for 40% to 75% of the area of the first doped layer 11, and the first protective layer 16 and the second doped layer 121 above the stacked area 104 should avoid contact with the first electrode 20.
  • the width of the first doped region 101 may range from 80 ⁇ m to 300 ⁇ m, and the width of the stacked region 104 may range from 60 ⁇ m to 860 ⁇ m.
  • the area of the stacked layer region 104 may account for 40%, 60% or 75% of the area of the first doped layer 11 .
  • the part arranged according to the stacked region 104, the first doped region 101, the stacked region 104, the third region 103, the second doped region 102 and the third region 103 can be called a period, and a The width of the period ranges from 400 ⁇ m to 2400 ⁇ m.
  • the embodiment of the present application also provides a method for manufacturing a back contact battery, including the following steps:
  • Step S100 providing a substrate 10, the substrate 10 has a first surface and a second surface opposite to each other, the first surface has first doped regions 101 and second doped regions 102 arranged alternately, and between the first doped region
  • the laminated region 104 and the third region 103 between the region 101 and the second doped region 102, the laminated region 104 is close to the first doped region 101;
  • Step S200 forming a first doped layer 11 on the first surface of the substrate 10;
  • Step S300 removing the first doped layer 11 located in the second doped region 102 and the third region 103;
  • Step S400 forming a doped film layer 12 on the first doped layer 11 and the first surface;
  • Step S500 removing the doped film layer 12 located on the third region 103 and the first doped region 101, so that the doped film layer 12 located on the stack region 104 is the second doped layer 121 located on the first surface
  • the doped film layer 12 is the third doped layer 122;
  • Step S600 forming the first electrode 20 on the first doped layer 11 , and forming the second electrode 21 on the third doped layer 122 .
  • the beneficial effect of the manufacturing method of the back-contact battery provided by the embodiment of the present application is the same as that of the above-mentioned back-contact battery, and will not be repeated here.
  • the thickness range of the first doped layer 11 , the second doped layer 121 and the third doped layer 122 is 50 nm ⁇ 500 nm.
  • the process of forming the first doped layer 11 on the substrate 10 and the process of forming the doped film layer 12 on the first doped layer 11 and the first surface can be plasma chemical vapor deposition (PECVD) process, hot wire chemical vapor Deposition process, physical vapor deposition (PVD) process, low pressure chemical vapor deposition (LPCVD) process or catalytic chemical vapor deposition process, etc.
  • PECVD plasma chemical vapor deposition
  • PVD physical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • catalytic chemical vapor deposition process etc.
  • the process of removing the first doped layer 11 located in the second doped region 102 and the third region 103 and the process of removing the doped film layer 12 located in the third region 103 and the first doped region 101 may be laser engraved Etching process, ion milling etching process, plasma etching process, reactive ion etching process, alkali etching process and acid etching process, etc.
  • the width range of the first electrode 20 and the second electrode 21 is 5 ⁇ m ⁇ 100 ⁇ m.
  • the formed first electrode 20 and second electrode 21 may be continuous contact electrodes.
  • the first electrode 20 includes a first electrode main electrode 201 and a first electrode sub-gate line 202
  • the second electrode 21 includes a second electrode main electrode 211 and a second electrode sub-gate line 212 .
  • the formed first electrode 20 and second electrode 21 may also be local contact electrodes.
  • the first electrode 20 may include connection electrodes 203 and thin grid lines 204 .
  • the continuous electrode is not in contact with the first doped layer 121
  • the thin grid line 204 is in contact with the first doped layer 121 , or part of the area on the thin grid line 204 is in contact with the first doped layer 121 , and the rest of the area is not in contact.
  • the connection electrode 203 serves as a confluence
  • the fine grid line 204 serves as a transmission function, and is not in contact with the first doped layer 121 .
  • the thin grid lines 204 can be prepared using different electrode pastes.
  • the thin grid lines 204 are composed of conductive paste 1 and conductive paste 2 after metallization heat treatment, wherein the conductive paste 1 has the property of penetrating the dielectric film,
  • the second conductive paste does not have the property of penetrating the dielectric film.
  • the first conductive paste is discontinuously distributed.
  • the second conductive paste partially or completely covers the first conductive paste and connects the area of the first conductive paste.
  • the process of forming the first electrode 20 and the second electrode 21 can be an electroplating process, a transfer process (such as a laser transfer process, a thermal transfer process, etc.), screen printing, physical vapor deposition of metal or metal oxidation.
  • Electrode technology etc.
  • various processes can also be used in combination, for example, printing electrodes first to form power supply points, and then using electroplating process to form the final first electrode 20 and second electrode 21 at the power supply points; or using vapor deposition of metal oxides, for example, A transparent conductive oxide (TCO) may be used, and then the first electrode 20 and the second electrode 21 etc. may be formed by screen printing or transfer printing.
  • TCO transparent conductive oxide
  • the formation method of the first doped layer 11 and the doped film layer 12 is an in-situ doping method or an ex-situ doping method. That is, the first doped layer 11 and the doped film layer 12 can be directly formed, or the intrinsic semiconductor layer and the intrinsic semiconductor film layer can be formed first, and then doped to form the first doped layer 11 and the doped film layer 12 respectively.
  • the first doped layer 11 located in the second doped region 102 and the third region 103 is removed, specifically: in the first doped region 101 and the laminated layer
  • a first protective layer 16 is formed on the first doped layer 11 in the region 104 .
  • the first doped layer 11 and the first protective layer 16 on the second doped region 102 and the third region 103 are removed.
  • the process for forming the first protection layer 16 can be selected from plasma chemical vapor deposition (PECVD) process, atmospheric pressure vapor deposition (APCVD) process and thermal growth process.
  • the method for removing the first protective layer 16 can be pickling, alkali washing, water washing, etc., and can also be removed by using an ultraviolet laser with a smaller pulse width.
  • the first protective layer 16 can be formed by a thermal growth process, that is, under oxidizing atmosphere conditions (such as air, oxygen, etc.), using a heating method, so that the first doped layer 11 A layer of silicon oxide forms on the surface.
  • the first protective layer 16 when the first protective layer 16 is silicon oxide and the first doped layer 11 is a boron-doped p-type polysilicon layer, the first protective layer 16 and the first doped layer 11 can also be processed together formed in.
  • the intrinsic polysilicon layer after forming a layer of intrinsic polysilicon layer, the intrinsic polysilicon layer is doped by using a thermal diffusion process to introduce gases such as BCl 3 or BBr 3 in a heated state (oxygen must be introduced during the thermal diffusion process). , thereby forming a p-type polysilicon layer, and at the same time, a layer of silicon oxide is formed on the surface of the p-type polysilicon layer.
  • the substrate 10 When the substrate 10 is a p-type silicon substrate 10, it can be replaced by a phosphorus-doped thermal diffusion process. At this time, the in-situ doped p-type polysilicon layer can also be replaced by an n-type polysilicon layer.
  • the POCl 3 used for thermal diffusion can likewise form a phosphorus-doped n-type polysilicon layer and silicon oxide on top of it.
  • the mask layer when removing the first protective layer 16 of the laminated structure in which the dielectric layer is silicon oxide, the mask layer can be patterned first, and then use a solution containing fluorine, such as hydrofluoric acid (HF) or fluorine A solution such as ammonium chloride (NH 4 F) is used to clean the first surface of the back contact cell, thereby removing the silicon oxide at the place where no mask material is provided, which is conducive to better passivation in the subsequent process. Afterwards, the mask layer can be removed by alkali washing.
  • fluorine such as hydrofluoric acid (HF) or fluorine
  • NH 4 F ammonium chloride
  • the first doped layer 11 and the first protective layer 16 on the second doped region 102 and the third region 103 can also be removed at one time by using laser etching process, but the damage to the substrate 10 is relatively large.
  • a second protective layer 17 is formed on the doped film layer 12 in the region 102 .
  • the doped film layer 12 located on the third region 103 and the first doped region 101 is removed.
  • the second protective layer 17 is removed.
  • the material selection, processing method and embodiment of the second protection layer 17 are the same as those of the first protection layer 16 .
  • the second protective layer 17 is used to protect the second doped layer 121 and the third doped layer 122, so that the second doped layer 121 and the third doped layer 122 will not be corroded or damaged in the subsequent cleaning or etching process. damage. Since the second protective layer 17 may contain metal ions or other contaminations, in order to ensure better passivation of the back contact cell in the subsequent process, the second protective layer 17 is removed after it is not needed.
  • the second protection layer 17 includes a mask layer.
  • the mask layer is a mask layer of silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon carbide (SiC) deposited by PECVD process.
  • the process of removing the second protection layer 17 may be laser etching.
  • the second protective layer 17 located at the first doped region 101 can be removed first, and then the second protective layer 17 located at the third region 103 can be removed, and the second protective layer 17 located at the third region 103 can also be removed at the same time.
  • the second protective layer 17 on the first doped region 101 and the third region 103 preferably, the second protective layer 17 on the first doped region 101 and the third region 103 is removed at the same time.
  • a step is further included: forming a first interface on the first surface of the substrate 10 Passivation layer 14; In the step of removing the first doped layer 11 located in the second doped region 102 and the third region 103, the step of removing the first doped layer 11 located in the second doped region 102 and the third region 103 is also included.
  • Interface passivation layer 14 The process for forming the first interface passivation layer 14 may be a plasma chemical vapor deposition (PECVD) process, an atmospheric pressure vapor deposition (APCVD) process, a thermal growth process, and the like.
  • PECVD plasma chemical vapor deposition
  • APCVD atmospheric pressure vapor deposition
  • the process for removing the first interface passivation layer 14 may be a laser etching process, an ion milling etching process, a plasma etching process, a reactive ion etching process, an alkali etching process, an acid etching process, and the like.
  • the first interface passivation layer 14 may be a tunnel oxide layer, and the thickness of the tunnel oxide layer ranges from 0.5 nm to 5 nm.
  • the first interface passivation layer 14 is a tunnel oxide layer and the first doped layer 11 is a boron-doped p-type polysilicon layer
  • the first interface passivation layer 14 and the first doped layer 11 can be It is formed in one process, that is, directly grows the tunnel oxide layer and the boron-doped p-type polysilicon layer.
  • the doped film layer 12 after removing the first doped layer 11 located in the second doped region 102 and the third region 103, and Before forming the doped film layer 12 on one surface, it also includes the steps of: forming an interface passivation film layer 15 on the first protective layer 16 and the first surface; In the step of the impurity film layer 12, a step is also included: removing the interface passivation film layer 15 located in the third region 103 and the first doped region 101, so that the interface passivation layer located on the first protective layer 16 in the laminated layer region 104
  • the film layer 15 is the second interface passivation layer 151
  • the interface passivation film layer 15 on the first surface is the third interface passivation layer 152 .
  • the process for forming the interface passivation film layer 15 may be a plasma chemical vapor deposition (PECVD) process, an atmospheric pressure vapor deposition (APCVD) process, a thermal growth process, and the like.
  • the process for removing the interface passivation film layer 15 may be a laser etching process, an ion milling etching process, a plasma etching process, a reactive ion etching process, an alkali etching process, an acid etching process, and the like.
  • the interface passivation layer 15 may be a tunnel oxide layer with a thickness ranging from 1 nm to 2 nm.
  • the interface passivation layer 15 is a tunneling oxide layer and the doped layer 12 is a phosphorus-doped n-type polysilicon layer
  • the interface passivation layer 15 and the doped layer 12 can be formed in one process. , that is, directly grow the tunnel oxide layer and the phosphorus-doped n-type polysilicon layer.
  • removing the first doped layer 11 located in the second doped region 102 and the third region 103 and/or removing the doped film layer 12 located in the third region 103 and the first doped region 101 The method is alkali etching. During the alkali etching process, since both the first interface passivation layer 14 and the interface passivation film layer 15 have relatively thin thicknesses, they can be washed away by alkali together.
  • a step is further included: performing texturing treatment on the third region 103 .
  • the texturing treatment of the third region 103 and the removal of the doped film layer 12 located in the third region 103 can be completed in the same process.
  • alkali etching is used to remove the doped film layer 12 located in the third region 103
  • a textured structure can be formed on the third region 103 at the same time.
  • the first electrode 20 is formed on the first doped layer 11
  • the second electrode 21 is formed on the third doped layer 122 , specifically:
  • the first surface passivation layer 13 is formed on the doped layer 11 , the second doped layer 121 , the third doped layer 122 and the third region 103 .
  • the first electrode 20 is formed on the first surface passivation layer 13 located on the first doped layer 11 .
  • the second electrode 21 is formed on the first surface passivation layer 13 located on the third doped layer 122 .
  • the first electrode 20 is in electrical contact with the first doped layer 11 .
  • the second electrode 21 is in electrical contact with the third doped layer 122 .
  • the process for forming the first surface passivation layer 13 may be a plasma chemical vapor deposition (PECVD) process, a hot wire chemical vapor deposition process, a physical vapor deposition (PVD) process, or a low pressure chemical vapor deposition (LPCVD) process. Or catalytic chemical vapor deposition process, etc.
  • PECVD plasma chemical vapor deposition
  • PVD physical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • catalytic chemical vapor deposition process etc.
  • the method for forming the first electrode 20 and the second electrode 21 can also be coating the electrode slurry on The first surface passivation layer 13 is then sintered, so that the electrode paste passes through the first surface passivation layer 13 to form electrical contact with the first doped layer 11 and the third doped layer 122 respectively.
  • the method for forming the first electrode 20 and the second electrode 21 can also be to first passivate the first surface
  • the first opening 130 and the second opening 131 are opened on the layer 13, and then physical vapor deposition such as printing paste, laser transfer method, electroplating, electroless plating, light-induced electroplating, or vacuum evaporation, magnetron sputtering, etc.
  • the method forms the first electrode 20 and the second electrode 21 in local contact.
  • the hole opening method may include laser film opening, or using an etching slurry that can react with the first surface passivation layer 13 to open a film.
  • the method of making electrical contact through openings can enable the back contact cell to obtain lower metal region recombination, ensuring high conversion efficiency of the back contact cell.
  • the first electrode 20 and the second electrode 21 can also be formed by using one or a combination of the above methods.
  • the substrate 10 is an n-type silicon substrate 10 and the first doped layer 11 is a p-type polysilicon layer
  • a p-type doped region 101 and the stack region 104 are formed.
  • the carriers of the first polarity in the first doped region 101 are collected by the first electrode 20 through the first doped layer 11 through the tunneling effect of carriers.
  • An n-type contact region is formed on the second doped region 102 , and the carriers of the second polarity in the second doped region 102 are collected by the second electrode 21 through the third doped layer 122 .
  • conductive paste can be printed on the first surface passivation layer 13 and sintered to form a metallized contact, a p-type metal region is formed on the p-type contact region, and an n-type metal region is formed on the n-type contact region.
  • the burn-through paste can be printed directly on the first surface passivation layer 13 to form corresponding P-type metal regions and N-type metal regions.
  • first electrode 20 and the second electrode 21 there may be other steps.
  • light injection or electric carrier injection or other heat treatment processes as well as steps such as efficiency binning or slicing.
  • the step of forming the third region 103 may be performed before forming the passivation film on the first surface.
  • the step of forming the third region 103 can also be arranged after the preparation of the outer city back contact cell, but in this way, the passivation of the third region 103 will be sacrificed.
  • a step is further included: A heat treatment process, the heat treatment process crystallizes at least a part of the first doped layer 11 and/or the second doped layer 121 and/or the third doped layer 122 .
  • Heat treatment can be performed on the p-type or n-type semiconductor layer, so that the dopant can be further distributed, or the structure of the semiconductor layer can be changed, which is more conducive to the improvement of battery performance.
  • thermal annealing can make the first doped layer 11 and/or the second doped layer Crystallization of at least a portion of layer 121 and/or third doped layer 122 increases the electrical conductivity of first doped layer 11 , second doped layer 121 and third doped layer 122 .
  • heating and annealing can also make the tunnel oxide layer more favorable for the selective transport of carriers; heating can also allow doping elements to enter the tunnel oxide layer and the substrate 10 , thereby reducing the transmission resistance.
  • a step is further included: performing texturing treatment on the second surface, and forming a second surface passivation layer 18 on the second surface.
  • the process of forming the second surface passivation layer 18 can be plasma chemical vapor deposition (PECVD) process, hot wire chemical vapor deposition process, physical vapor deposition (PVD) process, low pressure chemical vapor deposition (LPCVD) process or catalytic chemical vapor deposition craft etc.
  • PECVD plasma chemical vapor deposition
  • PVD physical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • the patterning treatment of the third region 103 and the texturing treatment of the second surface can be completed in the same process, which reduces one or more production processes. The commercial production capacity is greatly improved.
  • the step of texturing the second surface may be performed after forming the second doped layer 121 and the third doped layer 122 .
  • the step of second surface texturing treatment is usually carried out before the formation of the first doped layer 11 on the first surface, so that the textured surface of the second surface can be easily applied to the first doped layer 11. 1.
  • the second doped layer 121 or the third doped layer 122 is damaged during the removal process or the cleaning process.
  • the second surface texturing process is placed after the formation of the second doped layer 121 and the third doped layer 122 to ensure the integrity of the textured structure and its good light trapping. performance.
  • the textured structure of the second surface is a nano-textured structure
  • various cleaning processes and patterning processes such as etching will almost certainly destroy the textured structure of the nano-textured surface.
  • the textured structure of the light-receiving surface has increasingly used nano-microstructures, so the advantages of post-texturing have become more prominent.
  • the nano-textured textured structure has a better light trapping effect, and since the light-receiving surface of the back-contact cell has no electrodes, the color of the second surface will be more beautiful after applying the nano-textured textured structure on the back-contact cell . Therefore, the nano-textured textured structure is more suitable for back contact batteries.
  • texturing the second surface, texturing the third region 103 and removing the doped film layer 12 located in the first doped region 101 can be completed in the same process.
  • solutions such as potassium hydroxide (KOH), sodium hydroxide (NaOH) or tetramethylammonium hydroxide (TMAH) to remove the doped film layer 12 located in the first doped region 101 by an alkali etching process
  • KOH potassium hydroxide
  • NaOH sodium hydroxide
  • TMAH tetramethylammonium hydroxide
  • the step of forming the second surface passivation layer 18 may be performed simultaneously with the step of forming the first surface passivation layer 13 .
  • an anti-reflection layer may also be formed on the second surface passivation layer 18 .
  • the production method is as follows:
  • an n-type silicon substrate 10 is provided, and then the n-type silicon substrate 10 is sequentially subjected to polishing, cleaning and other damage removal treatments;
  • the second step is to deposit a layer of silicon oxide tunnel oxide layer on the first surface of the n-type silicon substrate 10 as the first interface passivation layer 14 by using PECVD equipment;
  • the third step utilizes PECVD equipment to deposit a layer of intrinsic polysilicon layer on the first interface passivation layer 14, adopts thermal diffusion process then, feeds BCl3 gas under heating state to intrinsic polysilicon layer. doping the polysilicon layer, and simultaneously forming a boron-doped p-type polysilicon layer and a silicon oxide layer located on the surface of the p-type polysilicon layer as the first protective layer 16;
  • the silicon oxide layer on the third region 103 and the second doped region 102 is removed by using an ultraviolet laser, and then the silicon oxide layer on the third region 103 and the second doped region 102 is removed by an alkali etching process.
  • the fifth step is to deposit a silicon oxide layer on the first protective layer 16, the third region 103 and the second doped region 102 as the interface passivation film layer 15 by using PECVD equipment;
  • the sixth step is to deposit a layer of phosphorus-doped n-type polysilicon layer on the interface passivation film layer 15 by PECVD equipment to form the structure shown in Figure 7;
  • a silicon nitride mask layer is deposited on the n-type polysilicon layer as the second protective layer 17 by using PECVD equipment, and then the second protection layer 17 of the first region and the third region 103 is removed by laser. protective layer 17;
  • the eighth step is to remove the n-type polysilicon layer and the interface passivation film layer 15 on the first doped region 101 and the third region 103 by an alkali treatment process, so that the first protection layer located in the stack region 104
  • the interface passivation film layer 15 on the layer 16 is the second interface passivation layer 151
  • the interface passivation film layer 15 located on the first surface is the third interface passivation layer 152, while the third region 103 and the second surface for texturing;
  • the ninth step is to remove the second protective layer 17 by laser
  • the first protective layer 16 on the first doped region 101 is removed by an alkali etching process
  • a layer of silicon nitride is deposited on the first doped region 101, the laminated region 104, the third region 103, and the second doped region 102 as the passivation layer on the first surface by using PECVD equipment.
  • layer 13 while depositing a layer of silicon nitride on the textured structure of the second surface as the second surface passivation layer 18;
  • the twelfth step is to open a first opening 130 with a laser on the first surface passivation layer 13 at the first doped region 101, and then form a first electrode 20 by printing conductive paste.
  • the first electrode 20 is in electrical contact with the first doped layer 11 through the first opening 130;
  • the second opening 131 is opened on the first surface passivation layer 13 at the second doped region 102 by laser, and then printed
  • the second electrode 21 is formed by using a conductive paste, and the second electrode 21 is in electrical contact with the third doped layer 122 through the second opening 131 to form a back contact cell.

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Abstract

本申请公开一种背接触电池及其制作方法，涉及光伏技术领域，用于在保证高的光电转换效率的情况下简化背接触电池的制作工艺。所述背接触电池包括：基底，基底具有相对的第一表面和第二表面，第一表面上具有交错排列的第一掺杂区和第二掺杂区，和介于第一掺杂区和第二掺杂区之间的叠层区和第三区域，叠层区靠近第一掺杂区；形成于第一掺杂区和叠层区上的第一掺杂层；形成于第一掺杂层上且位于叠层区上方的第二掺杂层，形成于第二掺杂区上的第三掺杂层，第三掺杂层和第二掺杂层与第一掺杂层的导电类型相反；以及与第一掺杂层电接触的第一电极和与第三掺杂层电接触的第二电极。本申请提供的背接触电池的制作方法用于制作背接触电池。

Description

一种背接触电池及其制作方法
相关申请的交叉引用
本申请要求在2021年09月30日提交中国专利局、申请号为202111162148.1、名称为“一种背接触电池及其制作方法”的中国专利公开的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及光伏技术领域，尤其涉及一种背接触电池及其制作方法。
背景技术
背接触电池指发射极和金属接触都处于电池的背面，正面没有金属电极遮挡的电池。与正面有遮挡的电池相比，背接触电池具有更高的短路电流和光电转换效率，是目前实现高效晶体硅电池的技术方向之一。
现有的背接触电池制作方法较为复杂，因此需要一种简单并且保证高效率的太阳电池的制作方法。
概述
本申请的目的在于提供一种背接触电池及其制作方法，用于在保证高的光电转换效率的情况下简化背接触电池的制作工艺。
第一方面，发明提供一种背接触电池，包括：基底，基底具有相对的第一表面和第二表面。第一表面上具有交错排列的第一掺杂区和第二掺杂区，以及介于第一掺杂区和第二掺杂区之间的叠层区和第三区域。叠层区靠近第一掺杂区。形成于第一掺杂区和叠层区上的第一掺杂层。形成于第一掺杂层上的第二掺杂层。第二掺杂层仅位于叠层区上方。第一掺杂层与第二掺杂层的导电类型相反。形成于第二掺杂区上的第三掺杂层，第三掺杂层与第一掺杂层的导电类型相反。以及第一电极和第二电极。第一电极与第一掺杂层电接触。第二电极与第三掺杂层电接触。
采用上述技术方案的情况下，基底的第一表面上具有位于第一掺杂区和 第二掺杂区之间且靠近第一掺杂区的叠层区，叠层区上具有依次形成的第一掺杂层和第二掺杂层，第一掺杂层和第二掺杂层的导电类型相反。基于此，第二掺杂层覆盖住其下方的第一掺杂层，保护了第一掺杂层的部分表面，避免了叠层区处的第一掺杂层在后续的工艺处理过程中被破坏或引入杂质，提高了背接触电池的良率和生产效率，同时对第一电性载流子的收集有保证。此外，保留下来的第二掺杂层减少了图形化处理工艺中的处理面积和难度，降低了生产成本，提高了量产时的产能及生产效率。除此之外，第三区域可以将第一掺杂区上的第一掺杂层和第二掺杂区上的第三掺杂层分隔开，有利于保证电池优异的正负极绝缘性能。
在一些可能的实现方式中，还包括位于叠层区上方且位于第一掺杂层和第二掺杂层之间的第一保护层。
采用上述技术方案的情况下，一方面，在逐步形成背接触电池的过程中，形成的第一保护层可以在后续的图形化处理、表面织构化处理和清洗过程中保护第一掺杂层，使得第一掺杂层不会被腐蚀或损伤。另一方面，第一保护层可以将第一掺杂层和第二掺杂层完全分隔开，从而减少后续工艺中第二掺杂层为第一掺杂层带来的不利影响。例如，在没有第一保护层，第一掺杂层直接与第二掺杂层接触的情况下，当第一掺杂层和第二掺杂层中的至少一个为需要晶化转变为掺杂多晶硅层的掺杂非晶硅层时，由于晶化的时间较长，且第二掺杂层和第一掺杂层的导电类型相反，长时间的晶化会使得第二掺杂层中的掺杂元素进入第一掺杂层，对第一掺杂层造成破坏，甚至可能使得第一掺杂层的导电类型改变，导致电池无法正常发电。
在一些可能的实现方式中，第一保护层至少包括介电层和掩膜层中的一种。第一保护层所使用的介电层和/或掩膜层在物理特性或化学特性上与第一掺杂层有较为明显的差异，以保证在利用刻蚀工艺或腐蚀工艺去除位于第二掺杂区和第三区域的第一掺杂层时，第一保护层可以被有效地保留下来。
在一些可能的实现方式中，第一保护层包括硼硅玻璃层和磷硅玻璃层中的一种。此时，第一保护层可以和第一掺杂层一起掺杂形成。
在一些可能的实现方式中，第三区域的表面具有绒面结构。第三区域上不设置电极，可以对第三区域进行织构化处理，使得第三区域上具有绒面结构。由于绒面结构具有良好的陷光效应和减反效应，使得入射到第一表面的 光线也可以被利用，增加了背接触电池在第一表面的吸光效果，使得背接触电池可以双面吸收光能，实现了对光能的进一步利用，提高了背接触电池的发电效率。
在一些可能的实现方式中，第一掺杂区的表面和/或第二掺杂区的表面和/或叠层区的表面为抛光面。
采用上述技术方案的情况下，第一掺杂区、第二掺杂区和叠层区的表面均可以为抛光面，使得从第二表面入射并穿过背接触电池的光线进行再反射，从而使得光线有机会被背接触电池再次利用，从而提高了背接触电池的光电转换效率。此外，抛光后的表面具有更好的平整度，后续在抛光面上形成其他层的效果会更好，有利于减少界面缺陷的产生，进而减少由于缺陷导致的载流子的复合，有利于背接触电池钝化性能的提升，从而提高了背接触电池的光电转换效率。
在一些可能的实现方式中，还包括第一界面钝化层、第二界面钝化层和第三界面钝化层。第一界面钝化层位于基底与第一掺杂层之间。第二界面钝化层位于第二掺杂层与第一保护层之间。第三界面钝化层位于基底与第三掺杂层之间。第一界面钝化层、第二界面钝化层和第三界面钝化层分别对基底、第一保护层和第一掺杂层进行界面钝化，降低界面处载流子的复合，保证了载流子的传输效率。
在一些可能的实现方式中，基底为n型基底，第一掺杂层为p型掺杂层，第二掺杂层和第三掺杂层为n型掺杂层；或，基底为p型基底，第一掺杂层为n型掺杂层，第二掺杂层和第三掺杂层为p型掺杂层。当基底为n型基底时，第一掺杂层为p型掺杂层，第二掺杂层和第三掺杂层均可以为磷掺杂的n型掺杂层，此时，由于磷重掺的区域对金属杂质具有更大的溶解度，第二掺杂层内具有的磷可以为第一掺杂层提供磷吸杂钝化的作用，提高电池效率。
在一些可能的实现方式中，还包括第一表面钝化层。第一表面钝化层覆盖在第一掺杂层、第二掺杂层、第三掺杂层和第三区域上方。第一表面钝化层与第一掺杂层的接触面处具有第一开孔。第一电极通过第一开孔与第一掺杂层电接触。第一表面钝化层与第三掺杂层的接触面处具有第二开孔。第二电极通过第二开孔与第三掺杂层电接触。
采用上述技术方案的情况下，第一掺杂层、第二掺杂层、第三掺杂层和 第三区域的外侧形成一层第一表面钝化层。第一表面钝化层可以对背接触电池进行表面钝化，钝化第一掺杂层、第二掺杂层、第三掺杂层和第三区域处的悬挂键，降低第一表面的载流子复合速度，提高光电转换效率。第一电极和第二电极分别通过第一开孔和第二开孔与第一掺杂层和第三掺杂层电接触，形成金属和半导体的局部欧姆接触，减少了金属电极与第一掺杂层和第三掺杂层的接触面积，降低了接触电阻，进一步降低了载流子在电极表面处的复合速率，提高了开路电压。
在一些可能的实现方式中，叠层区面积占第一掺杂层面积的5％～95％。优选的，叠层区面积占第一掺杂层面积的20％～95％，叠层区的面积越大，第二掺杂层覆盖的第一掺杂层的面积越大，即被保护的第一掺杂层的面积越大，可以更好地保护第一掺杂层在后续的工艺处理中不被腐蚀或损伤。更优的，叠层区面积占第一掺杂层面积的40％～75％，叠层区上方的第一保护层、第二掺杂层等应避免与电极发生接触，此外，叠层区面积过大会有漏电的风险。
第二方面，本申请还提供一种背接触电池的制作方法，包括：
提供一基底，基底具有相对的第一表面和第二表面，第一表面上具有交错排列的第一掺杂区和第二掺杂区，以及介于第一掺杂区和第二掺杂区之间的叠层区和第三区域，叠层区靠近第一掺杂区；
在基底的第一表面上形成第一掺杂层；
去除位于第二掺杂区和第三区域的第一掺杂层；
在第一掺杂层和第一表面上形成掺杂膜层；
去除位于第三区域和第一掺杂区上的掺杂膜层，使得位于叠层区上的掺杂膜层为第二掺杂层，位于第一表面上的掺杂膜层为第三掺杂层；
在第一掺杂层上形成第一电极，在第三掺杂层上形成第二电极。
第二方面或第二方面任一可能的实现方式所提供的背接触电池的制作方法的有益效果，可以参考第一方面或第一方面任一可能的实现方式所描述的背接触电池的有益效果，在此不做赘述。
在一些可能的实现方式中，去除位于第二掺杂区和第三区域的第一掺杂层，具体为：在第一掺杂区和叠层区的第一掺杂层上形成第一保护层。去除第二掺杂区和第三区域上的第一掺杂层和第一保护层。
在一些可能的实现方式中，去除位于第三区域和第一掺杂区上掺杂膜层， 具体为：在位于叠层区和第二掺杂区的掺杂膜层上形成第二保护层。去除位于第三区域和第一掺杂区上的掺杂膜层。去除第二保护层。
在一些可能的实现方式中，在在基底的第一表面上形成第一掺杂层之前，还包括步骤：在基底的第一表面上形成第一界面钝化层；在去除位于第二掺杂区和第三区域的第一掺杂层的步骤中，还包括步骤：去除位于第二掺杂区和第三区域的第一界面钝化层；和/或，在去除位于第二掺杂区和第三区域的第一掺杂层之后，且在在第一掺杂层和第一表面上形成掺杂膜层之前，还包括步骤：在第一保护层和第一表面上形成界面钝化膜层；在去除位于第三区域和第一掺杂区的掺杂膜层的步骤中，还包括步骤：去除位于第三区域和第一掺杂区的界面钝化膜层，使得位于叠层区的第一保护层上的界面钝化膜层为第二界面钝化层，位于第一表面上的界面钝化膜层为第三界面钝化层。
在一些可能的实现方式中，第一掺杂层和掺杂膜层的形成方法为原位掺杂方法或者非原位掺杂方法。
在一些可能的实现方式中，在去除位于第三区域上的掺杂膜层后，还包括步骤：对第三区域进行织构化处理。
在一些可能的实现方式中，在第一掺杂层上形成第一电极，在第三掺杂层上形成第二电极，具体为：在第一掺杂层、第二掺杂层、第三掺杂层和第三区域上形成第一表面钝化层。在位于第一掺杂层的第一表面钝化层上形成第一电极。在位于第三掺杂层的第一表面钝化层上形成第二电极。第一电极与第一掺杂层电接触。第二电极与第三掺杂层电接触。
在一些可能的实现方式中，在在第一掺杂层、第二掺杂层、第三掺杂层和第三区域上形成第一表面钝化层之前，还包括步骤：进行热处理过程，热处理过程将第一掺杂层和/或第二掺杂层和/或第三掺杂层的至少一部分晶化。
在一些可能的实现方式中，去除位于第二掺杂区和第三区域的第一掺杂层和/或去除位于第三区域和第一掺杂区上的掺杂膜层的方法为碱刻蚀。
附图简述
此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1～图3为本申请实施例提供的背接触电池的结构示意图；
图4～图13为本申请实施例提供的背接触电池制作流程的各个阶段状态示意图；
图14为本申请实施例提供的背接触电池的第一表面的示意图；
图15为图14的局部放大图；
图16为本申请实施例提供的具有连续接触电极的背接触电池的第一表面示意图；
图17为本申请实施例提供的具有局部接触电极的背接触电池的第一表面局部示意图。
附图标记：
10-基底，                        101-第一掺杂区，
102-第二掺杂区，                 103-第三区域，
104-叠层区，                     11-第一掺杂层，
12-掺杂膜层，                    121-第二掺杂层，
122-第三掺杂层，                 13-第一表面钝化层，
130-第一开孔，                   131-第二开孔，
14-第一界面钝化层，              15-界面钝化膜层，
151-第二界面钝化层，             152-第三界面钝化层，
16-第一保护层，                  17-第二保护层，
20-第一电极，                    21-第二电极，
201-第一电极主电极，             202-第一电极副栅线，
211-第二电极主电极，             212-第二电极副栅线，
203-连接电极，                   204-细栅线，
18-第二表面钝化层，              205-局部接触点。
详细描述
为了使本申请所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
需要说明的是，当元件被称为“固定于”或“设置于”另一个元件，它可以直 接在另一个元件上或者间接在该另一个元件上。当一个元件被称为是“连接于”另一个元件，它可以是直接连接到另一个元件或间接连接至该另一个元件上。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。“若干”的含义是一个或一个以上，除非另有明确具体的限定。
在本申请的描述中，需要理解的是，术语“上”、“下”、“前”、“后”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
太阳能电池作为新的能源替代方案，在目前的使用越来越广泛。太阳能电池是将太阳的光能转换为电能的装置。太阳能电池利用光生伏特原理产生载流子，然后使用电极将载流子引出，从而利于将电能有效利用。
指状交叉背接触电池，又称为IBC电池。其中IBC是指Interdigitated back contact(中文名称：指状交叉背接触)。IBC电池最大的特点是发射极和金属接触都处于电池的背面，正面没有金属电极遮挡的影响，因此具有更高的短路电流Isc，同时背面可以容许较宽的金属栅线来降低串联电阻Rs从而提高填充因子FF；并且这种正面无遮挡的电池不仅转换效率高，而且看上去更美观，同时，全背电极的组件更易于装配。IBC电池是目前实现高效晶体硅电池的技术方向之一。
但由于IBC电池的制作方法较为复杂，通常需要多步图形化工艺才能完成制备。需要一种简单并且保证高效率的太阳电池的制作方法。
为了解决上述技术问题，在保证高的光电转换效率的情况下简化背接触 电池的制作工艺，本申请实施例提供一种背接触电池。
如图1～图3和图14～图15所示，本申请实施例提供的背接触电池包括：基底10，基底10具有相对的第一表面和第二表面。第一表面上具有交错排列的第一掺杂区101和第二掺杂区102，以及介于第一掺杂区101和第二掺杂区102之间的叠层区104和第三区域103。叠层区104靠近第一掺杂区101。形成于第一掺杂区101和叠层区104上的第一掺杂层11。形成于第一掺杂层11上的第二掺杂层121。第二掺杂层121仅位于叠层区104上方。第一掺杂层11与第二掺杂层121的导电类型相反。形成于第二掺杂区102上的第三掺杂层122，第三掺杂层122与第一掺杂层11的导电类型相反。以及第一电极20和第二电极21。第一电极20与第一掺杂层11电接触。第二电极21与第三掺杂层122电接触。
通过上述背接触电池的结构可知，基底10的第一表面上具有位于第一掺杂区101和第二掺杂区102之间且靠近第一掺杂区101的叠层区104，叠层区104上具有依次形成的第一掺杂层11和第二掺杂层121，第一掺杂层11和第二掺杂层121的导电类型相反。基于此，第二掺杂层121覆盖住其下方的第一掺杂层11，保护了第一掺杂层11的部分表面，避免了叠层区104处的第一掺杂层11在后续的工艺处理过程中被破坏或引入杂质，提高了背接触电池的良率和生产效率，同时对第一电性载流子的收集有保证。此外，保留下来的第二掺杂层121减少了图形化处理工艺中的处理面积和难度，降低了生产成本，提高了量产时的产能及生产效率。除此之外，第三区域103可以将第一掺杂区101上的第一掺杂层11和第二掺杂区102上的第三掺杂层122分隔开，有利于保证电池优异的正负极绝缘性能。
在一些示例中，如图1～图3所示，沿着第一掺杂区101和第二掺杂区102交错排列的方向，第三区域103的宽度范围为10μm～100μm。第三区域103太宽可能会导致背接触电池的有效面积被浪费，有效载流子也难以被收集，从而降低了电池性能。设置在第一掺杂区101和第二掺杂区102之间的第三区域103，使得第一掺杂区101和第二掺杂区102在边界处彼此隔开，取消了现有技术中正电极和负电极之间的绝缘体设计，可以减少生产工艺流程，还可以减少空间复杂度。这样的结构在垂直方向上不会有正负极共存的现象，避免了背接触电池漏电现象的产生；并且可以提高电池在后期产品的可靠性 表现，减少背接触电池的生产工艺难度。
示例性的，如图1～图3所示，第三区域103的宽度可以为10μm，也可以为100μm，还可以为60μm。
其中，基底10为半导体基底10。基底10的材料可以选择硅(Si)或者锗(Ge)等材料或者砷化镓(GaAs)等材料，显然的，在导电类型方面，基底10可以为本征导电基底10、n型导电基底10或者p型导电基底10。优选的，基底10为p型导电基底10或n型导电基底10。与本征导电基底10相比，p型导电基底10或n型导电基底10具有更好的导电率，从而使得最终制得的背接触电池具有更低的体电阻率，从而提高背接触电池的效率。
示例性的，基底10为n型硅基底10。与p型导电基底10相比，n型导电基底10具有少子寿命高、无光衰、弱光性能好等等优点。
第一掺杂层11、第二掺杂层121和第三掺杂层122也均为半导体掺杂层。在物质的内部排列形式方面，第一掺杂层11、第二掺杂层121和第三掺杂层122可以为非晶、微晶、单晶、纳米晶或多晶等。在具体材料方面，第一掺杂层11、第二掺杂层121和第三掺杂层122的材料可以为硅(Si)、锗(Ge)、碳化硅(SiC x)或砷化镓(GaAs)等。在导电类型方面，第一掺杂层11、第二掺杂层121和第三掺杂层122可以为n型掺杂层或p型掺杂层。
在一些示例中，当基底10为n型基底10时，第一掺杂层11可以为p型掺杂层，第二掺杂层121和第三掺杂层122可以为n型掺杂层；或，当基底10为p型基底10时，第一掺杂层11可以为n型掺杂层，第二掺杂层121和第三掺杂层122可以为p型掺杂层。
示例性的，如图1～图3所示，基底10为n型硅基底10，第一掺杂层11为硼掺杂的p型掺杂层，第二掺杂层121和第三掺杂层122均为磷掺杂的n型掺杂层。此时，由于磷重掺的区域对金属杂质具有更大的溶解度，第二掺杂层121内具有的磷可以为第一掺杂层11提供磷吸杂钝化的作用，提高电池效率。
在实际应用中，当第一掺杂区101上的第一掺杂层11为p型掺杂层时，叠层区104上整体的叠层实际上也起p型掺杂层的作用，即叠层区104上第一掺杂层11上方的第二掺杂层121并不导电，只有第一掺杂区101和叠层区104上的第一掺杂层11起传输载流子的作用，之后，第一掺杂层11上的载流 子通过与第一掺杂层11电接触的第一电极20被引出。也可以认为整个电池上的p型区域为第一掺杂区101和叠层区104的合集。
作为一些可能的实现方式，如图1～图3所示，还包括位于叠层区104上方且位于第一掺杂层11和第二掺杂层121之间的第一保护层16。
基于此，一方面，在逐步形成背接触电池的过程中，形成的第一保护层16可以在后续的图形化处理、表面织构化处理和清洗过程中保护第一掺杂层11，使得第一掺杂层11不会被腐蚀或损伤。另一方面，第一保护层16可以将第一掺杂层11和第二掺杂层121完全分隔开，从而减少后续工艺中第二掺杂层121为第一掺杂层11带来的不利影响。例如，在没有第一保护层16，第一掺杂层11直接与第二掺杂层121接触的情况下，当第一掺杂层11和第二掺杂层121中的至少一个为需要晶化转变为掺杂多晶硅层的掺杂非晶硅层时，由于晶化的时间较长，且第二掺杂层121和第一掺杂层11的导电类型相反，长时间的晶化会使得第二掺杂层121中的掺杂元素进入第一掺杂层11，对第一掺杂层11造成破坏，甚至可能使得第一掺杂层11的导电类型改变，导致电池无法正常发电。举例来说，在没有第一保护层16，第一掺杂层11直接与第二掺杂层121接触的情况下，当第一掺杂层11为掺杂硼的P型多晶硅层，第二掺杂层121为掺杂磷的N型非晶硅层，且第二掺杂层121需要晶化转变为N型多晶硅层时，在晶化过程中，第二掺杂层121含有的磷元素可能会进入第一掺杂层11中，对第一掺杂层11造成破坏；进入的磷元素过多还可能导致第一掺杂层11从P型转变为N型，与基底10的导电类型相同，致使电池无法发电。
在一些示例中，第一保护层16至少包括介电层和掩膜层中的一种。第一保护层16所使用的介电层和/或掩膜层在物理特性或化学特性上与第一掺杂层11有较为明显的差异，以保证在利用刻蚀工艺或腐蚀工艺去除位于第二掺杂区102和第三区域103的第一掺杂层11时，第一保护层16可以被有效地保留下来。
在实际应用中，第一保护层16的材料可以为氧化物、氮化物、碳化物、氢化非晶硅中的一种或多种，其中，氧化物包括氧化硅、氮氧化硅、氧化铝、氧化钛、二氧化铪(HfO 2)、氧化镓(Ga 2O 3)、五氧化二钽(Ta 2O 5)、五氧化铌(Nb 2O 5)等物质中的一种或多种；氮化物包括氮化硅、碳氮化硅、氮 化铝、氮化钛(TiN)、氮碳化钛(TiCN)等物质中的一种或多种；碳化物包括碳化硅(SiC)。
例如，当使用碱刻蚀工艺来去除位于第二掺杂区102和第三区域103的第一掺杂层11时，可以选用不会与所使用的碱发生反应的介质层作为第一保护层16，相反的，第一掺杂层11会与所选用的碱反应。基于此，在图形化处理第一掺杂层11的过程中，位于第二掺杂区102和第三区域103的第一掺杂层11被去除，被第一保护层16覆盖的第一掺杂层11得以完整保留。示例性的，可以选用氧化硅、氮化硅或者碳化硅(SiC x)等介电材料作为介电层。其中，当选用氧化物作为介电层时，可以采用热生长工艺形成介电层，即在氧化气氛条件下(如空气、氧气等)，利用加热方法，使得在第一掺杂层11表面形成氧化物介电层。
再例如，当使用激光刻蚀工艺来去除位于第二掺杂区102和第三区域103的第一掺杂层11时，可以选用耐激光烧蚀的掩膜层作为第一保护层16，相反的，第一掺杂层11会被激光烧蚀。基于此，在图形化处理第一掺杂层11的过程中，位于第二掺杂区102和第三区域103的第一掺杂层11被去除，被第一保护层16覆盖的第一掺杂层11得以完整保留。示例性的，所使用的掩膜层可以选用光刻显影或激光图形化的掩膜、可以印刷的胶质掩膜、氮化硅(SiN x)、氧化硅(SiO x)或碳化硅(SiC)等材料。
此外，当第一保护层16为介电层与掩膜层的叠层结构时，优选的，介电层应靠近第一掺杂层11，以保证第一掺杂层11的钝化效果；掩膜层由于具有较多杂质，应远离第一掺杂层11，避免第一掺杂层11被污染。
在一些示例中，第一保护层16包括硼硅玻璃(BSG)层和磷硅玻璃(PSG)层中的一种。此时，第一保护层16可以和第一掺杂层11一起掺杂形成，节省了单独形成第一保护层16的工序。当位于第一保护层16上的第二掺杂层121也需要进行掺杂处理时，位于第一掺杂层11和第二掺杂层121之间的BSG或PSG可以阻挡磷元素或硼元素的扩散，起到隔离作用，更好地保护了第一掺杂层11。
在实际应用中，第一保护层16的材料可以为氧化硅。由于氧化硅不与碱反应的特性，当后续工序中使用碱来进行刻蚀时，氧化硅可以更好地保护第一掺杂层11的完整性。此外，氧化硅具有良好的界面钝化效果，可以钝化第 一掺杂层11表面的悬挂键，抑制载流子在第一掺杂层11表面的复合，进而提高电池的光电转换效率。当第一保护层16的材料为氧化硅时，第一保护层16的厚度范围为20nm～100nm。为了更好地在刻蚀或清洗时保护第一掺杂层11，第一保护层16可以较厚。
作为一些可能的实现方式，如图2和图3所示，第三区域103的表面具有绒面结构。第三区域103上不设置电极，可以对第三区域103进行织构化处理，使得第三区域103上具有绒面结构。由于绒面结构具有良好的陷光效应和减反效应，使得入射到第一表面的光线也可以被利用，增加了背接触电池在第一表面的吸光效果，使得背接触电池可以双面吸收光能，实现了对光能的进一步利用，提高了背接触电池的发电效率。
作为一些可能的实现方式，如图1～图3所示，第一掺杂区101的表面和/或第二掺杂区102的表面和/或叠层区104的表面为抛光面。此时，第一掺杂区101、第二掺杂区102和叠层区104的表面均可以为抛光面，使得从第二表面入射并穿过背接触电池的光线进行再反射，从而使得光线有机会被背接触电池再次利用，从而提高了背接触电池的光电转换效率。此外，抛光后的表面具有更好的平整度，后续在抛光面上形成其他层的效果会更好，有利于减少界面缺陷的产生，进而减少由于缺陷导致的载流子的复合，有利于背接触电池钝化性能的提升，从而提高了背接触电池的光电转换效率。
作为一些可能的实现方式，如图3所示，背接触电池还包括第一界面钝化层14、第二界面钝化层151和第三界面钝化层152。第一界面钝化层14位于基底10与第一掺杂层11之间。第二界面钝化层151位于第二掺杂层121与第一保护层16之间。第三界面钝化层152位于基底10与第三掺杂层122之间。第一界面钝化层14、第二界面钝化层151和第三界面钝化层152分别对基底10、第一保护层16和第一掺杂层11进行界面钝化，降低界面处载流子的复合，保证了载流子的传输效率。
在一些示例中，第一界面钝化层14、第二界面钝化层151和第三界面钝化层152可以为氧化物、氮化物、碳化物、氢化非晶硅中的一种或多种。其中，氧化物包括氧化硅、氮氧化硅、氧化铝、氧化钛、二氧化铪(HfO 2)、氧化镓(Ga 2O 3)、五氧化二钽(Ta 2O 5)、五氧化铌(Nb 2O 5)等物质中的一种或多种；氮化物包括氮化硅、碳氮化硅、氮化铝、氮化钛(TiN)、氮碳化 钛(TiCN)等物质中的一种或多种；碳化物包括碳化硅(SiC)。
在一些示例中，当第一掺杂层11、第二掺杂层121和第三掺杂层122为半导体掺杂层时，第一界面钝化层14、第二界面钝化层151和第三界面钝化层152可以为隧穿氧化层。隧穿氧化层允许多子隧穿进入半导体掺杂层同时阻挡少子通过，进而多子在半导体掺杂层内横向运输被电极收集，减少了载流子的复合，提高了背接触电池的开路电压和短路电流。此时，隧穿氧化层与半导体掺杂层构成隧穿氧化层钝化接触结构，可以实现优异的界面钝化和载流子的选择性收集，提高了背接触电池的光电转换效率。第一界面钝化层14、第二界面钝化层151和第三界面钝化层152均可以为氧化硅界面钝化层。与高温下会晶化转变为多晶硅的非晶硅界面钝化层相比，氧化硅的界面钝化层更耐高温。
作为一些可能的实现方式，如图1～图3所示，背接触电池还包括第一表面钝化层13。第一表面钝化层13覆盖在第一掺杂层11、第二掺杂层121、第三掺杂层122和第三区域103上方。第一表面钝化层13与第一掺杂层11的接触面处具有第一开孔130。第一电极20通过第一开孔130与第一掺杂层11电接触。第一表面钝化层13与第三掺杂层122的接触面处具有第二开孔131。第二电极21通过第二开孔131与第三掺杂层122电接触。
基于此，第一掺杂层11、第二掺杂层121、第三掺杂层122和第三区域103的外侧形成一层第一表面钝化层13。第一表面钝化层13可以对背接触电池进行表面钝化，钝化第一掺杂层11、第二掺杂层121、第三掺杂层122和第三区域103处的悬挂键，降低第一表面的载流子复合速度，提高光电转换效率。第一电极20和第二电极21分别通过第一开孔130和第二开孔131与第一掺杂层11和第三掺杂层122电接触，形成金属和半导体的局部欧姆接触，减少了金属电极与第一掺杂层11和第三掺杂层122的接触面积，降低了接触电阻，进一步降低了载流子在电极表面处的复合速率，提高了开路电压。同时，位于第三区域103的第一表面钝化层13也起到了隔离第二掺杂层121和第三掺杂层122的作用。
在一些示例中，第一表面钝化层13的材料可以为氮化硅、氧化硅、氮氧化硅、氧化铝、碳化硅、非晶硅中的一种或多种。
作为一些可能的实现方式，如图1～图3所示，第二表面具有绒面结构。 第二表面上还具有第二表面钝化层18。第二表面的绒面结构具有良好的陷光效应，可以减少入射到第二表面的光线的反射，提高了对光线的利用率。第二表面钝化层18为第二表面提供了钝化基底10界面的作用，降低了界面处载流子的复合，提高载流子的传输效率，进而提高背接触电池的光电转换效率。
在一些示例中，第二表面钝化层18的材料可以为氮化硅、氧化硅、氮氧化硅、氧化铝、碳化硅、非晶硅中的一种或多种。
作为一些可能的实现方式，背接触电池的第二表面还包括减反射层。减反射层可以形成在第二表面钝化层18上。减反射层可以减少对入射到第二表面的光线的反射，提高对光线的折射，增加对入射到第二表面的光线的利用率，进而提高了背接触电池的光电转换效率。
在一些示例中，第一表面钝化层13和第二表面钝化层18也具有减反射的作用。也可以将钝化层与减反射层层叠，整体起减反射作用。
在一些示例中，减反射层可以为氟化镁(MgF 2)、二氧化硅(SiO 2)、氧化铝(Al 2O 3)、硫化锌(ZnS)、氮化硅(SiN)、二氧化钛(TiO 2)等物质中的一种或多种。
示例性的，减反射层可以为氧化铝减反射层，还可以为氮化硅和氧化硅叠层组成的减反射层。
作为一些可能的实现方式，如图1～图3所示，叠层区104面积占第一掺杂层11面积的5％～95％。优选的，叠层区104面积占第一掺杂层11面积的20％～95％，叠层区104的面积越大，第二掺杂层121覆盖的第一掺杂层11的面积越大，即被保护的第一掺杂层11的面积越大，可以更好地保护第一掺杂层11在后续的工艺处理中不被腐蚀或损伤。更优的，叠层区104面积占第一掺杂层11面积的40％～75％，叠层区104上方的第一保护层16、第二掺杂层121等应避免与第一电极20发生接触，此外，叠层区104面积过大会有漏电的风险。示例性的，第一掺杂区101的宽度范围可以为80μm～300μm，叠层区104的宽度范围可以为60μm～860μm。
示例性的，如图1～图3所示，叠层区104面积可以占第一掺杂层11面积的40％、60％或75％。
在实际应用中，可以将按照叠层区104、第一掺杂区101、叠层区104、 第三区域103、第二掺杂区102和第三区域103排列的部分称为一个周期，一个周期的宽度范围为400μm～2400μm。
如图4～图13所示，基于以上任一实施例所描述的背接触电池，本申请实施例还提供一种背接触电池的制作方法，包括以下步骤：
步骤S100，提供一基底10，基底10具有相对的第一表面和第二表面，第一表面上具有交错排列的第一掺杂区101和第二掺杂区102，以及介于第一掺杂区101和第二掺杂区102之间的叠层区104和第三区域103，叠层区104靠近第一掺杂区101；
步骤S200，在基底10的第一表面上形成第一掺杂层11；
步骤S300，去除位于第二掺杂区102和第三区域103的第一掺杂层11；
步骤S400，在第一掺杂层11和第一表面上形成掺杂膜层12；
步骤S500，去除位于第三区域103和第一掺杂区101上的掺杂膜层12，使得位于叠层区104上的掺杂膜层12为第二掺杂层121，位于第一表面上的掺杂膜层12为第三掺杂层122；
步骤S600，在第一掺杂层11上形成第一电极20，在第三掺杂层122上形成第二电极21。
与现有技术相比，本申请实施例提供的背接触电池的制作方法的有益效果与上述背接触电池的有益效果相同，此处不做赘述。
其中，在实际应用中，基底10需要进行抛光和清洗等去损伤处理。第一掺杂层11、第二掺杂层121和第三掺杂层122的厚度范围均为50nm～500nm。在基底10上形成第一掺杂层11的工艺以及在第一掺杂层11和第一表面上形成掺杂膜层12的工艺可以为等离子体化学气相沉积(PECVD)工艺、热丝化学气相沉积工艺、物理气相沉积(PVD)工艺、低压化学气相沉积(LPCVD)工艺或催化化学气相沉积工艺等。去除位于第二掺杂区102和第三区域103的第一掺杂层11的工艺以及去除位于第三区域103和第一掺杂区101上的掺杂膜层12的工艺，可以为激光刻蚀工艺、离子铣刻蚀工艺、等离子刻蚀工艺、反应离子刻蚀工艺、碱刻蚀工艺和酸刻蚀工艺等。
在实际应用中，如图13所示，第一电极20和第二电极21的宽度范围为5μm～100μm。形成的第一电极20和第二电极21可以为连续接触电极。此时，如图16所示，第一电极20包括第一电极主电极201和第一电极副栅线202， 第二电极21包括第二电极主电极211和第二电极副栅线212。形成的第一电极20和第二电极21也可以为局部接触电极。如图17所示，以第一电极20为例，此时的第一电极20可以包括连接电极203和细栅线204，细栅线204与连接电极203相连，并通过连接电极203导出电流。其中，连续电极与第一掺杂层121不接触，细栅线204与第一掺杂层121接触，或细栅线204上的部分区域与第一掺杂层121接触，其余区域不接触。示例性的，如图17所示，其中连接电极203起到汇流作用，细栅线204起传输作用，不与第一掺杂层121接触，细栅线204上仅有局部接触点205与第一掺杂层121接触。主电极上还可以设置焊盘或电极输出触点以使得电池的电能得以输出。细栅线204可以使用不同的电极浆料制备而成，例如细栅线204由导电浆料一和导电浆料二经金属化热处理后组成，其中导电浆料一具备穿透介质膜的特性，导电浆料二不具备穿透介质膜的特性，导电浆料一为间断式分布，导电浆料二的部分或完全覆盖导电浆料一之上，并将导电浆料一的区域连通。
在实际应用中，形成第一电极20和第二电极21的工艺可以为电镀工艺、转印工艺(例如激光转印工艺，热转印工艺等)、丝网印刷、物理气相沉积金属或者金属氧化物电极的工艺等。显然，各种工艺也可以结合使用，例如先印刷电极形成供电点，然后在供电点加电使用电镀工艺形成最终的第一电极20和第二电极21；或者使用气相沉积金属氧化物，例如，可以使用透明导电氧化物(TCO)，然后通过丝网印刷或者转印形成第一电极20和第二电极21等。
在一些示例中，第一掺杂层11和掺杂膜层12的形成方法为原位掺杂方法或者非原位掺杂方法。即可以直接形成第一掺杂层11和掺杂膜层12，也可以先形成本征半导体层和本征半导体膜层，再分别掺杂形成第一掺杂层11和掺杂膜层12。
作为一些可能的实现方式，如图4～图6所示，去除位于第二掺杂区102和第三区域103的第一掺杂层11，具体为：在第一掺杂区101和叠层区104的第一掺杂层11上形成第一保护层16。去除第二掺杂区102和第三区域103上的第一掺杂层11和第一保护层16。
在实际应用中，形成第一保护层16的工艺可以选用等离子体化学气相沉积(PECVD)工艺、常压气相沉积(APCVD)工艺和热生长工艺等。去除第 一保护层16的方法可以为酸洗、碱洗和水洗等，还可以使用脉冲宽度较小的紫外激光去除。当选用氧化硅作为第一保护层16时，可以采用热生长工艺形成第一保护层16，即在氧化气氛条件下(如空气、氧气等)，利用加热方法，使得在第一掺杂层11表面形成一层氧化硅。
在一些示例中，当第一保护层16为氧化硅，第一掺杂层11为硼掺杂的p型多晶硅层时，还可以将第一保护层16和第一掺杂层11在一道工序中形成。例如，在形成一层本征多晶硅层后，采用热扩散工艺，在加热状态下通入BCl 3或BBr 3等气体(热扩散过程中必定会通入氧气)，将本征多晶硅层进行掺杂，从而形成p型多晶硅层，同时，在p型多晶硅层的表面会形成一层氧化硅。
当基底10为p型硅基底10时，可以替换为掺杂磷的热扩散工艺。此时，原位掺杂的p型多晶硅层也可以替换为n型多晶硅层。热扩散使用的POCl 3也可以同样地形成磷掺杂的n型多晶硅层以及位于其上的氧化硅。
此外，在去除介电层为氧化硅的叠层结构的第一保护层16时，可以先将掩膜层图形化处理，再使用含氟元素的溶液，例如含氢氟酸(HF)或氟化铵(NH 4F)等的溶液对背接触电池的第一表面进行清洗，从而去除未设置掩膜材料处的氧化硅，有利于后续工序中钝化的更好进行。之后可以采用碱洗的方法去除掩膜层。
还可以采用激光刻蚀工艺一次性去除第二掺杂区102和第三区域103上的第一掺杂层11和第一保护层16，但对基底10的损伤较大。
作为一些可能的实现方式，如图6～图10所示，去除位于第三区域103和第一掺杂区101上掺杂膜层12，具体为：在位于叠层区104和第二掺杂区102的掺杂膜层12上形成第二保护层17。去除位于第三区域103和第一掺杂区101上的掺杂膜层12。去除第二保护层17。第二保护层17的材料选择、工艺处理方法及实施例与第一保护层16相同。第二保护层17用于保护第二掺杂层121和第三掺杂层122，使得第二掺杂层121和第三掺杂层122在后续的清洗或刻蚀工序中不会被腐蚀或损伤。由于第二保护层17可能带有金属离子或者其他沾污，为了保证后续工序对背接触电池进行更好地钝化，所以在不需要第二保护层17后进行了去除。
在一些示例中，第二保护层17包括掩膜层。优选的，掩膜层为采用PECVD工艺沉积的一层氮化硅(SiN x)、氧化硅(SiO x)或碳化硅(SiC)掩膜层。 去除第二保护层17的工艺可以为激光刻蚀。在去除第二保护层17的过程中，可以先去除位于第一掺杂区101处的第二保护层17，再去除位于第三区域103处的第二保护层17，也可以同时去除位于第一掺杂区101和第三区域103上的第二保护层17，优选的，同时去除位于第一掺杂区101和第三区域103上的第二保护层17。
作为一些可能的实现方式，如图4～图6所示，在在基底10的第一表面上形成第一掺杂层11之前，还包括步骤：在基底10的第一表面上形成第一界面钝化层14；在去除位于第二掺杂区102和第三区域103的第一掺杂层11的步骤中，还包括步骤：去除位于第二掺杂区102和第三区域103的第一界面钝化层14。形成第一界面钝化层14的工艺可以为等离子体化学气相沉积(PECVD)工艺、常压气相沉积(APCVD)工艺和热生长工艺等。去除第一界面钝化层14的工艺可以为激光刻蚀工艺、离子铣刻蚀工艺、等离子刻蚀工艺、反应离子刻蚀工艺、碱刻蚀工艺和酸刻蚀工艺等。
在一些示例中，第一界面钝化层14可以为隧穿氧化层，隧穿氧化层的厚度范围为0.5nm～5nm。
此外，当第一界面钝化层14为隧穿氧化层，第一掺杂层11为硼掺杂的p型多晶硅层时，可以将第一界面钝化层14和第一掺杂层11在一道工序中形成，即直接生长隧穿氧化层和硼掺杂的p型多晶硅层。
作为一些可能的实现方式，如图6～图10所示，在去除位于第二掺杂区102和第三区域103的第一掺杂层11之后，且在在第一掺杂层11和第一表面上形成掺杂膜层12之前，还包括步骤：在第一保护层16和第一表面上形成界面钝化膜层15；在去除位于第三区域103和第一掺杂区101的掺杂膜层12的步骤中，还包括步骤：去除位于第三区域103和第一掺杂区101的界面钝化膜层15，使得位于叠层区104的第一保护层16上的界面钝化膜层15为第二界面钝化层151，位于第一表面上的界面钝化膜层15为第三界面钝化层152。形成界面钝化膜层15的工艺可以为等离子体化学气相沉积(PECVD)工艺、常压气相沉积(APCVD)工艺和热生长工艺等。去除界面钝化膜层15的工艺可以为激光刻蚀工艺、离子铣刻蚀工艺、等离子刻蚀工艺、反应离子刻蚀工艺、碱刻蚀工艺和酸刻蚀工艺等。
在一些示例中，界面钝化膜层15可以为隧穿氧化层，厚度范围为 1nm～2nm。
此外，当界面钝化膜层15为隧穿氧化层，掺杂膜层12为磷掺杂的n型多晶硅层时，可以将界面钝化膜层15、掺杂膜层12在一道工序中形成，即直接生长隧穿氧化层和磷掺杂的n型多晶硅层。
作为一些可能的实现方式，去除位于第二掺杂区102和第三区域103的第一掺杂层11和/或去除位于第三区域103和第一掺杂区101上的掺杂膜层12的方法为碱刻蚀。在碱刻蚀的过程中，由于第一界面钝化层14和界面钝化膜层15均具有较薄的厚度，可以一起被碱清洗掉。
作为一些可能的实现方式，在去除位于第三区域103上的掺杂膜层12后，还包括步骤：对第三区域103进行织构化处理。
优选的，可以将对第三区域103进行织构化处理和去除位于第三区域103的掺杂膜层12在同一工序中完成。例如，在采用碱刻蚀去除位于第三区域103的掺杂膜层12时，可以同时在第三区域103上形成绒面结构。
作为一些可能的实现方式，如图11～图13所示，在第一掺杂层11上形成第一电极20，在第三掺杂层122上形成第二电极21，具体为：在第一掺杂层11、第二掺杂层121、第三掺杂层122和第三区域103上形成第一表面钝化层13。在位于第一掺杂层11的第一表面钝化层13上形成第一电极20。在位于第三掺杂层122的第一表面钝化层13上形成第二电极21。第一电极20与第一掺杂层11电接触。第二电极21与第三掺杂层122电接触。
在实际应用中，形成第一表面钝化层13的工艺可以为等离子体化学气相沉积(PECVD)工艺、热丝化学气相沉积工艺、物理气相沉积(PVD)工艺、低压化学气相沉积(LPCVD)工艺或催化化学气相沉积工艺等。当背接触电池具有第一表面钝化层13，第一电极20和第二电极21为连续接触电极时，形成第一电极20和第二电极21的方法还可以为将电极浆料涂覆在第一表面钝化层13上，然后经过烧结，使得电极浆料穿过第一表面钝化层13，分别与第一掺杂层11和第三掺杂层122形成电接触。当背接触电池具有第一表面钝化层13，第一电极20和第二电极21为局部接触电极时，形成第一电极20和第二电极21的方法还可以为先在第一表面钝化层13上开设第一开孔130和第二开孔131，然后采用印刷浆料、激光转印法、电镀、化学镀、光诱导电镀、或者真空蒸镀、磁控溅射等物理气相沉积等方法形成局部接触的第一电极20 和第二电极21。开孔方法可以包括激光开膜，或者使用可以和第一表面钝化层13反应的刻蚀浆料开膜。通过开孔进行电接触的方式可以使得背接触电池获得较低的金属区复合，保证了背接触电池的高转换效率。显然的，也可以使用以上方法中的一种或者多种方法的结合来形成第一电极20和第二电极21。例如，使用物理气相沉积(PVD)的种子层配合印刷电极的方法，亦或是丝网印刷电极浆料配合电镀方法，或是激光转印方法和丝网印刷烧结方法的结合等。
当基底10为n型硅基底10，第一掺杂层11为p型多晶硅层时，在上述开膜形成电极的方法下，在第一掺杂区101和叠层区104上形成了p型接触区，通过载流子的隧穿作用，使得第一掺杂区101的第一极性载流子通过第一掺杂层11被第一电极20进行收集。在第二掺杂区102上形成n型接触区，第二掺杂区102的第二极性载流子通过第三掺杂层122被第二电极21进行收集。之后，可以在第一表面钝化层13上印刷导电浆料并烧结形成金属化接触，在p型接触区上形成p型金属区，在n型接触区上形成n型金属区。或者可以直接在第一表面钝化层13上印刷烧穿型浆料，形成对应的P型金属区和N型金属区。最终形成第一电极20和第二电极21。
示例性的，在形成第一电极20和第二电极21后，还可以有其他的步骤。例如光注入或者电注入载流子或者其他热处理的过程等，以及效率分档或者切片等步骤。
在一些示例中，形成第三区域103的步骤可以设在第一表面钝化膜形成前。形成第三区域103的步骤也可以设在外城背接触电池的制备之后，但这样会牺牲第三区域103的部分钝化。
作为一些可能的实现方式，在在第一掺杂层11、第二掺杂层121、第三掺杂层122和第三区域103上形成第一表面钝化层13之前，还包括步骤：进行热处理过程，热处理过程将第一掺杂层11和/或第二掺杂层121和/或第三掺杂层122的至少一部分晶化。可以对p型或n型半导体层进行热处理，使得掺杂剂进一步分布，或者使得半导体层的结构发生变化，更有利于电池性能的提升。例如，当第一掺杂层11、第二掺杂层121和第三掺杂层122为非晶半导体或微晶半导体时，加热退火可以使得第一掺杂层11和/或第二掺杂层121和/或第三掺杂层122的至少一部分晶化，提高了第一掺杂层11、第二掺 杂层121和第三掺杂层122的电导率。此外，加热退火还可以使得隧穿氧化层更有利于进行载流子的选择性传输；加热还可以使得掺杂元素进入隧穿氧化层和基底10中，从而减少传输电阻。
作为一种可能的实现方式，还包括步骤：对第二表面进行织构化处理，并在第二表面上形成第二表面钝化层18。形成第二表面钝化层18的工艺可以为等离子体化学气相沉积(PECVD)工艺、热丝化学气相沉积工艺、物理气相沉积(PVD)工艺、低压化学气相沉积(LPCVD)工艺或催化化学气相沉积工艺等。优选的，对第三区域103的图形化处理和对第二表面的织构化处理可以在同一工序中完成，减少了一个或者多个生产工序。使得商业化生产能力大大提高。
在一些示例中，对第二表面进行织构化处理的步骤可以在形成第二掺杂层121和第三掺杂层122之后。现有技术中，第二表面织构化处理的步骤通常在第一表面上的第一掺杂层11形成之前进行，使得第二表面的织构化表面很容易在对第一掺杂层11、第二掺杂层121或第三掺杂层122的去除过程或者清洗过程中损坏。而本申请实施例中第二表面织构化处理的工序，置于了形成第二掺杂层121和第三掺杂层122之后，保证了织构化结构的完整性和其良好的陷光性能。尤其当第二表面的织构化结构为纳米绒面结构时，各类清洗过程和刻蚀等图形化过程，几乎必定会破坏纳米绒面织构化结构。近年来，受光面的织构化结构越来越广泛使用纳米微结构，因此织构化后置的优势越发凸显。纳米绒面织构化结构具有更好的陷光效果，并且由于背接触电池的受光面没有电极，因此在背接触电池上应用纳米绒面织构化结构后，第二表面的颜色会更加美观。因此，纳米绒面织构化结构更加适用于背接触电池。
优选的，可以将对第二表面进行织构化处理、对第三区域103进行织构化处理和去除位于第一掺杂区101的掺杂膜层12在同一工序中完成。例如，在使用氢氧化钾(KOH)、氢氧化钠(NaOH)或四甲基氢氧化铵(TMAH)等溶液采用碱刻蚀工艺去除位于第一掺杂区101的掺杂膜层12时，可以同时在第三区域103和第二表面上形成绒面结构。
在一些示例中，形成第二表面钝化层18的步骤可以和形成第一表面钝化层13的步骤同时进行。
在一些示例中，在形成第二表面钝化层18后，还可以在第二表面钝化层18上形成一层减反射层。
下面结合具体实施例对本申请进行描述，所举的实施例只用于解释本申请，并非用于限定本申请的范围。
以制作图1所示的n型背接触电池为例，其制作方法具体如下所述：
第一步，提供一n型硅基底10，然后对n型硅基底10依次进行抛光、清洗等去损伤处理；
第二步，利用PECVD设备在n型硅基底10的第一表面上沉积一层氧化硅隧穿氧化层作为第一界面钝化层14；
第三步，如图4和图5所示，在第一界面钝化层14上利用PECVD设备沉积一层本征多晶硅层，然后采用热扩散工艺，在加热状态下通入BCl 3气体对本征多晶硅层进行掺杂，同时形成硼掺杂的p型多晶硅层以及位于p型多晶硅层表面作为第一保护层16的氧化硅层；
第四步，如图6所示，利用紫外激光去除第三区域103和第二掺杂区102上的氧化硅层，然后采用碱刻蚀工艺去除第三区域103和第二掺杂区102上的第一界面钝化层14、p型多晶硅层和第一保护层16；
第五步，利用PECVD设备在第一保护层16、第三区域103和第二掺杂区102上沉积一层氧化硅层作为界面钝化膜层15；
第六步，利用PECVD设备在界面钝化膜层15上沉积一层磷掺杂的n型多晶硅层，形成如图7所示的结构；
第七步，如图8所示，利用PECVD设备在n型多晶硅层上沉积一层氮化硅掩膜层作为第二保护层17，然后利用激光去除第一区域和第三区域103的第二保护层17；
第八步，如图9所示，采用碱处理工艺去除第一掺杂区101和第三区域103上的n型多晶硅层和界面钝化膜层15，使得位于叠层区104的第一保护层16上的界面钝化膜层15为第二界面钝化层151，位于第一表面上的界面钝化膜层15为第三界面钝化层152，同时对第三区域103和第二表面进行织构化处理；
第九步，如图10所示，利用激光去除第二保护层17；
第十步，如图11所示，采用碱刻蚀工艺去除第一掺杂区101上的第一保 护层16；
第十一步，如图12所示，利用PECVD设备在第一掺杂区101、叠层区104、第三区域103和第二掺杂区102上沉积一层氮化硅作为第一表面钝化层13，同时在第二表面的绒面结构上沉积一层氮化硅作为第二表面钝化层18；
第十二步，如图13所示，在第一掺杂区101处的第一表面钝化层13上利用激光开设第一开孔130，然后采用印刷导电浆料的方法形成第一电极20，第一电极20通过第一开孔130与第一掺杂层11电接触；在第二掺杂区102处的第一表面钝化层13上利用激光开设第二开孔131，然后采用印刷导电浆料的方法形成第二电极21，第二电极21通过第二开孔131与第三掺杂层122电接触，形成背接触电池。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种背接触电池，其特征在于，包括：
    基底，所述基底具有相对的第一表面和第二表面，所述第一表面上具有交错排列的第一掺杂区和第二掺杂区，以及介于所述第一掺杂区和所述第二掺杂区之间的叠层区和第三区域，所述叠层区靠近所述第一掺杂区；
    形成于所述第一掺杂区和所述叠层区上的第一掺杂层；
    形成于所述第一掺杂层上的第二掺杂层，所述第二掺杂层仅位于所述叠层区上方，所述第一掺杂层与所述第二掺杂层的导电类型相反；
    形成于所述第二掺杂区上的第三掺杂层，所述第三掺杂层与所述第一掺杂层的导电类型相反；
    以及第一电极和第二电极，所述第一电极与所述第一掺杂层电接触，所述第二电极与所述第三掺杂层电接触。
  2. 根据权利要求1所述的背接触电池，其特征在于，还包括位于所述叠层区上方且位于所述第一掺杂层和所述第二掺杂层之间的第一保护层。
  3. 根据权利要求2所述的背接触电池，其特征在于，所述第一保护层至少包括介电层和掩膜层中的一种。
  4. 根据权利要求3所述的背接触电池，其特征在于，所述第一保护层包括硼硅玻璃层和磷硅玻璃层中的一种。
  5. 根据权利要求1所述的背接触电池，其特征在于，所述第三区域的表面具有绒面结构。
  6. 根据权利要求1所述的背接触电池，其特征在于，所述第一掺杂区的表面和/或所述第二掺杂区的表面和/或所述叠层区的表面为抛光面。
  7. 根据权利要求2所述的背接触电池，其特征在于，还包括第一界面钝化层、第二界面钝化层和第三界面钝化层，所述第一界面钝化层位于所述基底与所述第一掺杂层之间，所述第二界面钝化层位于所述第二掺杂层与所述第一保护层之间，所述第三界面钝化层位于所述基底与所述第三掺杂层之间。
  8. 根据权利要求1所述的背接触电池，其特征在于，所述基底为n型基底，所述第一掺杂层为p型掺杂层，所述第二掺杂层和所述第三掺杂层为n型掺杂层；或，
    所述基底为p型基底，所述第一掺杂层为n型掺杂层，所述第二掺杂层和所述第三掺杂层为p型掺杂层。
  9. 根据权利要求1所述的背接触电池，其特征在于，还包括第一表面钝化层，所述第一表面钝化层覆盖在所述第一掺杂层、所述第二掺杂层、所述第三掺杂层和所述第三区域上方；
    所述第一表面钝化层与所述第一掺杂层的接触面处具有第一开孔，所述第一电极通过所述第一开孔与所述第一掺杂层电接触；所述第一表面钝化层与所述第三掺杂层的接触面处具有第二开孔，所述第二电极通过所述第二开孔与所述第三掺杂层电接触。
  10. 根据权利要求1所述的背接触电池，其特征在于，所述叠层区面积占所述第一掺杂层面积的5％～95％。
  11. 根据权利要求1所述的背接触电池，其特征在于，所述叠层区面积占所述第一掺杂层面积的40％～75％。
  12. 一种权利要求1～11任一项所述的背接触电池的制作方法，其特征在于，包括：
    提供一基底，所述基底具有相对的第一表面和第二表面，所述第一表面上具有交错排列的第一掺杂区和第二掺杂区，以及介于所述第一掺杂区和所述第二掺杂区之间的叠层区和第三区域，所述叠层区靠近所述第一掺杂区；
    在基底的第一表面上形成第一掺杂层；
    去除位于第二掺杂区和第三区域的第一掺杂层；
    在第一掺杂层和第一表面上形成掺杂膜层；
    去除位于第三区域和第一掺杂区上的掺杂膜层，使得位于所述叠层区上的掺杂膜层为第二掺杂层，位于所述第一表面上的掺杂膜层为第三掺杂层；
    在第一掺杂层上形成第一电极，在第三掺杂层上形成第二电极。
  13. 根据权利要求12所述的背接触电池的制作方法，其特征在于，所述去除位于第二掺杂区和第三区域的第一掺杂层，具体为：
    在第一掺杂区和叠层区的第一掺杂层上形成第一保护层；
    去除第二掺杂区和第三区域上的第一掺杂层和第一保护层；和/或，
    所述去除位于第三区域和第一掺杂区上掺杂膜层，具体为：
    在位于叠层区和第二掺杂区的掺杂膜层上形成第二保护层；
    去除位于第三区域和第一掺杂区上的掺杂膜层；
    去除第二保护层。
  14. 根据权利要求13所述的背接触电池的制作方法，其特征在于，在所述在基底的第一表面上形成第一掺杂层之前，还包括步骤：在基底的第一表面上形成第一界面钝化层；
    在所述去除位于第二掺杂区和第三区域的第一掺杂层的步骤中，还包括步骤：去除位于第二掺杂区和第三区域的所述第一界面钝化层；和/或，
    在所述去除位于第二掺杂区和第三区域的第一掺杂层之后，且在所述在第一掺杂层和第一表面上形成掺杂膜层之前，还包括步骤：在第一保护层和第一表面上形成界面钝化膜层；
    在所述去除位于第三区域和第一掺杂区的掺杂膜层的步骤中，还包括步骤：去除位于第三区域和第一掺杂区的界面钝化膜层，使得位于所述叠层区的第一保护层上的界面钝化膜层为第二界面钝化层，位于所述第一表面上的界面钝化膜层为第三界面钝化层。
  15. 根据权利要求12所述的背接触电池的制作方法，其特征在于，所述第一掺杂层和所述掺杂膜层的形成方法为原位掺杂方法或者非原位掺杂方法。
  16. 根据权利要求12所述的背接触电池的制作方法，其特征在于，在所述去除位于第三区域上的掺杂膜层后，还包括步骤：对所述第三区域进行织构化处理。
  17. 根据权利要求12所述的背接触电池的制作方法，其特征在于，所述在第一掺杂层上形成第一电极，在第三掺杂层上形成第二电极，具体为：
    在第一掺杂层、第二掺杂层、第三掺杂层和第三区域上形成第一表面钝化层；
    在位于第一掺杂层的第一表面钝化层上形成第一电极，在位于第三掺杂层的第一表面钝化层上形成第二电极，所述第一电极与所述第一掺杂层电接触，所述第二电极与所述第三掺杂层电接触。
  18. 根据权利要求17所述的背接触电池的制作方法，其特征在于，在所述在第一掺杂层、第二掺杂层、第三掺杂层和第三区域上形成第一表面钝化层之前，还包括步骤：进行热处理过程，所述热处理过程将所述第一掺杂层和/或所述第二掺杂层和/或所述第三掺杂层的至少一部分晶化。
  19. 根据权利要求12所述的背接触电池的制作方法，其特征在于，所述去除位于第二掺杂区和第三区域的第一掺杂层和/或所述去除位于第三区域和第一掺杂区上的掺杂膜层的方法为碱刻蚀。
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