WO2024131681A1 - 一种叠层太阳能电池及其制造方法、光伏组件 - Google Patents

一种叠层太阳能电池及其制造方法、光伏组件 Download PDF

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WO2024131681A1
WO2024131681A1 PCT/CN2023/139251 CN2023139251W WO2024131681A1 WO 2024131681 A1 WO2024131681 A1 WO 2024131681A1 CN 2023139251 W CN2023139251 W CN 2023139251W WO 2024131681 A1 WO2024131681 A1 WO 2024131681A1
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type
layer
cell
transparent conductive
cadmium telluride
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PCT/CN2023/139251
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English (en)
French (fr)
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李春秀
洪承健
殷实
曲铭浩
徐希翔
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隆基绿能科技股份有限公司
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Publication of WO2024131681A1 publication Critical patent/WO2024131681A1/zh

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  • the present invention relates to the technical field of solar cells, and in particular to a stacked solar cell and a manufacturing method thereof, and a photovoltaic module.
  • a tandem solar cell is a cell structure composed of a top cell and a bottom cell.
  • the top cell is made of a light-transmitting material with a wide bandgap.
  • the bottom cell is made of a light-transmitting material with a narrower bandgap. Based on this, sunlight with a shorter wavelength can be used by the top cell located above, and sunlight with a longer wavelength can be transmitted through the top cell to the bottom cell and used by the bottom cell. Therefore, the tandem solar cell can use a wider range of sunlight wavelengths and has a higher light energy utilization rate.
  • the carrier transport capacity of the back contact layer of the cadmium telluride cell is relatively poor, which is not conducive to improving the electrical performance of the tandem solar cell.
  • the object of the present invention is to provide a stacked solar cell and a manufacturing method thereof, and a photovoltaic module, which are used to enhance the carrier transport capacity of the back contact layer included in the cadmium telluride battery, thereby improving the electrical performance of the stacked solar cell.
  • the present invention provides a stacked solar cell, which includes: a bottom cell, a cadmium telluride top cell, an N-type transparent conductive layer and a P-type transparent conductive layer.
  • the cadmium telluride top cell is located above the bottom cell and is connected in series with the bottom cell.
  • the material of the back contact layer included in the cadmium telluride top cell includes at least one of copper-doped zinc telluride, copper-doped magnesium telluride and copper-doped zinc nitride.
  • the N-type transparent conductive layer and the P-type transparent conductive layer are sequentially stacked between the bottom cell and the cadmium telluride top cell.
  • the N-type transparent conductive layer and the front contact layer included in the bottom cell have the same conductivity type.
  • the material of the P-type transparent conductive layer includes at least one of CuAlO x , BaCuSF and CuI, and the concentration of copper ions on the side of the P-type transparent conductive layer facing the light surface is greater than the concentration of copper ions on the side of the back contact layer included in the cadmium telluride top cell facing the backlight surface.
  • the N-type The transparent conductive layer and the P-type transparent conductive layer are sequentially stacked between the bottom cell and the cadmium telluride top cell.
  • the P-type transparent conductive layer contacts the back contact layer included in the cadmium telluride top cell.
  • the material of the back contact layer included in the cadmium telluride top cell includes at least one of copper-doped zinc telluride, copper-doped magnesium telluride and copper-doped zinc nitride.
  • the back contact layer included in the cadmium telluride top cell has the same conductivity type as the P-type transparent conductive layer.
  • the material of the above-mentioned P-type transparent conductive layer includes at least one of CuAlO x , BaCuSF and CuI.
  • the concentration of copper ions on the side of the P-type transparent conductive layer facing the light is greater than the concentration of copper ions on the side of the back contact layer included in the cadmium telluride top cell facing the backlight side.
  • the P-type transparent conductive layer can be used as a doping source, so that the copper ions contained therein are at least diffused into the back contact layer included in the cadmium telluride top cell, so as to increase the concentration of copper ions in the back contact layer included in the cadmium telluride top cell, thereby improving the conductivity of the back contact layer included in the cadmium telluride top cell, which is beneficial to the transport of holes.
  • the contact between the back contact layer included in the cadmium telluride top cell and the P-type transparent conductive layer can also be improved, the back surface field passivation effect can be optimized, and the electrical performance of the stacked solar cell can be improved.
  • the light absorption layer of the cadmium telluride top cell is doped with copper ions.
  • the concentration of copper ions on the back contact layer of the cadmium telluride top cell facing the light side is greater than the concentration of copper ions on the light absorption layer of the cadmium telluride top cell facing the backlight side.
  • the P-type transparent conductive layer can be used as a doping source, so that the copper ions contained therein are diffused in the direction of the light surface to the back contact layer and the light absorption layer included in the cadmium telluride top cell in sequence, thereby improving the conductivity of the back contact layer and the light absorption layer included in the cadmium telluride top cell at the same time, increasing the carrier concentration in the light absorption layer, and making the cadmium telluride top cell have good PN junction characteristics, which is beneficial to the separation and transport of electrons and holes generated after the cadmium telluride top cell absorbs photons, thereby improving the photoelectric conversion efficiency of the cadmium telluride top cell.
  • the refractive index of the P-type transparent conductive layer is less than the refractive index of the back contact layer included in the cadmium telluride top cell.
  • the reflectivity of the backlight side of the cadmium telluride top cell can be reduced, which is conducive to the absorption of the photons reflected back to the cadmium telluride top cell by the bottom cell when the photons refracted by the cadmium telluride top cell enter the bottom cell, thereby improving the utilization rate of the cadmium telluride top cell for short-wavelength sunlight.
  • the refractive index of the P-type transparent conductive layer is less than that of the N-type transparent conductive layer.
  • the reflectivity of the light-facing side of the bottom cell can be reduced, so that more light passing through the cadmium telluride top cell can be refracted into the bottom cell, thereby improving the utilization rate of the bottom cell for long-wavelength sunlight.
  • the carrier concentration of the P-type transparent conductive layer is 8.0 ⁇ 10 19 cm -3 to 3.0 ⁇ 10 20 cm -3 .
  • the width of the space charge region depends on the carrier concentration in the semiconductor layer. Specifically, within a certain range, the higher the carrier concentration in the semiconductor layer, the narrower the width of the space charge region. Based on this, the carrier concentration of the above-mentioned P-type transparent conductive layer is in the range of 8.0 ⁇ 10 19 cm -3 to 3.0 ⁇ 10 20 cm -3 , which can prevent the space charge region of the tunnel junction formed by the P-type transparent conductive layer and the N-type transparent conductive layer from being wide due to the small carrier concentration of the P-type transparent conductive layer, which is beneficial for the holes in the cadmium telluride top cell to tunnel through the space charge region, facilitating the transport of holes. In addition, when the carrier concentration of the P-type transparent conductive layer is within this range, the P-type transparent conductive layer can also have good conductivity, which is beneficial to improving the electron transmission capacity of the P-type transparent conductive layer.
  • the thickness of the N-type transparent conductive layer is 115 nm to 135 nm.
  • the film when the thickness of the film is one-fourth of the wavelength of the light in the film, the film is an anti-reflection film, which has an anti-reflection effect on the incident light. Based on this, the wavelength of the light passing through the cadmium telluride top cell is greater than 850nm. In addition, the thickness of the N-type transparent conductive layer is 115nm to 135nm.
  • the thickness of the N-type transparent conductive layer is equal to one-fourth of the wavelength of the light passing through the cadmium telluride top cell in the N-type transparent conductive layer, so that the N-type transparent conductive layer has an anti-reflection effect on this part of the light, which can make more long-wavelength sunlight refracted into the bottom cell, thereby improving the utilization rate of the bottom cell for long-wavelength sunlight.
  • the carrier concentration of the N-type transparent conductive layer is 8.0 ⁇ 10 19 cm -3 to 3.0 ⁇ 10 20 cm -3 .
  • the beneficial effects in this case can be referred to the beneficial effects analysis when the carrier concentration of the P-type transparent conductive layer is 8.0 ⁇ 10 19 cm -3 to 3.0 ⁇ 10 20 cm -3 , which will not be repeated here.
  • the material of the N-type transparent conductive layer is doped indium oxide and/or doped zinc oxide.
  • the doping element of the doped indium oxide includes at least one of Sn, W, Ce, F, Zr, Ti, Ga, Zn and H.
  • the doping element in the doped zinc oxide includes at least one of Al, Ga and H.
  • doped indium oxide and doped zinc oxide have good light transmittance and conductivity
  • the material of the N-type transparent conductive layer is doped indium oxide and/or doped zinc oxide
  • the doping elements in doped indium oxide and doped zinc oxide are of various types, which is convenient for selecting the appropriate type according to different application scenarios, thereby improving the stacked solar cell provided by the invention. Applicability in different application scenarios.
  • the bottom cell includes a P-type doped silicon layer, an intrinsic silicon layer, an N-type silicon substrate and an N-type doped silicon layer stacked in sequence.
  • the N-type doped silicon layer is the front contact layer of the bottom cell
  • the P-type doped silicon layer is the back contact layer of the bottom cell.
  • the intrinsic silicon layer and the P-type doped silicon layer located on the backlight side of the N-type silicon substrate can form a heterogeneous contact structure.
  • the heterogeneous contact structure has a passivation effect that is better than the tunnel passivation contact structure
  • the carrier recombination rate at the interface between the N-type silicon substrate and the intrinsic silicon layer can be further reduced, which is beneficial to improving the photoelectric conversion efficiency of the bottom cell.
  • the conversion efficiency of the N-type cell is higher. Based on this, when the light absorption layer of the bottom cell is an N-type silicon substrate, the bottom cell can have a higher conversion efficiency, thereby further improving the electrical performance of the stacked solar cell.
  • the N-type doped silicon layer is an N-type doped polysilicon layer.
  • the bottom cell further includes a tunnel passivation layer located between the N-type silicon substrate and the N-type doped polysilicon layer.
  • the tunneling passivation contact structure composed of the tunneling passivation layer and the N-type doped polysilicon layer located on the light-facing side of the N-type silicon substrate can achieve good interface passivation and carrier selective collection, which is beneficial to improve the photoelectric conversion efficiency of the bottom cell.
  • the heterogeneous contact structure made of amorphous silicon and/or microcrystalline silicon materials formed on the light-facing side of the bottom cell will cause the bottom cell to have a low utilization rate of light energy due to severe parasitic absorption.
  • the parasitic absorption generated by the tunneling passivation contact structure in the long wavelength range is weak, so that the long-wavelength sunlight transmitted through the cadmium telluride top cell can be refracted into the bottom cell through the tunneling passivation contact structure, further improving the photoelectric conversion efficiency of the bottom cell.
  • the doping concentration of the doping element in the above-mentioned P-type doped silicon layer gradually decreases along the direction from the bottom cell to the cadmium telluride top cell.
  • a high-low junction can be formed in the P-type doped silicon layer along the direction from the bottom cell to the cadmium telluride top cell.
  • the built-in electric field direction of the high-low junction points from the low doping concentration to the high doping concentration, that is, from the light-facing surface of the P-type doped silicon layer to the backlight surface. Based on this, because the built-in electric field direction of the high-low junction is consistent with the transport direction of holes in the bottom cell, the hole transport capacity of the P-type doped silicon layer can be enhanced, and the photoelectric conversion efficiency of the bottom cell can be further improved.
  • the doping concentration of the doping element on the side of the P-type doped silicon layer away from the intrinsic silicon layer is 5.0 ⁇ 10 20 cm -3 to 1.0 ⁇ 10 22 cm -3 .
  • the doping concentration of the doping element on the side of the P-type doped silicon layer away from the intrinsic silicon layer is higher, so as to improve the height of the P-type doped silicon layer.
  • the built-in electric field strength of the junction further improves the hole transport capacity of the P-type doped silicon layer.
  • the doping concentration of the doping element on the side of the P-type doped silicon layer close to the intrinsic silicon layer is 1.0 ⁇ 10 18 cm -3 to 5.0 ⁇ 10 19 cm -3 .
  • the doping concentration of the doping element on the side of the P-type doped silicon layer close to the intrinsic silicon layer is low, which is conducive to increasing the doping concentration difference between the two opposite sides of the P-type doped silicon layer along the thickness direction, thereby increasing the built-in electric field strength of the high-low junction in the P-type doped silicon layer, and further improving the hole transport capacity of the P-type doped silicon layer.
  • the present invention further provides a photovoltaic module, which includes the stacked solar cell provided by the first aspect and various implementations thereof.
  • the present invention further provides a method for manufacturing a stacked solar cell, the method for manufacturing a stacked solar cell comprising:
  • a semiconductor substrate is formed.
  • An N-type transparent conductive layer and a P-type transparent conductive layer are sequentially stacked on the light-facing surface of the semiconductor substrate.
  • the material of the P-type transparent conductive layer includes at least one of CuAlO x , BaCuSF and CuI.
  • a cadmium telluride top cell is formed on the P-type transparent conductive layer.
  • the formed structure is heat treated so that the copper ions in the P-type transparent conductive layer diffuse into at least the back contact layer included in the cadmium telluride top cell.
  • the material of the back contact layer included in the cadmium telluride top cell includes at least one of copper-doped zinc telluride, copper-doped magnesium telluride and copper-doped zinc nitride.
  • the concentration of copper ions on the side of the P-type transparent conductive layer facing the light surface is greater than the concentration of copper ions on the side of the back contact layer included in the cadmium telluride top cell facing the back light surface.
  • the bottom cell is formed based on the semiconductor substrate.
  • the cadmium telluride top cell is connected in series with the bottom cell.
  • the N-type transparent conductive layer has the same conductivity type as the front contact layer included in the bottom cell.
  • the copper ions in the P-type transparent conductive layer also diffuse into the light absorption layer included in the cadmium telluride top cell.
  • the light absorption layer included in the cadmium telluride top cell is doped with copper ions.
  • the concentration of copper ions on the side of the back contact layer of the cadmium telluride top cell facing the light surface is greater than the concentration of copper ions on the side of the light absorption layer of the cadmium telluride top cell facing the backlight surface.
  • the above-mentioned forming of the semiconductor substrate includes: providing an N-type silicon substrate and forming an N-type doped silicon layer on the light-facing surface of the N-type silicon substrate.
  • the above-mentioned bottom cell formed based on the semiconductor substrate includes: forming an intrinsic silicon layer and a P-type doped silicon layer stacked in sequence on the backlight surface of the N-type silicon substrate in a direction away from the N-type silicon substrate. In the direction from the bottom cell to the cadmium telluride top cell, the bottom cell includes a P-type doped silicon layer stacked in sequence. Silicon layer, intrinsic silicon layer, N-type silicon substrate and N-type doped silicon layer.
  • the manufacturing temperature of the heterogeneous contact structure composed of the intrinsic silicon layer and the P-type doped silicon layer is relatively low, and the formation temperature of the cadmium telluride top cell is relatively high (about 500°C to 700°C)
  • the P-type transparent conductive layer and the cadmium telluride top cell are sequentially formed on the light-facing surface of the semiconductor substrate, the intrinsic silicon layer and the P-type doped silicon layer are then formed on the backlight surface of the semiconductor substrate, which can prevent the high-temperature manufacturing from affecting the intrinsic silicon layer and the P-type doped silicon layer, and ensure that the heterogeneous contact structure composed of the intrinsic silicon layer and the P-type doped silicon layer has excellent interface passivation effect and selective collection of carriers.
  • the N-type transparent conductive layer, the P-type transparent conductive layer and the cadmium telluride top cell are sequentially formed on the N-type doped silicon layer. Based on this, as mentioned above, the formation temperature of the cadmium telluride top cell is relatively high.
  • the doping elements in the N-type doped silicon layer can be diffused to the light-facing side of the N-type silicon substrate, which is beneficial to make the energy band transition between the N-type silicon substrate and the N-type doped silicon layer smoother, thereby improving the field passivation effect on the light-facing side of the N-type silicon substrate and improving the photoelectric conversion efficiency of the bottom cell.
  • a low-temperature manufacturing process is used to form an intrinsic silicon layer and a P-type doped silicon layer stacked in sequence on the backlight surface of the N-type silicon substrate in a direction away from the N-type silicon substrate.
  • the manufacturing temperature range of the low-temperature manufacturing process is 100°C to 200°C. In this case, the manufacturing temperature is within this range, which can prevent the intrinsic silicon layer and the P-type doped silicon layer from being affected by the high manufacturing process temperature, and ensure that the heterogeneous contact structure composed of the intrinsic silicon layer and the P-type doped silicon layer has excellent interface passivation effect and selective collection of carriers.
  • the N-type doped silicon layer is an N-type doped polysilicon layer.
  • the method for manufacturing a stacked solar cell further includes: forming a tunneling passivation layer on the light-facing surface of the N-type silicon substrate.
  • FIG1 is a schematic longitudinal cross-sectional view of the structure of a stacked solar cell provided by an embodiment of the present invention
  • FIG2 is a structural schematic diagram 1 of a tandem solar cell during the manufacturing process provided by an embodiment of the present invention
  • FIG3 is a second structural schematic diagram of a tandem solar cell during the manufacturing process provided by an embodiment of the present invention.
  • FIG4 is a third structural schematic diagram of a tandem solar cell during the manufacturing process provided by an embodiment of the present invention.
  • FIG5 is a fourth structural schematic diagram of a tandem solar cell during the manufacturing process provided by an embodiment of the present invention.
  • FIG6 is a fifth structural diagram of a tandem solar cell during the manufacturing process provided by an embodiment of the present invention.
  • FIG7 is a sixth structural diagram of a tandem solar cell during the manufacturing process provided by an embodiment of the present invention.
  • FIG8 is a seventh structural diagram of a tandem solar cell during the manufacturing process provided by an embodiment of the present invention.
  • FIG9 is a structural schematic diagram 8 of a stacked solar cell during the manufacturing process provided by an embodiment of the present invention.
  • FIG. 10 is a ninth structural diagram of a stacked solar cell during the manufacturing process provided by an embodiment of the present invention.
  • Figure numerals: 1 is an N-type silicon substrate, 2 is a tunneling passivation layer, 3 is an N-type doped silicon layer, 4 is an N-type transparent conductive layer, 5 is a P-type transparent conductive layer, 6 is a back contact layer included in the cadmium telluride top cell, 7 is a light absorption layer included in the cadmium telluride top cell, 8 is a window layer, 9 is an anti-reflection layer, 10 is an intrinsic silicon layer, 11 is a P-type doped silicon layer, 12 is a backlight transparent conductive layer, 13 is a positive electrode, and 14 is a negative electrode.
  • a layer/element when a layer/element is referred to as being "on" another layer/element, the layer/element may be directly on the other layer/element, or there may be an intermediate layer/element between them.
  • the layer/element may be "under” the other layer/element.
  • first and second are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as “first” and “second” may explicitly or implicitly include one or more of the features.
  • the meaning of “multiple” is two or more, unless otherwise clearly and specifically defined.
  • the meaning of “several” is one or more, unless otherwise clearly and specifically defined.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements.
  • installed should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements.
  • a tandem solar cell is a cell structure composed of a top cell and a bottom cell.
  • the top cell is made of a light-transmitting material with a wide bandgap.
  • the bottom cell is made of a light-transmitting material with a narrower bandgap. Based on this, sunlight with a shorter wavelength can be used by the top cell located above, and sunlight with a longer wavelength can be transmitted through the top cell to the bottom cell and used by the bottom cell. Therefore, the tandem solar cell can use a wider range of sunlight wavelengths and has a higher light energy utilization rate.
  • tandem solar cells including a bottom cell and a cadmium telluride top cell
  • the carrier transport capacity of the back contact layer of the cadmium telluride cell is relatively poor, which affects the improvement of the electrical performance of the tandem solar cell.
  • an embodiment of the present invention provides a tandem solar cell.
  • the tandem solar cell comprises: a bottom cell, a cadmium telluride top cell, an N-type transparent conductive layer 4 and a P-type transparent conductive layer 5 .
  • the cadmium telluride top cell is located above the bottom cell and is connected in series with the bottom cell.
  • the material of the back contact layer 6 included in the cadmium telluride top cell includes at least one of copper-doped zinc telluride, copper-doped magnesium telluride and copper-doped zinc nitride.
  • the N-type transparent conductive layer 4 and the P-type transparent conductive layer 5 are sequentially stacked between the bottom cell and the cadmium telluride top cell.
  • the N-type transparent conductive layer 4 and the front contact layer included in the bottom cell have the same conductivity type.
  • the material of the P-type transparent conductive layer 5 includes at least one of CuAlO x , BaCuSF and CuI, and the concentration of copper ions on the side of the P-type transparent conductive layer 5 facing the light side is greater than the concentration of copper ions on the side of the back contact layer 6 included in the cadmium telluride top cell facing the backlight side.
  • the type and structure of the bottom cell can be set according to actual needs, as long as it can be applied to the stacked solar cell provided by the embodiment of the present invention.
  • the bottom cell can be a copper indium gallium selenide bottom cell, a crystalline silicon cell or an amorphous silicon cell.
  • the cadmium telluride top cell may include a window layer 8, a light absorption layer and a back contact layer.
  • the window layer 8 and the back contact layer included in the cadmium telluride top cell have opposite conductivity types.
  • the material of the back contact layer 6 included in the cadmium telluride top cell includes at least one of copper-doped zinc telluride, copper-doped magnesium telluride and copper-doped zinc nitride.
  • the above-mentioned zinc telluride, magnesium telluride and zinc nitride are all P-type semiconductor materials, so
  • the conductivity type of the window layer 8 is N type.
  • the material of the above-mentioned window layer can be any N-type semiconductor material, as long as it can be applied to the stacked solar cell provided in the embodiment of the present invention.
  • the material of the window layer can be doped indium oxide, can be doped zinc oxide, or can be a mixed material of doped indium oxide and doped zinc oxide.
  • the doping elements of doped indium oxide include at least one of Sn, W, Ce, F, Zr, Ti, Ga, Zn and H.
  • the doping elements in doped zinc oxide include at least one of Al, Ga, and H.
  • doped indium oxide and doped zinc oxide have high light transmittance and conductivity
  • the material of the window layer is doped indium oxide and/or doped zinc oxide, not only can more sunlight be refracted from the window layer into the cadmium telluride top cell, thereby improving the utilization rate of light energy of the cadmium telluride top cell, but also can improve the transport capacity of the window layer for electrons, accelerate the separation rate of electrons and holes at the interface of the light absorption layer and the window layer included in the cadmium telluride top cell, suppress carrier recombination, and further improve the photoelectric conversion efficiency of the cadmium telluride top cell.
  • the thickness of the above-mentioned window layer can be set according to actual needs, and is not specifically limited here.
  • the thickness of the above-mentioned window layer can be 30nm to 52nm.
  • the thickness of the window layer can also be set to other appropriate values according to the requirements of the actual application scenario.
  • the light absorption layer included in the above-mentioned cadmium telluride top cell can be any compound absorption layer containing Cd and Te, as long as it can be applied to the stacked solar cell provided in the embodiment of the present invention.
  • the material of the light absorption layer included in the cadmium telluride top cell can include at least one of CdTe, CdSeTe, CdZnTe, CdMgTe and CdMnTe.
  • the thickness of the light absorption layer included in the cadmium telluride top cell in the embodiment of the present invention is not specifically limited.
  • the thickness of the light absorption layer included in the cadmium telluride top cell can be 1 ⁇ m to 4 ⁇ m.
  • the light absorption layer included in the cadmium telluride top cell can be an intrinsic layer or a copper-doped light absorption layer. The concentration of copper ions in the copper-doped light absorption layer is not specifically limited.
  • the material of the back contact layer included in the above-mentioned cadmium telluride top battery may include only one of copper-doped zinc telluride, copper-doped magnesium telluride and copper-doped zinc nitride. Alternatively, it may include any two of copper-doped zinc telluride, copper-doped magnesium telluride and copper-doped zinc nitride. Alternatively, it may also include copper-doped zinc telluride, copper-doped magnesium telluride and copper-doped zinc nitride at the same time.
  • the stoichiometric ratio between different materials and the positional distribution relationship between different materials can be determined according to the actual application scenario, and no specific limitation is made here.
  • the concentration of copper ions in the back contact layer included in the cadmium telluride top battery can also be determined according to the actual application scenario, and no specific limitation is made here.
  • the material of the N-type transparent conductive layer can be indium tin oxide, fluorine-doped tin oxide, doped zinc oxide or doped zinc oxide.
  • the material of the electrical layer is doped indium oxide and/or doped zinc oxide.
  • the doping elements of doped indium oxide include at least one of Sn, W, Ce, F, Zr, Ti, Ga, Zn and H.
  • the doping elements in doped zinc oxide include at least one of Al, Ga, and H.
  • doped indium oxide and doped zinc oxide have good light transmittance and conductivity
  • the material of the N-type transparent conductive layer is doped indium oxide and/or doped zinc oxide, not only can more long-wavelength sunlight be refracted into the bottom battery, thereby improving the utilization rate of the bottom battery for long-wavelength sunlight, but also the electron transport layer of the N-type transparent conductive layer can be improved.
  • the doping elements in doped indium oxide and doped zinc oxide are of multiple types, which is convenient for selecting suitable types according to different application scenarios, thereby improving the applicability of the stacked solar cells provided by the invention in different application scenarios.
  • the thickness of the N-type transparent conductive layer it can be set according to actual needs.
  • the thickness of the N-type transparent conductive layer can be 115nm to 135nm.
  • the film is an anti-reflection film, which has an anti-reflection effect on the incident light. Based on this, the wavelength of the light passing through the cadmium telluride top battery is greater than 850nm.
  • the thickness of the N-type transparent conductive layer is 115nm to 135nm.
  • the thickness of the N-type transparent conductive layer is equal to one-fourth of the wavelength of the light passing through the cadmium telluride top battery in the N-type transparent conductive layer, so that the N-type transparent conductive layer has an anti-reflection effect on this part of the light, which can make more long-wavelength sunlight refracted into the bottom battery, thereby improving the utilization rate of the bottom battery for long-wavelength sunlight.
  • the material of the P-type transparent conductive layer may include only one of CuAlO x , BaCuSF and CuI, or may include any two of CuAlO x , BaCuSF and CuI, or may include CuAlO x , BaCuSF and CuI at the same time. Because the above-mentioned CuAlO x , BaCuSF and CuI are all copper-containing P-type transparent conductive layers. And as shown in FIG1 , the P-type transparent conductive layer 5 is in contact with the back contact layer 6 included in the cadmium telluride top cell.
  • the concentration of copper ions on the side of the P-type transparent conductive layer 5 facing the light side is greater than the concentration of copper ions on the side of the back contact layer 6 included in the cadmium telluride top cell facing the back light side.
  • the diffusion direction is from the high concentration to the low concentration, so the P-type transparent conductive layer 5 can be used as a doping source, so that the copper ions contained therein are at least diffused into the back contact layer 6 included in the cadmium telluride top cell, so as to increase the concentration of copper ions in the back contact layer 6 included in the cadmium telluride top cell, thereby improving the conductivity of the back contact layer 6 included in the cadmium telluride top cell, which is beneficial to the transportation of holes.
  • the contact between the back contact layer 6 included in the cadmium telluride top cell and the P-type transparent conductive layer 5 can also be improved, the back surface field passivation effect can be optimized, and the electrical performance of the stacked solar cell can be improved.
  • the concentration of copper ions on the side of the P-type transparent conductive layer facing the light side is greater than the concentration of copper ions on the side of the back contact layer of the cadmium telluride top cell facing the back light side.
  • the difference between them can be determined according to the requirements for the conductivity of the P-type transparent conductive layer and the back contact layer included in the cadmium telluride top cell in the actual application scenario, and is not specifically limited here.
  • the light absorption layer included in the cadmium telluride top cell may be doped with copper ions. Based on this, the concentration of copper ions on the light absorption layer of the cadmium telluride top cell facing the backlight side may be less than or equal to the concentration of copper ions on the back contact layer of the cadmium telluride top cell facing the light side.
  • the P-type transparent conductive layer can be used as a doping source, so that the copper ions contained therein are diffused in the direction of the light surface to the back contact layer and the light absorption layer of the cadmium telluride top cell in sequence, thereby improving the conductivity of the back contact layer and the light absorption layer of the cadmium telluride top cell at the same time, so that the cadmium telluride top cell has good PN junction characteristics, which is beneficial to the separation and transport of electrons and holes generated after the cadmium telluride top cell absorbs photons, thereby improving the photoelectric conversion efficiency of the cadmium telluride top cell.
  • the refractive index of the above-mentioned P-type transparent conductive layer is smaller than the refractive index of the back contact layer included in the cadmium telluride top cell.
  • the refractive index of the P-type transparent conductive layer and the back contact layer included in the cadmium telluride top cell can be set according to actual needs, and no specific limitation is made here.
  • the refractive index of the P-type transparent conductive layer can be 1.7 to 1.88.
  • the refractive index of the back contact layer included in the cadmium telluride top cell can be about 2.9 to 3.1.
  • the refractive index of the two film layers can be changed by adjusting the manufacturing process and doping concentration of the two film layers, so that the refractive index of the P-type transparent conductive layer is less than the refractive index of the back contact layer included in the cadmium telluride top cell, so as to reduce the reflectivity of the backlight side of the cadmium telluride top cell, which is conducive to the absorption of the photons reflected back to the cadmium telluride top cell by the bottom cell when the photons refracted to the bottom cell by the cadmium telluride top cell enter the bottom cell, thereby improving the utilization rate of the cadmium telluride top cell for short-wavelength sunlight.
  • the refractive index of the P-type transparent conductive layer is smaller than the refractive index of the N-type transparent conductive layer.
  • the refractive index of the P-type transparent conductive layer can be referred to in the previous text and will not be repeated here.
  • the refractive index of the above-mentioned N-type transparent conductive layer can be set according to actual needs, as long as it can be applied to the stacked solar cell provided in the embodiment of the present invention.
  • the refractive index of the N-type transparent conductive layer can be about 1.9 to 2.3.
  • the material of the N-type transparent conductive layer, as well as the manufacturing process and doping concentration of the P-type transparent conductive layer and the N-type transparent conductive layer can be adjusted.
  • the refractive index is changed by methods such as the above, so that the refractive index of the P-type transparent conductive layer is smaller than that of the N-type transparent conductive layer, so as to reduce the reflectivity of the light-facing side of the bottom cell, thereby allowing more light passing through the cadmium telluride top cell to be refracted into the bottom cell, thereby improving the utilization rate of the bottom cell for long-wavelength sunlight.
  • a tunnel junction can be formed between the N-type transparent conductive layer and the P-type transparent conductive layer stacked in sequence along the direction from the bottom battery to the cadmium telluride top battery.
  • the width of the space charge region of the tunnel junction depends on the carrier concentration of the N-type transparent conductive layer and the P-type transparent conductive layer. Specifically, within a certain range, the lower the carrier concentration of at least one of the N-type transparent conductive layer and the P-type transparent conductive layer, the wider the width of the space charge region. On the contrary, the higher the carrier concentration of the N-type transparent conductive layer and the P-type transparent conductive layer, the narrower the width of the space charge region.
  • the carrier concentrations of the P-type transparent conductive layer and the N-type transparent conductive layer can be set according to the requirements for conducting holes in the actual application scenario, and are not specifically limited here.
  • the carrier concentration of the above-mentioned P-type transparent conductive layer is 8.0 ⁇ 10 19 cm -3 to 3.0 ⁇ 10 20 cm -3 .
  • the carrier concentration of the P-type transparent conductive layer when the carrier concentration of the P-type transparent conductive layer is within this range, it can prevent the space charge region of the tunnel junction formed by the P-type transparent conductive layer and the N-type transparent conductive layer from being wide due to the small carrier concentration of the P-type transparent conductive layer, which is beneficial for the holes in the cadmium telluride top cell to tunnel through the space charge region, facilitating the transport of holes.
  • the P-type transparent conductive layer can also have good conductivity, which is beneficial to improving the electron transport capacity of the P-type transparent conductive layer.
  • the carrier concentration of the N-type transparent conductive layer is 8.0 ⁇ 10 19 cm -3 to 3.0 ⁇ 10 20 cm -3 .
  • the beneficial effects in this case can be analyzed with reference to the beneficial effects of the carrier concentration of the P-type transparent conductive layer being 8.0 ⁇ 10 19 cm -3 to 3.0 ⁇ 10 20 cm -3 , which will not be repeated here.
  • the bottom cell may be a crystalline silicon cell.
  • the specific structure of the crystalline silicon cell may be set according to actual needs.
  • the crystalline silicon cell may be a conventional crystalline silicon cell on which a passivation contact structure is not formed.
  • the bottom cell may include a silicon substrate, an N-type doped silicon layer formed on the light-facing surface of the silicon substrate, and a P-type doped silicon layer formed on the backlight surface of the silicon substrate.
  • the silicon substrate may be an intrinsic silicon substrate, an N-type silicon substrate, or a P-type silicon substrate.
  • the crystalline silicon cell may also be a crystalline silicon cell having a passivation contact structure formed thereon.
  • the type of passivation contact structure of the crystalline silicon cell may only include a tunnel passivation contact.
  • the structure may include only a heterogeneous contact structure, or may include both a tunnel passivation contact structure and a heterogeneous contact structure.
  • a tunneling passivation contact structure can be formed only on the light-facing side of the silicon substrate (the tunneling passivation contact structure includes a tunneling passivation layer and an N-type doped polysilicon layer stacked in sequence along a direction away from the silicon substrate), or a tunneling passivation contact structure can be formed only on the backlight side of the silicon substrate (the tunneling passivation contact structure includes a tunneling passivation layer and a P-type doped polysilicon layer stacked in sequence along a direction away from the silicon substrate), and a tunneling passivation contact structure can also be formed on both the light-facing side and the backlight side of the silicon substrate.
  • the heterocontact structure can be formed only on the backlight side of the silicon substrate. Based on this, the formation temperature of the cadmium telluride top cell is relatively high, and the cadmium telluride cell is formed on the light-facing side of the bottom cell. Amorphous silicon and microcrystalline silicon materials are easy to form polycrystalline silicon or monocrystalline silicon at high temperatures. Therefore, forming a heterocontact structure only on the backlight side of the silicon substrate can form a heterocontact structure on the backlight side of the silicon substrate after the cadmium telluride top cell is formed in the actual manufacturing process, so as to prevent the high temperature process from affecting the passivation effect of the heterocontact structure.
  • the bottom cell may include a P-type doped silicon layer, an intrinsic silicon layer, an N-type silicon substrate and an N-type doped silicon layer stacked in sequence.
  • the N-type doped silicon layer is the front contact layer of the bottom cell
  • the P-type doped silicon layer is the back contact layer of the bottom cell.
  • the intrinsic silicon layer and the P-type doped silicon layer located on the backlight side of the N-type silicon substrate can form a heterogeneous contact structure.
  • the heterogeneous contact structure has a passivation effect superior to that of the tunnel passivation contact structure, when a heterogeneous contact structure is formed on the backlight side of the N-type silicon substrate, the carrier recombination rate at the interface between the N-type silicon substrate and the intrinsic silicon layer can be further reduced, which is conducive to improving the photoelectric conversion efficiency of the bottom cell.
  • the conversion efficiency of the N-type cell is higher. Based on this, when the light absorption layer of the bottom cell is an N-type silicon substrate, the bottom cell can have a higher conversion efficiency, thereby further improving the electrical performance of the stacked solar cell.
  • the P-type doped silicon layer may be a P-type amorphous silicon layer, a P-type doped microcrystalline silicon layer, or a mixed layer of P-type doped amorphous silicon and microcrystalline silicon layers.
  • the thickness of the P-type doped silicon layer may be 10 nm to 20 nm.
  • the intrinsic silicon layer may be an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer or a mixed layer of intrinsic amorphous silicon and microcrystalline silicon.
  • the thickness of the intrinsic silicon layer may be 5 nm to 10 nm.
  • the doping concentration of the N-type silicon substrate may be 3.0 ⁇ 10 15 cm -3 to 1.0 ⁇ 10 17 cm -3 .
  • the thickness of the above-mentioned N-type silicon substrate can be 90 ⁇ m to 150 ⁇ m. In this case, the thickness of the N-type silicon substrate is within this range, which can prevent the light absorption depth of the N-type silicon substrate from being insufficient due to the small thickness of the N-type silicon substrate, and improve the utilization rate of the N-type silicon substrate for light energy. At the same time, it can also prevent material waste and low efficiency due to the large thickness of the N-type silicon substrate, and reduce the manufacturing cost of the bottom battery.
  • the light-facing surface and the backlight surface of the above-mentioned N-type silicon substrate can be flat polished surfaces.
  • the light-facing surface and the backlight surface of the N-type silicon substrate 1 can also be velvet. Based on this, because the velvet structure has a light trapping effect, when the light-facing surface and the backlight surface of the N-type silicon substrate 1 are both velvet, the reflectivity of the two surfaces can be reduced, so that more light can be refracted from the two surfaces into the bottom battery, thereby improving the utilization rate of the bottom battery for light energy.
  • the surface of each film layer included in the cadmium telluride top cell will also fluctuate accordingly, thereby reducing the reflectivity of the light-facing surface of the cadmium telluride top cell, which is conducive to refracting more light into the cadmium telluride top cell and improving the utilization rate of light energy by the cadmium telluride top cell.
  • the N-type doped silicon layer may be an N-type doped polysilicon layer or an N-type doped single crystal silicon layer, etc., which is not specifically limited here.
  • the thickness of the N-type doped silicon layer may be 100 nm to 200 nm.
  • the doping concentration of the N-type doped silicon layer may be 7.0 ⁇ 10 19 cm -3 to 1.0 ⁇ 10 20 cm -3 .
  • the thicknesses of the P-type doped silicon layer, intrinsic silicon layer and N-type doped silicon layer, as well as the doping concentrations of the N-type silicon substrate and the N-type doped silicon layer can also be set to other appropriate values according to the requirements of the actual application scenario, and are not specifically limited here.
  • the bottom cell may include a P-type doped silicon layer 11, an intrinsic silicon layer 10, an N-type silicon substrate 1, a tunnel passivation layer 2, and an N-type doped polycrystalline silicon layer stacked in sequence.
  • the N-type doped polycrystalline silicon layer is the front contact layer of the bottom cell
  • the P-type doped silicon layer 11 is the back contact layer of the bottom cell.
  • the tunnel passivation contact structure composed of the tunnel passivation layer 2 and the N-type doped polycrystalline silicon layer located on the light-facing side of the N-type silicon substrate 1 can achieve good interface passivation and carrier selective collection, which is beneficial to improve the photoelectric conversion efficiency of the bottom cell.
  • the heterogeneous contact structure made of amorphous silicon and/or microcrystalline silicon materials formed on the light-facing side of the bottom cell will result in a low utilization rate of light energy by the bottom cell due to severe parasitic absorption.
  • the parasitic absorption produced by the tunnel passivation contact structure in the long wavelength range is relatively weak, so that the long-wavelength sunlight transmitted through the cadmium telluride top cell can be refracted more into the bottom cell through the tunnel passivation contact structure, further improving the photoelectric conversion efficiency of the bottom cell.
  • the material and thickness of the P-type doped silicon layer and the intrinsic silicon layer, and the N-type The materials and doping concentrations of the silicon substrate and the N-type doped silicon layer can refer to the above text and will not be repeated here.
  • the material of the tunneling passivation layer may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium nitride carbide.
  • the embodiment of the present invention does not specifically limit the thickness of the tunneling passivation layer.
  • the thickness of the tunneling passivation layer can be 1nm to 5nm.
  • the doping concentration of the doping element in the above-mentioned P-type doped silicon layer can be gradually reduced along the direction from the bottom cell to the cadmium telluride top cell.
  • a high-low junction can be formed in the P-type doped silicon layer along the direction from the bottom cell to the cadmium telluride top cell.
  • the built-in electric field direction of the high-low junction points from the low doping concentration to the high doping concentration, that is, from the light-facing side of the P-type doped silicon layer to the backlight side. Based on this, because the built-in electric field direction of the high-low junction is consistent with the transport direction of holes in the bottom cell, the hole transport capacity of the P-type doped silicon layer can be enhanced, and the photoelectric conversion efficiency of the bottom cell can be further improved.
  • the doping concentration of the doping element on the side of the P-type doped silicon layer away from the intrinsic silicon layer and the side of the P-type doped silicon layer close to the intrinsic silicon layer can be set according to the requirements for the ability of the P-type doped silicon layer to conduct holes in actual application scenarios, and no specific limitation is made here.
  • the doping concentration of the doping element on the side of the P-type doped silicon layer away from the intrinsic silicon layer may be 5.0 ⁇ 10 20 cm -3 to 1.0 ⁇ 10 22 cm -3 .
  • the doping concentration of the doping element on the side of the P-type doped silicon layer away from the intrinsic silicon layer is higher, so as to improve the built-in electric field strength of the high-low junction in the P-type doped silicon layer, and further improve the hole transport capacity of the P-type doped silicon layer.
  • the doping concentration of the doping element on the side of the P-type doped silicon layer close to the intrinsic silicon layer is 1.0 ⁇ 10 18 cm -3 to 5.0 ⁇ 10 19 cm -3 .
  • the doping concentration of the doping element on the side of the P-type doped silicon layer close to the intrinsic silicon layer is low, which is conducive to increasing the doping concentration difference between the two opposite sides of the P-type doped silicon layer along the thickness direction, thereby increasing the built-in electric field strength of the high-low junction in the P-type doped silicon layer, and further improving the hole transport capacity of the P-type doped silicon layer.
  • the tandem solar cell further includes a positive electrode 13 and a negative electrode 14.
  • the positive electrode 13 is formed on the light-facing side of the window layer 8 included in the cadmium telluride top cell.
  • the negative electrode 14 is formed on the back-facing side of the back contact layer included in the bottom cell.
  • the materials of the positive electrode 13 and the negative electrode 14 can be conductive materials such as silver and/or copper.
  • the bottom cell further includes a backlight transparent conductive layer 12 formed on the side of the P-type doped silicon layer 11 away from the intrinsic silicon layer 10.
  • the backlight transparent conductive layer 12 is formed on the side of the P-type doped silicon layer 11 away from the intrinsic silicon layer 10, which is beneficial for the lateral transport of electrons and then collected by the negative electrode 14.
  • the backlight side of the P-type doped silicon layer 11 can also be field passivated to reduce the recombination rate of carriers on the backlight side of the P-type doped silicon layer 11, thereby improving the photoelectric conversion efficiency of the bottom cell.
  • the conductivity type of the backlight transparent conductive layer can be P-type or N-type.
  • the conductivity type of the backlight transparent conductive layer is preferably N-type.
  • the material and thickness of the backlight transparent conductive layer can be set with reference to the material and thickness of the N-type transparent conductive layer described above, and will not be repeated here.
  • the cadmium telluride top cell further includes an anti-reflection layer 9 formed on the light-facing side of the window layer 8 to allow more light to be refracted into the stacked solar cell, further improving the photoelectric conversion efficiency of the stacked solar cell.
  • the material of the anti-reflection layer may include at least one of magnesium fluoride, silicon oxide, silicon nitride and aluminum oxide.
  • the refractive index of the anti-reflection layer may gradually decrease from the cadmium telluride top cell to the bottom cell to further reduce the reflectivity of the stacked solar cell toward the light-filled side.
  • the thickness of the anti-reflection layer may be set according to the actual application scenario, and is not specifically limited here. For example, the thickness of the anti-reflection layer may be 90nm to 150nm.
  • an embodiment of the present invention further provides a photovoltaic module, which includes the stacked solar cell provided by the first aspect and various implementations thereof.
  • an embodiment of the present invention further provides a method for manufacturing a stacked solar cell.
  • the manufacturing process will be described below based on the cross-sectional views of the operations shown in FIG. 2 to FIG. 10.
  • the method for manufacturing a stacked solar cell includes the following steps:
  • a semiconductor substrate is formed.
  • the semiconductor substrate is used to manufacture a bottom cell included in a stacked solar cell, so the specific formation process of the semiconductor substrate can be determined according to the specific structure of the bottom cell.
  • the bottom cell only includes a P-type doped silicon layer, an intrinsic silicon layer, an N-type silicon substrate, and an N-type doped silicon layer stacked in sequence.
  • the semiconductor substrate may include an N-type silicon substrate and an N-type doped silicon layer.
  • an N-type silicon substrate is provided.
  • an N-type doped silicon layer is formed on the light-facing surface of the N-type silicon substrate.
  • the light-facing surface of the N-type silicon substrate can be directly doped by diffusion or ion implantation to form an N-type doped silicon layer.
  • a layer of intrinsic silicon material layer can be first formed on the light-facing surface of the N-type silicon substrate by low-pressure chemical vapor deposition or other processes. Then, the intrinsic silicon material layer is doped to form an N-type doped silicon layer, thereby obtaining a semiconductor substrate.
  • the N-type silicon substrate can also be subjected to a velvet treatment before forming the N-type doped silicon layer.
  • the base width of the velvet surface can be set according to actual needs.
  • the base width of the velvet surface can be 1 ⁇ m to 5 ⁇ m.
  • the base width of the velvet structure is within this range, which can reduce the reflectivity of the light-facing surface and the backlight surface of the N-type silicon substrate to between 11% and 13%, which is beneficial to increase the short-circuit current of the bottom battery.
  • the base width of the velvet surface is difficult to be less than 1 ⁇ m. Therefore, when the base width of the velvet surface can be 1 ⁇ m to 5 ⁇ m, the difficulty of the velvet treatment can also be reduced.
  • the bottom cell may include a P-type doped silicon layer, an intrinsic silicon layer, an N-type silicon substrate, a tunnel passivation layer, and an N-type doped polysilicon layer stacked in sequence.
  • the semiconductor substrate may include an N-type silicon substrate, a tunnel passivation layer, and an N-type doped polysilicon layer.
  • the N-type silicon substrate 1 may be firstly subjected to a texturing treatment in the above manner.
  • a tunnel passivation layer 2 and an intrinsic silicon material layer located on the tunnel passivation layer 2 may be sequentially formed on the light-facing surface of the N-type silicon substrate 1 by a process such as plasma enhanced chemical vapor deposition. Then, as shown in FIG3 , the intrinsic silicon material layer may be doped by a diffusion combined annealing process, an ion implantation process, or the like, so that the intrinsic silicon material layer forms an N-type doped silicon layer 3, thereby obtaining a semiconductor substrate.
  • a stacked N-type transparent conductive layer 4 and a P-type transparent conductive layer 5 are sequentially formed on the light-facing surface of the semiconductor substrate.
  • the material of the P-type transparent conductive layer 5 includes at least one of CuAlOx , BaCuSF and CuI.
  • the N-type transparent conductive layer and the P-type transparent conductive layer may be formed by sputtering, reactive plasma deposition or spray pyrolysis.
  • the materials, thickness and carrier concentration of the N-type transparent conductive layer and the P-type transparent conductive layer may be referred to above and will not be described here.
  • a cadmium telluride top cell is formed on the P-type transparent conductive layer 5.
  • the formed structure is heat treated so that the copper ions in the P-type transparent conductive layer 5 diffuse into at least the back contact layer 6 included in the cadmium telluride top cell.
  • the material of the back contact layer 6 included in the cadmium telluride top cell includes The copper ion concentration of the P-type transparent conductive layer 5 facing the light side is greater than the copper ion concentration of the back contact layer 6 of the cadmium telluride top cell facing the back light side.
  • a back contact layer 6 included in the cadmium telluride top cell can be formed on the P-type transparent conductive layer 5 by a process such as thermal evaporation or sputtering.
  • the concentration of copper ions in the back contact layer can be greater than or equal to 0, as long as it is less than the concentration of copper ions in the back contact layer after the stacked solar cell is finally manufactured.
  • a light absorption layer 7 included in the cadmium telluride top cell can be formed by a process such as vapor transport or near-space sublimation.
  • a window layer 8 included in the cadmium telluride top cell can be formed by a process such as sputtering, reactive plasma deposition or spray pyrolysis, thereby obtaining a cadmium telluride top cell.
  • information such as the materials and thickness of the back contact layer 6, light absorption layer and window layer 8 included in the cadmium telluride top cell can refer to the previous text.
  • the formed structure can be heat treated by annealing in an annealing furnace and annealing in a vacuum or nitrogen atmosphere, so that the copper ions in the P-type transparent conductive layer are at least diffused into the back contact layer included in the cadmium telluride top battery, so as to at least increase the concentration of copper ions in the back contact layer included in the cadmium telluride top battery, thereby improving the conductivity of the back contact layer included in the cadmium telluride top battery, which is beneficial to the transport of holes.
  • the contact between the back contact layer included in the cadmium telluride top battery and the P-type transparent conductive layer can also be improved, and the back surface field passivation effect can be optimized, thereby improving the electrical performance of the stacked solar cell.
  • the processing temperature and processing time and other conditions of the heat treatment can be set according to actual needs, and are not specifically limited here.
  • an N-type transparent conductive layer, a P-type transparent conductive layer and a cadmium telluride top cell are sequentially formed on the N-type doped silicon layer.
  • the formation temperature of the cadmium telluride top cell is relatively high, so in the process of manufacturing the cadmium telluride top cell at high temperature, the doping elements in the N-type doped silicon layer can be diffused to the light-facing surface of the N-type silicon substrate, which is conducive to making the energy band transition between the N-type silicon substrate and the N-type doped silicon layer smoother, thereby improving the field passivation effect on the light-facing side of the N-type silicon substrate and improving the photoelectric conversion efficiency of the bottom cell.
  • the structure formed above includes a semiconductor substrate, an N-type transparent conductive layer 4 , a P-type transparent conductive layer 5 and a cadmium telluride top cell.
  • the concentration of copper ions on the side of the light absorption layer included in the cadmium telluride top cell facing the backlight side is less than the concentration of copper ions on the side of the back contact layer included in the cadmium telluride top cell facing the light side
  • the copper ions in the P-type transparent conductive layer can be sequentially diffused into the back contact layer and the light absorption layer included in the cadmium telluride top cell. At this time, the cadmium telluride top cell can be simultaneously improved.
  • the conductivity of the back contact layer and the light absorption layer makes the cadmium telluride top cell have good PN junction characteristics, which is beneficial to the separation and transportation of electrons and holes generated after the cadmium telluride top cell absorbs photons, thereby improving the photoelectric conversion efficiency of the cadmium telluride top cell.
  • the cadmium telluride top cell further includes an anti-reflection layer
  • an anti-reflection layer 9 after forming the window layer 8 and before performing the heat treatment, a chemical vapor deposition process or the like can be used to form an anti-reflection layer 9 on the window layer 8.
  • Information such as the material and thickness of the anti-reflection layer 9 can be referred to above.
  • a bottom cell is formed based on a semiconductor substrate.
  • a cadmium telluride top cell is connected in series with the bottom cell.
  • the N-type transparent conductive layer 4 has the same conductivity type as the front contact layer included in the bottom cell.
  • the specific process of forming the bottom cell based on the semiconductor substrate can be determined according to the structure of the bottom cell.
  • the bottom cell may include a P-type doped silicon layer, an intrinsic silicon layer, an N-type silicon substrate, and an N-type doped silicon layer stacked in sequence.
  • the semiconductor substrate includes an N-type silicon substrate and an N-type doped silicon layer.
  • the above-mentioned formation of the bottom cell based on the semiconductor substrate includes the following steps: As shown in FIG8 , along the direction away from the N-type silicon substrate 1, a plasma enhanced chemical vapor deposition process or the like may be used to form an intrinsic silicon layer 10 and a P-type doped silicon layer 11 stacked in sequence on the backlight surface of the N-type silicon substrate 1. Specifically, the materials and thicknesses of the intrinsic silicon layer 10 and the P-type doped silicon layer 11 may refer to the above.
  • the manufacturing temperature of the heterogeneous contact structure composed of the intrinsic silicon layer and the P-type doped silicon layer is relatively low, and the formation temperature of the cadmium telluride top cell is relatively high (approximately 500°C to 700°C)
  • the P-type transparent conductive layer and the cadmium telluride top cell are sequentially formed on the light-facing surface of the semiconductor substrate, the intrinsic silicon layer and the P-type doped silicon layer are then formed on the backlight surface of the semiconductor substrate.
  • a low-temperature manufacturing process can be used to form the above-mentioned intrinsic silicon layer and P-type doped silicon layer.
  • the manufacturing temperature of the low-temperature manufacturing process can be set according to actual needs.
  • the manufacturing temperature range of the low-temperature manufacturing process can be 100°C to 200°C. In this case, the manufacturing temperature is within this range, which can prevent the intrinsic silicon layer and the P-type doped silicon layer from being affected by the high manufacturing process temperature, and ensure that the heterogeneous contact structure composed of the intrinsic silicon layer and the P-type doped silicon layer has excellent interface passivation effect and selective collection of carriers.
  • the manufactured tandem solar cell further includes a backlight surface.
  • a process such as sputtering, reactive plasma deposition or spray pyrolysis can be used to form the backlight side transparent conductive layer 12 located on the side of the P-type doped silicon layer 11 away from the intrinsic silicon layer 10.
  • the material and thickness of the backlight side transparent conductive layer 12 can refer to the above.
  • a negative electrode 14 can be formed on the light-facing side of the cadmium telluride top cell by screen printing, laser transfer or electroplating, and a positive electrode 13 can be formed on the backlight side of the bottom cell to obtain a stacked solar cell.
  • the materials of the positive electrode 13 and the negative electrode 14 can refer to the above.
  • the manufactured laminated solar cell can also be subjected to annealing treatment to crystallize each transparent conductive layer included in the laminated solar cell, remove organic matter in the positive electrode and the negative electrode, and improve the conductivity of each transparent conductive layer, the positive electrode and the negative electrode.
  • the temperature and time of the above annealing treatment can be set according to actual needs.
  • the temperature of the annealing treatment can be 180°C to 220°C, and the annealing time can be 30min to 50min.

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Abstract

本发明公开一种叠层太阳能电池及其制造方法、光伏组件，涉及太阳能电池技术领域，以增强碲化镉电池包括的背接触层的载流子输运能力。叠层太阳能电池包括底电池、碲化镉顶电池、N型透明导电层和P型透明导电层。碲化镉顶电池与底电池串联、且其包括的背接触层的材料包括掺铜碲化锌、掺铜碲化镁和掺铜氮化锌中的至少一种。沿底电池至碲化镉顶电池的方向，N型透明导电层和P型透明导电层依次层叠设置于底电池和碲化镉顶电池之间。N型透明导电层和底电池包括的前接触层的导电类型相同。P型透明导电层的材料包括CuAlOx、BaCuSF和CuI中的至少一种，P型透明导电层朝向向光面一侧的铜离子的浓度大于碲化镉顶电池包括的背接触层朝向背光面一侧的铜离子的浓度。

Description

一种叠层太阳能电池及其制造方法、光伏组件
本申请要求在2022年12月22日提交中国专利局、申请号为202211659430.5、申请名称为“一种叠层太阳能电池及其制造方法、光伏组件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及太阳能电池技术领域，尤其涉及一种叠层太阳能电池及其制造方法、光伏组件。
背景技术
叠层太阳能电池是一种由顶电池和底电池复合而成的电池结构。顶电池由宽带隙的透光材料制造形成。底电池由较窄禁带宽度的透光材料制造形成。基于此，波长较短的太阳光可以被位于上方的顶电池所利用，波长较长的太阳光可以经顶电池透射至底电池内，并被底电池所利用，因此，叠层太阳能电池可以利用太阳光波长范围比较广，具有较高的光能利用率。
但是，现有的包括底电池和碲化镉顶电池的叠层太阳能电池中，碲化镉电池的背接触层的载流子输运能力较差，不利于提升叠层太阳能电池的电学性能。
申请内容
本发明的目的在于提供一种叠层太阳能电池及其制造方法、光伏组件，用于增强碲化镉电池包括的背接触层的载流子输运能力，利于提升叠层太阳能电池的电学性能。
为了实现上述目的，本发明提供了一种叠层太阳能电池，该叠层太阳能电池包括：底电池、碲化镉顶电池、N型透明导电层和P型透明导电层。
上述碲化镉顶电池位于底电池的上方、且与底电池串联。碲化镉顶电池包括的背接触层的材料包括掺铜碲化锌、掺铜碲化镁和掺铜氮化锌中的至少一种。沿底电池至碲化镉顶电池的方向，N型透明导电层和P型透明导电层依次层叠设置于底电池和碲化镉顶电池之间。N型透明导电层和底电池包括的前接触层的导电类型相同。P型透明导电层的材料包括CuAlOx、BaCuSF和CuI中的至少一种，P型透明导电层朝向向光面一侧的铜离子的浓度大于碲化镉顶电池包括的背接触层朝向背光面一侧的铜离子的浓度。
采用上述技术方案的情况下，沿底电池至碲化镉顶电池的方向，N型透 明导电层和P型透明导电层依次层叠设置于底电池和碲化镉顶电池之间。此时，P型透明导电层和碲化镉顶电池包括的背接触层接触。另外，碲化镉顶电池包括的背接触层的材料包括掺铜碲化锌、掺铜碲化镁和掺铜氮化锌中的至少一种。因碲化锌、碲化镁和氮化锌均为P型半导体材料，故碲化镉顶电池包括的背接触层与P型透明导电层的导电类型相同。并且，上述P型透明导电层的材料包括CuAlOx、BaCuSF和CuI中的至少一种。同时，P型透明导电层朝向向光面一侧的铜离子的浓度大于碲化镉顶电池包括的背接触层朝向背光面一侧的铜离子的浓度。在此情况下，在实际的制造过程中，可以将P型透明导电层作为掺杂源，使得其含有的铜离子至少扩散到碲化镉顶电池包括的背接触层内，以增大碲化镉顶电池包括的背接触层内铜离子的浓度，从而可以提高碲化镉顶电池包括的背接触层的导电性，利于空穴的输运。同时，还可以改善碲化镉顶电池包括的背接触层与P型透明导电层之间的接触，优化背面场钝化效果，进而提升叠层太阳能电池的电学性能。
作为一种可能的实现方式，上述碲化镉顶电池包括的光吸收层内掺杂有铜离子。碲化镉顶电池包括的背接触层朝向向光面一侧的铜离子的浓度大于碲化镉顶电池包括的光吸收层朝向背光面一侧的铜离子的浓度。
采用上述技术方案的情况下，在实际的制造过程中，可以将P型透明导电层作为掺杂源，使得其含有的铜离子朝向向光面的方向依次扩散至碲化镉顶电池包括的背接触层和光吸收层，从而可以同时提高碲化镉顶电池包括的背接触层和光吸收层的导电性，增加光吸收层内载流子浓度，使得碲化镉顶电池具有良好的PN结特性，利于碲化镉顶电池吸收光子后产生的电子和空穴的分离和输运，提高碲化镉顶电池的光电转换效率。
作为一种可能的实现方式，上述P型透明导电层的折射率小于碲化镉顶电池包括的背接触层的折射率。在此情况下，可以降低碲化镉顶电池的背光面一侧的反射率，利于经碲化镉顶电池折射至底电池部分光子在进入底电池时，被经底电池反射回碲化镉顶电池的光子所吸收，提高碲化镉顶电池对短波长的太阳光的利用率。
作为一种可能的实现方式，上述P型透明导电层的折射率小于N型透明导电层的折射率。在此情况下，可以降低底电池的向光面一侧的反射率，从而能够使得透过碲化镉顶电池的更多光线折射至底电池内，提高底电池对长波长的太阳光的利用率。
作为一种可能的实现方式，P型透明导电层的载流子浓度为8.0× 1019cm-3至3.0×1020cm-3。
采用上述技术方案的情况下，空间电荷区的宽度取决于半导体层内的载流子浓度。具体的，在一定的范围内，半导体层内的载流子浓度越高空间电荷区的宽度越窄。基于此，上述P型透明导电层的载流子浓度在8.0×1019cm-3至3.0×1020cm-3范围内，可以防止因P型透明导电层的载流子浓度较小而导致由P型透明导电层和N型透明导电层形成的隧穿结的空间电荷区较宽，利于碲化镉顶电池内的空穴隧穿通过该空间电荷区，便于空穴的输运。另外，P型透明导电层的载流子浓度在此范围内，还可以使得P型透明导电层具有良好的导电性，利于提高P型透明导电层的电子传输能力。
作为一种可能的实现方式，上述N型透明导电层的厚度为115nm至135nm。
采用上述技术方案的情况下，当薄膜的厚度为光在该薄膜中波长的四分之一时，该薄膜为增透膜，对入射光具有减反作用。基于此，因透过碲化镉顶电池的光线的波长大于850nm。并且，N型透明导电层的厚度为115nm至135nm。此时，N型透明导电层的厚度等于透过碲化镉顶电池的光线在N型透明导电层中波长的四分之一，使得N型透明导电层对该部分光线具有减反作用，可以使得更多的长波长的太阳光折射至底电池内，提高底电池对长波长太阳光的利用率。
作为一种可能的实现方式，上述N型透明导电层的载流子浓度为8.0×1019cm-3至3.0×1020cm-3。该情况下具有的有益效果可以参考前文所述的P型透明导电层的载流子浓度为8.0×1019cm-3至3.0×1020cm-3时的有益效果分析，此处不再赘述。
作为一种可能的实现方式，上述N型透明导电层的材料为掺杂氧化铟和/或掺杂氧化锌。其中，掺杂氧化铟的掺杂元素包括Sn、W、Ce、F、Zr、Ti、Ga、Zn和H中的至少一种。掺杂氧化锌内的掺杂元素包括Al、Ga、H中的至少一种。
采用上述技术方案的情况下，因掺杂氧化铟和掺杂氧化锌均具有良好的透光性和导电性，故在N型透明导电层的材料为掺杂氧化铟和/或掺杂氧化锌的情况下，不仅可以使得更多的长波长的太阳光折射至底电池内，提高底电池对长波长太阳光的利用率，还可以提高N型透明导电层的电子传输层。另外，掺杂氧化铟和掺杂氧化锌中的掺杂元素均具有多种类型，便于根据不同的应用场景选择合适的种类，从而可以提高被发明提供的叠层太阳能电池 在不同应用场景下的适用性。
作为一种可能的实现方式，沿底电池至碲化镉顶电池的方向，底电池包括依次层叠设置的P型掺杂硅层、本征硅层、N型硅衬底和N型掺杂硅层。N型掺杂硅层为底电池的前接触层，P型掺杂硅层为底电池的背接触层。
采用上述技术方案的情况下，位于N型硅衬底背光面一侧的本征硅层和P型掺杂硅层可以组成异质接触结构。基于此，因异质接触结构具有优于隧穿钝化接触结构的钝化效果，故在N型硅衬底的背光面一侧形成有异质接触结构的情况下，可以进一步降低N型硅衬底与本征硅层界面处的载流子复合速率，利于提高底电池的光电转换效率。另外，与P型电池相比，N型电池的转换效率更高。基于此，在底电池的光吸收层为N型硅衬底的情况下，可以使得底电池具有更高的转换效率，从而可以进一步提高叠层太阳能电池的电学性能。
作为一种可能的实现方式，上述N型掺杂硅层为N型掺杂多晶硅层。底电池还包括位于N型硅衬底与N型掺杂多晶硅层之间的隧穿钝化层。
采用上述技术方案的情况下，位于N型硅衬底的向光面一侧的隧穿钝化层和N型掺杂多晶硅层组成的隧穿钝化接触结构，其能够实现良好的界面钝化和载流子选择性收集，利于提高底电池的光电转换效率。另外，因非晶硅和微晶硅材料具有较高的吸光系数，故在底电池的向光面一侧形成非晶硅和/或微晶硅材料制成的异质接触结构会因严重的寄生吸收而导致底电池对光能的利用率较低。而隧穿钝化接触结构在长波长范围内产生的寄生吸收较弱，使得经碲化镉顶电池透过的长波长太阳光可以更多经隧穿钝化接触结构折射至底电池内，进一步提高底电池的光电转换效率。
作为一种可能的实现方式，上述P型掺杂硅层内掺杂元素的掺杂浓度沿底电池至碲化镉顶电池的方向逐渐降低。在此情况下，沿底电池至碲化镉顶电池的方向，P型掺杂硅层内可以形成高低结。并且，该高低结的内建电场方向由低掺杂浓度指向高掺杂浓度，即由P型掺杂硅层的向光面指向背光面。基于此，因该高低结的内建电场方向与底电池内空穴的输运方向一致，从而可以增强P型掺杂硅层的空穴传输能力，进一步提高底电池的光电转换效率。
作为一种可能的实现方式，上述P型掺杂硅层背离本征硅层一侧的掺杂元素的掺杂浓度为5.0×1020cm-3至1.0×1022cm-3。此时，P型掺杂硅层背离本征硅层一侧的掺杂元素的掺杂浓度较高，以利于提高P型掺杂硅层内高低 结的内建电场强度，进一步提高P型掺杂硅层的空穴传输能力。
作为一种可能的实现方式，上述P型掺杂硅层靠近本征硅层一侧的掺杂元素的掺杂浓度为1.0×1018cm-3至5.0×1019cm-3。此时，P型掺杂硅层靠近本征硅层一侧的掺杂元素的掺杂浓度较低，利于增大P型掺杂硅层沿厚度方向相对两面的掺杂浓度差，从而可以提高P型掺杂硅层内高低结的内建电场强度，进一步提高P型掺杂硅层的空穴传输能力。
第二方面，本发明还提供了一种光伏组件，该光伏组件包括上述第一方面及其各种实现方式提供的叠层太阳能电池。
第三方面，本发明还提供了一种叠层太阳能电池的制造方法，该叠层太阳能电池的制造方法包括：
形成半导体基底。
在半导体基底的向光面上依次形成层叠设置的N型透明导电层和P型透明导电层。P型透明导电层的材料包括CuAlOx、BaCuSF和CuI中的至少一种。
在P型透明导电层上形成碲化镉顶电池。
对已形成的结构进行热处理，以使得P型透明导电层内的铜离子至少扩散到碲化镉顶电池包括的背接触层内。碲化镉顶电池包括的背接触层的材料包括掺铜碲化锌、掺铜碲化镁和掺铜氮化锌中的至少一种。P型透明导电层朝向向光面一侧的铜离子的浓度大于碲化镉顶电池包括的背接触层朝向背光面一侧的铜离子的浓度。
基于半导体基底形成底电池。碲化镉顶电池与底电池串联。N型透明导电层与底电池包括的前接触层的导电类型相同。
作为一种可能的实现方式，在热处理过程中，P型透明导电层内的铜离子还扩散至碲化镉顶电池包括的光吸收层内。其中，碲化镉顶电池包括的光吸收层内掺杂有铜离子。碲化镉顶电池包括的背接触层朝向向光面一侧的铜离子的浓度大于碲化镉顶电池包括的光吸收层朝向背光面一侧的铜离子的浓度。
作为一种可能的实现方式，上述形成半导体基底，包括：提供一N型硅衬底。在N型硅衬底的向光面上形成N型掺杂硅层。
上述基于半导体基底形成底电池，包括：沿背离N型硅衬底的方向，形成依次层叠设置于N型硅衬底的背光面上的本征硅层和P型掺杂硅层。其中，沿底电池至碲化镉顶电池的方向，底电池包括依次层叠设置的P型掺杂 硅层、本征硅层、N型硅衬底和N型掺杂硅层。
采用上述技术方案的情况下，因本征硅层和P型掺杂硅层组成的异质接触结构的制造温度相对较低，而碲化镉顶电池的形成温度较高(大约在500℃至700℃)，故在半导体基底的向光面上依次形成N型透明导电层、P型透明导电层和碲化镉顶电池后，再在半导体基底的背光面上形成本征硅层和P型掺杂硅层，可以防止高温制造对本征硅层和P型掺杂硅层造成影响，确保本征硅层和P型掺杂硅层组成的异质接触结构具有优异的界面钝化效果和载流子的选择性收集。另外，在N型硅衬底的向光面上形成N型掺杂硅层后，依次在N型掺杂硅层上形成N型透明导电层、P型透明导电层和碲化镉顶电池。基于此，如前文所述，碲化镉顶电池的形成温度较高，因此在高温下制造碲化镉顶电池的过程中可以使得N型掺杂硅层内的掺杂元素扩散至N型硅衬底的向光面，利于使得N型硅衬底和N型掺杂硅层之间的能带过渡的更为平缓，进而可以提高N型硅衬底向光面一侧的场钝化效果，提升底电池的光电转换效率。
作为一种可能的实现方式，采用低温制造工艺，沿背离N型硅衬底的方向，形成依次层叠设置于N型硅衬底的背光面上的本征硅层和P型掺杂硅层。其中，低温制造工艺的制造温度范围为100℃至200℃。在此情况下，制造温度在此范围内，可以防止因制造工艺温度较高而对本征硅层和P型掺杂硅层造成影响，确保本征硅层和P型掺杂硅层组成的异质接触结构具有优异的界面钝化效果和载流子的选择性收集。
作为一种可能的实现方式，上述N型掺杂硅层为N型掺杂多晶硅层。在此情况下，上述提供一N型硅衬底后，在N型硅衬底的向光面上形成N型掺杂硅层前，叠层太阳能电池的制造方法还包括：在N型硅衬底的向光面上形成隧穿钝化层。
本发明中第二方面和第三方面及其各种实现方式的有益效果，可以参考第一方面及其各种实现方式中的有益效果分析，此处不再赘述。
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其它目的、特征和优点能够更明显易懂，以下特举本申请的具体实施方式。
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此处所说明的附图用来提供对本申请的进一步理解，构成本申请的一部分，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的不当限定。在附图中：
图1为本发明实施例提供的叠层太阳能电池的结构纵向剖视示意图；
图2为本发明实施例提供的一种叠层太阳能电池的制造过程中的结构示意图一；
图3为本发明实施例提供的一种叠层太阳能电池的制造过程中的结构示意图二；
图4为本发明实施例提供的一种叠层太阳能电池的制造过程中的结构示意图三；
图5为本发明实施例提供的一种叠层太阳能电池的制造过程中的结构示意图四；
图6为本发明实施例提供的一种叠层太阳能电池的制造过程中的结构示意图五；
图7为本发明实施例提供的一种叠层太阳能电池的制造过程中的结构示意图六；
图8为本发明实施例提供的一种叠层太阳能电池的制造过程中的结构示意图七；
图9为本发明实施例提供的一种叠层太阳能电池的制造过程中的结构示意图八；
图10为本发明实施例提供的一种叠层太阳能电池的制造过程中的结构示意图九。
附图标记：1为N型硅衬底，2为隧穿钝化层，3为N型掺杂硅层，4为N型透明导电层，5为P型透明导电层，6为碲化镉顶电池包括的背接触层，7为碲化镉顶电池包括的光吸收层，8为窗口层，9为减反射层，10为本征硅层，11为P型掺杂硅层，12为背光面透明导电层，13为正电极，14为负电极。
具体实施例
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描 述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
为了使本申请所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
在附图中示出了根据本公开实施例的各种结构示意图。这些图并非是按比例绘制的，其中为了清楚表达的目的，放大了某些细节，并且可能省略了某些细节。图中所示出的各种区域、层的形状以及它们之间的相对大小、位置关系仅是示例性的，实际中可能由于制造公差或技术限制而有所偏差，并且本领域技术人员根据实际所需可以另外设计具有不同形状、大小、相对位置的区域/层。
在本公开的上下文中，当将一层/元件称作位于另一层/元件“上”时，该层/元件可以直接位于该另一层/元件上，或者它们之间可以存在居中层/元件。另外，如果在一种朝向中一层/元件位于另一层/元件“上”，那么当调转朝向时，该层/元件可以位于该另一层/元件“下”。为了使本发明所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本发明的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。“若干”的含义是一个或一个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而 言，可以根据具体情况理解上述术语在本发明中的具体含义。
下面结合具体的实施例对本申请的技术方案进行详细说明。下面这些具体的实施例可以相互结合，对于相同或相似的概念或过程可能在某些实施例不再赘述。
叠层太阳能电池是一种由顶电池和底电池复合而成的电池结构。顶电池由宽带隙的透光材料制造形成。底电池由较窄禁带宽度的透光材料制造形成。基于此，波长较短的太阳光可以被位于上方的顶电池所利用，波长较长的太阳光可以经顶电池透射至底电池内，并被底电池所利用，因此，叠层太阳能电池可以利用太阳光波长范围比较广，具有较高的光能利用率。
但是，现有的包括底电池和碲化镉顶电池的叠层太阳能电池中，碲化镉电池的背接触层的载流子输运能力较差，影响叠层太阳能电池的电学性能的提升。
为了解决上述技术问题，第一方面，本发明实施例提供了一种叠层太阳能电池。如图1所示，该叠层太阳能电池包括：底电池、碲化镉顶电池、N型透明导电层4和P型透明导电层5。
如图1所示，上述碲化镉顶电池位于底电池的上方、且与底电池串联。碲化镉顶电池包括的背接触层6的材料包括掺铜碲化锌、掺铜碲化镁和掺铜氮化锌中的至少一种。沿底电池至碲化镉顶电池的方向，N型透明导电层4和P型透明导电层5依次层叠设置于底电池和碲化镉顶电池之间。N型透明导电层4和底电池包括的前接触层的导电类型相同。P型透明导电层5的材料包括CuAlOx、BaCuSF和CuI中的至少一种，P型透明导电层5朝向向光面一侧的铜离子的浓度大于碲化镉顶电池包括的背接触层6朝向背光面一侧的铜离子的浓度。
具体来说，上述底电池的类型和结构可以根据实际需求设置，只要能够应用至本发明实施例提供的叠层太阳能电池中均可。例如：底电池可以为铜铟镓硒底电池、晶硅电池或非晶硅电池等。
对于上述碲化镉顶电池来说，如图1所示，沿碲化镉顶电池至底电池的方向，该碲化镉顶电池可以包括窗口层8、光吸收层和背接触层。其中，碲化镉顶电池包括的窗口层8和背接触层的导电类型相反。并且，碲化镉顶电池包括的背接触层6的材料包括掺铜碲化锌、掺铜碲化镁和掺铜氮化锌中的至少一种。而上述碲化锌、碲化镁和氮化锌均为P型半导体材料，因此 窗口层8的导电类型为N型。
具体的，上述窗口层的材料可以为任一种N型半导体材料，只要能够应用至本发明实施例提供的叠层太阳能电池中均可。例如：窗口层的材料可以为掺杂氧化铟，也可以为掺杂氧化锌，还可以为掺杂氧化铟和掺杂氧化锌的混合材料。其中，掺杂氧化铟的掺杂元素包括Sn、W、Ce、F、Zr、Ti、Ga、Zn和H中的至少一种。掺杂氧化锌内的掺杂元素包括Al、Ga、H中的至少一种。在此情况下，因掺杂氧化铟和掺杂氧化锌具有较高的透光性和导电性，故在窗口层的材料为掺杂氧化铟和/或掺杂氧化锌的情况下，不仅可以使得更多的太阳光由窗口层折射至碲化镉顶电池内，提高碲化镉顶电池对光能的利用率，还可以提高窗口层对电子的输运能力，加速电子和空穴对在碲化镉顶电池包括的光吸收层和窗口层界面处的分离速率，抑制载流子复合，进一步提高碲化镉顶电池的光电转换效率。
上述窗口层的厚度可以根据实际需求进行设置，此处不做具体限定。例如：上述窗口层的厚度可以为30nm至52nm。当然，还可以根据实际应用场景要求，将窗口层的厚度设置为其它合适数值。
上述碲化镉顶电池包括的光吸收层可以为任一含Cd和Te的化合物吸收层，只要能够应用至本发明实施例提供的叠层太阳能电池中均可。例如：碲化镉顶电池包括的光吸收层的材料可以包括CdTe、CdSeTe、CdZnTe、CdMgTe和CdMnTe中的至少一种。另外，本发明实施例中对碲化镉顶电池包括的光吸收层的厚度不做具体限定。例如：碲化镉顶电池包括的光吸收层的厚度可以为1μm至4μm。再者，碲化镉顶电池包括的光吸收层可以为本征层，也可以为掺铜光吸收层。该掺铜光吸收层内铜离子的浓度不做具体限定。
上述碲化镉顶电池包括的背接触层的材料可以仅包括掺铜碲化锌、掺铜碲化镁和掺铜氮化锌中的一种。或者，也可以包括掺铜碲化锌、掺铜碲化镁和掺铜氮化锌中的任意两种。又或者，还可以同时包括掺铜碲化锌、掺铜碲化镁和掺铜氮化锌。其中，当该背接触层的材料包括两种以上时，不同材料之间的化学计量比、以及不同材料之间的位置分布关系可以根据实际应用场景确定，此处不做具体限定。另外，碲化镉顶电池包括的背接触层内铜离子的浓度也可以根据实际应用场景确定，此处不做具体限定。
对于上述N型透明导电层来说，N型透明导电层的材料可以为氧化铟锡、氟掺杂的氧化锡、掺杂氧化锌或掺杂氧化锌等。优选的，N型透明导 电层的材料为掺杂氧化铟和/或掺杂氧化锌。其中，掺杂氧化铟的掺杂元素包括Sn、W、Ce、F、Zr、Ti、Ga、Zn和H中的至少一种。掺杂氧化锌内的掺杂元素包括Al、Ga、H中的至少一种。在此情况下，因掺杂氧化铟和掺杂氧化锌均具有良好的透光性和导电性，故在N型透明导电层的材料为掺杂氧化铟和/或掺杂氧化锌的情况下，不仅可以使得更多的长波长的太阳光折射至底电池内，提高底电池对长波长太阳光的利用率，还可以提高N型透明导电层的电子传输层。另外，掺杂氧化铟和掺杂氧化锌中的掺杂元素均具有多种类型，便于根据不同的应用场景选择合适的种类，从而可以提高被发明提供的叠层太阳能电池在不同应用场景下的适用性。
至于N型透明导电层的厚度可以根据实际需求进行设置。例如：N型透明导电层的厚度可以为115nm至135nm。在此情况下，当薄膜的厚度为光在该薄膜中波长的四分之一时，该薄膜为增透膜，对入射光具有减反作用。基于此，因透过碲化镉顶电池的光线的波长大于850nm。并且，N型透明导电层的厚度为115nm至135nm。此时，N型透明导电层的厚度等于透过碲化镉顶电池的光线在N型透明导电层中波长的四分之一，使得N型透明导电层对该部分光线具有减反作用，可以使得更多的长波长的太阳光折射至底电池内，提高底电池对长波长太阳光的利用率。
对于上述P型透明导电层来说，P型透明导电层的材料可以仅包括CuAlOx、BaCuSF和CuI中的一种，也可以包括CuAlOx、BaCuSF和CuI中的任意两种，还可以同时包括CuAlOx、BaCuSF和CuI。因上述CuAlOx、BaCuSF和CuI均为含铜的P型透明导电层。并且如图1所示，P型透明导电层5和碲化镉顶电池包括的背接触层6接触。同时，P型透明导电层5朝向向光面一侧的铜离子的浓度大于碲化镉顶电池包括的背接触层6朝向背光面一侧的铜离子的浓度。在此情况下，在实际的制造过程中，扩散方向是由高浓度处传递至低浓度处，因此可以将P型透明导电层5作为掺杂源，使得其含有的铜离子至少扩散到碲化镉顶电池包括的背接触层6内，以增大碲化镉顶电池包括的背接触层6内铜离子的浓度，从而可以提高碲化镉顶电池包括的背接触层6的导电性，利于空穴的输运。同时，还可以改善碲化镉顶电池包括的背接触层6与P型透明导电层5之间的接触，优化背面场钝化效果，进而提升叠层太阳能电池的电学性能。
在实际的应用过程中，上述P型透明导电层朝向向光面一侧的铜离子的浓度与碲化镉顶电池包括的背接触层朝向背光面一侧的铜离子的浓度之 间的差值可以根据实际应用场景中对P型透明导电层和碲化镉顶电池包括的背接触层的导电性的要求进行确定，此处不做具体限定。
另外，如前文所述，上述碲化镉顶电池包括的光吸收层内可以掺杂有铜离子。基于此，碲化镉顶电池包括的光吸收层朝向背光面一侧的铜离子的浓度可以小于或等于碲化镉顶电池包括的背接触层朝向向光面一侧的铜离子的浓度。其中，当碲化镉顶电池包括的背接触层朝向向光面一侧的铜离子的浓度可以大于碲化镉顶电池包括的光吸收层朝向背光面一侧的铜离子的浓度时，在实际的制造过程中，可以将P型透明导电层作为掺杂源，使得其含有的铜离子朝向向光面的方向依次扩散至碲化镉顶电池包括的背接触层和光吸收层，从而可以同时提高碲化镉顶电池包括的背接触层和光吸收层的导电性，使得碲化镉顶电池具有良好的PN结特性，利于碲化镉顶电池吸收光子后产生的电子和空穴的分离和输运，提高碲化镉顶电池的光电转换效率。
作为一种可能的实现方式，上述P型透明导电层的折射率小于碲化镉顶电池包括的背接触层的折射率。
具体的，上述P型透明导电层和碲化镉顶电池包括的背接触层的折射率大小可以根据实际需求进行设置，此处不做具体限定。例如：P型透明导电层层的折射率可以为1.7至1.88。碲化镉顶电池包括的背接触层的折射率可以约为2.9至3.1。在实际的应用过程中，在P型透明导电层和碲化镉顶电池包括的背接触层的材料确定的情况下，可以通过调整这两个膜层的制造工艺和掺杂浓度等方式改变其折射率，使得P型透明导电层的折射率小于碲化镉顶电池包括的背接触层的折射率，以降低碲化镉顶电池的背光面一侧的反射率，利于经碲化镉顶电池折射至底电池部分光子在进入底电池时，被经底电池反射回碲化镉顶电池的光子所吸收，提高碲化镉顶电池对短波长的太阳光的利用率。
作为一种可能的实现方式，上述P型透明导电层的折射率小于N型透明导电层的折射率。
具体的，P型透明导电层的折射率可以参考前文，此处不再赘述。上述N型透明导电层的折射率可以根据实际需求进行设置，只要能够应用至本发明实施例提供的叠层太阳能电池中均可。例如：N型透明导电层的折射率可以约为1.9至2.3。在实际的应用过程中，可以通过调整N型透明导电层的材料、以及P型透明导电层和N型透明导电层的制造工艺和掺杂浓度 等方式改变其折射率，使得P型透明导电层的折射率小于N型透明导电层的折射率，以降低底电池的向光面一侧的反射率，从而能够使得透过碲化镉顶电池的更多光线折射至底电池内，提高底电池对长波长的太阳光的利用率。
在实际的应用过程中，沿底电池至碲化镉顶电池的方向，依次层叠设置的N型透明导电层和P型透明导电层之间可以形成隧穿结。该隧穿结具有的空间电荷区的宽度取决于N型透明导电层和P型透明导电层的载流子浓度。具体的，在一定的范围，N型透明导电层和P型透明导电层中的至少一者的载流子浓度越低，该空间电荷区的宽度越宽。相反的，N型透明导电层和P型透明导电层的载流子越高，该空间电荷区的宽度越窄。另外，空间电荷区越窄越利于空穴的输运。在此情况下，可以根据实际应用场景中对传导空穴等要求设置P型透明导电层和N型透明导电层的载流子浓度，此处不做具体限定。
示例性的，上述P型透明导电层的载流子浓度为8.0×1019cm-3至3.0×1020cm-3。在此情况下，在P型透明导电层的载流子浓度在此范围内，可以防止因P型透明导电层的载流子浓度较小而导致由P型透明导电层和N型透明导电层形成的隧穿结的空间电荷区较宽，利于碲化镉顶电池内的空穴隧穿通过该空间电荷区，便于空穴的输运。另外，P型透明导电层的载流子浓度在此范围内，还可以使得P型透明导电层具有良好的导电性，利于提高P型透明导电层的电子传输能力。
示例性的，N型透明导电层的载流子浓度为8.0×1019cm-3至3.0×1020cm-3。该情况下具有的有益效果可以参考前文所述的P型透明导电层的载流子浓度为8.0×1019cm-3至3.0×1020cm-3的有益效果分析，此处不再赘述。
作为一种可能的实现方式，如前文所述，底电池可以为晶硅电池。该晶硅电池的具体的结构可以根据实际需求进行设置。从钝化方面来讲，该晶硅电池可以为其上未形成有钝化接触结构的常规晶硅电池。例如：底电池可以包括硅衬底、形成在硅衬底向光面上的N型掺杂硅层、以及形成在硅衬底背光面上的P型掺杂硅层。其中，硅衬底可以为本征硅衬底，也可以为N型硅衬底，还可以为P型硅衬底。
或者，该晶硅电池还可以为其上形成有钝化接触结构的晶硅电池。在此情况下，晶硅电池具有的钝化接触结构的种类可以仅包括隧穿钝化接触 结构，也可以仅包括异质接触结构，还可以同时包括隧穿钝化接触结构和异质接触结构。
其中，当晶硅电池具有的钝化接触结构的种类仅包括隧穿钝化接触结构时，可以仅在硅衬底的向光面一侧形成有隧穿钝化接触结构(该隧穿钝化接触结构包括沿背离硅衬底的方向依次层叠设置的隧穿钝化层和N型掺杂多晶硅层)，也可以仅在硅衬底的背光面一侧形成有隧穿钝化接触结构(该隧穿钝化接触结构包括沿背离硅衬底的方向依次层叠设置的隧穿钝化层和P型掺杂多晶硅层)，还可以在硅衬底的向光面和背光面均形成有隧穿钝化接触结构。
当晶硅电池具有的钝化接触结构的种类仅包括异质接触结构时，可以仅在硅衬底的背光面一侧形成异质接触结构。基于此，碲化镉顶电池的形成温度相对较高，并且碲化镉电池形成在底电池的向光面一侧。而非晶硅和微晶硅材料在高温下容易形成多晶硅或单晶硅，因此仅在硅衬底的背光面一侧形成异质接触结构可以在实际的制造过程中，在形成了碲化镉顶电池之后再在硅衬底的背光面一侧形成异质接触结构，防止高温工艺对异质接触结构的钝化效果造成影响。
示例性的，沿底电池至碲化镉顶电池的方向，底电池可以包括依次层叠设置的P型掺杂硅层、本征硅层、N型硅衬底和N型掺杂硅层。N型掺杂硅层为底电池的前接触层，P型掺杂硅层为底电池的背接触层。其中，位于N型硅衬底背光面一侧的本征硅层和P型掺杂硅层可以组成异质接触结构。基于此，因异质接触结构具有优于隧穿钝化接触结构的钝化效果，故在N型硅衬底的背光面一侧形成有异质接触结构的情况下，可以进一步降低N型硅衬底与本征硅层界面处的载流子复合速率，利于提高底电池的光电转换效率。另外，与P型电池相比，N型电池的转换效率更高。基于此，在底电池的光吸收层为N型硅衬底的情况下，可以使得底电池具有更高的转换效率，从而可以进一步提高叠层太阳能电池的电学性能。
具体的，上述P型掺杂硅层可以为P型非晶硅层、P型掺杂微晶硅层或P型掺杂非晶硅和微晶硅层的混合层。P型掺杂硅层的厚度可以为10nm至20nm。
上述本征硅层可以为本征非晶硅层、本征微晶硅层或本征非晶硅和微晶硅的混合层。本征硅层的厚度可以为5nm至10nm。
上述N型硅衬底的掺杂浓度可以为3.0×1015cm-3至1.0×1017cm-3。另 外，上述N型硅衬底的厚度可以为90μm至150μm。在此情况下，N型硅衬底的厚度在此范围内，可以防止因N型硅衬底的厚度较小导致N型硅衬底的光吸收深度不足，提高N型硅衬底对光能的利用率。同时，还可以防止因N型硅衬底的厚度较大导致材料浪费和效率偏低，降低底电池的制造成本。另外，上述N型硅衬底的向光面和背光面可以为平坦的抛光面。或者，如图1所示，N型硅衬底1的向光面和背光面也可以为绒面。基于此，因绒面结构具有陷光作用，故在N型硅衬底1的向光面和背光面均为绒面的情况下，可以降低这两个表面的反射率，可以使得更多的光线可以由这两个表面折射至底电池内，提高底电池对光能的利用率。并且，因碲化镉顶电池形成在底电池上，故碲化镉顶电池包括的各膜层的表面也会随之起伏，进而还可以降低碲化镉顶电池的向光面的反射率，利于使得更多的光线折射至碲化镉顶电池内，提高碲化镉顶电池对光能的利用率。
上述N型掺杂硅层可以为N型掺杂多晶硅层或N型掺杂单晶硅层等，此处不做具体限定。N型掺杂硅层的厚度可以为100nm至200nm。N型掺杂硅层的掺杂浓度可以为7.0×1019cm-3至1.0×1020cm-3。
当然，上述P型掺杂硅层、本征硅层和N型掺杂硅层的厚度、以及N型硅衬底和N型掺杂硅层的掺杂浓度还可以根据实际应用场景的要求设置为其它合适数值，此处不做具体限定。
当晶硅电池具有的钝化接触结构的种类包括隧穿钝化接触结构和异质接触结构时，如图1所示，沿底电池至碲化镉顶电池的方向，底电池可以包括依次层叠设置的P型掺杂硅层11、本征硅层10、N型硅衬底1、隧穿钝化层2和N型掺杂多晶硅层。N型掺杂多晶硅层为底电池的前接触层，P型掺杂硅层11为底电池的背接触层。在此情况下，位于N型硅衬底1的向光面一侧的隧穿钝化层2和N型掺杂多晶硅层组成的隧穿钝化接触结构，其能够实现良好的界面钝化和载流子选择性收集，利于提高底电池的光电转换效率。另外，因非晶硅和微晶硅材料具有较高的吸光系数，故在底电池的向光面一侧形成非晶硅和/或微晶硅材料制成的异质接触结构会因严重的寄生吸收而导致底电池对光能的利用率较低。而隧穿钝化接触结构在长波长范围内产生的寄生吸收较弱，使得经碲化镉顶电池透过的长波长太阳光可以更多经隧穿钝化接触结构折射至底电池内，进一步提高底电池的光电转换效率。
具体得，该情况下P型掺杂硅层和本征硅层的材料和厚度、以及N型 硅衬底和N型掺杂硅层的材料和掺杂浓度可以参考前文，此处不再赘述。对于上述隧穿钝化层来说，隧穿钝化层的材料可以包括氧化硅、氧化铝、氧化钛、二氧化铪、氧化镓、五氧化二钽、五氧化铌、氮化硅、碳氮化硅、氮化铝、氮化钛、氮碳化钛中的一种或多种。本发明实施例对隧穿钝化层厚度不做具体限定。例如：隧穿钝化层的厚度可以为1nm至5nm。
另外，不管是仅在底电池的背光面形成有异质接触结构，还是又在底电池的向光面形成有隧穿钝化层接触结构，上述P型掺杂硅层内掺杂元素的掺杂浓度均可以沿底电池至碲化镉顶电池的方向逐渐降低。在此情况下，沿底电池至碲化镉顶电池的方向，P型掺杂硅层内可以形成高低结。并且，该高低结的内建电场方向由低掺杂浓度指向高掺杂浓度，即由P型掺杂硅层的向光面指向背光面。基于此，因该高低结的内建电场方向与底电池内空穴的输运方向一致，从而可以增强P型掺杂硅层的空穴传输能力，进一步提高底电池的光电转换效率。
可以理解的是，在一定的范围内，P型掺杂硅层沿厚度方向相对两面的掺杂浓度差越大，P型掺杂硅层内高低结的内建电场强度越高，可以进一步提高P型掺杂硅层的空穴传输能力。基于此，可以根据实际应用场景中对P型掺杂硅层传导空穴的能力要求设置P型掺杂硅层背离本征硅层一侧、以及P型掺杂硅层靠近本征硅层一侧的掺杂元素的掺杂浓度，此处不做具体限定。
示例性的，上述P型掺杂硅层背离本征硅层一侧的掺杂元素的掺杂浓度可以为5.0×1020cm-3至1.0×1022cm-3。此时，P型掺杂硅层背离本征硅层一侧的掺杂元素的掺杂浓度较高，以利于提高P型掺杂硅层内高低结的内建电场强度，进一步提高P型掺杂硅层的空穴传输能力。
示例性的，上述P型掺杂硅层靠近本征硅层一侧的掺杂元素的掺杂浓度为1.0×1018cm-3至5.0×1019cm-3。此时，P型掺杂硅层靠近本征硅层一侧的掺杂元素的掺杂浓度较低，利于增大P型掺杂硅层沿厚度方向相对两面的掺杂浓度差，从而可以提高P型掺杂硅层内高低结的内建电场强度，进一步提高P型掺杂硅层的空穴传输能力。
在一些情况下，如图1所示，上述叠层太阳电池还包括正电极13和负电极14。正电极13形成在碲化镉顶电池包括的窗口层8的向光面一侧。负电极14形成在底电池包括的背接触层的背光面一侧。具体的，该正电极13和负电极14的材料可以为银和/或铜等导电材料。
在一些情况下，如图1所示，上述底电池还包括形成在P型掺杂硅层11背离本征硅层10一侧的背光面透明导电层12。在此情况下，因P型掺杂硅层11的载流子横向迁移率较差，而背光面透明导电层12具有较高的导电性，故在P型掺杂硅层11背离本征硅层10的一侧形成背光面透明导电层12利于电子横向输运进而被负电极14所收集。同时，还可以对P型掺杂硅层11的背光面进行场钝化，降低载流子在P型掺杂硅层11的背光面一侧的复合速率，提高底电池的光电转换效率。
其中，该背光面透明导电层的导电类型可以为P型，也可以为N型。在实际的应用过程中，因导电类型为P型的透明导电层的制造难度较大、且其实际迁移率并不理想，故背光面透明导电层的导电类型优选为N型。此时，该背光面透明导电层的材料和厚度等信息可以参考前文所述的N型透明导电层的材料和厚度等信息进行设置，此处不再赘述。
在一些情况下，如图1所示，上述碲化镉顶电池还包括形成在窗口层8向光面一侧的减反射层9，以使得更多的光线折射至叠层太阳能电池内，进一步提高叠层太阳能电池的光电转换效率。
其中，该减反射层的材料可以包括氟化镁、氧化硅、氮化硅和氧化铝中的至少一种。具体的，在减反射层的材料包括至少两种的情况下，该减反射层的折射率可以沿碲化镉顶电池至底电池的方向逐渐减小，以进一步降低叠层太阳电池向光满一侧的反射率。另外，该减反射层的厚度可以为根据实际应用场景设置，此处不做具体限定。例如：该减反射层的厚度可以为90nm至150nm。
第二方面，本发明实施例还提供了一种光伏组件，该光伏组件包括上述第一方面及其各种实现方式提供的叠层太阳能电池。
第三方面，本发明实施例还提供了一种叠层太阳能电池的制造方法。下文将根据图2至图10示出的操作的剖视图，对制造过程进行描述。具体的，该叠层太阳能电池的制造方法包括以下步骤：
首先，如图3所示，形成半导体基底。
具体的，该半导体基底用于制造叠层太阳能电池包括的底电池，因此可以根据底电池的具体结构确定半导体基底的具体形成过程。
例如：如前文所述，沿底电池至碲化镉顶电池的方向，底电池仅包括依次层叠设置的P型掺杂硅层、本征硅层、N型硅衬底和N型掺杂硅层。此时，半导体基底可以包括N型硅衬底和N型掺杂硅层。在此情况下，可以 先提供一N型硅衬底。接下来，在N型硅衬底的向光面上形成N型掺杂硅层。
具体的，在实际的应用过程中，可以采用扩散或离子注入等工艺直接对N型硅衬底的向光面进行掺杂，以形成N型掺杂硅层。或者，也可以采用低压化学气相沉积等工艺先在N型硅衬底的向光面形成一层本征硅材料层。然后对本征硅材料层进行掺杂，形成N型掺杂硅层，从而获得半导体基底。
另外，如前文所述，当N型硅衬底的向光面和背光面均为绒面时，还可以在形成N型掺杂硅层前，对N型硅衬底进行制绒处理。该绒面的塔基宽度可以根据实际需求进行设置。例如：绒面的塔基宽度可以1μm至5μm。此时，绒面结构的塔基宽度在此范围内，可以使得N型硅衬底的向光面和背光面的反射率降低至11％至13％之间，利于增大底电池的短路电流。并且，在实际的制造过程中，绒面的塔基宽度难以做到小于1μm，因此，当绒面的塔基宽度可以1μm至5μm时，还可以降低制绒处理的难度。
又例如：如前文所述，沿底电池至碲化镉顶电池的方向，底电池可以包括依次层叠设置的P型掺杂硅层、本征硅层、N型硅衬底、隧穿钝化层和N型掺杂多晶硅层。此时，半导体基底可以包括N型硅衬底、隧穿钝化层和N型掺杂多晶硅层。在此情况下，如图2所示，可以采用上述方式先对N型硅衬底1进行制绒处理。接下来，可以采用等离子体增强化学气相沉积等工艺在N型硅衬底1的向光面上依次形成隧穿钝化层2、以及位于隧穿钝化层2上的本征硅材料层。然后，如图3所示，可以采用扩散结合退火工艺、离子注入工艺等对本征硅材料层进行掺杂，以使得本征硅材料层形成N型掺杂硅层3，从而获得半导体基底。
在形成了半导体基底后，如图4所示，在半导体基底的向光面上依次形成层叠设置的N型透明导电层4和P型透明导电层5。P型透明导电层5的材料包括CuAlOx、BaCuSF和CuI中的至少一种。
具体的，可以采用溅射、反应等离子体沉积或喷雾热解等工艺形成上述N型透明导电层和P型透明导电层。其中，N型透明导电层和P型透明导电层的材料、厚度和载流子浓度等信息可以参考前文，此处不再赘述。
如图5和图6所示，在P型透明导电层5上形成碲化镉顶电池。并对已形成的结构进行热处理，以使得P型透明导电层5内的铜离子至少扩散到碲化镉顶电池包括的背接触层6内。碲化镉顶电池包括的背接触层6的材料包 括掺铜碲化锌、掺铜碲化镁和掺铜氮化锌中的至少一种。P型透明导电层5朝向向光面一侧的铜离子的浓度大于碲化镉顶电池包括的背接触层6朝向背光面一侧的铜离子的浓度。
示例性的，如图5所示，可以采用热蒸发或溅射等工艺在P型透明导电层5上形成碲化镉顶电池包括的背接触层6。此时，该背接触层内铜离子的浓度可以大于或等于0，只要小于最后完成叠层太阳能电池制造完成后该背接触层内铜离子的浓度即可。接下来，可采用蒸汽输运或近空间升华等工艺形成碲化镉顶电池包括的光吸收层7。然后，如图6所示，可以溅射、反应等离子体沉积或喷雾热解等工艺形成碲化镉顶电池包括的窗口层8，从而获得碲化镉顶电池。其中，碲化镉顶电池包括的背接触层6、光吸收层和窗口层8的材料和厚度等信息可以参考前文。最后，可以通过退火炉，并在真空或氮气氛围下进行退火的方式对已形成的结构进行热处理，使得P型透明导电层内的铜离子至少扩散到碲化镉顶电池包括的背接触层内，以至少增大碲化镉顶电池包括的背接触层内铜离子的浓度，从而可以提高碲化镉顶电池包括的背接触层的导电性，利于空穴的输运。同时，还可以改善碲化镉顶电池包括的背接触层与P型透明导电层之间的接触，优化背面场钝化效果，进而提升叠层太阳能电池的电学性能。具体的，该热处理的处理温度和处理时间等条件可以根据实际需求进行设置，此处不做具体限定。
值得注意的是，在N型硅衬底的向光面上形成N型掺杂硅层后，依次在N型掺杂硅层上形成N型透明导电层、P型透明导电层和碲化镉顶电池。基于此，如前文所述，碲化镉顶电池的形成温度较高，因此在高温下制造碲化镉顶电池的过程中可以使得N型掺杂硅层内的掺杂元素扩散至N型硅衬底的向光面，利于使得N型硅衬底和N型掺杂硅层之间的能带过渡的更为平缓，进而可以提高N型硅衬底向光面一侧的场钝化效果，提升底电池的光电转换效率。
需要说明的是，如图6所示，上述已形成的结构包括半导体基底、N型透明导电层4、P型透明导电层5和碲化镉顶电池。
另外，如前文所述，在碲化镉顶电池包括的光吸收层为掺铜光吸收层，且碲化镉顶电池包括的光吸收层朝向背光面一侧的铜离子的浓度小于碲化镉顶电池包括的背接触层朝向向光面一侧的铜离子的浓度的情况下，经上述热处理后P型透明导电层内的铜离子可以依次扩散到碲化镉顶电池包括的背接触层和光吸收层内。此时，可以同时提高碲化镉顶电池包括的 背接触层和光吸收层的导电性，使得碲化镉顶电池具有良好的PN结特性，利于碲化镉顶电池吸收光子后产生的电子和空穴的分离和输运，提高碲化镉顶电池的光电转换效率。
再者，如前文所述，在碲化镉顶电池还包括减反射层的情况下，如图7所示，在形成窗口层8后，并在进行热处理前，可以采用化学气相沉积等工艺在窗口层8上形成减反射层9。该减反射层9的材料和厚度等信息可以参考前文。
如图8所示，基于半导体基底形成底电池。碲化镉顶电池与底电池串联。N型透明导电层4与底电池包括的前接触层的导电类型相同。
具体的，可以根据底电池的结构确定基于半导体基底形成底电池的具体过程。
示例性的，如前文所述，沿底电池至碲化镉顶电池的方向，底电池可以包括依次层叠设置的P型掺杂硅层、本征硅层、N型硅衬底和N型掺杂硅层。并且，半导体基底包括N型硅衬底和N型掺杂硅层。在该情况下，上述基于半导体基底形成底电池包括步骤：如图8所示，沿背离N型硅衬底1的方向，可以采用等离子体增强化学气相沉积等工艺，形成依次层叠设置于N型硅衬底1的背光面上的本征硅层10和P型掺杂硅层11。具体的，本征硅层10和P型掺杂硅层11的材料和厚度可以参考前文。
采用上述技术方案的情况下，因本征硅层和P型掺杂硅层组成的异质接触结构的制造温度相对较低，而碲化镉顶电池的形成温度较高(大约在500℃至700℃)，故在半导体基底的向光面上依次形成N型透明导电层、P型透明导电层和碲化镉顶电池后，再在半导体基底的背光面上形成本征硅层和P型掺杂硅层，可以防止高温制造对本征硅层和P型掺杂硅层造成影响，确保本征硅层和P型掺杂硅层组成的异质接触结构具有优异的界面钝化效果和载流子的选择性收集。
由此可见，可以采用低温制造工艺形成上述本征硅层和P型掺杂硅层。该低温制造工艺的制造温度可以根据实际需求设置。例如：低温制造工艺的制造温度范围可以为100℃至200℃。在此情况下，制造温度在此范围内，可以防止因制造工艺温度较高而对本征硅层和P型掺杂硅层造成影响，确保本征硅层和P型掺杂硅层组成的异质接触结构具有优异的界面钝化效果和载流子的选择性收集。
在一些情况下，如图10所示，在所制造的叠层太阳电池还包括背光面 透明导电层12的情况下，在形成上述P型掺杂硅层11后，可以采用溅射、反应等离子体沉积或喷雾热解等工艺形成位于P型掺杂硅层11背离本征硅层10一侧的背光面透明导电层12。该背光面透明导电层12的材料和厚度等信息可以参考前文。
接下来，如图10所示，可采用丝网印刷、激光转印或电镀等工艺在碲化镉顶电池的向光面一侧形成负电极14，以及在底电池背光面一侧形成正电极13，获得叠层太阳能电池。该正电极13和负电极14的材料可以参考前文。
最后，还可以对制造获得的叠层太阳能电池进行退火处理，以使得叠层太阳能电池包括的各透明导电层晶化、以及去除正电极和负电极中的有机物，提高各透明导电层、正电极和负电极的导电性。其中，上述退火处理的温度和时间可以根据实际需求进行设置。例如：退火处理的温度可以为180℃至220℃，退火时间为30min至50min。
在以上的描述中，对于各层的构图、刻蚀等技术细节并没有做出详细的说明。但是本领域技术人员应当理解，可以通过各种技术手段，来形成所需形状的层、区域等。另外，为了形成同一结构，本领域技术人员还可以设计出与以上描述的方法并不完全相同的方法。另外，尽管在以上分别描述了各实施例，但是这并不意味着各个实施例中的措施不能有利地结合使用。
以上对本公开的实施例进行了描述。但是，这些实施例仅仅是为了说明的目的，而并非为了限制本公开的范围。本公开的范围由所附权利要求及其等价物限定。不脱离本公开的范围，本领域技术人员可以做出多种替代和修改，这些替代和修改都应落在本公开的范围之内。

Claims (15)

  1. 一种叠层太阳能电池，包括：
    底电池，
    碲化镉顶电池，位于所述底电池的上方、且与所述底电池串联；所述碲化镉顶电池包括的背接触层的材料包括掺铜碲化锌、碲化镁和掺铜氮化锌中的至少一种；以及
    沿所述底电池至所述碲化镉顶电池的方向，依次层叠设置于所述底电池和所述碲化镉顶电池之间的N型透明导电层和P型透明导电层；所述N型透明导电层和所述底电池包括的前接触层的导电类型相同；所述P型透明导电层的材料包括CuAlOx、BaCuSF和CuI中的至少一种，所述P型透明导电层朝向向光面一侧的铜离子的浓度大于所述碲化镉顶电池包括的背接触层朝向背光面一侧的铜离子的浓度。
  2. 根据权利要求1所述的叠层太阳能电池，其中，所述碲化镉顶电池包括的光吸收层内掺杂有铜离子；
    所述碲化镉顶电池包括的背接触层朝向向光面一侧的铜离子的浓度大于所述碲化镉顶电池包括的光吸收层朝向背光面一侧的铜离子的浓度。
  3. 根据权利要求1所述的叠层太阳能电池，其中，所述P型透明导电层的折射率小于所述碲化镉顶电池包括的背接触层的折射率；和/或，
    所述P型透明导电层的折射率小于所述N型透明导电层的折射率。
  4. 根据权利要求1所述的叠层太阳能电池，其中，所述P型透明导电层的载流子浓度为8.0×1019cm-3至3.0×1020cm-3。
  5. 根据权利要求1所述的叠层太阳能电池，其中，所述N型透明导电层的厚度为115nm至135nm；和/或，
    所述N型透明导电层的载流子浓度为8.0×1019cm-3至3.0×1020cm-3；和/或，
    所述N型透明导电层的材料为掺杂氧化铟和/或掺杂氧化锌；其中，所述掺杂氧化铟的掺杂元素包括Sn、W、Ce、F、Zr、Ti、Ga、Zn和H中的至少一种；所述掺杂氧化锌内的掺杂元素包括Al、 Ga、H中的至少一种。
  6. 根据权利要求1所述的叠层太阳能电池，其中，沿所述底电池至所述碲化镉顶电池的方向，所述底电池包括依次层叠设置的P型掺杂硅层、本征硅层、N型硅衬底和N型掺杂硅层；所述N型掺杂硅层为所述底电池的前接触层，所述P型掺杂硅层为所述底电池的背接触层。
  7. 根据权利要求6所述的叠层太阳能电池，其中，所述N型掺杂硅层为N型掺杂多晶硅层；所述底电池还包括位于所述N型硅衬底与所述N型掺杂多晶硅层之间的隧穿钝化层。
  8. 根据权利要求6所述的叠层太阳能电池，其中，所述P型掺杂硅层内掺杂元素的掺杂浓度沿所述底电池至所述碲化镉顶电池的方向逐渐降低。
  9. 根据权利要求8所述的叠层太阳能电池，其中，所述P型掺杂硅层背离所述本征硅层一侧的掺杂元素的掺杂浓度为5.0×1020cm-3至1.0×1022cm-3；和/或，
    所述P型掺杂硅层靠近所述本征硅层一侧的掺杂元素的掺杂浓度为1.0×1018cm-3至5.0×1019cm-3。
  10. 一种光伏组件，所述光伏组件包括权利要求1～9任一项所述的叠层太阳能电池。
  11. 一种叠层太阳能电池的制造方法，包括：
    形成半导体基底；
    在所述半导体基底的向光面上依次形成层叠设置的N型透明导电层和P型透明导电层；所述P型透明导电层的材料包括CuAlOx、BaCuSF和CuI中的至少一种；
    在所述P型透明导电层上形成碲化镉顶电池；
    对已形成的结构进行热处理，以使得所述P型透明导电层内的铜离子至少扩散到所述碲化镉顶电池包括的背接触层内；所述碲化镉顶电池包括的背接触层的材料包括掺铜碲化锌、掺铜碲化镁和掺铜氮化锌中的至少一种；所述P型透明导电层朝向向光面一侧的铜离子的浓度大于所述碲化镉顶电池包括的背接触层朝向背光面一侧的铜离子的浓度；
    基于所述半导体基底形成底电池；所述碲化镉顶电池与所述底 电池串联；所述N型透明导电层与所述底电池包括的前接触层的导电类型相同。
  12. 根据权利要求11所述的叠层太阳能电池的制造方法，其中，在所述热处理过程中，所述P型透明导电层内的铜离子还扩散至所述碲化镉顶电池包括的光吸收层内；其中，
    所述碲化镉顶电池包括的光吸收层内掺杂有铜离子；所述碲化镉顶电池包括的背接触层朝向向光面一侧的铜离子的浓度大于所述碲化镉顶电池包括的光吸收层朝向背光面一侧的铜离子的浓度。
  13. 根据权利要求11所述的叠层太阳能电池的制造方法，其中，所述形成半导体基底，包括：提供一N型硅衬底；在所述N型硅衬底的向光面上形成N型掺杂硅层；
    所述基于所述半导体基底形成底电池，包括：沿背离所述N型硅衬底的方向，形成依次层叠设置于所述N型硅衬底的背光面上的本征硅层和P型掺杂硅层；其中，
    沿所述底电池至所述碲化镉顶电池的方向，所述底电池包括依次层叠设置的所述P型掺杂硅层、所述本征硅层、所述N型硅衬底和所述N型掺杂硅层。
  14. 根据权利要求13所述的叠层太阳能电池的制造方法，其中，采用低温制造工艺，沿背离所述N型硅衬底的方向，形成依次层叠设置于所述N型硅衬底的背光面上的本征硅层和P型掺杂硅层；其中，
    所述低温制造工艺的制造温度范围为100℃至200℃。
  15. 根据权利要求13所述的叠层太阳能电池的制造方法，其中，所述N型掺杂硅层为N型掺杂多晶硅层；
    所述提供一N型硅衬底后，所述在所述N型硅衬底的向光面上形成N型掺杂硅层前，所述叠层太阳能电池的制造方法还包括：
    在所述N型硅衬底的向光面上形成隧穿钝化层。
PCT/CN2023/139251 2022-12-22 2023-12-15 一种叠层太阳能电池及其制造方法、光伏组件 WO2024131681A1 (zh)

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