WO2022062381A1 - 一种叠层电池结构及其制备方法 - Google Patents

一种叠层电池结构及其制备方法 Download PDF

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WO2022062381A1
WO2022062381A1 PCT/CN2021/089363 CN2021089363W WO2022062381A1 WO 2022062381 A1 WO2022062381 A1 WO 2022062381A1 CN 2021089363 W CN2021089363 W CN 2021089363W WO 2022062381 A1 WO2022062381 A1 WO 2022062381A1
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layer
unit
single crystal
silicon
backside
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PCT/CN2021/089363
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English (en)
French (fr)
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张树德
赵保星
倪志春
魏青竹
连维飞
符欣
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苏州腾晖光伏技术有限公司
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Priority to US17/430,887 priority Critical patent/US20220310865A1/en
Publication of WO2022062381A1 publication Critical patent/WO2022062381A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/078—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers including different types of potential barriers provided for in two or more of groups H01L31/062 - H01L31/075
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the technical field of solar cells, in particular to a laminated cell structure and a preparation method thereof.
  • a solar cell is a semiconductor device that directly converts the light energy of the sun into electrical energy. Using light energy as a renewable resource, solar cells have broad prospects for development in today's energy shortage situation.
  • tandem solar cells are an effective means to further greatly improve the conversion efficiency of cells.
  • the principle of tandem solar cells is to integrate cells with different photovoltaic responses by various means, and the two-terminal (2T) tandem cells in the tandem solar cell structure have more application prospects.
  • CIGS thin-film cells and silicon thin-film cells are expensive and cannot be directly compatible with the industry's mass-produced cell structures.
  • the present invention proposes a laminated battery structure and a preparation method thereof.
  • the present application provides a stacked battery structure including a top battery unit, a bottom battery unit, and an intermediate layer unit disposed between the top battery unit and the bottom battery unit;
  • the top cell includes an electron transport layer, a perovskite photosensitive layer, a hole transport layer and a front electrode;
  • the electron transport layer, the perovskite photosensitive layer, and the hole transport layer are stacked in sequence in a direction from far away to approaching the intermediate layer unit, and the hole transport layer is connected to the intermediate layer unit;
  • the front electrode is disposed on the electron transport layer
  • the bottom battery unit includes a passivation contact layer, a silicon oxide layer, a single crystal silicon base layer, a backside passivation film layer, a backside protective layer and a backside electrode that are sequentially stacked in a direction from approaching to being away from the intermediate layer;
  • the passivation contact layer, the silicon oxide layer, the monocrystalline silicon base layer, the backside passivation film layer and the backside protective layer are stacked in sequence from approaching to the direction away from the intermediate layer unit.
  • the intermediate layer unit is connected;
  • the back electrode is arranged on the back protective layer
  • the intermediate layer unit includes a p + silicon thin film layer and an n + silicon thin film layer, and the structure of the intermediate layer unit is a tunnel junction composed of the p + silicon thin film layer and the n + silicon thin film layer.
  • the top battery unit further includes the anti-reflection layer, the transparent conductive layer and the passivation protective film layer provided on the electron transport layer, the anti-reflection layer, the transparent conductive layer and the passivation protective film The layers are stacked in sequence from the direction away from the electron transport layer.
  • the hole transport layer is a nickel oxide layer; the electron transport layer is a zinc oxide layer or a lithium fluoride layer.
  • the passivation contact layer of the bottom battery unit is an n-layer silicon thin film passivation contact layer, which is structured as a textured structure.
  • the passivation contact layer is formed with an internal electrode on the surface facing the intermediate layer unit.
  • the present application provides a method for preparing a laminated battery structure, the preparation method comprising the following steps:
  • the interlayer unit is constructed as a tunnel junction consisting of a p + silicon thin film layer and an n + silicon thin film layer;
  • a top cell unit with a perovskite photoactive layer is prepared on the interlayer unit.
  • the preparation of the bottom battery unit specifically includes the following steps:
  • the suede is prepared on the front and back of the single crystal silicon wafer by using an alkaline solution
  • oxidative annealing is performed on the second silicon dioxide layer, and aluminum oxide is deposited on the second silicon dioxide layer to form a backside passivation film;
  • a back electrode is arranged on the back passivation film layer
  • the forming of the first silicon oxide layer and the second silicon dioxide layer on the front and back textured surfaces of the single crystal silicon wafer respectively includes the following steps:
  • Phosphorus is diffused on the front textured surface of the single crystal silicon wafer to obtain the front textured surface forming the n-type emission region;
  • the single crystal silicon wafer is thermally oxidized in an oxidation furnace, and a first silicon oxide layer and a second silicon dioxide layer are respectively formed on the front and back textured surfaces of the single crystal silicon wafer.
  • Front cleaning front oxidation to form a thin oxide layer of 1-10 nm on the front surface; front passivation contact deposition to form n-type doped amorphous/polysilicon on top of the silicon oxide layer.
  • the intermediate layer unit is prepared on the bottom battery unit, specifically by a deposition method, and the method includes PVD physical vapor deposition or RPD reactive plasma deposition,
  • the suede surface is prepared by using an alkaline solution on the front and back sides of the single crystal silicon wafer, and the suede surface structure is in the shape of a pyramid.
  • Laser grooves are formed on the back textured surface of the single crystal silicon wafer to locally ablate the aluminum oxide and silicon nitride layers;
  • the thickness of the thin oxide layer is 1-10 nm;
  • a passivation contact layer is deposited on the first silicon oxide layer, the passivation contact layer being n-type doped amorphous or polycrystalline silicon.
  • the present invention provides a stacked battery structure including a top battery unit, a bottom battery unit, and an intermediate layer between the top battery unit and the bottom battery unit; the intermediate layer is configured as p + /n + tunneling junction composed of double-layer silicon film;
  • the top cell unit includes an electron transport layer, a perovskite photosensitive layer, a hole transport layer and a front electrode provided on the electron transport layer, which are sequentially stacked in a direction from away from the middle layer;
  • the bottom cell unit is a PERC solar cell.
  • the top battery unit further includes an anti-reflection layer, a transparent conductive layer, and a passivation protective film layer that are sequentially stacked in a direction from far away to approaching the electron transport layer.
  • the bottom battery unit includes a passivation contact layer, a silicon oxide layer, a single crystal silicon base layer, and a backside passivation film layer, which are sequentially stacked in a direction from approaching to moving away from the intermediate layer. , back protective layer and back electrode.
  • the hole transport layer is a nickel oxide layer; the electron transport layer is a zinc oxide layer or a lithium fluoride layer.
  • the passivation contact layer of the bottom battery unit is an n-type silicon thin film passivation contact layer, and is structured as a textured structure.
  • the passivation contact layer is formed with an internal electrode on the surface facing the intermediate layer.
  • the present invention provides a method for preparing the above-mentioned laminated battery structure, the preparation method comprising the following steps:
  • the intermediate layer is configured as a tunnel junction composed of p + /n + double-layer silicon thin films
  • the top cell unit includes an electron transport layer, a perovskite photosensitive layer, a hole transport layer and a front electrode deposited on the electron transport layer, which are sequentially stacked in a direction from away from the middle layer.
  • the formation of the intermediate layer on the PERC solar cell is specifically formed by deposition, including PVD physical vapor deposition or RPD reactive plasma deposition,
  • the front and back sides of the intermediate layer are textured to prepare a pyramid-shaped textured structure.
  • providing a PERC solar cell includes the following specific steps:
  • the front and back sides of the single crystal silicon wafer are textured with an alkaline solution to prepare a textured structure with a side length of 1-10 ⁇ m of the pyramid base;
  • Alumina and silicon nitride are deposited on the backside; laser grooving on the backside, local ablation of alumina and silicon nitride layers; backside aluminum paste, silver paste printing, and sintering;
  • the anti-reflection layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, and magnesium fluoride.
  • the backside passivation film layer includes an aluminum oxide layer and a silicon oxide layer that are arranged in layers.
  • the protective layer is silicon nitride or silicon oxynitride.
  • the surface of the midsole battery of the present invention adopts an alkali-textured pyramid textured structure, which overcomes the problem of poor plane light trapping effect, and can greatly improve the optical performance of the battery; it can also be seamlessly upgraded with the industry, and realize the low cost of the laminated structure battery.
  • the present invention adopts the tunnel junction as the link layer of the two cells when the perovskite cell and the crystalline silicon solar cell form a 2T tandem solar cell, which overcomes the need for special deposition equipment in the prior art or in the TCO
  • the above-prepared perovskite cells have the technical defects of uneven and poor performance.
  • FIG. 1 is a schematic diagram of a laminated battery structure provided by an embodiment of the present invention
  • FIG. 2 is a flowchart of a stacked battery structure and a method for preparing the same according to an embodiment of the present invention.
  • the example in the figure is expressed as: 1-top cell; 11-electron transport layer; 12-perovskite photosensitive layer; 13-hole transport layer; 14-anti-reflection layer; 15-transparent conductive layer; 16-passivation protection film layer; 17-front electrode; 2-bottom battery cell; 21-passivation contact layer; 22-silicon oxide layer; 23-monocrystalline silicon base layer; 24-backside passivation film layer; 25-backside protective layer; 26 Back electrode; 3-intermediate layer unit; 31-p + silicon thin film layer; 32-n + silicon thin film layer.
  • the present application provides a stacked battery structure, including a top battery unit 1, a bottom battery unit 2, and an intermediate layer unit 3 disposed between the top battery unit 1 and the bottom battery unit 2.
  • the top cell 1 includes an electron transport layer 11 , a perovskite photosensitive layer 12 , a hole transport layer 13 and a front electrode 17 .
  • the electron transport layer 11 , the perovskite photosensitive layer 12 and the hole transport layer 13 are stacked in sequence from the direction away from the intermediate layer unit 3 .
  • the hole transport layer 13 and the intermediate layer unit 3 are stacked in sequence. 3 connection; the front electrode 17 is arranged on the electron transport layer 11 .
  • the bottom battery unit 2 includes a passivation contact layer 21 , a silicon oxide layer 22 , a single crystal silicon base layer 23 , a backside passivation film layer 24 , and a backside protective layer, which are sequentially stacked in the direction from approaching to the middle layer. 25 and back electrode 26.
  • the passivation contact layer 21 , the silicon oxide layer 22 , the single crystal silicon base layer 23 , the backside passivation film layer 24 and the backside protective layer 25 are sequentially stacked in the direction from approaching to the middle layer unit 3 , so The passivation contact layer 21 is connected to the intermediate layer unit 3 ; the back electrode 26 is arranged on the back protective layer 25 .
  • the intermediate layer unit 3 includes a p + silicon thin film layer 31 and an n + silicon thin film layer 32 , and the structure of the intermediate layer unit 3 is a tunnel formed by the p + silicon thin film layer 31 and the n + silicon thin film layer 32 . Thread the knot.
  • the top battery unit 1 further includes the anti-reflection layer 14 , the transparent conductive layer 15 and the passivation protective film layer 16 disposed on the electron transport layer 11 , the anti-reflection layer 14.
  • the transparent conductive layer 15 and the passivation protective film layer 16 are stacked in sequence from the direction away from the electron transport layer 11 .
  • the hole transport layer 13 is a nickel oxide layer; the electron transport layer 11 is a zinc oxide layer or a lithium fluoride layer.
  • the passivation contact layer 21 of the bottom battery unit 2 is an n-type silicon thin film passivation contact layer, and is configured as a textured structure.
  • the passivation contact layer 21 is formed with an internal electrode on the surface facing the intermediate layer unit 3 .
  • an embodiment of the preparation method may include the following steps:
  • S2 preparing an intermediate layer unit on the bottom battery unit; the structure of the intermediate layer unit is a tunnel junction composed of a p + silicon thin film layer and an n + silicon thin film layer;
  • a top cell unit with a perovskite photoactive layer is prepared on the interlayer unit.
  • the preparation of the bottom battery unit may include the following steps:
  • the suede is prepared on the front and back of the single crystal silicon wafer by using an alkaline solution
  • oxidative annealing is performed on the second silicon dioxide layer, and aluminum oxide is deposited on the second silicon dioxide layer to form a backside passivation film;
  • the forming of the first silicon oxide layer and the second silicon dioxide layer on the front and back textured surfaces of the single crystal silicon wafer respectively includes the following steps:
  • Phosphorus is diffused on the front textured surface of the single crystal silicon wafer to obtain the front textured surface forming the n-type emission region;
  • the single crystal silicon wafer is thermally oxidized in an oxidation furnace, and a first silicon oxide layer and a second silicon dioxide layer are respectively formed on the front and back textured surfaces of the single crystal silicon wafer.
  • Front cleaning front oxidation to form a thin oxide layer of 1-10 nm on the front surface; front passivation contact deposition to form n-type doped amorphous/polysilicon on top of the silicon oxide layer.
  • the intermediate layer unit is prepared on the bottom battery unit, specifically by a deposition method, and the method includes PVD physical vapor deposition or RPD reactive plasma deposition,
  • the suede surface is prepared by using an alkaline solution on the front and back sides of the single crystal silicon wafer, and the suede surface structure is in the shape of a pyramid.
  • Laser grooves are formed on the back textured surface of the single crystal silicon wafer to locally ablate the aluminum oxide and silicon nitride layers;
  • the thickness of the thin oxide layer is 1-10 nm;
  • a passivation contact layer is deposited on the first silicon oxide layer, the passivation contact layer being n-type doped amorphous or polycrystalline silicon.
  • An embodiment of the present invention provides a laminated battery structure, as shown in FIG. 1 , including a top battery unit 1, a bottom battery unit 2, and an intermediate layer unit 3 located between the top battery unit 1 and the bottom battery unit 2; the intermediate layer The unit 3 is constructed as a tunneling junction composed of p + /n + double-layer silicon thin films, and specifically includes a p + silicon thin film layer 31 and an n + silicon thin film layer 32 ;
  • the top cell unit 1 includes an electron transport layer 11, a perovskite photosensitive layer 12, a hole transport layer 13 and a front electrode provided on the electron transport layer 11, which are sequentially stacked in the direction from away from the intermediate layer unit 3;
  • the bottom battery unit 2 is a PERC solar cell.
  • the top battery unit 1 further includes an anti-reflection layer 14, a transparent conductive layer 15, and a passivation protective film layer 16 that are sequentially stacked in a direction from far away to approaching the electron transport layer.
  • the front electrode 17 can be one or more of gold, silver, copper, and aluminum;
  • the anti-reflection layer 14 can be one or more of silicon oxide, silicon nitride, silicon oxynitride, and MgF;
  • the transparent conductive layer 15 can be one or more of zinc oxide, tin oxide, molybdenum oxide, and indium oxide;
  • the passivation protective film layer 16 is a C60 material;
  • the electron transport layer 11 is a LiF layer; and the hole transport layer 13 is Spiro-MeOTAD.
  • the bottom battery unit 2 includes a passivation contact layer 21 , a silicon oxide layer 22 , a monocrystalline silicon base layer 23 , a backside passivation film layer 24 , a backside protection layer 21 , a silicon oxide layer 22 , a single crystal silicon base layer 23 , a backside passivation film layer 24 and a backside protection layer, which are sequentially stacked in the direction from approaching to the middle layer unit 3 .
  • layer 25 and back electrode 26 are sequentially stacked in the direction from approaching to the middle layer unit 3 .
  • the hole transport layer 13 is a nickel oxide layer; the electron transport layer 11 is a lithium fluoride layer, and a zinc oxide layer can also be selected.
  • the passivation contact layer 21 of the bottom battery unit 2 is an n-type silicon thin film passivation contact layer, and is structured as a textured structure.
  • the passivation contact layer 21 is formed with an internal electrode on the surface facing the intermediate layer unit 3 .
  • the backside passivation film layer 24 includes an aluminum oxide layer and a silicon oxide layer, and a p ++ localized back field layer is also formed on the lower surface of the p-type single crystal silicon base layer.
  • the backside protective layer 25 is a silicon nitride layer; the backside electrode 26 can be one or more of gold, silver, copper, and aluminum.
  • the embodiment of the present invention provides a method for preparing the above-mentioned laminated battery structure, and the preparation method includes the following steps:
  • the intermediate layer is configured as a tunnel junction composed of p + /n + double-layer silicon thin films
  • the top cell unit includes an electron transport layer, a perovskite photosensitive layer, a hole transport layer and a front electrode deposited on the electron transport layer, which are sequentially stacked in a direction from away from the middle layer.
  • the formation of the intermediate layer on the PERC solar cell is specifically formed by deposition, including PVD physical vapor deposition or RPD reactive plasma deposition,
  • the front and back sides of the intermediate layer are textured to prepare a pyramid-shaped textured structure.
  • providing a PERC solar cell includes the following specific steps:
  • the front and back sides of the single crystal silicon wafer are textured with an alkaline solution to prepare a textured structure with a side length of 1-10 ⁇ m of the pyramid base;
  • Alumina and silicon nitride are deposited on the backside; laser grooving on the backside, local ablation of alumina and silicon nitride layers; backside aluminum paste, silver paste printing, and sintering;
  • Front cleaning front oxidation to form a thin oxide layer of 1-10 nm on the front surface; front passivation contact deposition to form n-type doped amorphous/polysilicon on top of the silicon oxide layer.
  • the anti-reflection layer is one or more of silicon oxide, silicon nitride, silicon oxynitride, and magnesium fluoride.
  • the backside passivation film layer includes an aluminum oxide layer and a silicon oxide layer that are arranged in layers.
  • the surface of the mid-bottom battery of the present invention adopts an alkali-textured pyramid textured structure, which overcomes the problem of poor flat light trapping effect and can greatly improve the optical performance of the battery;
  • the bottom battery of the present invention adopts PERC battery, which can be seamlessly upgraded with the industry, and realizes low-cost mass production of laminated structure battery;
  • the tunnel junction is used as the link layer of the two cells, which overcomes the need for special deposition equipment or preparation on TCO in the prior art.
  • the technical defects of the perovskite cells are very uneven and poor performance.

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Abstract

公开了一种叠层电池结构，包括顶电池单元（1）、底电池单元（2）以及位于所述顶电池单元（1）与所述底电池单元（2）之间的中间层（3）；所述中间层（3）构造为p +/n +双层硅薄膜组成的隧穿结；所述顶电池单元（1）包括在自远离至靠近所述中间层（3）方向上依次层叠设置的电子传输层（11）、钙钛矿光敏层（12）、空穴传输层（13）和在所述电子传输层（11）上设有的正面电极（17）；所述底电池单元（2）为PERC太阳能电池；公开了上述叠层电池结构的制备方法。通过采用硅薄膜隧穿结结构可以获得良好的钙钛矿电池性能。该结构叠层电池光电转换效率高。

Description

一种叠层电池结构及其制备方法 技术领域
本发明涉及太阳能电池技术领域，尤其涉及一种叠层电池结构及其制备方法。
背景技术
太阳能电池是一种将太阳的光能直接转化为电能的半导体器件，利用光能这一可再生资源，在当今能源短缺的情形下太阳能电池具有广阔的发展前景。
目前太阳能电池行业中，钝化发射区和背面电池(Passivated Emitter and Rear Cell，PERC)、异质结电池(Heterojunction with Intrinsic Thin film，HIT)以及隧穿氧化层钝化接触电池(Tunnel Oxide Passivated Contact,TOPCon)等规模量产效率不断提升，逐渐逼近转换效率极限，叠层太阳能电池是进一步大幅提升电池转换效率的有效手段。叠层太阳能电池的原理为将不同光伏响应的电池采用各种手段集成到一起，在叠层太阳能电池结构中两端(2T)叠层电池更具应用前景。在各种叠层电池中，CIGS薄膜电池和硅薄膜电池的成本高昂，且无法和行业量产电池结构直接兼容。尽管有报道异质结电池和钙钛矿电池组成叠层太阳能电池，但是，目前行业中产量最高的电池结构为PERC电池，以PERC电池和钙钛矿电池组成两端叠层太阳能电池鲜有报道。此外，由于钙钛矿电池制备的工艺特性，多数报道的叠层电池中，钙钛矿电池制备都是基于底电池为平面结构。而平面结构大幅提升了电池反射率，造成底电池的转换效率急剧降低，无法充分发挥电池光电转换性能。
发明内容
为了解决现有技术的问题，本发明提出了一种叠层电池结构及其制备方法。
一方面，本申请提供了一种叠层电池结构，包括顶电池单元、底电池单元以及设置在所述顶电池单元与所述底电池单元之间的中间层单元；
所述顶电池单元包括电子传输层、钙钛矿光敏层、空穴传输层以及正面电极；
所述电子传输层、钙钛矿光敏层和空穴传输层在从远离至靠近所述中间层单元方向上，依次层叠设置，所述空穴传输层与所述中间层单元连接；
所述正面电极设置在所述电子传输层上；
所述底电池单元包括在从靠近至远离所述中间层方向上依次层叠设置的钝化接触层、氧化硅层、单晶硅基底层、背面钝化膜层、背面保护层和背面电极；
所述钝化接触层、氧化硅层、单晶硅基底层、背面钝化膜层和背面保护层在从靠近至远离所述中间层单元方向上，依次层叠设置，所述钝化接触层与所述中间层单元连接；
所述背面电极设置在背面保护层上；
所述中间层单元包括p +硅薄膜层和n +硅薄膜层，所述中间层单元的构造为所述p +硅薄膜层和所述n +硅薄膜层组成的隧穿结。
所述顶电池单元还包括设置在所述电子传输层上的所述减反射层、透明导电层和钝化保护膜层，所述减反射层、所述透明导电层和所述钝化保护膜层从远离至靠近所述电子传输层方向上，依次层叠设置。
所述空穴传输层为氧化镍层；所述电子传输层为氧化锌层或氟化锂层。
所述底电池单元的钝化接触层为n层硅薄膜钝化接触层，构造为绒面结构。
所述钝化接触层在面向所述中间层单元的表面形成有内接电极。
另一方面，本申请提供了一种叠层电池结构的制备方法，所述制备方法包括以下步骤：
制备底电池单元；
在所述底电池单元上制备中间层单元；所述中间层单元的构造为由p +硅薄膜层和n +硅薄膜层组成的隧穿结；
在所述中间层单元上制备具有钙钛矿光敏层的顶电池单元。
所述制备底电池单元，具体包括以下步骤：
在单晶硅片的正面和反面采用碱性溶液制备绒面；
在所述单晶硅片的正面和反面绒面上分别形成第一氧化硅层和第二氧化硅层；
对所述第二氧化硅层进行氧化退火，在所述第二氧化硅层上沉积氧化铝，构成背面钝化膜层；
在所述背面钝化膜层上沉积背面保护层，
在所述背面钝化膜层上设置背面电极；
在所述第一氧化硅层上沉积钝化接触层；
所述在所述单晶硅片的正面和反面绒面上分别形成第一氧化硅层和第二氧化硅层，具体包括以下步骤：
对单晶硅片的正面绒面上进行磷扩散，得到形成n型发射区的正面绒面；
对单晶硅片的背面绒面进行刻蚀抛光，得到去除背面扩散层和侧面导电通道的背面绒面；
在氧化炉中对单晶硅片进行热氧化，所述单晶硅片的正面和反面绒面上分别形成第一氧化硅层和第二氧化硅层。
正面清洗；正面氧化，在正表面形成薄氧化层1-10nm；正面钝化接触层沉积，在氧化硅层之上形成n型掺杂的非晶/多晶硅。
在所述底电池单元上制备中间层单元，具体采用沉积的方法制备，所述方法包括PVD物理气相沉积或RPD反应等离子体沉积，
所述在单晶硅片的正面和反面采用碱性溶液制备绒面，所述绒面结构为金字塔形状。
对单晶硅片的背面绒面进行刻蚀抛光后，具体还包括以下步骤：
在所述单晶硅片的背面绒面上沉积氧化铝、氮化硅；
在所述单晶硅片的背面绒面上激光开槽，局部消融氧化铝和氮化硅层；
在所述单晶硅片的背面绒面上印刷铝浆和银浆，并进行烧结；
对所述单晶硅片的正面绒面进行清洗和氧化，在正表面形成薄氧化层，所述薄氧化层的厚度为1-10nm；
在所述第一氧化硅层上沉积钝化接触层，所述钝化接触层为n型掺杂的非晶或多晶硅。
再一方面，本发明提供了一种叠层电池结构，包括顶电池单元、底电池单元以及位于所述顶电池单元与所述底电池单元之间的中间层；所述中间层构造为p +/n +双层硅薄膜组成的隧穿结；
所述顶电池单元包括在自远离至靠近所述中间层方向上依次层叠设置的电子传输层、钙钛矿光敏层、空穴传输层和在所述电子传输层上设有的正面电极；
所述底电池单元为PERC太阳能电池。
作为本发明实施方式的进一步改进，所述顶电池单元还包括在自远离至靠近所述电子传输层方向上依次层叠设置减反射层、透明导电层、钝化保护膜层。
作为本发明实施方式的进一步改进，所述底电池单元包括在自靠近至远离所述中间层方向上依次层叠设置的钝化接触层、氧化硅层、单晶硅基底层、背面钝化膜层、背面保护层和背面电极。
作为本发明实施方式的进一步改进，所述空穴传输层为氧化镍层；所述电子传输层为氧化锌层或氟化锂层。
作为本发明实施方式的进一步改进，所述底电池单元的钝化接触层为n型硅薄膜钝化接触层，构造为绒面结构。
作为本发明实施方式的进一步改进，所述钝化接触层在面向所述中间层的表面形成有内接电极。
又一方面，本发明提供了上述叠层电池结构的制备方法，所述制备方法包括以下步骤：
提供PERC太阳能电池；
在所述PERC太阳能电池上形成中间层；所述中间层构造为p +/n +双层硅薄膜组成的隧穿结；
在所述中间层上形成具有钙钛矿光敏层的顶电池单元；
所述顶电池单元包括在自远离至靠近所述中间层方向上依次层叠设置的电子传输层、钙钛矿光敏层、空穴传输层和在所述电子传输层上沉积正面电极。
作为本发明实施方式的进一步改进，在所述PERC太阳能电池上形成中间层具体采用沉积的方式形成，包括PVD物理气相沉积或RPD反应等离子体沉积，
作为本发明实施方式的进一步改进，所述中间层的正面和反面制绒，制备出金字塔形状的绒面结构。
作为本发明实施方式的进一步改进，提供PERC太阳能电池包括以下具体步骤：
S101、对单晶硅片的正面和反面采用碱性溶液进行制绒，制备出金字塔底座边长1-10μm的绒面结构；
S102、对单晶硅片的正面进行磷扩散形成n层，形成正面n型发射区；
S103、用酸或碱溶液对单晶硅片的背面进行刻蚀抛光，去除背面扩散层和侧面导电通道；
S104、在氧化炉中对单晶硅片进行热氧化，在正面和反面形成氧化硅层；
S105、对背面进行氧化退火，在背面沉积氧化铝钝化层；
S106、退火后在背面沉积保护层。
S107、制备背面电极。
作为本发明实施方式的进一步改进，在背面刻蚀抛光后具体包括以下步骤：
背面沉积氧化铝、氮化硅；背面激光开槽，局部消融氧化铝和氮化硅层；背面铝浆、银浆印刷，并烧结；
正面清洗；正面氧化，在正表面形成薄氧化层1-10nm；正面钝化接触层沉积，在 氧化硅层之上形成n型掺杂的非晶/多晶硅。
作为本发明实施方式的进一步改进，所述减反射层为氧化硅、氮化硅、氮氧化硅、氟化镁中一种或多种。
作为本发明实施方式的进一步改进，所述背面钝化膜层包括层叠设置的氧化铝层和氧化硅层。
作为本发明实施方式的进一步改进，所述保护层为氮化硅或氮氧化硅。
本发明中底电池表面采用了碱制绒金字塔绒面结构，克服了平面陷光效果差的问题，可以大幅提升电池光学性能；还可以和产业进行无缝升级，实现叠层结构电池低成本量产；另外，本发明在钙钛矿电池与晶硅太阳能电池组成2T叠层太阳能电池时采用了隧穿结作为两个电池的链接层，克服了现有技术中需要专门的沉积设备或在TCO上面制备的钙钛矿电池不均匀、性能较差的技术缺陷。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种叠层电池结构的示意图；
图2为本发明实施例提供的一种叠层电池结构及其制备方法的流程图。
图中示例表示为：1-顶电池单元；11-电子传输层；12-钙钛矿光敏层；13-空穴传输层；14-减反射层；15-透明导电层；16-钝化保护膜层；17-正面电极；2-底电池单元；21-钝化接触层；22-氧化硅层；23-单晶硅基底层；24-背面钝化膜层；25-背面保护层；26背面电极；3-中间层单元；31-p +硅薄膜层；32-n +硅薄膜层。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请提供了一种叠层电池结构，包括顶电池单元1、底电池单元2以及设置在 所述顶电池单元1与所述底电池单元2之间的中间层单元3。
其中，所述顶电池单元1包括电子传输层11、钙钛矿光敏层12、空穴传输层13以及正面电极17。
所述电子传输层11、钙钛矿光敏层12和空穴传输层13在从远离至靠近所述中间层单元3方向上，依次层叠设置，所述空穴传输层13与所述中间层单元3连接；所述正面电极17设置在所述电子传输层11上。
所述底电池单元2包括在从靠近至远离所述中间层方向上依次层叠设置的钝化接触层21、氧化硅层22、单晶硅基底层23、背面钝化膜层24、背面保护层25和背面电极26。
所述钝化接触层21、氧化硅层22、单晶硅基底层23、背面钝化膜层24和背面保护层25在从靠近至远离所述中间层单元3方向上，依次层叠设置，所述钝化接触层21与所述中间层单元3连接；所述背面电极26设置在背面保护层25上。
所述中间层单元3包括p +硅薄膜层31和n +硅薄膜层32，所述中间层单元3的构造为所述p +硅薄膜层31和所述n +硅薄膜层32组成的隧穿结。
在另一种实现方式中，所述顶电池单元1还包括设置在所述电子传输层11上的所述减反射层14、透明导电层15和钝化保护膜层16，所述减反射层14、所述透明导电层15和所述钝化保护膜层16从远离至靠近所述电子传输层11方向上，依次层叠设置。
在另一种实现方式中，所述空穴传输层13为氧化镍层；所述电子传输层11为氧化锌层或氟化锂层。
在另一种实现方式中，所述底电池单元2的钝化接触层21为n型硅薄膜钝化接触层，构造为绒面结构。
在另一种实现方式中，所述钝化接触层21在面向所述中间层单元3的表面形成有内接电极。
与本申请的电池结构的实施例相对应，本申请还提供了电池制备方法的实施例。如图x所示，所述制备方法的实施例可以包括以下步骤：
S1：制备底电池单元；
S2：在所述底电池单元上制备中间层单元；所述中间层单元的构造为由p +硅薄膜层和n +硅薄膜层组成的隧穿结；
S3：在所述中间层单元上制备具有钙钛矿光敏层的顶电池单元。
其中，所述制备底电池单元，可以包括以下步骤：
在单晶硅片的正面和反面采用碱性溶液制备绒面；
在所述单晶硅片的正面和反面绒面上分别形成第一氧化硅层和第二氧化硅层；
对所述第二氧化硅层进行氧化退火，在所述第二氧化硅层上沉积氧化铝，构成背面钝化膜层；
在所述背面钝化膜层上沉积背面保护层，
在所述背面保护层上设置背面电极；
在所述第一氧化硅层上沉积钝化接触层；
所述在所述单晶硅片的正面和反面绒面上分别形成第一氧化硅层和第二氧化硅层，具体包括以下步骤：
对单晶硅片的正面绒面上进行磷扩散，得到形成n型发射区的正面绒面；
对单晶硅片的背面绒面进行刻蚀抛光，得到去除背面扩散层和侧面导电通道的背面绒面；
在氧化炉中对单晶硅片进行热氧化，所述单晶硅片的正面和反面绒面上分别形成第一氧化硅层和第二氧化硅层。
正面清洗；正面氧化，在正表面形成薄氧化层1-10nm；正面钝化接触层沉积，在氧化硅层之上形成n型掺杂的非晶/多晶硅。
在所述底电池单元上制备中间层单元，具体采用沉积的方法制备，所述方法包括PVD物理气相沉积或RPD反应等离子体沉积，
所述在单晶硅片的正面和反面采用碱性溶液制备绒面，所述绒面结构为金字塔形状。
对单晶硅片的背面绒面进行刻蚀抛光后，具体还包括以下步骤：
在所述单晶硅片的背面绒面上沉积氧化铝、氮化硅；
在所述单晶硅片的背面绒面上激光开槽，局部消融氧化铝和氮化硅层；
在所述单晶硅片的背面绒面上印刷铝浆和银浆，并进行烧结；
对所述单晶硅片的正面绒面进行清洗和氧化，在正表面形成薄氧化层，所述薄氧化层的厚度为1-10nm；
在所述第一氧化硅层上沉积钝化接触层，所述钝化接触层为n型掺杂的非晶或多晶硅。
下面结合一些实施例对本申请的技术方案进行进一步的说明。
实施例1
本发明实施例提供了一种叠层电池结构，如图1所示，包括顶电池单元1、底电池单元2以及位于顶电池单元1与底电池单元2之间的中间层单元3；中间层单元3构造为p +/n +双层硅薄膜组成的隧穿结，具体包括p +硅薄膜层31和n +硅薄膜层32；
顶电池单元1包括在自远离至靠近中间层单元3方向上依次层叠设置的电子传输层11、钙钛矿光敏层12、空穴传输层13和在电子传输层11上设有的正面电极；
所述底电池单元2为PERC太阳能电池。
在本发明实施例中，顶电池单元1还包括在自远离至靠近所述电子传输层方向上依次层叠设置减反射层14、透明导电层15、钝化保护膜层16。其中，正面电极17可以为金、银、铜、铝中的一种或多种；减反射层14可以为氧化硅、氮化硅、氮氧化硅、MgF中一种或多种；透明导电层15可为氧化锌、氧化锡、氧化钼、氧化铟中的一种或多种；钝化保护膜层16为C60材料；电子传输层11为LiF层；空穴传输层13为Spiro-MeOTAD。
进一步地，底电池单元2包括在自靠近至远离中间层单元3方向上依次层叠设置的钝化接触层21、氧化硅层22、单晶硅基底层23、背面钝化膜层24、背面保护层25和背面电极26。
空穴传输层13为氧化镍层；电子传输层11为氟化锂层，也可以选择氧化锌层。底电池单元2的钝化接触层21为n型硅薄膜钝化接触层，构造为绒面结构。钝化接触层21在面向中间层单元3的表面形成有内接电极。
背面钝化膜层24包括氧化铝层和氧化硅层，p型单晶硅基底层下表面还有p ++局域背场层。背面保护层25为氮化硅层；背面电极26可为金、银、铜、铝中的一种或多种。
实施例2
本发明实施例提供了上述叠层电池结构的制备方法，所述制备方法包括以下步骤：
提供PERC太阳能电池；
在所述PERC太阳能电池上形成中间层；所述中间层构造为p +/n +双层硅薄膜组成的隧穿结；
在所述中间层上形成具有钙钛矿光敏层的顶电池单元；
所述顶电池单元包括在自远离至靠近所述中间层方向上依次层叠设置的电子传输层、钙钛矿光敏层、空穴传输层和在所述电子传输层上沉积正面电极。
作为本发明实施方式的进一步改进，在所述PERC太阳能电池上形成中间层具体 采用沉积的方式形成，包括PVD物理气相沉积或RPD反应等离子体沉积，
作为本发明实施方式的进一步改进，所述中间层的正面和反面制绒，制备出金字塔形状的绒面结构。
作为本发明实施方式的进一步改进，提供PERC太阳能电池包括以下具体步骤：
S101、对单晶硅片的正面和反面采用碱性溶液进行制绒，制备出金字塔底座边长1-10μm的绒面结构；
S102、对单晶硅片的正面进行磷扩散，形成正面n型发射区；
S103、用酸或碱溶液对单晶硅片的背面进行刻蚀抛光，去除背面扩散层和侧面导电通道；
S104、在氧化炉中对单晶硅片进行热氧化，在正面和反面形成氧化硅层；
S105、对背面进行氧化退火，在背面沉积氧化铝钝化层；
S106、退火后在背面沉积保护层。
S107、制备背面电极。
作为本发明实施方式的进一步改进，在背面刻蚀抛光后具体包括以下步骤：
背面沉积氧化铝、氮化硅；背面激光开槽，局部消融氧化铝和氮化硅层；背面铝浆、银浆印刷，并烧结；
正面清洗；正面氧化，在正表面形成薄氧化层1-10nm；正面钝化接触层沉积，在氧化硅层之上形成n型掺杂的非晶/多晶硅。
作为本发明实施方式的进一步改进，所述减反射层为氧化硅、氮化硅、氮氧化硅、氟化镁中一种或多种。
作为本发明实施方式的进一步改进，所述背面钝化膜层包括层叠设置的氧化铝层和氧化硅层。
本发明具有如下有益效果：
1、本发明中底电池表面采用了碱制绒金字塔绒面结构，克服了平面陷光效果差的问题，可以大幅提升电池光学性能；
2、本发明底电池采用PERC电池，可以和产业进行无缝升级，实现叠层结构电池低成本量产；
3、本发明在钙钛矿电池与晶硅太阳能电池组成2T叠层太阳能电池时采用了隧穿结作为两个电池的链接层，克服了现有技术中需要专门的沉积设备或在TCO上面制备的钙钛矿电池很不均匀、性能较差的技术缺陷。
上述所有可选技术方案，可以采用任意结合形成本发明的可选实施例，在此不再一一赘述。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (11)

  1. 一种叠层电池结构，其特征在于，包括顶电池单元(1)、底电池单元(2)以及设置在所述顶电池单元(1)与所述底电池单元(2)之间的中间层单元(3)；
    所述顶电池单元(1)包括电子传输层(11)、钙钛矿光敏层(12)、空穴传输层(13)以及正面电极(17)；
    所述电子传输层(11)、钙钛矿光敏层(12)和空穴传输层(13)在从远离至靠近所述中间层单元(3)方向上，依次层叠设置，所述空穴传输层(13)与所述中间层单元(3)连接；
    所述正面电极(17)设置在所述电子传输层(11)上；
    所述底电池单元(2)包括在从靠近至远离所述中间层单元(3)方向上依次层叠设置的钝化接触层(21)、氧化硅层(22)、单晶硅基底层(23)、背面钝化膜层(24)、背面保护层(25)和背面电极(26)；
    所述钝化接触层(21)、氧化硅层(22)、单晶硅基底层(23)、背面钝化膜层(24)和背面保护层(25)在从靠近至远离所述中间层单元(3)方向上，依次层叠设置，所述钝化接触层(21)与所述中间层单元(3)连接；
    所述背面电极(26)设置在背面保护层(25)上；
    所述中间层单元(3)包括p +硅薄膜层(31)和n +硅薄膜层(32)，所述中间层单元(3)的构造为所述p +硅薄膜层(31)和所述n +硅薄膜层(32)组成的隧穿结。
  2. 根据权利要求1所述的叠层电池结构，其特征在于，所述顶电池单元(1)还包括设置在所述电子传输层(11)上的减反射层(14)、透明导电层(15)和钝化保护膜层(16)，所述减反射层(14)、所述透明导电层(15)和所述钝化保护膜层(16)从远离至靠近所述电子传输层(11)方向上，依次层叠设置。
  3. 根据权利要求1所述的叠层电池结构，其特征在于，所述空穴传输层(13)为氧化镍层，所述电子传输层(11)为氧化锌层或氟化锂层。
  4. 根据权利要求1所述的叠层电池结构，其特征在于，所述钝化接触层(21)为n型硅薄膜钝化接触层，构造为绒面结构。
  5. 根据权利要求1所述的叠层电池结构，其特征在于，所述钝化接触层(21)在面向所述中间层单元(3)的表面形成有内接电极。
  6. 一种叠层电池结构的制备方法，其特征在于，包括以下步骤：
    制备底电池单元；
    在所述底电池单元上制备中间层单元；所述中间层单元的构造为由p +硅薄膜层和n +硅薄膜层组成的隧穿结；
    在所述中间层单元上制备具有钙钛矿光敏层的顶电池单元。
  7. 根据权利要求6所述的叠层电池结构的制备方法，其特征在于，所述制备底电池单元，具体包括以下步骤：
    在单晶硅片的正面和反面采用碱性溶液制备绒面；
    在所述单晶硅片的正面和反面绒面上分别形成第一氧化硅层和第二氧化硅层；
    对所述第二氧化硅层进行氧化退火，在所述第二氧化硅层上沉积氧化铝，构成背面钝化膜层；
    在所述背面钝化膜层上沉积背面保护层，
    在所述背面保护层上设置背面电极；
    在所述第一氧化硅层上沉积钝化接触层。
  8. 根据权利要求7所述的叠层电池结构的制备方法，其特征在于，所述在所述单晶硅片的正面和反面绒面上分别形成第一氧化硅层和第二氧化硅层，具体包括以下步骤：
    对单晶硅片的正面绒面上进行磷扩散，得到形成n型发射区的正面绒面；
    对单晶硅片的背面绒面进行刻蚀抛光，得到去除背面扩散层和侧面导电通道的背面绒面；
    在氧化炉中对单晶硅片进行热氧化，所述单晶硅片的正面和反面绒面上分别形成第一氧化硅层和第二氧化硅层。
  9. 根据权利要求7所述的叠层电池结构的制备方法，其特征在于，在所述底电池单元上制备中间层单元，具体采用沉积的方法制备，所述方法包括PVD物理气相沉积或RPD反应等离子体沉积。
  10. 根据权利要求8所述的叠层电池结构的制备方法，其特征在于，所述在单晶硅片的正面和反面采用碱性溶液制备绒面，所述绒面结构为金字塔形状。
  11. 根据权利要求9所述的叠层电池结构的制备方法，其特征在于，对单晶硅片的背面绒面进行刻蚀抛光后，具体还包括以下步骤：
    在所述单晶硅片的背面绒面上沉积氧化铝和氮化硅；
    在所述单晶硅片的背面绒面上激光开槽，局部消融氧化铝和氮化硅层；
    在所述单晶硅片的背面绒面上印刷铝浆和银浆，并进行烧结；
    对所述单晶硅片的正面绒面进行清洗和氧化，在正表面形成薄氧化层，所述薄氧化层的厚度为1-10nm；
    在所述第一氧化硅层上沉积钝化接触层，所述钝化接触层为n型掺杂的非晶或多晶硅。
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