WO2021180121A1 - 半导体结构的处理方法 - Google Patents

半导体结构的处理方法 Download PDF

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Publication number
WO2021180121A1
WO2021180121A1 PCT/CN2021/079971 CN2021079971W WO2021180121A1 WO 2021180121 A1 WO2021180121 A1 WO 2021180121A1 CN 2021079971 W CN2021079971 W CN 2021079971W WO 2021180121 A1 WO2021180121 A1 WO 2021180121A1
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Prior art keywords
semiconductor structure
etching
processing
transition layer
substrate
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PCT/CN2021/079971
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English (en)
French (fr)
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李世鸿
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21768606.2A priority Critical patent/EP3951837A4/en
Priority to KR1020227022239A priority patent/KR102717795B1/ko
Priority to JP2022540435A priority patent/JP2023508553A/ja
Priority to US17/371,027 priority patent/US20210335594A1/en
Publication of WO2021180121A1 publication Critical patent/WO2021180121A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate

Definitions

  • This application relates to the field of semiconductor manufacturing technology, and in particular to a processing method of a semiconductor structure.
  • HAR high-aspect-ratio
  • the semiconductor structure such as DRAM completes the etching process of the trench and other patterns
  • the pattern may collapse or deform due to capillary force.
  • the fluid tension that may appear in the semiconductor structure is greater.
  • the first is Laplace pressure
  • the second is adhesion
  • the third is electrostatic force, van der Waals force and hydrogen bonding.
  • the surface effect of the cleaning liquid has become the main factor that affects the quality of the process. factor.
  • the capillary force acting on the pattern structure may cause the pattern to collapse.
  • this treatment method will lead to the appearance of other negative effects, such as the super-hydrophobic effect of the HAR structure.
  • This super-hydrophobic effect prevents the aqueous solution from penetrating between the structures, resulting in a decrease in the effectiveness of wet cleaning.
  • adding a surface modifier before the drying process after cleaning can effectively prevent the pattern from collapsing, but the surface modifier may remain at the bottom of the STI structure, which may cause abnormalities in the semiconductor device.
  • the present application provides a processing method of a semiconductor structure, which is used to solve the problem of pattern collapse and deformation of the semiconductor structure during the cleaning process, so as to improve the performance of the semiconductor structure and increase the yield of the semiconductor device.
  • the present application provides a method for processing a semiconductor structure, which includes the following steps:
  • the semiconductor structure including a substrate and a plurality of etching structures located on a surface area of the substrate;
  • transition layer covering at least the inner wall of the etching structure, the transition layer being used to reduce the capillary force of the fluid on the etching structure and as a sacrificial layer for repairing the collapsed structure;
  • the etching structure is a trench, and the number of the trenches located on the surface area of the substrate is multiple;
  • the ratio between the depth of the groove and the minimum width of the groove is greater than 8.
  • a plurality of the grooves are arranged in parallel on the surface area of the substrate;
  • the pattern line width between adjacent grooves is less than 20 nm.
  • providing a semiconductor structure specifically includes the following steps:
  • the specific steps of cleaning the semiconductor structure include:
  • the semiconductor structure is treated with a wet cleaning process to remove by-products and contaminants after the etching and ashing process.
  • the specific steps of using a plasma ashing process to process the semiconductor structure include:
  • the surface of the semiconductor structure is ashing treated with plasma oxygen gas to remove the polymer residue after etching to form the trench.
  • the ratio of the flow rate of the oxygen to the flow rate of the mixed gas of hydrogen and nitrogen is 10:1, and the volume ratio of the hydrogen in the mixed gas of hydrogen and nitrogen is 4%.
  • the specific steps of forming a transition layer covering at least the inner wall of the etching structure include:
  • the semiconductor structure is oxidized to form an oxide layer covering at least the inner wall of the trench, and the oxide layer is the transition layer.
  • the specific step of oxidizing the semiconductor structure includes:
  • the oxidizing liquid is ozone water or a mixed solution of ammonia water and hydrogen peroxide.
  • the specific steps of treating the semiconductor structure with an oxidizing liquid include:
  • the oxidizing liquid is sprayed to the surface of the rotating semiconductor structure to infiltrate the semiconductor structure.
  • the thickness of the oxide layer is
  • the specific steps of removing the transition layer include:
  • a mixed gas of hydrogen fluoride and ammonia is used as an etching gas to remove the transition layer.
  • the total thickness of the transition layer and the substrate etched away by the mixed gas of hydrogen fluoride and ammonia as the etching gas is 1 nm-10 nm.
  • the flow ratio of hydrogen fluoride to ammonia gas is (1-2):1.
  • the specific step of drying the semiconductor structure includes:
  • the semiconductor structure is treated with isopropanol at a preset temperature to remove moisture in the surface area of the semiconductor structure.
  • the method further includes the following steps:
  • a transition layer is formed on the inner wall of the etched structure to reduce the capillary force of the fluid on the etched structure, so that the subsequent drying of the etched structure reduces the number of etched structures.
  • the etched structure is restored to an undeformed state, thereby further reducing the probability of collapse or deformation of the etched structure, improving the performance of the semiconductor structure, and increasing the yield and yield of semiconductor devices.
  • FIG. 1 is a flowchart of a processing method of a semiconductor structure in a specific embodiment of the present application
  • FIGS. 2A-2F are schematic diagrams of the main processes of a semiconductor structure in the process of the specific implementation of the present application.
  • Figs. 3A-3E are schematic diagrams of the main process of another semiconductor structure in the process of the specific embodiment of the present application.
  • FIGS. 4A-4H are schematic cross-sectional views of a processing chamber of a semiconductor structure during processing in a specific embodiment of the present application.
  • FIG. 1 is a flowchart of a method for processing a semiconductor structure in a specific embodiment of this application.
  • Figs. 4A-4H are schematic cross-sectional views of a processing chamber of a semiconductor structure in a specific embodiment of the present application. As shown in FIG. 1, FIG. 2A-FIG. 2F and FIG. 4A-FIG. 4H, the method for processing a semiconductor structure provided in this embodiment includes the following steps:
  • a semiconductor structure is provided.
  • the semiconductor structure includes a substrate 20 and a plurality of etched structures 22 located on the surface area of the substrate 20, as shown in FIG. 2A.
  • the etching structure 22 may be any structure formed in the substrate 20 by a process such as dry etching.
  • the etching structure is a trench, and the number of the trenches located on the surface area of the substrate is multiple;
  • the ratio between the depth H of the groove and the minimum width W of the groove is greater than 8.
  • a plurality of the grooves are arranged in parallel on the surface area of the substrate 20;
  • the pattern line width D between adjacent grooves is less than 20 nm.
  • the etching structure 22 may be a groove extending from the surface of the substrate 20 in a direction perpendicular to the substrate 20 (ie, the Y-axis direction in FIG. 2A) toward the interior of the substrate 20, for example, STI. Since the trenches with high aspect ratios are more likely to collapse or deform during the cleaning process in the semiconductor manufacturing process, the processing method of the semiconductor structure provided in this embodiment is effective in preventing the trenches with high aspect ratios from being cleaned. The effect of collapse or deformation during the process is more significant.
  • five grooves are arranged in parallel on the surface area of the substrate 20 (that is, the X-axis direction in FIG. 2A). In actual use, the specific number of grooves can be determined by those skilled in the art. Choose according to actual needs.
  • the aspect ratios of the plurality of grooves may be the same or different.
  • the "plurality" in this specific embodiment refers to two or more.
  • providing a semiconductor structure includes the following steps:
  • the specific steps of cleaning the semiconductor structure include:
  • the semiconductor structure is treated with a wet cleaning process to remove by-products and contaminants after the etching and ashing process.
  • the specific steps of using a plasma ashing process to process the semiconductor structure include:
  • the surface of the semiconductor structure is ashing treated with plasma oxygen gas to remove the polymer residue after etching to form the trench.
  • the specific steps of ashing the surface of the semiconductor structure with plasmaized oxygen include:
  • plasmaized oxygen and a mixed gas composed of hydrogen and nitrogen are introduced, and the ratio of the flow rate of the introduced oxygen to the flow rate of the mixed gas is 10:1.
  • the volume ratio of the hydrogen in the mixed gas composed of hydrogen and nitrogen is 4%.
  • the surface of the substrate 20 has a mask layer, such as a first mask layer 211 covering the surface of the substrate 20 and a second mask layer covering the surface of the first mask layer 211 in FIG. 2A 212.
  • the mask layer has a mask pattern, and the substrate 20 is etched along the mask pattern in the mask layer by a dry etching process or other etching processes to form the grooves. After the groove, some polymer will remain inside the groove, that is, the polymer remains. Due to the etching reaction between the etchant and the substrate 20, some by-products and contaminants may also be generated.
  • a plasma ashing process is first used to remove the polymer residue, and then a wet cleaning process is used to remove the by-products. And contaminants to ensure the cleanliness of the inside of the groove and the surface of the substrate.
  • the material of the first mask layer 211 may be silicon oxide, and the material of the second mask layer 212 may be silicon nitride.
  • the flow rate of oxygen is 5000ml/min ⁇ 30000ml/min
  • the flow rate of the mixed gas composed of hydrogen and nitrogen (the volume ratio of hydrogen is 4%) is 500ml/min ⁇ 3000ml/min
  • the process temperature The temperature is 100°C to 500°C
  • the process duration is 10 seconds to 120 seconds
  • the pressure in the processing chamber is 200 mtorr to 5000 mtorr
  • the radio frequency power is 1000W to 10000W.
  • the cleaning agent can be diluted HF (DHF), where the volume ratio of HF (49% HF liquid) to deionized water is 1:(1 ⁇ 1000), and the process duration It is 5 seconds to 600 seconds, the process temperature is 15°C to 60°C, and the rotation speed of the support table is 100rpm to 3000rpm.
  • DHF diluted HF
  • the substrate 20 with the trench is placed on the support table 41 in the processing chamber 40 as shown in FIG.
  • the shower head 42 transmits plasmaized oxygen to the substrate 20 at a flow rate of 13000ml/min, and simultaneously transmits the plasmaized mixed gas (consisting of hydrogen and nitrogen, and at a flow rate of 1300ml/min).
  • the volume ratio of hydrogen is 4%) to the substrate, and the temperature in the processing chamber 40 is 250° C., the pressure is 1200 mtorr, the radio frequency power (RF) is 4400 W, and the process duration is 21 seconds.
  • DHF (1:200) is used as the cleaning agent, and the cleaning agent is sprayed to the On the surface of the substrate 20, at the same time, the supporting table 41 rotates at a speed of 1500 rpm, the process temperature is room temperature, and the process duration is 130 seconds.
  • step S12 a transition layer 24 covering at least the inner wall of the etching structure 22 is formed, and the transition layer 24 is used to reduce the capillary force of the fluid on the etching structure 22, as shown in FIG. 2C.
  • the specific steps of forming the transition layer 24 covering at least the inner wall of the etching structure 22 include:
  • the semiconductor structure is oxidized to form an oxide layer covering at least the inner wall of the trench, and the oxide layer is the transition layer 24.
  • the specific step of oxidizing the semiconductor structure includes:
  • the oxidizing liquid is an ozone deionized aqueous solution (DIO 3 ) or a mixed solution of ammonia and hydrogen peroxide (ie, APM solution).
  • DIO 3 ozone deionized aqueous solution
  • APM solution a mixed solution of ammonia and hydrogen peroxide
  • the specific steps of treating the semiconductor structure with an oxidizing liquid include:
  • the oxidizing liquid is sprayed to the surface of the rotating semiconductor structure to infiltrate the semiconductor structure.
  • the thickness of the oxide layer is
  • an ozone deionized aqueous solution or an APM solution may be sprayed to the substrate 20 through the shower head 42, while the support platform maintains Spin.
  • the oxidizing liquid is an ozone deionized aqueous solution
  • the flow rate of O 3 mixed into the deionized water is 1L/min-10L/min
  • the flow rate of the ozone deionized aqueous solution is 1L/min-10L/min
  • the process temperature is 5°C to 35°C
  • the process duration is 6 seconds to 1800 seconds
  • the rotating speed of the support table is 100 rpm to 1200 rpm
  • the thickness of the formed oxide layer is
  • the oxidizing liquid is a solution of APM
  • APM solution of NH 4 OH, H 2 O 2 , H 2 O volume ratio of NH 4 OH: H 2 O 2 : H 2 O 1: (1 ⁇ 10) :(10 ⁇ 200)
  • the material of the transition layer 24 is silicon dioxide.
  • the formation of the transition layer 24 can prevent the semiconductor structure from using the transition layer 24 as the interface layer between the silicon and the fluid during the subsequent semiconductor rinsing process, thereby enhancing the trench pairing.
  • the resistance of the fluid tension is to reduce the capillary force of the fluid to the groove, thereby realizing the protection of the pattern structure such as the groove.
  • the formation of the transition layer 24 (such as an oxide layer) will also change the hydrophobicity of the semiconductor structure, thereby reducing the van der Waals force generated by the silicon surface on the particulate matter, which is more conducive to the etching of the particulate matter in the trench and other structures. Removal.
  • Step S13 drying the semiconductor structure, as shown in FIG. 2D.
  • the specific step of drying the semiconductor structure includes:
  • the semiconductor structure is treated with isopropanol at a preset temperature to remove moisture in the surface area of the semiconductor structure.
  • hot isopropanol (Hot-IPA) is used as the drying fluid.
  • hot isopropanol can replace the moisture in the surface area of the semiconductor structure, and on the other hand, it can also help Further reduce surface tension.
  • the drying fluid is sprayed onto the surface of the semiconductor structure through the shower head 42, and at the same time, nitrogen is introduced into the processing chamber as a purge gas to pass the isopropanol through the surface of the processing chamber.
  • the exhaust port is removed in time to achieve the drying of the semiconductor structure.
  • the flow rate of the isopropanol is 50ml/min ⁇ 500ml/min
  • the process temperature is 40°C ⁇ 80°C
  • the process duration is 10 seconds ⁇ 600 seconds
  • the rotation speed of the support table is 100rpm ⁇ 4000rpm.
  • the preset temperature is 40°C to 80°C, for example 60°C.
  • step S14 the transition layer 24 is removed, as shown in FIG. 2F.
  • the specific steps of removing the transition layer 24 include:
  • a mixed gas of hydrogen fluoride (99.999% HF gas) and ammonia is used as an etching gas to remove the transition layer 24.
  • the total thickness of the transition layer 24 and the substrate 20 etched away by the mixed gas of hydrogen fluoride and ammonia as the etching gas is 1 nm-10 nm.
  • the flow ratio of hydrogen fluoride to ammonia gas is (1-2):1.
  • HF and NH 3 are simultaneously introduced into the processing chamber, and the transition layer 24 is removed by a vapor etching method.
  • silicon dioxide as the material of the transition layer 24 as an example
  • the chemical reaction that occurs during the etching of the silicon dioxide by HF and NH 3 is shown in FIG. 2E.
  • the exhaust gas produced in the reaction process is drawn away in time through the exhaust port at the bottom of the processing chamber, as shown by the arrows in Figs. 4E and 4F.
  • the flow rate ratio of HF and NH 3 is (1-2):1
  • the flow rates of HF and NH 3 are both 10 sccm to 300 sccm (for example, 25 sccm)
  • the process temperature is 20° C. 150°C (for example, 130°C)
  • the process duration is 1 second to 60 seconds
  • the pressure in the processing chamber is 1 mtorr to 5000 mtorr
  • the support table temperature is 20°C to 150°C (for example, 35°C).
  • the transition layer 24 is over-etched to fully remove the transition layer, so that the etched structure deformed during the isopropanol drying process can be restored to the greatest extent.
  • the thickness of the transition layer 24 that is etched away may be 1 nm-10 nm.
  • a process of alternately and cyclically passing NH 3 /HF and N 2 may also be adopted, such as passing HF and NH 3 in the first stage, and passing N 2 in the second stage.
  • HF and NH 3 are introduced again, and in the fourth stage, N 2 is introduced , and so on alternately.
  • the method further includes the following steps:
  • the heater 43 inside the support table is used to heat the substrate 20 to evaporate the products in the etching reaction; on the other hand, , the nitrogen gas is introduced into the processing chamber and the processing chamber is continuously evacuated, so that the residue of the etching reaction is discharged from the processing chamber in time; finally, the processing chamber is continued to be purged with nitrogen, as shown in FIG. 4G As shown, until the support table stops rotating, the entire wet cleaning process is completed, as shown in FIG. 4H.
  • the flow rate of nitrogen is 200 sccm to 10000 sccm (for example, 2000 sccm)
  • the process temperature is 90 to 250° C. (for example, 95° C.)
  • the process duration is 20 seconds to 600 seconds ( For example, 120 seconds)
  • the pressure in the processing chamber is 200 mtorr to 10000 mtorr (for example, 2000 mtorr).
  • the pattern collapse or deformation after the cleaning is completed is less than 2%.
  • FIGS. 3A-3E are schematic diagrams of the main process of another semiconductor structure during processing in the specific embodiment of the present application, that is, FIGS. 3A-3E show schematic diagrams of processing a semiconductor structure without a mask layer on the surface of the substrate.
  • the process steps and the process conditions during the implementation of each process step can be the same as the conditions shown in FIGS. 2A to 2F and FIGS. 4A to 4H.
  • a transition layer is formed on the inner wall of the etched structure to reduce the capillary force of the fluid on the etched structure, so that the subsequent drying of the etched structure reduces the amount of etching.
  • the probability of collapse or deformation of the etched structure at the same time, the transition layer covering the inner wall of the etched structure is removed after drying, and the attraction between the patterns of the etched structure is interrupted, causing deformation in the pre-drying process
  • the etched structure is restored to an undeformed state, thereby further reducing the probability of collapse or deformation of the etched structure, improving the performance of the semiconductor structure, and increasing the yield and yield of semiconductor devices.

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  • Drying Of Semiconductors (AREA)

Abstract

本申请涉及半导体制造技术领域，尤其涉及一种半导体结构的处理方法。所述半导体结构的处理方法包括如下步骤：提供一半导体结构，所述半导体结构包括基底以及位于所述基底表面区域的若干个刻蚀结构；形成至少覆盖所述刻蚀结构内壁的过渡层，所述过渡层用于减少流体对所述刻蚀结构的毛细管力及当作修复倒塌结构的牺牲层；干燥所述半导体结构；去除所述过渡层。本申请减少了刻蚀结构在清洗过程中出现坍塌或变形的概率，改善了半导体结构的性能，提高了半导体器件的产率和良率。

Description

半导体结构的处理方法
相关申请引用说明
本申请要求于2020年3月11日递交的中国专利申请号202010166572.2、申请名为“半导体结构的处理方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种半导体结构的处理方法。
背景技术
随着近些年半导体行业的飞速发展，高深宽比(High-aspect-ratio，HAR)纳米结构在各领域都得到了广泛的应用。随着在技术上越来越追求纳米器件，芯片生产过程中的特征尺寸不断缩小，整个半导体生产技术仍然朝着关键尺寸进一步微细化方向发展。
在DRAM等半导体结构完成沟槽等图案的刻蚀工艺之后，通常需要进行湿法清洗和干燥步骤，以除去刻蚀过程中产生的副产物或者刻蚀残留的聚合物。然而，在湿法清洗和干燥的过程中，会因为毛细力作用导致图案出现坍塌或者变形。当刻蚀形成的沟槽尺寸越小时，半导体结构中可能出现的流体张力就越大。常见的引起图案坍塌的因素有三种：第一种是，拉普拉斯压力(Laplace pressure)；第二种是，粘附力；第三种是，静电力、范德华力和氢键作用。在先进DRAM制程工艺中，图案坍塌会严重影响后期芯片的良率和产率，也越来越成为决定制程成败的关键因素。特别的，具有高深宽比的浅沟槽隔离结构(Shallow Trench Isolation，STI)在湿法清洗过程中因毛细力作用导致图案坍塌或变形的情况更为严重。因此，消除或者降低图案坍塌的风险，对DARM等半导体器件的生产起着至关重要的作用。
但是，在更加先进的DRAM制程工艺中，随着结构尺寸的减小和对HAR的需求，对清洗时液体环境的稳定性提出了很大的挑战，清洗液体的表面效应成为影响制程质量的主要因素。具体来说，在湿法清洗过程中，作用于图案结构上的毛细力可能导致图案的坍塌。虽然，可以通过对HAR结构进行表面修饰处理，来减少图案的坍塌，但是，这种处理方法会导致其他负面效应的出现，例如HAR结构的超疏水效应。这种超疏水效应会阻止水溶液渗透到结构之间， 从而导致湿法清洗的效果降低。此外，以STI制程为例，清洗后于干燥工艺前添加表面修饰剂，虽然可有效地防止图案的坍塌，但表面修饰添加剂可能会残留在STI结构的底处，进而导致半导体器件异常。
因此，如何减少半导体结构在清洗过程中易出现图案坍塌变形的问题，以改善半导体结构的性能，并提高半导体器件的良率，是目前亟待解决的技术问题。
发明内容
本申请提供一种半导体结构的处理方法，用于解决半导体结构在清洗过程中易出现图案坍塌变形的问题，以改善半导体结构的性能，并提高半导体器件的良率。
为了解决上述问题，本申请提供了一种半导体结构的处理方法，包括如下步骤：
提供一半导体结构，所述半导体结构包括基底以及位于所述基底表面区域的若干个刻蚀结构；
形成至少覆盖所述刻蚀结构内壁的过渡层，所述过渡层用于减少流体对所述刻蚀结构的毛细管力及当作修复倒塌结构的牺牲层；
干燥所述半导体结构；
去除所述过渡层。
可选的，所述刻蚀结构为沟槽，且位于所述基底的表面区域的所述沟槽的数量为多个；
所述沟槽的深度与所述沟槽的最小宽度之间的比值大于8。
可选的，多个所述沟槽平行排列于所述基底的表面区域；
相邻所述沟槽之间的图形线宽小于20nm。
可选的，提供一半导体结构具体包括如下步骤：
提供基底；
刻蚀所述基底，于所述基底的表面区域形成多个所述沟槽，所述沟槽底部延伸至基底内部，以形成所述半导体结构；
清洁所述半导体结构，除去刻蚀形成所述沟槽之后的杂质。
可选的，清洁所述半导体结构的具体步骤包括：
采用等离子体灰化工艺处理所述半导体结构，除去刻蚀形成所述沟槽之后的聚合物残留；
采用湿法清洗工艺处理所述半导体结构，除去刻蚀以及灰化过程之后的副产物和污染物。
可选的，采用等离子体灰化工艺处理所述半导体结构的具体步骤包括：
用等离子体化的氧气对所述半导体结构表面进行灰化处理，以去除在刻蚀形成所述沟槽之后的所述聚合物残留。
可选的，所述氧气的流量与氢气和氮气的混合气体的流量比为10:1，在氢气和氮气的混合气体中所述氢气的体积比为4％。
可选的，形成至少覆盖所述刻蚀结构内壁的过渡层的具体步骤包括：
氧化所述半导体结构，形成至少覆盖所述沟槽内壁的氧化层，所述氧化层即为所述过渡层。
可选的，氧化所述半导体结构的具体步骤包括：
用氧化性液体处理所述半导体结构，所述氧化性液体至少填充满所述沟槽；
所述氧化性液体为臭氧水或者氨水与双氧水的混合溶液。
可选的，用氧化性液体处理所述半导体结构的具体步骤包括：
向旋转的所述半导体结构表面喷射所述氧化性液体，浸润所述半导体结构。
可选的，所述氧化层的厚度为
Figure PCTCN2021079971-appb-000001
可选的，去除所述过渡层的具体步骤包括：
采用氟化氢和氨气的混合气体作为刻蚀气体，去除所述过渡层。
可选的，氟化氢和氨气的混合气体作为刻蚀气体刻蚀掉的所述过渡层与所述基底的总厚度为1nm～10nm。
可选的，氟化氢与氨气的流量比为(1～2):1。
可选的，干燥所述半导体结构的具体步骤包括：
用预设温度的异丙醇处理所述半导体结构，以去除所述半导体结构表面区域的水分。
可选的，去除所述过渡层之后，还包括如下步骤：
气体吹扫所述半导体结构。
本申请提供的半导体结构的处理方法，在刻蚀结构的内壁形成了用于减少流体对刻蚀结构毛细管力的过渡层，使得后续在对刻蚀结构进行干燥的过程中，减少了刻蚀结构出现坍塌或变形的概率；同时，在干燥之后除去覆盖于所述刻蚀结构内壁的所述过渡层，刻蚀结构图形间的吸引力被打断，使得在前序干燥工艺中出现变形的所述刻蚀结构恢复至未变形的状态，从而进一步减少了刻蚀结构出现坍塌或变形的概率，改善了半导体结构的性能，提高了半导体器件的产率和良率。
附图说明
附图1是本申请具体实施方式中半导体结构的处理方法流程图；
附图2A-2F是本申请具体实施方式中一半导体结构在处理过程中的主要工艺示意图；
附图3A-3E是本申请具体实施方式中另一半导体结构在处理过程中的主工艺示意图；
附图4A-4H是本申请具体实施方式中一半导体结构在处理过程中处理腔室截面示意图。
具体实施方式
下面结合附图对本申请提供的半导体结构的处理方法的具体实施方式做详细说明。
本具体实施方式提供了一种半导体结构的处理方法，附图1是本申请具体实施方式中半导体结构的处理方法流程图，附图2A-2F是本申请具体实施方式中一半导体结构在处理过程中的主要工艺示意图，附图4A-4H是本申请具体实施方式中一半导体结构在处理过程中处理腔室截面示意图。如图1、图2A-图2F和图4A-图4H所示，本具体实施方式提供的半导体结构的处理方法，包括如下步骤：
步骤S11，提供一半导体结构，所述半导体结构包括基底20以及位于所述基底20表面区域的若干个刻蚀结构22，如图2A所示。
在本具体实施方式中，所述刻蚀结构22可以是通过干法刻蚀等工艺于所述基底20中形成的任何结构。可选的，所述刻蚀结构为沟槽，且位于所述基 底的表面区域的所述沟槽的数量为多个；
所述沟槽的深度H与所述沟槽的最小宽度W之间的比值大于8。
可选的，多个所述沟槽平行排列于所述基底20的表面区域；
相邻所述沟槽之间的图形线宽D小于20nm。
具体来说，所述刻蚀结构22可以为自所述基底20的表面沿垂直于所述基底20的方向(即图2A中的Y轴方向)向所述基底20内部延伸的沟槽，例如STI。由于在半导体制程工艺中，具有高深宽比的所述沟槽在清洗过程中更易出现坍塌或变形，本具体实施方式提供的所述半导体结构的处理方法对防止具有高深宽比的沟槽在清洗过程中出现坍塌或变形的效果更为显著。在图2A中示出了5个沟槽平行排列于所述基底20的表面区域(即图2A中的X轴方向)的情况，在实际使用过程中，沟槽的具体数量本领域技术人员可以根据实际需要进行选择。多个所述沟槽的深宽比可以相同，也可以不同。本具体实施方式中所述的“多个”是指两个以上。
可选的，提供一半导体结构包括如下步骤：
提供基底20；
刻蚀所述基底20，于所述基底20的表面区域形成多个所述沟槽，所述沟槽底部延伸至基底20内部，以形成所述半导体结构；
清洁所述半导体结构，除去刻蚀形成所述沟槽之后的杂质。
可选的，清洁所述半导体结构的具体步骤包括：
采用等离子体灰化工艺处理所述半导体结构，除去刻蚀形成所述沟槽之后的聚合物残留；
采用湿法清洗工艺处理所述半导体结构，除去刻蚀以及灰化过程之后的副产物和污染物。
可选的，采用等离子体灰化工艺处理所述半导体结构的具体步骤包括：
用等离子体化的氧气对所述半导体结构表面进行灰化处理，以去除在刻蚀形成所述沟槽之后的所述聚合物残留。
可选的，用等离子体化的氧气对所述半导体结构表面进行灰化处理的具体步骤包括：
同时通入等离子体化的氧气和由氢气和氮气构成的混合气体，且通入的所 述氧气的流量与通入的所述混合气体的流量比为10:1。在由氢气和氮气构成的所述混合气体中所述氢气的体积比为4％。
具体来说，所述基底20表面具有掩膜层，例如图2A中覆盖于所述基底20表面的第一掩膜层211和覆盖于所述第一掩膜层211表面的第二掩膜层212，所述掩膜层中具有掩膜图形，在采用干法刻蚀工艺或者其他刻蚀工艺沿所述掩膜层中的所述掩膜图形刻蚀所述基底20、以形成所述沟槽之后，会在所述沟槽内部残留一些聚合物，即所述聚合物残留。由于刻蚀剂与所述基底20之间的刻蚀反应，还会生成一些副产物和污染物。为了避免对后续工艺造成不良影响，本具体实施方式在完成所述沟槽的刻蚀之后，先采用等离子体灰化工艺除去所述聚合物残留，然后再采用湿法清洗工艺除去所述副产物和污染物，以确保所述沟槽内部及所述基底表面的清洁。所述第一掩膜层211的材料可以为氧化硅，所述第二掩膜层212的材料可以为氮化硅。
在等离子体灰化工艺中，氧气的流速为5000ml/min～30000ml/min，由氢气和氮气构成的混合气体(氢气的体积比为4％)的流速为500ml/min～3000ml/min，工艺温度为100℃～500℃，工艺持续时间为10秒～120秒，处理腔室内的压力为200mtorr～5000mtorr，射频功率为1000W～10000W。在湿法清洗工艺中，清洗剂可以为经稀释的HF(DHF,dilute HF)，其中，HF(49％HF液态)与去离子水的体积比为1:(1～1000)，工艺持续时间为5秒～600秒，工艺温度为15℃～60℃，支撑台转速为100rpm～3000rpm。
举例来说，在完成所述沟槽的刻蚀之后，将具有所述沟槽的所述基底20置于如图4A所示的处理腔室40内的支撑台41上，在等离子体灰化过程中，喷淋头42以13000ml/min的流速传输等离子体化的氧气至所述基底20、并同时以1300ml/min的流速传输等离子体化的所述混合气体(由氢气和氮气构成，且氢气的体积比为4％)至所述基底，并保持所述处理腔室40内的温度为250℃、压力为1200mtorr，射频功率(RF)为4400W，制程持续时间为21秒。在完成等离体子灰化工艺之后，进行湿法清洗的过程中，如图4B所示，采用DHF(1:200)作为清洗剂，通过喷淋头42将所述清洗剂喷射至所述基底20表面，同时，所述支撑台41以1500rpm的转速转动，制程温度为室温，制程持续时间为130秒。
步骤S12，形成至少覆盖所述刻蚀结构22内壁的过渡层24，所述过渡层24用于减少流体对所述刻蚀结构22的毛细管力，如图2C所示。
可选的，形成至少覆盖所述刻蚀结构22内壁的过渡层24的具体步骤包括：
氧化所述半导体结构，形成至少覆盖所述沟槽内壁的氧化层，所述氧化层即为所述过渡层24。
可选的，氧化所述半导体结构的具体步骤包括：
用氧化性液体处理所述半导体结构，所述氧化性液体至少填充满所述沟槽，如图2B所示；
所述氧化性液体为臭氧去离子水溶液(DIO 3)或者为氨水与双氧水的混合溶液(即APM溶液)。
可选的，用氧化性液体处理所述半导体结构的具体步骤包括：
向旋转的所述半导体结构表面喷射所述氧化性液体，浸润所述半导体结构。
可选的，所述氧化层的厚度为
Figure PCTCN2021079971-appb-000002
具体来说，在完成所述半导体结构的清洁之后，还可以如图4C所示，通过所述喷淋头42向所述基底20喷射臭氧去离子水溶液或者APM溶液，同时，所述支撑台保持旋转。例如，当所述氧化性液体为臭氧去离子水溶液时，O 3混入去离子水的流速为1L/min～10L/min，臭氧去离子水溶液的流速为1L/min～10L/min，工艺温度为5℃～35℃，工艺持续时间为6秒～1800秒，支撑台转速为100rpm～1200rpm，形成的所述氧化层的厚度为
Figure PCTCN2021079971-appb-000003
当所述氧化性液体为APM溶液时，APM溶液中NH 4OH、H 2O 2、H 2O的体积比为NH 4OH:H 2O 2:H 2O＝1:(1～10):(10～200)，例如：NH 4OH:H 2O 2:H 2O＝1:7:58，工艺温度为20℃～65℃，工艺持续时间为10秒～600秒，APM溶液的流速和支撑台转速等工艺条件可以与臭氧去离子水溶液作为氧化性溶液时的条件相同，形成的所述氧化层的厚度为
Figure PCTCN2021079971-appb-000004
本领域技术人员可以通过调整工艺条件来调整生成的所述过渡层24的厚度。
当所述基底20的材料为硅时，所述过渡层24的材料为二氧化硅。所述过渡层24的形成，可以避免所述半导体结构在后续需要进行半导体浸润(rinse)的工艺中，以所述过渡层24作为硅与流体之间的界面层，从而增强所述沟槽 对流体张力的抵抗力，即减小流体对所述沟槽的毛细管力，从而实现对所述沟槽等图案结构的保护。另外，所述过渡层24(例如氧化层)的生成还会改变所述半导体结构的疏水性，从而可以降低硅表面对颗粒物所产生的范德华力，从而更加有利于沟槽等刻蚀结构内部颗粒物的去除。
步骤S13，干燥所述半导体结构，如图2D所示。
可选的，干燥所述半导体结构的具体步骤包括：
用预设温度的异丙醇处理所述半导体结构，以去除所述半导体结构表面区域的水分。
具体来说，如图4D所示，以热的异丙醇(Hot-IPA)作为干燥流体，热的异丙醇一方面能够置换所述半导体结构表面区域的水分，另一方面还有助于进一步降低表面张力。通过所述喷淋头42将所述干燥流体喷射至所述半导体结构表面，同时向所述处理腔室内部通入氮气作为吹扫气体，以将所述异丙醇通过所述处理腔室的排气口及时抽走，实现所述半导体结构的干燥。其中，所述异丙醇的流速为50ml/min～500ml/min，工艺温度为40℃～80℃，工艺持续时间为10秒～600秒，支撑台转速为100rpm～4000rpm。所述预设温度为40℃～80℃，例如60℃。
步骤S14，去除所述过渡层24，如图2F所示。
在干燥过程中，由于受到晶圆表面膜层的表面能影响，会释放静电摩擦力和/或受到分子间相互吸引力，而所述刻蚀结构的顶部相较于其底部更加脆弱，所述刻蚀结构在上述作用力的影响下易在顶部出现倾斜现象，如图2D的虚线框中所示。然而，在弹性极限内，所述过渡层24被去除之后，刻蚀结构之间的吸引力被打断，刻蚀图案在恢复力的作用下会弹开，以恢复到未变形的状态，如图2F所示。
可选的，去除所述过渡层24的具体步骤包括：
采用氟化氢(99.999％HF气态)和氨气的混合气体作为刻蚀气体，去除所述过渡层24。
可选的，氟化氢和氨气的混合气体作为刻蚀气体刻蚀掉的所述过渡层24与所述基底20的总厚度为1nm～10nm。
可选的，氟化氢与氨气的流量比为(1～2):1。
具体来说，如图4E、4F所示，向所述处理腔室同时通入HF和NH 3，采用蒸气刻蚀的方法去除所述过渡层24。以所述过渡层24的材料为二氧化硅为例，在采用HF和NH 3刻蚀所述二氧化硅的过程中，发生的化学反应如图2E所示。在去除所述过渡层的过程中，反应过程中产的废气通过所述处理腔室底部的排气口及时抽走，如图4E、4F中的箭头所示。在刻蚀所述过渡层24的过程中，HF与NH 3的流量比为(1～2):1，HF与NH 3的流速均为10sccm～300sccm(例如25sccm)，工艺温度为20℃～150℃(例如130℃)，工艺持续时间为1秒～60秒，处理腔室内的压力为1mtorr～5000mtorr，支撑台温度为20℃～150℃(例如35℃)。本步骤中对所述过渡层24进行过刻蚀，以充分去除所述过渡层，使得在异丙醇干燥过程中发生形变的所述刻蚀结构能够最大限度的恢复。其中，刻蚀掉的所述过渡层24的厚度可以为1nm～10nm。在本步骤去除所述过渡层24的过程中，也可以采取交替、循环通入NH 3/HF和N 2的工艺，例如第一阶段通入HF和NH 3、第二阶段通入N 2、第三阶段再次通入HF和NH 3、第四阶段通入N 2……，如此循环交替进行。
可选的，去除所述过渡层24之后，还包括如下步骤：
气体吹扫所述半导体结构，如图4G和4H所示。
具体来说，在刻蚀所述过渡层24的工艺结束之后，一方面，采用所述支撑台内部的加热器43对所述基底20加热，以将刻蚀反应中的产物蒸发；另一方面，向所述处理腔室内通入氮气并持续对所述处理腔室抽气，将刻蚀反应的残留物及时排出所述处理腔室；最后利用氮气继续净化所述处理腔室，如图4G所示，直至所述支撑台停止旋转、完成整个湿法清洗过程，如图4H所示。在对所述半导体结构进行气体吹扫的过程中，氮气的流速为200sccm～10000sccm(例如2000sccm)，工艺温度为90℃～250℃(例如95℃)，工艺持续时间为20秒～600秒(例如120秒)，处理腔室内的压力为200mtorr～10000mtorr(例如2000mtorr)。
采用本具体实施方式提供的半导体结构的处理方法，当所述沟槽的深度H为300nm或310nm时，清洗结束之后发生图案坍塌或变形的情况均小于2％。
图2A-图2F示出了对通过掩膜层形成刻蚀结构的半导体结构的处理方法。在其他具体实施方式中，在处理过程中，所述基底20表面也可以没有掩膜层。 附图3A-3E是本申请具体实施方式中另一半导体结构在处理过程中的主工艺示意图，即图3A-图3E示出了对基底表面没有掩膜层的半导体结构进行处理的示意图。其工艺步骤以及每一工艺步骤实施过程中的工艺条件，可以与图2A-图2F以及图4A-图4H所示的条件相同。
本具体实施方式提供的半导体结构的处理方法，在刻蚀结构的内壁形成了用于减少流体对刻蚀结构毛细管力的过渡层，使得后续在对刻蚀结构进行干燥的过程中，减少了刻蚀结构出现坍塌或变形的概率；同时，在干燥之后除去覆盖于所述刻蚀结构内壁的所述过渡层，刻蚀结构图形间的吸引力被打断，使得在前序干燥工艺中出现变形的所述刻蚀结构恢复至未变形的状态，从而进一步减少了刻蚀结构出现坍塌或变形的概率，改善了半导体结构的性能，提高了半导体器件的产率和良率。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (15)

  1. 一种半导体结构的处理方法，包括如下步骤：
    提供一半导体结构，所述半导体结构包括基底以及位于所述基底表面区域的若干个刻蚀结构；
    形成至少覆盖所述刻蚀结构内壁的过渡层，所述过渡层用于减少流体对所述刻蚀结构的毛细管力及当作修复倒塌结构的牺牲层；
    干燥所述半导体结构；
    去除所述过渡层。
  2. 根据权利要求1所述的半导体结构的处理方法，其中，所述刻蚀结构为沟槽，且位于所述基底的表面区域的所述沟槽的数量为多个；
    所述沟槽的深度与所述沟槽的最小宽度之间的比值大于8。
  3. 根据权利要求2所述的半导体结构的处理方法，其中，多个所述沟槽平行排列于所述基底的表面区域；
    相邻所述沟槽之间的图形线宽小于20nm。
  4. 根据权利要求2所述的半导体结构的处理方法，其中，提供一半导体结构具体包括如下步骤：
    提供基底；
    刻蚀所述基底，于所述基底的表面区域形成多个所述沟槽，所述沟槽底部延伸至基底内部，以形成所述半导体结构；
    清洁所述半导体结构，除去刻蚀形成所述沟槽之后的杂质。
  5. 根据权利要求4所述的半导体结构的处理方法，其中，清洁所述半导体结构的具体步骤包括：
    采用等离子体灰化工艺处理所述半导体结构，除去刻蚀形成所述沟槽之后的聚合物残留；
    采用湿法清洗工艺处理所述半导体结构，除去刻蚀以及灰化过程之后的副产物和污染物。
  6. 根据权利要求5所述的半导体结构的处理方法，其中，采用等离子体灰化工艺处理所述半导体结构的具体步骤包括：
    用等离子体化的氧气对所述半导体结构表面进行灰化处理，以去除在刻蚀形成所述沟槽之后的所述聚合物残留。
  7. 根据权利要求2所述的半导体结构的处理方法，其中，形成至少覆盖所述刻蚀结构内壁的过渡层的具体步骤包括：
    氧化所述半导体结构，形成至少覆盖所述沟槽内壁的氧化层，所述氧化层即为所述过渡层。
  8. 根据权利要求7所述的半导体结构的处理方法，其中，氧化所述半导体结构的具体步骤包括：
    用氧化性液体处理所述半导体结构，所述氧化性液体至少填充满所述沟槽；
    所述氧化性液体为臭氧去离子水溶液或者为氨水与双氧水的混合溶液。
  9. 根据权利要求8所述的半导体结构的处理方法，其中，用氧化性液体处理所述半导体结构的具体步骤包括：
    向旋转的所述半导体结构表面喷射所述氧化性液体，浸润所述半导体结构。
  10. 根据权利要求7所述的半导体结构的处理方法，其中，所述氧化层的厚度为
    Figure PCTCN2021079971-appb-100001
  11. 根据权利要求7所述的半导体结构的处理方法，其中，去除所述过渡层的具体步骤包括：
    采用氟化氢和氨气的混合气体作为刻蚀气体，去除所述过渡层。
  12. 根据权利要求11所述的半导体结构的处理方法，其中，氟化氢和氨气的混合气体作为刻蚀气体刻蚀去除的所述过渡层与所述基底的总厚度为1nm～10nm。
  13. 根据权利要求11所述的半导体结构的处理方法，其中，氟化氢与氨气的流量比为(1～2):1。
  14. 根据权利要求2所述的半导体结构的处理方法，其中，干燥所述半导体结构的具体步骤包括：
    用预设温度的异丙醇处理所述半导体结构，以去除所述半导体结构表面区域的水分。
  15. 根据权利要求1所述的半导体结构的处理方法，其中，去除所述过渡层之 后，还包括如下步骤：
    气体吹扫所述半导体结构。
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