WO2021180121A1 - 半导体结构的处理方法 - Google Patents
半导体结构的处理方法 Download PDFInfo
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- WO2021180121A1 WO2021180121A1 PCT/CN2021/079971 CN2021079971W WO2021180121A1 WO 2021180121 A1 WO2021180121 A1 WO 2021180121A1 CN 2021079971 W CN2021079971 W CN 2021079971W WO 2021180121 A1 WO2021180121 A1 WO 2021180121A1
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- semiconductor structure
- etching
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- transition layer
- substrate
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 134
- 238000000034 method Methods 0.000 title claims abstract description 101
- 230000008569 process Effects 0.000 claims abstract description 72
- 238000005530 etching Methods 0.000 claims abstract description 58
- 230000007704 transition Effects 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000004140 cleaning Methods 0.000 claims abstract description 27
- 238000001035 drying Methods 0.000 claims abstract description 21
- 239000012530 fluid Substances 0.000 claims abstract description 12
- 239000007789 gas Substances 0.000 claims description 26
- 230000001590 oxidative effect Effects 0.000 claims description 21
- 239000007788 liquid Substances 0.000 claims description 20
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 19
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 16
- 238000004380 ashing Methods 0.000 claims description 16
- 238000003672 processing method Methods 0.000 claims description 11
- 229920000642 polymer Polymers 0.000 claims description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 9
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 9
- 229910021529 ammonia Inorganic materials 0.000 claims description 8
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 7
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- 239000007864 aqueous solution Substances 0.000 claims description 6
- 239000006227 byproduct Substances 0.000 claims description 6
- 239000000356 contaminant Substances 0.000 claims description 5
- 238000010926 purge Methods 0.000 claims description 5
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 3
- 229910001882 dioxygen Inorganic materials 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 19
- 239000001257 hydrogen Substances 0.000 description 11
- 229910052739 hydrogen Inorganic materials 0.000 description 11
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 10
- 229910052757 nitrogen Inorganic materials 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 239000000243 solution Substances 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000012459 cleaning agent Substances 0.000 description 3
- 239000008367 deionised water Substances 0.000 description 3
- 229910021641 deionized water Inorganic materials 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000005411 Van der Waals force Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000003607 modifier Substances 0.000 description 2
- 239000013618 particulate matter Substances 0.000 description 2
- 230000003075 superhydrophobic effect Effects 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
Definitions
- This application relates to the field of semiconductor manufacturing technology, and in particular to a processing method of a semiconductor structure.
- HAR high-aspect-ratio
- the semiconductor structure such as DRAM completes the etching process of the trench and other patterns
- the pattern may collapse or deform due to capillary force.
- the fluid tension that may appear in the semiconductor structure is greater.
- the first is Laplace pressure
- the second is adhesion
- the third is electrostatic force, van der Waals force and hydrogen bonding.
- the surface effect of the cleaning liquid has become the main factor that affects the quality of the process. factor.
- the capillary force acting on the pattern structure may cause the pattern to collapse.
- this treatment method will lead to the appearance of other negative effects, such as the super-hydrophobic effect of the HAR structure.
- This super-hydrophobic effect prevents the aqueous solution from penetrating between the structures, resulting in a decrease in the effectiveness of wet cleaning.
- adding a surface modifier before the drying process after cleaning can effectively prevent the pattern from collapsing, but the surface modifier may remain at the bottom of the STI structure, which may cause abnormalities in the semiconductor device.
- the present application provides a processing method of a semiconductor structure, which is used to solve the problem of pattern collapse and deformation of the semiconductor structure during the cleaning process, so as to improve the performance of the semiconductor structure and increase the yield of the semiconductor device.
- the present application provides a method for processing a semiconductor structure, which includes the following steps:
- the semiconductor structure including a substrate and a plurality of etching structures located on a surface area of the substrate;
- transition layer covering at least the inner wall of the etching structure, the transition layer being used to reduce the capillary force of the fluid on the etching structure and as a sacrificial layer for repairing the collapsed structure;
- the etching structure is a trench, and the number of the trenches located on the surface area of the substrate is multiple;
- the ratio between the depth of the groove and the minimum width of the groove is greater than 8.
- a plurality of the grooves are arranged in parallel on the surface area of the substrate;
- the pattern line width between adjacent grooves is less than 20 nm.
- providing a semiconductor structure specifically includes the following steps:
- the specific steps of cleaning the semiconductor structure include:
- the semiconductor structure is treated with a wet cleaning process to remove by-products and contaminants after the etching and ashing process.
- the specific steps of using a plasma ashing process to process the semiconductor structure include:
- the surface of the semiconductor structure is ashing treated with plasma oxygen gas to remove the polymer residue after etching to form the trench.
- the ratio of the flow rate of the oxygen to the flow rate of the mixed gas of hydrogen and nitrogen is 10:1, and the volume ratio of the hydrogen in the mixed gas of hydrogen and nitrogen is 4%.
- the specific steps of forming a transition layer covering at least the inner wall of the etching structure include:
- the semiconductor structure is oxidized to form an oxide layer covering at least the inner wall of the trench, and the oxide layer is the transition layer.
- the specific step of oxidizing the semiconductor structure includes:
- the oxidizing liquid is ozone water or a mixed solution of ammonia water and hydrogen peroxide.
- the specific steps of treating the semiconductor structure with an oxidizing liquid include:
- the oxidizing liquid is sprayed to the surface of the rotating semiconductor structure to infiltrate the semiconductor structure.
- the thickness of the oxide layer is
- the specific steps of removing the transition layer include:
- a mixed gas of hydrogen fluoride and ammonia is used as an etching gas to remove the transition layer.
- the total thickness of the transition layer and the substrate etched away by the mixed gas of hydrogen fluoride and ammonia as the etching gas is 1 nm-10 nm.
- the flow ratio of hydrogen fluoride to ammonia gas is (1-2):1.
- the specific step of drying the semiconductor structure includes:
- the semiconductor structure is treated with isopropanol at a preset temperature to remove moisture in the surface area of the semiconductor structure.
- the method further includes the following steps:
- a transition layer is formed on the inner wall of the etched structure to reduce the capillary force of the fluid on the etched structure, so that the subsequent drying of the etched structure reduces the number of etched structures.
- the etched structure is restored to an undeformed state, thereby further reducing the probability of collapse or deformation of the etched structure, improving the performance of the semiconductor structure, and increasing the yield and yield of semiconductor devices.
- FIG. 1 is a flowchart of a processing method of a semiconductor structure in a specific embodiment of the present application
- FIGS. 2A-2F are schematic diagrams of the main processes of a semiconductor structure in the process of the specific implementation of the present application.
- Figs. 3A-3E are schematic diagrams of the main process of another semiconductor structure in the process of the specific embodiment of the present application.
- FIGS. 4A-4H are schematic cross-sectional views of a processing chamber of a semiconductor structure during processing in a specific embodiment of the present application.
- FIG. 1 is a flowchart of a method for processing a semiconductor structure in a specific embodiment of this application.
- Figs. 4A-4H are schematic cross-sectional views of a processing chamber of a semiconductor structure in a specific embodiment of the present application. As shown in FIG. 1, FIG. 2A-FIG. 2F and FIG. 4A-FIG. 4H, the method for processing a semiconductor structure provided in this embodiment includes the following steps:
- a semiconductor structure is provided.
- the semiconductor structure includes a substrate 20 and a plurality of etched structures 22 located on the surface area of the substrate 20, as shown in FIG. 2A.
- the etching structure 22 may be any structure formed in the substrate 20 by a process such as dry etching.
- the etching structure is a trench, and the number of the trenches located on the surface area of the substrate is multiple;
- the ratio between the depth H of the groove and the minimum width W of the groove is greater than 8.
- a plurality of the grooves are arranged in parallel on the surface area of the substrate 20;
- the pattern line width D between adjacent grooves is less than 20 nm.
- the etching structure 22 may be a groove extending from the surface of the substrate 20 in a direction perpendicular to the substrate 20 (ie, the Y-axis direction in FIG. 2A) toward the interior of the substrate 20, for example, STI. Since the trenches with high aspect ratios are more likely to collapse or deform during the cleaning process in the semiconductor manufacturing process, the processing method of the semiconductor structure provided in this embodiment is effective in preventing the trenches with high aspect ratios from being cleaned. The effect of collapse or deformation during the process is more significant.
- five grooves are arranged in parallel on the surface area of the substrate 20 (that is, the X-axis direction in FIG. 2A). In actual use, the specific number of grooves can be determined by those skilled in the art. Choose according to actual needs.
- the aspect ratios of the plurality of grooves may be the same or different.
- the "plurality" in this specific embodiment refers to two or more.
- providing a semiconductor structure includes the following steps:
- the specific steps of cleaning the semiconductor structure include:
- the semiconductor structure is treated with a wet cleaning process to remove by-products and contaminants after the etching and ashing process.
- the specific steps of using a plasma ashing process to process the semiconductor structure include:
- the surface of the semiconductor structure is ashing treated with plasma oxygen gas to remove the polymer residue after etching to form the trench.
- the specific steps of ashing the surface of the semiconductor structure with plasmaized oxygen include:
- plasmaized oxygen and a mixed gas composed of hydrogen and nitrogen are introduced, and the ratio of the flow rate of the introduced oxygen to the flow rate of the mixed gas is 10:1.
- the volume ratio of the hydrogen in the mixed gas composed of hydrogen and nitrogen is 4%.
- the surface of the substrate 20 has a mask layer, such as a first mask layer 211 covering the surface of the substrate 20 and a second mask layer covering the surface of the first mask layer 211 in FIG. 2A 212.
- the mask layer has a mask pattern, and the substrate 20 is etched along the mask pattern in the mask layer by a dry etching process or other etching processes to form the grooves. After the groove, some polymer will remain inside the groove, that is, the polymer remains. Due to the etching reaction between the etchant and the substrate 20, some by-products and contaminants may also be generated.
- a plasma ashing process is first used to remove the polymer residue, and then a wet cleaning process is used to remove the by-products. And contaminants to ensure the cleanliness of the inside of the groove and the surface of the substrate.
- the material of the first mask layer 211 may be silicon oxide, and the material of the second mask layer 212 may be silicon nitride.
- the flow rate of oxygen is 5000ml/min ⁇ 30000ml/min
- the flow rate of the mixed gas composed of hydrogen and nitrogen (the volume ratio of hydrogen is 4%) is 500ml/min ⁇ 3000ml/min
- the process temperature The temperature is 100°C to 500°C
- the process duration is 10 seconds to 120 seconds
- the pressure in the processing chamber is 200 mtorr to 5000 mtorr
- the radio frequency power is 1000W to 10000W.
- the cleaning agent can be diluted HF (DHF), where the volume ratio of HF (49% HF liquid) to deionized water is 1:(1 ⁇ 1000), and the process duration It is 5 seconds to 600 seconds, the process temperature is 15°C to 60°C, and the rotation speed of the support table is 100rpm to 3000rpm.
- DHF diluted HF
- the substrate 20 with the trench is placed on the support table 41 in the processing chamber 40 as shown in FIG.
- the shower head 42 transmits plasmaized oxygen to the substrate 20 at a flow rate of 13000ml/min, and simultaneously transmits the plasmaized mixed gas (consisting of hydrogen and nitrogen, and at a flow rate of 1300ml/min).
- the volume ratio of hydrogen is 4%) to the substrate, and the temperature in the processing chamber 40 is 250° C., the pressure is 1200 mtorr, the radio frequency power (RF) is 4400 W, and the process duration is 21 seconds.
- DHF (1:200) is used as the cleaning agent, and the cleaning agent is sprayed to the On the surface of the substrate 20, at the same time, the supporting table 41 rotates at a speed of 1500 rpm, the process temperature is room temperature, and the process duration is 130 seconds.
- step S12 a transition layer 24 covering at least the inner wall of the etching structure 22 is formed, and the transition layer 24 is used to reduce the capillary force of the fluid on the etching structure 22, as shown in FIG. 2C.
- the specific steps of forming the transition layer 24 covering at least the inner wall of the etching structure 22 include:
- the semiconductor structure is oxidized to form an oxide layer covering at least the inner wall of the trench, and the oxide layer is the transition layer 24.
- the specific step of oxidizing the semiconductor structure includes:
- the oxidizing liquid is an ozone deionized aqueous solution (DIO 3 ) or a mixed solution of ammonia and hydrogen peroxide (ie, APM solution).
- DIO 3 ozone deionized aqueous solution
- APM solution a mixed solution of ammonia and hydrogen peroxide
- the specific steps of treating the semiconductor structure with an oxidizing liquid include:
- the oxidizing liquid is sprayed to the surface of the rotating semiconductor structure to infiltrate the semiconductor structure.
- the thickness of the oxide layer is
- an ozone deionized aqueous solution or an APM solution may be sprayed to the substrate 20 through the shower head 42, while the support platform maintains Spin.
- the oxidizing liquid is an ozone deionized aqueous solution
- the flow rate of O 3 mixed into the deionized water is 1L/min-10L/min
- the flow rate of the ozone deionized aqueous solution is 1L/min-10L/min
- the process temperature is 5°C to 35°C
- the process duration is 6 seconds to 1800 seconds
- the rotating speed of the support table is 100 rpm to 1200 rpm
- the thickness of the formed oxide layer is
- the oxidizing liquid is a solution of APM
- APM solution of NH 4 OH, H 2 O 2 , H 2 O volume ratio of NH 4 OH: H 2 O 2 : H 2 O 1: (1 ⁇ 10) :(10 ⁇ 200)
- the material of the transition layer 24 is silicon dioxide.
- the formation of the transition layer 24 can prevent the semiconductor structure from using the transition layer 24 as the interface layer between the silicon and the fluid during the subsequent semiconductor rinsing process, thereby enhancing the trench pairing.
- the resistance of the fluid tension is to reduce the capillary force of the fluid to the groove, thereby realizing the protection of the pattern structure such as the groove.
- the formation of the transition layer 24 (such as an oxide layer) will also change the hydrophobicity of the semiconductor structure, thereby reducing the van der Waals force generated by the silicon surface on the particulate matter, which is more conducive to the etching of the particulate matter in the trench and other structures. Removal.
- Step S13 drying the semiconductor structure, as shown in FIG. 2D.
- the specific step of drying the semiconductor structure includes:
- the semiconductor structure is treated with isopropanol at a preset temperature to remove moisture in the surface area of the semiconductor structure.
- hot isopropanol (Hot-IPA) is used as the drying fluid.
- hot isopropanol can replace the moisture in the surface area of the semiconductor structure, and on the other hand, it can also help Further reduce surface tension.
- the drying fluid is sprayed onto the surface of the semiconductor structure through the shower head 42, and at the same time, nitrogen is introduced into the processing chamber as a purge gas to pass the isopropanol through the surface of the processing chamber.
- the exhaust port is removed in time to achieve the drying of the semiconductor structure.
- the flow rate of the isopropanol is 50ml/min ⁇ 500ml/min
- the process temperature is 40°C ⁇ 80°C
- the process duration is 10 seconds ⁇ 600 seconds
- the rotation speed of the support table is 100rpm ⁇ 4000rpm.
- the preset temperature is 40°C to 80°C, for example 60°C.
- step S14 the transition layer 24 is removed, as shown in FIG. 2F.
- the specific steps of removing the transition layer 24 include:
- a mixed gas of hydrogen fluoride (99.999% HF gas) and ammonia is used as an etching gas to remove the transition layer 24.
- the total thickness of the transition layer 24 and the substrate 20 etched away by the mixed gas of hydrogen fluoride and ammonia as the etching gas is 1 nm-10 nm.
- the flow ratio of hydrogen fluoride to ammonia gas is (1-2):1.
- HF and NH 3 are simultaneously introduced into the processing chamber, and the transition layer 24 is removed by a vapor etching method.
- silicon dioxide as the material of the transition layer 24 as an example
- the chemical reaction that occurs during the etching of the silicon dioxide by HF and NH 3 is shown in FIG. 2E.
- the exhaust gas produced in the reaction process is drawn away in time through the exhaust port at the bottom of the processing chamber, as shown by the arrows in Figs. 4E and 4F.
- the flow rate ratio of HF and NH 3 is (1-2):1
- the flow rates of HF and NH 3 are both 10 sccm to 300 sccm (for example, 25 sccm)
- the process temperature is 20° C. 150°C (for example, 130°C)
- the process duration is 1 second to 60 seconds
- the pressure in the processing chamber is 1 mtorr to 5000 mtorr
- the support table temperature is 20°C to 150°C (for example, 35°C).
- the transition layer 24 is over-etched to fully remove the transition layer, so that the etched structure deformed during the isopropanol drying process can be restored to the greatest extent.
- the thickness of the transition layer 24 that is etched away may be 1 nm-10 nm.
- a process of alternately and cyclically passing NH 3 /HF and N 2 may also be adopted, such as passing HF and NH 3 in the first stage, and passing N 2 in the second stage.
- HF and NH 3 are introduced again, and in the fourth stage, N 2 is introduced , and so on alternately.
- the method further includes the following steps:
- the heater 43 inside the support table is used to heat the substrate 20 to evaporate the products in the etching reaction; on the other hand, , the nitrogen gas is introduced into the processing chamber and the processing chamber is continuously evacuated, so that the residue of the etching reaction is discharged from the processing chamber in time; finally, the processing chamber is continued to be purged with nitrogen, as shown in FIG. 4G As shown, until the support table stops rotating, the entire wet cleaning process is completed, as shown in FIG. 4H.
- the flow rate of nitrogen is 200 sccm to 10000 sccm (for example, 2000 sccm)
- the process temperature is 90 to 250° C. (for example, 95° C.)
- the process duration is 20 seconds to 600 seconds ( For example, 120 seconds)
- the pressure in the processing chamber is 200 mtorr to 10000 mtorr (for example, 2000 mtorr).
- the pattern collapse or deformation after the cleaning is completed is less than 2%.
- FIGS. 3A-3E are schematic diagrams of the main process of another semiconductor structure during processing in the specific embodiment of the present application, that is, FIGS. 3A-3E show schematic diagrams of processing a semiconductor structure without a mask layer on the surface of the substrate.
- the process steps and the process conditions during the implementation of each process step can be the same as the conditions shown in FIGS. 2A to 2F and FIGS. 4A to 4H.
- a transition layer is formed on the inner wall of the etched structure to reduce the capillary force of the fluid on the etched structure, so that the subsequent drying of the etched structure reduces the amount of etching.
- the probability of collapse or deformation of the etched structure at the same time, the transition layer covering the inner wall of the etched structure is removed after drying, and the attraction between the patterns of the etched structure is interrupted, causing deformation in the pre-drying process
- the etched structure is restored to an undeformed state, thereby further reducing the probability of collapse or deformation of the etched structure, improving the performance of the semiconductor structure, and increasing the yield and yield of semiconductor devices.
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Abstract
Description
Claims (15)
- 一种半导体结构的处理方法,包括如下步骤:提供一半导体结构,所述半导体结构包括基底以及位于所述基底表面区域的若干个刻蚀结构;形成至少覆盖所述刻蚀结构内壁的过渡层,所述过渡层用于减少流体对所述刻蚀结构的毛细管力及当作修复倒塌结构的牺牲层;干燥所述半导体结构;去除所述过渡层。
- 根据权利要求1所述的半导体结构的处理方法,其中,所述刻蚀结构为沟槽,且位于所述基底的表面区域的所述沟槽的数量为多个;所述沟槽的深度与所述沟槽的最小宽度之间的比值大于8。
- 根据权利要求2所述的半导体结构的处理方法,其中,多个所述沟槽平行排列于所述基底的表面区域;相邻所述沟槽之间的图形线宽小于20nm。
- 根据权利要求2所述的半导体结构的处理方法,其中,提供一半导体结构具体包括如下步骤:提供基底;刻蚀所述基底,于所述基底的表面区域形成多个所述沟槽,所述沟槽底部延伸至基底内部,以形成所述半导体结构;清洁所述半导体结构,除去刻蚀形成所述沟槽之后的杂质。
- 根据权利要求4所述的半导体结构的处理方法,其中,清洁所述半导体结构的具体步骤包括:采用等离子体灰化工艺处理所述半导体结构,除去刻蚀形成所述沟槽之后的聚合物残留;采用湿法清洗工艺处理所述半导体结构,除去刻蚀以及灰化过程之后的副产物和污染物。
- 根据权利要求5所述的半导体结构的处理方法,其中,采用等离子体灰化工艺处理所述半导体结构的具体步骤包括:用等离子体化的氧气对所述半导体结构表面进行灰化处理,以去除在刻蚀形成所述沟槽之后的所述聚合物残留。
- 根据权利要求2所述的半导体结构的处理方法,其中,形成至少覆盖所述刻蚀结构内壁的过渡层的具体步骤包括:氧化所述半导体结构,形成至少覆盖所述沟槽内壁的氧化层,所述氧化层即为所述过渡层。
- 根据权利要求7所述的半导体结构的处理方法,其中,氧化所述半导体结构的具体步骤包括:用氧化性液体处理所述半导体结构,所述氧化性液体至少填充满所述沟槽;所述氧化性液体为臭氧去离子水溶液或者为氨水与双氧水的混合溶液。
- 根据权利要求8所述的半导体结构的处理方法,其中,用氧化性液体处理所述半导体结构的具体步骤包括:向旋转的所述半导体结构表面喷射所述氧化性液体,浸润所述半导体结构。
- 根据权利要求7所述的半导体结构的处理方法,其中,去除所述过渡层的具体步骤包括:采用氟化氢和氨气的混合气体作为刻蚀气体,去除所述过渡层。
- 根据权利要求11所述的半导体结构的处理方法,其中,氟化氢和氨气的混合气体作为刻蚀气体刻蚀去除的所述过渡层与所述基底的总厚度为1nm~10nm。
- 根据权利要求11所述的半导体结构的处理方法,其中,氟化氢与氨气的流量比为(1~2):1。
- 根据权利要求2所述的半导体结构的处理方法,其中,干燥所述半导体结构的具体步骤包括:用预设温度的异丙醇处理所述半导体结构,以去除所述半导体结构表面区域的水分。
- 根据权利要求1所述的半导体结构的处理方法,其中,去除所述过渡层之 后,还包括如下步骤:气体吹扫所述半导体结构。
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JP2022540435A JP2023508553A (ja) | 2020-03-11 | 2021-03-10 | 半導体構造の処理方法 |
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100122711A1 (en) * | 2008-11-14 | 2010-05-20 | Advanced Micro Devices, Inc. | wet clean method for semiconductor device fabrication processes |
CN102714155A (zh) * | 2010-01-26 | 2012-10-03 | 朗姆研究公司 | 用于半导体设备的无图案塌陷湿处理的方法和装置 |
CN102741984A (zh) * | 2010-02-01 | 2012-10-17 | 朗姆研究公司 | 在高深宽比纳米结构中减少图案塌陷的方法 |
US20160172433A1 (en) * | 2012-12-21 | 2016-06-16 | SK Hynix Inc. | Surface treatment method for semiconductor device |
CN107068538A (zh) * | 2009-10-28 | 2017-08-18 | 中央硝子株式会社 | 保护膜形成用化学溶液 |
US20190267232A1 (en) * | 2018-02-26 | 2019-08-29 | Micron Technology, Inc. | Using sacrificial polymer materials in semiconductor processing |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5838055A (en) * | 1997-05-29 | 1998-11-17 | International Business Machines Corporation | Trench sidewall patterned by vapor phase etching |
US6258663B1 (en) * | 1998-05-01 | 2001-07-10 | Vanguard International Semiconductor Corporation | Method for forming storage node |
KR100505419B1 (ko) * | 2003-04-23 | 2005-08-04 | 주식회사 하이닉스반도체 | 반도체 소자의 소자분리막 제조방법 |
US20040235299A1 (en) * | 2003-05-22 | 2004-11-25 | Axcelis Technologies, Inc. | Plasma ashing apparatus and endpoint detection process |
JP5229711B2 (ja) * | 2006-12-25 | 2013-07-03 | 国立大学法人名古屋大学 | パターン形成方法、および半導体装置の製造方法 |
US7838425B2 (en) * | 2008-06-16 | 2010-11-23 | Kabushiki Kaisha Toshiba | Method of treating surface of semiconductor substrate |
JP5413016B2 (ja) * | 2008-07-31 | 2014-02-12 | 東京エレクトロン株式会社 | 基板の洗浄方法、基板の洗浄装置及び記憶媒体 |
JP5404361B2 (ja) * | 2009-12-11 | 2014-01-29 | 株式会社東芝 | 半導体基板の表面処理装置及び方法 |
JP5424848B2 (ja) * | 2009-12-15 | 2014-02-26 | 株式会社東芝 | 半導体基板の表面処理装置及び方法 |
JP5678720B2 (ja) * | 2011-02-25 | 2015-03-04 | セントラル硝子株式会社 | ウェハの洗浄方法 |
SG187959A1 (en) * | 2010-08-27 | 2013-03-28 | Advanced Tech Materials | Method for preventing the collapse of high aspect ratio structures during drying |
JP2012084789A (ja) * | 2010-10-14 | 2012-04-26 | Toshiba Corp | 半導体装置の製造方法および半導体製造装置 |
US20120187522A1 (en) * | 2011-01-20 | 2012-07-26 | International Business Machines Corporation | Structure and method for reduction of vt-w effect in high-k metal gate devices |
KR102084073B1 (ko) * | 2012-12-21 | 2020-03-04 | 에스케이하이닉스 주식회사 | 반도체 장치의 표면 처리 방법 |
JP6466315B2 (ja) * | 2015-12-25 | 2019-02-06 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理システム |
JP6966698B2 (ja) * | 2017-02-20 | 2021-11-17 | セントラル硝子株式会社 | 撥水性保護膜形成用薬液 |
US10475656B2 (en) * | 2017-12-19 | 2019-11-12 | Micron Technology, Inc. | Hydrosilylation in semiconductor processing |
JP7077184B2 (ja) * | 2018-08-30 | 2022-05-30 | キオクシア株式会社 | 基板処理方法及び半導体装置の製造方法 |
-
2020
- 2020-03-11 CN CN202010166572.2A patent/CN113394074A/zh active Pending
-
2021
- 2021-03-10 JP JP2022540435A patent/JP2023508553A/ja active Pending
- 2021-03-10 EP EP21768606.2A patent/EP3951837A4/en active Pending
- 2021-03-10 WO PCT/CN2021/079971 patent/WO2021180121A1/zh active Application Filing
- 2021-07-08 US US17/371,027 patent/US20210335594A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100122711A1 (en) * | 2008-11-14 | 2010-05-20 | Advanced Micro Devices, Inc. | wet clean method for semiconductor device fabrication processes |
CN107068538A (zh) * | 2009-10-28 | 2017-08-18 | 中央硝子株式会社 | 保护膜形成用化学溶液 |
CN102714155A (zh) * | 2010-01-26 | 2012-10-03 | 朗姆研究公司 | 用于半导体设备的无图案塌陷湿处理的方法和装置 |
CN102741984A (zh) * | 2010-02-01 | 2012-10-17 | 朗姆研究公司 | 在高深宽比纳米结构中减少图案塌陷的方法 |
US20160172433A1 (en) * | 2012-12-21 | 2016-06-16 | SK Hynix Inc. | Surface treatment method for semiconductor device |
US20190267232A1 (en) * | 2018-02-26 | 2019-08-29 | Micron Technology, Inc. | Using sacrificial polymer materials in semiconductor processing |
Non-Patent Citations (1)
Title |
---|
See also references of EP3951837A4 * |
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JP2023508553A (ja) | 2023-03-02 |
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