WO2021164608A1 - 应用于半导体光刻工艺中的掩膜版及光刻工艺方法 - Google Patents

应用于半导体光刻工艺中的掩膜版及光刻工艺方法 Download PDF

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Publication number
WO2021164608A1
WO2021164608A1 PCT/CN2021/075946 CN2021075946W WO2021164608A1 WO 2021164608 A1 WO2021164608 A1 WO 2021164608A1 CN 2021075946 W CN2021075946 W CN 2021075946W WO 2021164608 A1 WO2021164608 A1 WO 2021164608A1
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Prior art keywords
light
area
mask
pattern
wafer
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PCT/CN2021/075946
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English (en)
French (fr)
Inventor
范聪聪
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长鑫存储技术有限公司
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Priority to US17/426,361 priority Critical patent/US20220317560A1/en
Priority to EP21756231.3A priority patent/EP4109177A4/en
Publication of WO2021164608A1 publication Critical patent/WO2021164608A1/zh

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/54—Absorbers, e.g. of opaque materials
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G03F1/42—Alignment or registration features, e.g. alignment marks on the mask substrates
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70681—Metrology strategies
    • G03F7/70683—Mark designs
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment

Definitions

  • This application relates to the field of semiconductor manufacturing, and in particular to a mask and a photolithography process method used in semiconductor photolithography processes.
  • the photolithography process is mainly to transfer the layout on the mask to the wafer, and then other subsequent processes can be carried out to complete the entire semiconductor. Manufacture of devices. Therefore, the quality of the photolithography process will directly affect the performance of the final semiconductor device.
  • the pattern size may change, the pattern shape changes, or the pattern is not displayed, which affects the performance of the semiconductor device.
  • alignment is one of the most important mechanisms for a lithography system.
  • the alignment accuracy is the positioning accuracy of the pattern between layers during multi-layer exposure.
  • the alignment accuracy is an important indicator of the lithography system in the semiconductor production process.
  • Alignment marks are needed to align.
  • the alignment marks currently used in the SMASH system mainly include DPCM, NSSM11, NSSM53, XPAAA5, BF2u3F, etc.
  • the lithography system can pre-compensate the pattern overlap deviation of some wafers caused by the previous process.
  • the manufacturing process of the alignment mark is to design a mask corresponding to the alignment mark; transfer the pattern on the mask to the wafer through a photolithography system, and then form the alignment mark on the wafer.
  • the pattern can be transferred to the wafer normally.
  • high transmittance masks which are affected by the side-lobe effect
  • after the graphics are transferred to the wafer there may be changes in the pattern size, pattern shape, or even non-existent patterns. Display the situation of the pattern.
  • Abnormal pattern transfer will make it impossible to form standard alignment marks on the wafer, which affects the accuracy of the lithography system, such as alignment accuracy, which in turn leads to a decrease in the accuracy of stacking in subsequent processes, and affects product quality and yield.
  • the technical problem to be solved by this application is to provide a mask and a photolithography process method used in semiconductor photolithography processes, which can form standard independent marks on wafers, improve the performance of the photolithography system, and improve product performance. Quality and yield.
  • the present application provides a mask applied in the semiconductor photolithography process, which includes at least one pattern group, and each of the pattern groups includes at least one light-transmitting area and at least one shielding area.
  • the light-transmitting area and the shielding area are arranged at intervals, and after exposure, each of the pattern groups forms an independent mark on the wafer.
  • the light-transmitting area and the shielding area in the pattern group are both rectangular.
  • the length of the light-transmitting area is the same as the length of the shielding area.
  • the independent mark is a rectangle.
  • width of the light-transmitting area and the width of the shielding area satisfy the following formula:
  • PITCH is the sum of the width of the light-transmitting area and the shielding area
  • ⁇ is the wavelength used in the photolithography process
  • ⁇ is the ratio of the inner and outer diameters of the diffractive optical element used in the photolithography process
  • NA is the ratio used in the photolithography process Numerical aperture.
  • the light transmittance of the shielding area is 0.06 to 0.3 times the light transmittance of the light transmitting area.
  • the light-transmitting areas are arranged in parallel.
  • the light-transmitting area and the shielding area are arranged at intervals along a horizontal direction, a vertical direction, or an acute angle direction with the horizontal direction.
  • the mask includes an alignment pattern area and a chip pattern area, the pattern group is arranged in the alignment pattern area, and the independent mark serves as an alignment mark of the wafer.
  • the alignment marks include alignment marks of the same layer and alignment marks between layers.
  • the present application also provides a photolithography process method, which uses the above-mentioned mask as a mask to form alignment marks on the wafer.
  • the advantage of the present application is that, on the mask, the pattern group is formed by spacing the light-transmitting area and the shielding area.
  • the independent marks formed on the wafer according to the pattern group have the same characteristics as those of the pattern group.
  • the contour shape of the pattern group is the same shape, the independent mark will not have pattern defects, the accuracy of forming the independent mark pattern on the wafer is improved, the alignment accuracy of the photolithography system is improved, and the subsequent semiconductor process is improved
  • the accuracy of stacking improves product quality and yield.
  • Figure 1 is a schematic diagram of the mask pattern used to form the alignment mark and the alignment mark formed by transferring it to the wafer, where (a) is the pattern of the mask and (b) is the final formation on the wafer The alignment mark on the
  • FIG. 2 is a schematic diagram of the first embodiment of the pattern group of the mask of the present application and a schematic diagram of an independent mark formed by using the mask, where (a) is a schematic diagram of the mask, and (b) is Schematic diagram of the independent marks formed on the wafer;
  • FIG. 3 is another schematic diagram of the structure of the mask
  • FIG. 4 is a schematic diagram of a second embodiment of the pattern group of the mask of the present application and a schematic diagram of an independent mark formed by using the mask, wherein (a) is a schematic diagram of the mask, and (b) is an on-chip Graphical schematic diagram of the independent mark formed on the circle;
  • FIG. 5 is a schematic diagram of a third embodiment of the pattern group of the mask of the present application and a schematic diagram of an independent mark formed by using the mask, wherein (a) is a schematic diagram of the mask pattern, (b) is an in-crystal diagram Graphical schematic diagram of the independent mark formed on the circle;
  • FIG. 6 is a schematic diagram of using a mask to form alignment marks on a wafer.
  • Figure 1 is a schematic diagram of the mask pattern used to form the alignment mark and the alignment mark formed by transferring it to the wafer, where GDS Level is the pattern of the mask, and Wafer Level is finally formed on the wafer Alignment mark.
  • GDS Level is the pattern of the mask
  • Wafer Level is finally formed on the wafer Alignment mark.
  • the pattern 10 of the mask is a large-size line, and in the alignment mark formed on the wafer, the pattern 11 becomes a short line, that is, the pattern size of the alignment mark has changed.
  • the alignment mark formed on the wafer using this mask as a mask can overcome the above-mentioned defects and form a standard independent mark.
  • FIG. 2 is a schematic diagram of the first embodiment of the pattern group of the mask of the present application and a schematic diagram of an independent mark formed by using the mask, wherein (a) is a schematic diagram of the mask, and (b) is on-chip Graphical schematic diagram of the independent marks formed on the circle.
  • the mask 20 includes at least one graphic group 210.
  • an independent mark 21 is formed on the corresponding area of the pattern group 210 on the wafer.
  • the outline of the graphic group 210 (shown by the dashed line A in FIG. 2) is the same as the outline of the independent mark 21.
  • the contour shape of the graphic group 210 is the same as the contour shape of the independent mark 21.
  • the independent mark 21 of the glyph shape needs to form a graphic group 210 with a cross-shaped outline.
  • the graphic group 210 may be a regular graphic, such as a rectangle, etc., or the graphic group 210 may be an irregular graphic, such as a graphic with an irregular outline. In this embodiment, if the outline shape of the graphic group 210 is a rectangle, it can form an independent rectangular independent mark.
  • the pattern group 210 includes at least one light-transmitting area 210A and at least one shielding area 210B.
  • the pattern group 210 includes a plurality of light-transmitting regions 210A and a plurality of shielding regions 210B.
  • the light transmittance of the light-transmitting area 210A is greater than the light transmittance of the shielding area 210B. In the subsequent photolithography process, light can pass through the light-transmitting area 210A and irradiate onto the wafer.
  • the light-transmitting area 210A and the shielding area 210B are arranged at intervals. Specifically, the light-transmitting area 210A and the shielding area 210B are arranged at intervals along a horizontal direction, a vertical direction, or an acute angle direction with the horizontal direction. For example, in this embodiment, the light-transmitting area 210A and the shielding area 210B are arranged at intervals along the horizontal direction (X direction).
  • the light-transmitting area 210A extends in one direction. This direction is perpendicular to the arrangement direction of the light-transmitting area 210A and the shielding area 210B. Specifically, in this embodiment, the light-transmitting area 210A and the shielding area 210B extend in a vertical direction.
  • a plurality of light-transmitting regions 210A are parallel to each other and extend along the Y direction, and the light-transmitting regions 210A and shielding regions 210B are arranged at intervals along the X direction to form the pattern group 210.
  • the light-transmitting area 210A can extend from the first side to the second side of the pattern group 210. Specifically, referring to FIG. 2, the light-transmitting area 210A extends from the first side 211 to the second side 212 of the pattern group 210, and the first side 211 and the second side 212 are not adjacent to each other. The two are set relative to each other.
  • the light-transmitting area 210A and the shielding area 210B are both rectangular, and the lengths of the two are equal, so the shape of the pattern group 210 formed by the light-transmitting area 210A and the shielding area 210B Also rectangular.
  • the lengths of a plurality of the light-transmitting regions 210A may be unequal, and the lengths of the shielding regions 210B may also be unequal, and the light-transmitting regions 210A and the The length of the shielding area 210B may also be unequal.
  • the mask of the present application When the mask of the present application is used for exposure, on the wafer, not only the area corresponding to the light-transmitting area 210A will be illuminated by light, but will also be affected by the characteristics of the light passing through the light-transmitting area 210A.
  • the area corresponding to 210B is also irradiated with light, thereby forming an independent mark 21 having the same contour shape as the pattern group 210 of the mask on the wafer.
  • the independent mark 21 is an independent overall graphic.
  • the light-transmitting area 210A has a width W1
  • the shielding area 210B has a width W2.
  • the width W1 of the light-transmitting area 210A is the same as the width W1 of the
  • the width W2 of the shielding area 210B needs to satisfy the following formula:
  • PITCH is the sum of the width W1 of the light-transmitting area 210A and the width W2 of the shielding area 210B
  • ⁇ is the wavelength used in the photolithography process
  • ⁇ is the ratio of the inner and outer diameters of the diffractive optical element used in the photolithography process
  • NA It is the numerical aperture used in the photolithography process. It can be seen that only when the sum of the width W1 of the light-transmitting area 210A and the width W2 of the shielding area 210B is less than ⁇ /((1+ ⁇ )*NA), can it be formed on the wafer with the
  • the graphic group 210 has independent marks 21 with the same shape.
  • the light transmittance of the shielding area 210B is 0.06 to 0.3 times the light transmittance of the light transmitting area 210A. If the light transmittance of the shielding area 210B is too small, The independent mark formed by the pattern group 210 may be a pattern composed of multiple bars. If the light transmittance of the shielding area 210B is too large, the independent mark formed by the pattern group 210 may have pattern defects. Will not form a standard independent marking graphics.
  • the present application divides the graphic group 210 into a plurality of light-transmitting areas 210A and shielding areas 210B arranged at intervals. Compared with the graphic group as a whole, the independent marks 21 formed by the graphic group 210 according to the present application have the same The contour shape of the pattern group 210 is the same shape without the aforementioned pattern defects, which improves the accuracy of the independent marking pattern, thereby improving the alignment accuracy of the photolithography system, and improving the accuracy of overlaying in subsequent processes. Improve product quality and yield.
  • the widths of the light-transmitting area 210A and the shielding area 210B may be equal or unequal. According to the parameters of different lithography machines, they may be appropriately selected so that the shape of the final independent mark 21 is the same as that of the independent mark 21.
  • the outline shape of the graphic group 210 is the same, and the final independent mark is more in line with the requirements.
  • FIG. 3 is a schematic diagram of the structure of the mask.
  • the mask 20 includes an alignment pattern area 22 and a chip pattern area 23.
  • the pattern group 210 is arranged in the alignment pattern area 22 to form alignment marks on the wafer.
  • the chip pattern area 23 can form a chip structure on the wafer.
  • the alignment marks formed on the wafer can be used for the same layer alignment, and can also be used for the alignment of different layers (ie, stack alignment). Specifically, when operations need to be performed on different areas of the same layer of the wafer, an alignment step needs to be performed before each area is operated, and the alignment mark used in the alignment step is the one used in this application. The mark formed by the mask. When it is necessary to perform operations on different layers of the wafer, an alignment step needs to be performed before each layer is operated, and the alignment mark used in the alignment step is the mark formed by using the mask of the present application.
  • the mask of this application also provides a second embodiment.
  • 4 is a schematic diagram of a second embodiment of the pattern group of the mask of the present application and a schematic diagram of an independent mark formed by using the mask, wherein (a) is a schematic diagram of the mask, and (b) is an on-chip Graphical schematic diagram of the independent marks formed on the circle.
  • the difference between the second embodiment and the first embodiment is that the arrangement direction and extension direction of the light-transmitting area 210A and the shielding area 210B are different.
  • the light-transmitting area 210A and the shielding area 210B are arranged in parallel along the vertical direction (Y direction) and extend along the horizontal direction (X direction).
  • the light-transmitting area 210A and the shielding area 210B extend from the first side 211 to the second side 212 of the pattern group 210, the first side 211 and the second side 212 are not adjacent, and they are disposed oppositely. That is to say, in this embodiment, a plurality of horizontally arranged light-transmitting regions 210A and shielding regions 210B are arranged at intervals along the vertical direction to form the pattern group 210.
  • FIG. 5 is a schematic diagram of a third embodiment of the pattern group of the mask of the present application and a schematic diagram of an independent mark formed by using the mask, wherein (a) is a schematic diagram of the mask pattern, (b) is an in-crystal diagram Graphical schematic diagram of the independent marks formed on the circle.
  • the difference between the third embodiment and the first embodiment is that the arrangement direction and extension direction of the light-transmitting area 210A and the shielding area 210B are different, which is only schematically shown in FIG. 5 One said graphic group 210.
  • the light-transmitting area 210A and the shielding area 210B are arranged in parallel along a direction (direction B) at an acute angle to the horizontal direction, and along a direction (direction C) at an obtuse angle to the horizontal direction. extend.
  • part of the light-transmitting area 210A and the shielding area 210B extend from the first side 211 of the pattern group 210 to the second side 212, and the first side 211 is adjacent to the second side 212; some of the The light-transmitting area 210A and the shielding area 210B extend from the first side 211 to the third side 213 of the pattern group 210, the first side 211 and the third side 213 are not adjacent, and they are disposed oppositely. That is to say, in this embodiment, a plurality of inclined transparent regions 210A and shielding regions 210B are arranged at intervals along a direction at an acute angle to the horizontal direction to form the pattern group 210.
  • the light-transmitting area 210A and the shielding area 210B are not equal in length, and their length depends on the position of the contour of the graphic group 210 formed by them, for example, the area located in the corner area of the graphic group 210
  • the length of the light-transmitting area 210A is smaller than the length of the light-transmitting area 210A located in the middle area of the pattern group 210.
  • the mask of the present application does not limit the arrangement direction and extension direction of the light-transmitting area 210A and the shielding area 210B, as long as the light-transmitting area 210A and the shielding area 210B extend in the same direction. It is sufficient that the pattern group can be formed.
  • the present application also provides a photolithography process method. During exposure, the above-mentioned mask is used to form independent marks on the wafer.
  • FIG. 6 is a schematic diagram of using a mask to form alignment marks on a wafer.
  • the mask 20 includes an alignment pattern area 22 and a chip pattern area 23.
  • the pattern group 210 is arranged on the pair of Quasi-graphic area 22.
  • the light-transmissive pattern group 210 is incident on the corresponding area of the wafer, and the pattern group 210 forms an alignment mark 31 on the wafer 30.
  • light also transmits through the chip pattern
  • the area 23 is incident on the corresponding area of the wafer, and the chip pattern area 23 forms a chip structure 32 on the wafer 30.
  • the mask 20 can be moved to form a plurality of chip structures 32 and alignment marks 31 on the wafer.
  • the photolithography process method of the present application adopts the above-mentioned mask structure as a mask, which can form standard independent marks on the wafer, thereby improving the accuracy of subsequent processes and improving product quality and yield.

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  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
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Abstract

一种应用于半导体光刻工艺中的掩膜版及光刻工艺方法，掩膜版（20）包括至少一图形组（210），每一图形组（210）包括至少一透光区（210A）和至少一遮挡区（210B），透光区（210A）和遮挡区（210B）间隔排列，经过曝光后，每一图形组（210）在晶圆上形成一独立标记（21）。根据掩膜版（20）在晶圆上形成的独立标记（21）具有与掩膜版（20）的图形轮廓形状相同的形状，不会出现图案缺陷，提高了在晶圆上形成的独立标记图形的准确度，进而提高了半导体光刻工艺的对准精度及半导体制程的后续工艺中叠对准确性，提高产品质量和良率。

Description

应用于半导体光刻工艺中的掩膜版及光刻工艺方法
相关申请引用说明
本申请要求于2020年02月22日递交的中国专利申请号202010109639.9，申请名为“应用于半导体光刻工艺中的掩膜版及光刻工艺方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本申请涉及半导体制造领域，尤其涉及一种应用于半导体光刻工艺中的掩膜版及光刻工艺方法。
背景技术
随着半导体制造工艺的发展，半导体芯片的面积越来越小，因此，半导体工艺的精度也变得更加重要。在半导体工艺制造过程中，一个重要的工艺环节就是光刻工艺(photography)，光刻工艺主要是将掩膜版上的版图转移到晶圆上，之后方可进行后续其他工艺过程，完成整个半导体器件的制作。因此，光刻工艺的质量将直接影响着最终形成的半导体器件的性能。
目前，掩膜版上的图形转移到晶圆上形成的标记，有可能会出现图案尺寸改变、图案形状变化，甚至不显示图案的情况，这影响了半导体器件的性能。
例如，对于光刻系统来说对准是其最重要机制之一，对准精度是在多层曝光时层间图案的定位精度，对准精度是半导体生产过程中光刻系统的重要指标。
想要对准就要用到对准标记。当前用于SMASH系统的对准标记(Alignment mark)主要有DPCM、NSSM11、NSSM53、XPAAA5、BF2u3F等。光刻系统经由粗/细对准图形的量测及分析运算,机台可预先补偿部分晶圆因为前工艺制程所造成的图形叠对偏差。
对准标记的制作过程是，设计与对准标记对应的掩膜版；通过光刻系统将所述掩膜版上的图形转移到晶圆上，进而在所述晶圆上形成对准标记。通常，图形能够正常转移到晶圆上。但是，对于一些特殊情况，例如高透过率掩膜版，受到旁瓣(side-lobe)效应的影响，图形转移到晶圆上后，有可能会出现图案尺寸改变、图案形状变化，甚至不显示图案的情况。图形的不正常转移会使得在晶圆上不能够形成标准的对准标记，影响光刻系统精度了，例如对准精度，进而导致后续工艺中叠对准确性降低，影响产品质量和良率。
因此，如何使在晶圆上形成标准的标记，成为目前亟需解决的技术问题。
发明内容
本申请所要解决的技术问题是，提供一种应用于半导体光刻工艺中的掩膜版及光刻工艺方法，其能够在晶圆上形成标准的独立标记，提高光刻系统性能，提高产品的质量及良率。
为了解决上述问题，本申请提供了一种应用于半导体光刻工艺中的掩膜版，其包括至少一图形组，每一所述图形组包括至少一透光区和至少一遮挡区，所述透光区和所述遮挡区间隔排列，经过曝光后，每一所述图形组在晶圆上形成一独立标记。
进一步，所述图形组中的透光区和遮挡区均为矩形。
进一步，所述透光区的长度与所述遮挡区的长度相同。
进一步，所述独立标记为矩形。
进一步，所述透光区的宽度与所述遮挡区的宽度满足如下公式：
PITCH≤λ/((1+σ)*NA)
其中，PITCH为所述透光区与所述遮挡区的宽度之和，λ为光刻工艺中所用波长，σ为光刻工艺中所用衍射光学元件内外径之比，NA为光刻工艺中所 用数值孔径。
进一步，所述遮挡区的透光率为所述透光区的透光率的0.06～0.3倍。
进一步，所述透光区平行设置。
进一步，所述透光区及所述遮挡区沿水平方向、竖直方向或者与所述水平方向呈一锐角方向间隔排列。
进一步，所述掩膜版包括对准图形区及芯片图形区，所述图形组设置在所述对准图形区，所述独立标记作为晶圆的对准标记。
进一步，所述对准标记包括同一层的对准标记和层与层之间的对准标记。
本申请还提供一种光刻工艺方法，所述光刻工艺方法采用如上所述的掩膜版作为掩膜，以在晶圆上形成对准标记。
本申请的优点在于，在所述掩膜版上，所述图形组由透光区与遮挡区间隔设置而形成，曝光时，根据所述图形组在晶圆上形成的独立标记具有与所述图形组的轮廓形状相同的形状，所述独立标记不会出现图案缺陷，提高了在晶圆上形成独立标记图形的准确度，提高了光刻系统的对准精度，且提高了后续半导体工艺中叠对的准确性，提高产品质量和良率。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是用于形成对准标记的掩膜版图形及其转移到晶圆上形成的对准标记的示意图，其中，(a)是掩膜版的图形，(b)是最终形成在晶圆上的对准标记；
图2是本申请掩膜版的图形组的第一具体实施方式的示意图及采用该掩膜 版形成的独立标记的示意图，其中，(a)为掩膜版的图形示意图，(b)为在晶圆上形成的独立标记的图形示意图；
图3是所述掩膜版的另一结构示意图；
图4是本申请掩膜版的图形组的第二实施例的示意图及采用该掩膜版形成的独立标记的示意图，其中，(a)为掩膜版的图形示意图，(b)为在晶圆上形成的独立标记的图形示意图；
图5是本申请掩膜版的图形组的第三实施例的示意图及采用该掩膜版形成的独立标记的示意图，其中，(a)为掩膜版的图形示意图，(b)为在晶圆上形成的独立标记的图形示意图；
图6是采用掩膜版在晶圆上形成对准标记的示意图。
具体实施方式
为了使本申请的目的、技术手段及其效果更加清楚明确，以下将结合附图对本申请作进一步地阐述。应当理解，此处所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例，并不用于限定本申请。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。发明人发现，在光刻工艺中，将掩膜版上的图形转移到晶圆上会出现各种缺陷。特别是对于在晶圆上形成的对准标记，其缺陷更明显。例如，图1是用于形成对准标记的掩膜版图形及其转移到晶圆上形成的对准标记的示意图，其中GDS Level是掩膜版的图形，Wafer Level是最终形成在晶圆上的对准标记。请参阅图1，掩膜版的图案10为大尺寸的线条，而在晶圆上形成的对准标记中，图案11变为短线条，即对准标记的图案尺寸发生了变化。
经发明人研究，提出一种新型的掩膜版。在光刻工艺中，采用该掩膜版作 为掩膜在晶圆上形成的对准标记能够克服上述缺陷，形成标准的独立标记。
图2是本申请掩膜版的图形组的第一实施例的示意图及采用该掩膜版形成的独立标记的示意图，其中，(a)为掩膜版的图形示意图，(b)为在晶圆上形成的独立标记的图形示意图。
请参阅图2，所述掩膜版20包括至少一图形组210。在将所述掩膜版20的图形转移到晶圆上后，在所述晶圆上，所述图形组210对应区域形成一个独立的独立标记21。具体地说，所述图形组210的轮廓(如图2中虚线A绘示)与所述独立标记21的轮廓相同。也就是说，所述图形组210的轮廓形状与所述独立标记21的轮廓形状相同，例如，若要形成矩形形状的独立标记21，则需要形成具有矩形轮廓的图形组210，若要形成十字形形状的独立标记21，则需要形成具有十字形轮廓的图形组210。进一步，根据所述独立标记21的形状，所述图形组210可为规则图形，例如矩形等，或者所述图形组210不规则图形，例如具有不规则轮廓的图形。在本实施例中，所述图形组210的轮廓形状为矩形，则其可形成独立的矩形独立标记。
在本实施例中，仅示意性地绘示三个图形组210。在其他实施例中，也可根据在晶圆上形成的独立标记21的要求而设置其他数量的图形组210，例如，在本申请另一实施例中，在所述晶圆上需要形成一个独立标记，则需要在所述掩膜版上设置一组图形组210。
所述图形组210包括至少一透光区210A和至少一遮挡区210B。在本实施例中，所述图形组210包括多个透光区210A和多个遮挡区210B。所述透光区210A的透光率大于所述遮挡区210B的透光率。在后续光刻工艺中，光能够穿过所述透光区210A照射至晶圆上。
所述透光区210A与所述遮挡区210B间隔排列。具体地说，所述透光区 210A与所述遮挡区210B沿水平方向、竖直方向，或者与所述水平方向呈一锐角方向间隔排列。例如，在本实施例中，所述透光区210A与所述遮挡区210B沿水平方向(X方向)间隔排列。所述透光区210A沿一方向延伸。该方向与所述透光区210A及遮挡区210B的排列方向垂直。具体地说，在本实施例中，所述透光区210A及遮挡区210B沿竖直方向延伸。也就是说，在本实施例中，多个透光区210A彼此平行，并沿Y方向延伸，且所述透光区210A与遮挡区210B沿X方向间隔排列，形成所述图形组210。
所述透光区210A能够自所述图形组210的第一边延伸至第二边。具体地说，请参阅图2，所述透光区210A自所述图形组210的第一边211延伸至第二边212，所述第一边211与所述第二边212不相邻，两者相对设置。
进一步，在本实施例中，所述透光区210A及所述遮挡区210B均为矩形，且两者长度相等，则所述透光区210A及所述遮挡区210B形成的图形组210的形状也为矩形。在本申请其他实施例中(如本申请第二实施例)，多个所述透光区210A的长度可不相等，所述遮挡区210B的长度也可不相等，所述透光区210A与所述遮挡区210B的长度也可不相等。
在采用本申请掩膜版进行曝光时，在所述晶圆上，不仅透光区210A对应的区域会被光照射，受到通过所述透光区210A的光的特性的影响，所述遮挡区210B对应的区域也会被光照射，从而在所述晶圆上形成与所述掩膜版的图形组210具有相同轮廓形状的独立标记21。所述独立标记21为一个独立的整体图形。
进一步，所述透光区210A具有一宽度W1，所述遮挡区210B具有一宽度W2，为了使所述图形组210能够形成一个独立的独立标记，所述透光区210A的宽度W1与所述遮挡区210B的宽度W2需要满足如下公式：
PITCH≤λ/((1+σ)*NA)
其中，PITCH为所述透光区210A的宽度W1与所述遮挡区210B的宽度W2之和，λ为光刻工艺中所用波长，σ为光刻工艺中所用衍射光学元件内外径之比，NA为光刻工艺中所用数值孔径。可见，只有在所述透光区210A的宽度W1与所述遮挡区210B的宽度W2之和小于λ/((1+σ)*NA)时，在所述晶圆上才能够形成与所述图形组210形状相同的独立标记21。
为了进一步保证所述图形组210能够形成一个独立的独立标记，遮挡区210B的透光率为透光区210A的透光率0.06～0.3倍，若所述遮挡区210B的透光率过小，则所述图形组210形成的独立标记可能为由多个条形构成的图案，若所述遮挡区210B的透光率过大，则所述图形组210形成的独立标记可能会存在图案缺陷，不会形成标准的独立标记图形。
本申请将所述图形组210分割为多个透光区210A及遮挡区210B间隔排列，相较于图形组为一个整体而言，根据本申请所述图形组210形成的的独立标记21具有与所述图形组210的轮廓形状相同的形状，不会出现上述的图案缺陷，提高了独立标记图形的准确度，进而提高了光刻系统的对准精度，且提高后续工艺中叠对准确性，提高产品质量和良率。
进一步，所述透光区210A及所述遮挡区210B的宽度可相等，也可不相等，根据不同的光刻机台的参数不同，可适当选择，以使最终形成的独立标记21的形状与所述图形组210的轮廓形状相同，最终获得的独立标记更符合要求。
进一步，所述独立标记可为对准标记。具体地说，图3是所述掩膜版的结构示意图，所述掩膜版20包括对准图形区22及芯片图形区23。所述图形组210设置在所述对准图形区22，以在所述晶圆上形成对准标记。所述芯片图形 区23可在所述晶圆上形成芯片结构。
其中，在所述晶圆上形成的对准标记可用于同层对准，也可用于不同层对准(即叠层对准)。具体地说，当需要在晶圆的同一层的不同区域进行操作时，在对每一个区域进行操作之前，均需要执行对准步骤，该对准步骤中采用的对准标记即为采用本申请掩膜版形成的标记。当需要在晶圆的不同层进行操作时，在对每一层进行操作之前，均需要执行对准步骤，该对准步骤中采用的对准标记即为采用本申请掩膜版形成的标记。
本申请掩膜版还提供一第二实施例。图4是本申请掩膜版的图形组的第二实施例的示意图及采用该掩膜版形成的独立标记的示意图，其中，(a)为掩膜版的图形示意图，(b)为在晶圆上形成的独立标记的图形示意图。请参阅图4，所述第二实施例与所述第一实施例的区别在于，所述透光区210A及遮挡区210B的排列方向及延伸方向不同。
具体地说，在第二实施例中，所述透光区210A及遮挡区210B沿竖直方向(Y方向)平行排列，并沿水平方向(X方向)延伸。所述透光区210A及遮挡区210B自所述图形组210的第一边211延伸至第二边212，所述第一边211与所述第二边212不相邻，两者相对设置。也就是说，在本实施例中，多个水平设置的透光区210A及遮挡区210B沿竖直方向间隔排列形成所述图形组210。
本申请掩膜版还提供一第三实施例。图5是本申请掩膜版的图形组的第三实施例的示意图及采用该掩膜版形成的独立标记的示意图，其中，(a)为掩膜版的图形示意图，(b)为在晶圆上形成的独立标记的图形示意图。请参阅图5，所述第三实施例与所述第一实施例的区别在于，所述透光区210A及遮挡区210B的排列方向及延伸方向不同，在图5中仅示意性地绘示一个所述图形组 210。
具体地说，在第三实施例中，所述透光区210A及遮挡区210B沿与水平方向呈一锐角方向(B方向)平行排列，并沿与水平方向呈一钝角的方向(C方向)延伸。其中，部分所述透光区210A及遮挡区210B自所述图形组210的第一边211延伸至第二边212，所述第一边211与所述第二边212相邻；部分所述透光区210A及遮挡区210B自所述图形组210的第一边211延伸至第三边213，所述第一边211与所述第三边213不相邻，两者相对设置。也就是说，在本实施例中，多个倾斜的透光区210A及遮挡区210B沿与水平方向呈一锐角的方向间隔排列形成所述图形组210。
进一步，在第三实施例中，所述透光区210A及所述遮挡区210B不等长，其长度取决于其形成的图形组210的轮廓的位置，例如，位于图形组210的角落区域的所述透光区210A的长度小于位于图形组210的中部区域的透光区210A的长度。
可以理解的是，本申请掩膜版对所述透光区210A及所述遮挡区210B的排列方向及延伸方向不进行限定，只要所述透光区210A及所述遮挡区210B延伸方向一致，能够形成所述图形组即可。
本申请还提供一种光刻工艺方法，在曝光时，采用上述的掩膜版在晶圆上形成独立标记。
下面以在所述晶圆上形成对准标记为例进行说明。请参阅图6，其为采用掩膜版在晶圆上形成对准标记的示意图，所述掩膜版20包括对准图形区22及芯片图形区23，所述图形组210设置在所述对准图形区22。在进行曝光时，光透光所述图形组210入射至所述晶圆对应区域，所述图形组210在所述晶圆30上形成对准标记31，同时，光也透过所述芯片图形区23入射至所述晶圆对 应区域，所述芯片图形区23在所述晶圆30上形成芯片结构32。进一步，可移动所述掩膜版20，以在所述晶圆上形成多个芯片结构32及对准标记31。
本申请光刻工艺方法采用上述掩膜版结构作为掩膜，其能够在所述晶圆上形成标准的符合要求的独立标记，从而能够提高后续工艺的准确性，提高产品质量及良率。
以上所述仅是本申请的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (11)

  1. 一种应用于半导体光刻工艺中的掩膜版，其中，包括至少一图形组，每一所述图形组包括至少一透光区和至少一遮挡区，所述透光区和所述遮挡区间隔排列，经过曝光后，每一所述图形组在晶圆上形成一独立标记。
  2. 根据权利要求1所述的掩膜版，其中，所述图形组中的透光区和遮挡区均为矩形。
  3. 根据权利要求2所述的掩膜版，其中，所述透光区的长度与所述遮挡区的长度相同。
  4. 根据权利要求2所述的掩膜版，其中，所述独立标记为矩形。
  5. 根据权利要求2所述的掩膜版，其中，所述透光区的宽度与所述遮挡区的宽度满足如下公式：
    PITCH≤λ/((1+σ)*NA)
    其中，PITCH为所述透光区与所述遮挡区的宽度之和，λ为光刻工艺中所用波长，σ为光刻工艺中所用衍射光学元件内外径之比，NA为光刻工艺中所用数值孔径。
  6. 根据权利要求1所述的掩膜版，其中，所述遮挡区的透光率为所述透光区的透光率的0.06～0.3倍。
  7. 根据权利要求1所述的掩膜版，其中，所述透光区平行设置。
  8. 根据权利要求1所述的掩膜版，其中，所述透光区及所述遮挡区沿水平方向、竖直方向或者与所述水平方向呈一锐角方向间隔排列。
  9. 根据权利要求1所述的掩膜版，其中，所述掩膜版包括对准图形区及芯片图形区，所述图形组设置在所述对准图形区，所述独立标记作为晶圆的对准标记。
  10. 根据权利要求9所述的掩膜版，其中，所述对准标记包括同一层的对准 标记和层与层之间的对准标记。
  11. 一种光刻工艺方法，其中，所述光刻工艺方法采用如权利要求1所述的掩膜版作为掩膜，以在晶圆上形成对准标记。
PCT/CN2021/075946 2020-02-22 2021-02-08 应用于半导体光刻工艺中的掩膜版及光刻工艺方法 WO2021164608A1 (zh)

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