WO2021164597A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2021164597A1
WO2021164597A1 PCT/CN2021/075809 CN2021075809W WO2021164597A1 WO 2021164597 A1 WO2021164597 A1 WO 2021164597A1 CN 2021075809 W CN2021075809 W CN 2021075809W WO 2021164597 A1 WO2021164597 A1 WO 2021164597A1
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WO
WIPO (PCT)
Prior art keywords
area
display
layer
static
binding
Prior art date
Application number
PCT/CN2021/075809
Other languages
English (en)
French (fr)
Inventor
祁亚亚
董殿正
闫岩
王骁
王雪
王婷婷
李晓颖
麻志强
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/433,164 priority Critical patent/US11805630B2/en
Publication of WO2021164597A1 publication Critical patent/WO2021164597A1/zh
Priority to US18/372,298 priority patent/US20240015939A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0067—Devices for protecting against damage from electrostatic discharge
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13458—Terminal pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05F—STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
    • H05F3/00—Carrying-off electrostatic charges
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05F—STATIC ELECTRICITY; NATURALLY-OCCURRING ELECTRICITY
    • H05F3/00—Carrying-off electrostatic charges
    • H05F3/02—Carrying-off electrostatic charges by means of earthing connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0064—Earth or grounding circuit
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133354—Arrangements for aligning or assembling substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/22—Antistatic materials or arrangements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0215—Grounding of printed circuits by connection to external grounding means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0257—Overvoltage protection
    • H05K1/0259—Electrostatic discharge [ESD] protection

Definitions

  • the present disclosure relates to the field of display technology, and in particular to display substrates and display devices.
  • the display substrate is constantly rubbed during the transmission and manufacturing process, resulting in the continuous generation of static electricity on the display substrate.
  • the substrate of the display substrate is made of insulating glass material, which makes it difficult for static electricity to be released, which makes it easy to accumulate a large amount of static charge on the surface of the display substrate. Under certain circumstances, static discharge will occur. After static electricity enters the display area, it is easy to cause Conductive structures such as signal lines are broken down, causing poor display.
  • the present disclosure provides a display substrate, including: a display area and a binding area located on one side of the display area, the binding area includes a plurality of binding sub-areas arranged at intervals, and each of the binding sub-areas Are arranged in the extending direction of the edge of the region, and the bonding sub-regions are used for bonding the chip-on-chip film, wherein,
  • the binding area is provided with a first antistatic layer, at least a part of the first antistatic layer is located between the adjacent binding sub-areas, and the first antistatic layer is electrically connected to the reference signal terminal .
  • the display substrate further includes a signal terminal configured to provide a display signal to the display area, and is located on a side of the binding area close to the display area, and the signal terminal The end is located between the display area and the first antistatic layer, and is isolated from the outside by the first antistatic layer.
  • the reference signal terminal is arranged on the bonding sub-region and is configured to be electrically connected to an external ground terminal through the flip chip film.
  • the first antistatic layer includes a first antistatic sublayer and a second antistatic sublayer
  • the second antistatic sublayer is disposed near the first antistatic sublayer.
  • both the first anti-static sub-layer and the second anti-static sub-layer are electrically connected to the reference signal terminal.
  • the first anti-static sub-layer is electrically isolated from the second anti-static sub-layer.
  • a first through hole is provided on the first antistatic layer.
  • the first through hole is a bar-shaped through hole.
  • the display substrate further includes a first frame area, a second frame area, and a third frame area that are sequentially connected, the first frame area, the second frame area, and the third frame area.
  • the binding area surrounds the display area, and the first frame area, the second frame area, and the third frame area are all provided with a second antistatic layer, the second antistatic layer It is electrically connected to the reference signal terminal.
  • the display substrate further includes a conductive layer, the conductive layer includes a connecting line and an auxiliary conductive part connected in parallel with the connecting line, and the second antistatic layer is connected to the reference through the connecting line.
  • the signal terminal is electrically connected.
  • the second antistatic layer is provided with a second through hole at a position close to the corner of the display substrate, and an alignment mark is provided in the second through hole, and the alignment mark is used for Position alignment and adjustment.
  • the present disclosure also provides a display device, including the above-mentioned display substrate,
  • the display device further includes a chip on film, one end of the chip on film is bound to the binding sub-region, and the other end of the chip on film is bound to the driving circuit board;
  • the driving circuit board is provided with a ground terminal, and the reference signal terminal is electrically connected to the ground terminal on the driving circuit board through the flip chip film.
  • the first anti-static layer and the chip-on-chip film adjacent to the first anti-static layer partially overlap in a first direction, and the first direction is the binding area and the display The arrangement direction of the zone.
  • the chip on film includes a body portion and a protrusion, and the protrusion portion protrudes from the body portion toward the adjacent chip on film;
  • the first anti-static sub-layer includes a first anti-static part, a second anti-static part, and a third anti-static part, and the second anti-static part is located between the body parts of two adjacent chip-on-chip films ,
  • the first anti-static part is located on a side of the second anti-static part away from the display area, and at least a part of the first anti-static part is located at the protrusions of two adjacent chip-on-chip films Between the parts, the third anti-static part is located on a side of the second anti-static part close to the display area.
  • the first anti-static part, the second anti-static part, and the third anti-static part are formed as an integral structure.
  • FIG. 1 is one of the schematic diagrams of a display substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic diagram of through holes provided on the first antistatic layer provided by an embodiment of the disclosure
  • FIG 3 is the second schematic diagram of the display substrate provided by the embodiment of the disclosure.
  • FIG. 4 is a schematic diagram of an alignment mark provided by an embodiment of the disclosure.
  • FIG. 5 is a schematic diagram of a display device provided by an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of the structure of the first antistatic layer in an embodiment of the disclosure.
  • FIG. 1 is one of the schematic diagrams of the display substrate provided by an embodiment of the present disclosure.
  • the display substrate includes: a display area 1 and a binding area located on one side of the display area 1.
  • the bonding area 2 includes a plurality of bonding sub-areas 21 arranged at intervals, and the bonding sub-areas 21 is used for bonding a chip on film (COF).
  • the binding area 2 is provided with a first antistatic layer 3, at least a part of the first antistatic layer 3 is located between adjacent binding sub-regions 21, and the first antistatic layer 3 is electrically connected to the reference signal terminal.
  • the first antistatic layer 3 may be made of a metal conductive material, and the plurality of bonding sub-regions 21 in the bonding area 2 may extend along the edge of the display area 1 (for example, as shown in FIG. 1), the adjacent bonding sub-regions 21 have a certain distance between them.
  • Each bonding sub-region 21 can be provided with a bonding electrode, and the bonding electrode is used to interact with the conductive part on the flip chip film. It is electrically connected to receive the driving signal provided by the flip chip film, and then provide a display signal for the display area 1.
  • the reference signal terminal may be arranged on the bonding sub-region 21, the flip chip film may be electrically connected to the driving circuit board, and the reference signal terminal may be electrically connected to the ground terminal on the driving circuit board through the flip chip film.
  • the binding area 2 may also be provided with a signal terminal 4 on the side close to the display area 1.
  • the signal terminal 4 is a common signal terminal (VCOM) for providing a common signal line in the display area 1. Common voltage signal. At least a part of the signal terminal 4 may correspond to the interval between the binding sub-regions 21, for example, at least a part of the signal terminal 4 may be located on the side of the first antistatic layer 3 close to the display area 1.
  • the static electricity generated in the process of manufacturing and moving the display substrate is easily conducted from the gap between the binding sub-regions 21 to the signal terminal 4, and then to the display area 1, so that display may occur in the display area 1. bad.
  • the first antistatic layer 3 since at least a part of the first antistatic layer 3 is located between the adjacent binding subregions 21, when static electricity is generated between the adjacent binding subregions 21, the first antistatic layer 3
  • the static electricity layer 3 can lead the static electricity to the ground terminal of the driving circuit board in time, so as to protect the signal terminal 4 from static electricity and improve the antistatic ability of the display substrate.
  • the specific shape of the bonding sub-region 21 may be the same as the shape of the part of the chip on film that is bound to the bonding sub-region 21.
  • the first anti-static layer 3 may include a first anti-static sub-layer 31 and a second anti-static sub-layer 32.
  • the second anti-static sub-layer 32 may be disposed near the first anti-static sub-layer 31.
  • the first anti-static sub-layer 31 and the second anti-static sub-layer 32 are both electrically connected to the reference signal terminal.
  • the first anti-static sub-layer 31 and the second anti-static sub-layer 32 may be electrically isolated.
  • the second anti-static sub-layer 32 can lead out the remaining static electricity, thereby improving the effect of static electricity protection.
  • a first through hole may be provided on the first antistatic layer 3.
  • FIG. 2 is a schematic diagram of a through hole provided on the first antistatic layer provided by an embodiment of the disclosure.
  • the shape of the first through hole V1 may be a bar shape.
  • the shape of the first through hole V1 may also be a shape such as a circle or a triangle, which is not limited here. Since the first antistatic layer 3 can be made of a metal conductive material, and the metal conductive material has a certain degree of light reflection, the first through hole V1 can be provided on the first antistatic layer 3 to reduce the first antistatic layer.
  • the first through hole V1 is a bar-shaped through hole extending along the arrangement direction of the plurality of binding sub-regions 21 (for example, the left and right direction in FIG.
  • the first through hole V1 may also It is a bar-shaped through hole extending perpendicular to the arrangement direction of the plurality of binding sub-regions 21, for example, it may be a bar-shaped through hole extending in the up-down direction in FIG. 1, or the first through hole V1 may also be along other Strip-shaped through holes extending in any direction are not limited here.
  • FIG. 3 is the second schematic diagram of the display substrate provided by the embodiment of the present disclosure.
  • the display substrate further includes a first frame area 11, a second frame area 12, and a third frame area connected in sequence 13.
  • the first frame area 11, the second frame area 12, the third frame area 13 and the binding area 2 surround the display area 1.
  • the first frame area 11 and the third frame area 13 are respectively located at two opposite sides of the display area 1.
  • the second frame area 12 and the binding area 2 are respectively located on opposite sides of the display area 1.
  • the first frame area 11, the second frame area 12, and the third frame area 13 can each be provided with a second antistatic layer 5 .
  • the second antistatic layer 5 may also be electrically connected to the reference signal terminal in the binding area 2.
  • the portions of the second antistatic layer 5 in the first frame area 11, the second frame area 12, and the third frame area 13 may be strip-shaped, and may be formed as an integral structure.
  • the portion of the electrostatic layer 5 located in the first frame area 11 and the third frame area 13 can extend along the first frame area 11 and the third frame area 13 to the two ends of the binding area 2 respectively, and are respectively adjacent to the binding members.
  • the reference signal terminal on the region 21 is electrically connected.
  • the portion of the second antistatic layer 5 located in the first frame region 11 can be connected to the reference signal terminal on the bonding subregion 21a that is close to it.
  • the portion of the second antistatic layer 5 located in the third frame area 13 may be electrically connected to the reference signal terminal on the binding sub-area 21b that it is close to.
  • electrostatic protection can be formed on the other three sides of the display substrate except the side where the binding area 2 is located.
  • the corresponding anti-static The layer leads the static electricity in time, thereby improving the antistatic ability of the display substrate.
  • the display substrate of the embodiment of the present disclosure may further include a conductive layer 6.
  • the conductive layer 6 includes a connecting wire 61 and an auxiliary conductive portion 62 connected in parallel with the connecting wire 61.
  • the layer 5 can be electrically connected to the reference signal terminal through a connecting wire 61.
  • the auxiliary conductive portion 62 can be arranged in the same layer as the connecting wire 61, and arranged on both sides of the connecting wire 61, so that the connecting wire 61 and the auxiliary conductive portion 62 form an entire continuous conductive layer, reducing the second antistatic layer. 5
  • the edge position of the display substrate may be provided with an alignment mark, and the alignment mark may include a plurality of marking lines to form a vernier mark.
  • Alignment marks are usually made of metal materials. However, this will cause electrostatic charges to accumulate on the alignment marks. After the electrostatic charges have accumulated to a certain extent, electrostatic discharge will occur. Large instantaneous currents may enter the adjacent second antistatic layer. 5. It is easy to cause the second antistatic layer 5 to be broken down, causing poor display.
  • the distance between the alignment mark and the edge of the display substrate can be increased, thereby improving the problem of electrostatic charge accumulation on the alignment mark.
  • 4 is a schematic diagram of the alignment mark provided by an embodiment of the disclosure.
  • the second antistatic layer 5 may be provided with a second through hole V2 at a position close to the corner of the display substrate.
  • Alignment marks 51 can be provided in the middle.
  • the alignment mark 51 is arranged in the second through hole V2, which can increase the distance between the alignment mark 51 and the edge of the display substrate. , To prevent electrostatic charges from accumulating on the alignment mark 51 and causing electrostatic discharge to break down the second antistatic layer 5 nearby.
  • the alignment mark may also be provided on the alignment mark used to be opposed to the display substrate. After the alignment mark 51 on the display substrate is increased from the edge of the display substrate, the alignment mark may also be set. The position of the alignment mark on the box substrate is adjusted accordingly, so that the alignment mark 51 on the display substrate corresponds to the alignment mark on the box substrate.
  • the alignment mark 51 can also be directly removed, so as to prevent static electricity from entering the display substrate, thereby preventing the second antistatic layer 5 from being broken down.
  • FIG. 5 is a schematic diagram of the display device provided by the embodiment of the disclosure.
  • the display device includes the display substrate of the above-mentioned embodiment, and the display device further includes: a chip on film 7, one end of the chip on film 7 is bound to the binding sub-region 21, and the other of the chip on film One end will be bound to the drive circuit board.
  • the driving circuit board may be provided with a ground terminal, and the reference signal terminal is electrically connected to the ground terminal on the driving circuit board through the flip chip film 7.
  • the reference signal terminal may be arranged on the bonding sub-region 21, and the ground signal line may be arranged on the flip chip film 7.
  • One end of the ground signal line is electrically connected to the reference signal terminal, and the other end is electrically connected to the ground terminal on the drive circuit board. Connection, so that the reference signal terminal is electrically connected to the ground terminal on the driving circuit board through the flip chip film 7.
  • Each bonding sub-region 21 may be provided with a bonding electrode, and one end of the chip-on-chip film 7 is bonded to the bonding sub-region 21 means that the conductive part at one end of the chip-on-chip film 7 is bonded to the bonding sub-region 21
  • the electrodes are electrically connected; the other end of the chip-on-chip film will be bound to the driving circuit board means that the conductive part at the other end of the chip-on-chip film 7 will be electrically connected to the signal output part on the driving circuit board.
  • the binding area 2 may also be provided with a signal terminal 4 on the side close to the display area 1.
  • the signal terminal 4 is a common signal terminal (VCOM) for providing a common signal line in the display area 1. Common voltage signal.
  • At least a part of the signal terminal 4 may correspond to the interval between the binding sub-regions 21, for example, at least a part of the signal terminal 4 may be located on the side of the first antistatic layer 3 close to the display area 1.
  • the first antistatic layer 3 since at least a part of the first antistatic layer 3 is located between the adjacent binding sub-regions 21 in the display substrate, when static electricity is generated between the adjacent binding sub-regions 21 At this time, the first anti-static layer 3 can lead static electricity to the ground terminal of the driving circuit board in time, so as to protect the signal terminal 4 from static electricity and improve the anti-static ability of the display substrate.
  • the signal terminal 4 is isolated from the outside by the first anti-static layer 3.
  • the first anti-static layer 3 can be connected to the flip-chip film 7 adjacent to the first anti-static layer 3, for example, in the first direction.
  • the first direction may be the arrangement direction of the binding area 2 and the display area 1 (the up and down direction in FIG. 5).
  • the first anti-static layer 3 and the flip-chip film 7 adjacent to the first anti-static layer 3 partially overlap in the first direction, so that the signal terminal 4 can be completely isolated from the outside through the first anti-static layer 3, improving electrostatic protection Effect.
  • the chip on film 7 includes a body portion 72 and a protrusion 71, and the protrusion portion 71 of each chip on film 7 protrudes from the body portion 72 toward the adjacent chip on film 7.
  • 6 is a schematic diagram of the structure of the first anti-static layer in the embodiment of the disclosure. As shown in FIG. 5 and FIG.
  • the first anti-static sub-layer 31 may include a first anti-static part 311, a second anti-static part 312, and a Three anti-static parts 313, the second anti-static part 312 is located between the body parts 72 of the adjacent chip on film 7, the first anti-static part 311 is located on the side of the second anti-static part 312 away from the display area 1, and At least a part of the first anti-static part 311 is located between the protruding parts 71 of the adjacent chip on film 7, and the third anti-static part 313 is located on the side of the second anti-static part 312 close to the display area 1.
  • the first anti-static part 311, the second anti-static part 312, and the third anti-static part 313 are formed as an integral structure.
  • the first anti-static layer 3 may further include a second anti-static sub-layer 32, and the second anti-static sub-layer 32 may be located on a side of the third anti-static part 313 close to the display area 1. Both the first antistatic sublayer 31 and the second antistatic sublayer 32 are electrically connected to the reference signal terminal, and the first antistatic sublayer 31 and the second antistatic sublayer 32 can be electrically isolated.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Theoretical Computer Science (AREA)

Abstract

一种显示基板和显示装置，显示基板包括显示区（1）和位于显示区（1）一侧的绑定区（2）。绑定区（2）包括多个间隔设置的绑定子区（21），各绑定子区（21）沿显示区（1）边缘的延伸方向排布，且绑定子区（21）用于绑定覆晶薄膜（7），其中绑定区（21）上还设置有第一防静电层（3），第一防静电层（3）的至少一部分位于相邻的绑定子区（21）之间，第一防静电层（3）与参考信号端电连接。

Description

显示基板和显示装置
相关申请的交叉引用
本申请要求于2020年2月19日提交的中国专利申请NO.202010101579.6的优先权，该中国专利申请的内容通过引用的方式整体合并于此。
技术领域
本公开涉及显示技术领域，具体涉及显示基板和显示装置。
背景技术
显示基板在传输和制造过程中不断地被摩擦，导致在显示基板上持续产生静电。显示基板的衬底采用绝缘的玻璃材料，静电难以释放，从而容易在显示基板的表面积累大量静电荷，在特定情况下就会产生静电释放现象，静电进入显示区后，容易导致显示区上的信号线等导电结构被击穿，从而引起显示不良。
公开内容
本公开提供一种显示基板，包括：显示区和位于所述显示区一侧的绑定区，所述绑定区包括多个间隔设置的绑定子区，各所述绑定子区沿显示区边缘的延伸方向排布，且所述绑定子区用于绑定覆晶薄膜，其中，
所述绑定区上设置有第一防静电层，所述第一防静电层的至少一部分位于相邻的所述绑定子区之间，所述第一防静电层与参考信号端电连接。
在一些实施方式中，所述显示基板还包括信号端，所述信号端配置为向所述显示区提供显示信号，位于所述绑定区内靠近所述显示区的一侧，且所述信号端位于所述显示区与所述第一防静电层之间， 通过所述第一防静电层与外界隔离。
在一些实施方式中，所述参考信号端设置在所述绑定子区上，且配置为能够通过所述覆晶薄膜电连接至外部接地端。
在一些实施方式中，所述第一防静电层包括第一防静电子层和第二防静电子层，所述第二防静电子层设置在所述第一防静电子层的靠近所述显示区的一侧，所述第一防静电子层和所述第二防静电子层均与所述参考信号端电连接。
在一些实施方式中，所述第一防静电子层与所述第二防静电子层电隔离设置。
在一些实施方式中，所述第一防静电层上设置有第一通孔。
在一些实施方式中，所述第一通孔为条形通孔。
在一些实施方式中，所述显示基板还包括依次连接的第一边框区、第二边框区和第三边框区，所述第一边框区、所述第二边框区、所述第三边框区和所述绑定区围绕所述显示区，且所述第一边框区、所述第二边框区和所述第三边框区上均设置有第二防静电层，所述第二防静电层与所述参考信号端电连接。
在一些实施方式中，所述显示基板还包括导电层，所述导电层包括连接线和与所述连接线并联的辅助导电部，所述第二防静电层通过所述连接线与所述参考信号端电连接。
在一些实施方式中，所述第二防静电层的靠近所述显示基板角部的位置设置有第二通孔，所述第二通孔中设置有对位标记，所述对位标记用于位置对准及调整。
本公开还提供一种显示装置，包括上述的显示基板，
所述显示装置还包括覆晶薄膜，所述覆晶薄膜的一端与所述绑定子区绑定，所述覆晶薄膜的另一端将与所述驱动电路板绑定；
所述驱动电路板上设置有接地端，所述参考信号端通过所述覆晶薄膜与所述驱动电路板上的接地端电连接。
在一些实施方式中，所述第一防静电层与邻近该第一防静电层的所述覆晶薄膜在第一方向上部分重叠，所述第一方向为所述绑定区与所述显示区的排列方向。
在一些实施方式中，所述覆晶薄膜包括本体部和突出部，所述突出部自所述本体部朝向相邻的所述覆晶薄膜突出；
所述第一防静电子层包括第一防静电部、第二防静电部和第三防静电部，所述第二防静电部位于相邻的两个所述覆晶薄膜的本体部之间，所述第一防静电部位于所述第二防静电部的远离所述显示区的一侧，且所述第一防静电部的至少一部分位于相邻的两个所述覆晶薄膜的突出部之间，所述第三防静电部位于所述第二防静电部的靠近所述显示区的一侧。
在一些实施方式中，所述第一防静电部、所述第二防静电部和所述第三防静电部形成为一体结构。
附图说明
附图用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为本公开实施例提供的显示基板的示意图之一；
图2为本公开实施例提供的第一防静电层上设置通孔的示意图；
图3为本公开实施例提供的显示基板的示意图之二；
图4为本公开实施例提供的对位标记的示意图；
图5为本公开实施例提供的显示装置的示意图；
图6为本公开实施例中第一防静电层的结构示意图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
除非另作定义，本公开实施例使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括” 或者“包含”等类似的词语意指出现在该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开提供一种显示基板，图1为本公开实施例提供的显示基板的示意图之一，如图1所示，所述显示基板包括：显示区1和位于显示区1一侧的绑定区2。绑定区2包括多个间隔设置的绑定子区21，绑定子区21用于绑定覆晶薄膜(Chip On Film，COF)。绑定区2上设置有第一防静电层3，第一防静电层3的至少一部分位于相邻的绑定子区21之间，第一防静电层3与参考信号端电连接。
具体地，如图1所示，第一防静电层3可以由金属导电材料制成，绑定区2中的多个绑定子区21可沿显示区1的边缘的延伸方向(例如，图1中的左右方向)排列，相邻的绑定子区21之间具有一定距离，每个绑定子区21上可设置有绑定电极，绑定电极用于与覆晶薄膜上的导电部电连接，从而接收覆晶薄膜提供的驱动信号，进而为显示区1提供显示信号。参考信号端可以设置在绑定子区21上，覆晶薄膜可以与驱动电路板电连接，参考信号端可以通过覆晶薄膜与驱动电路板上的接地端电连接。绑定区2的靠近显示区1的一侧还可以设置有信号端4，在一些实施方式中，该信号端4为公共信号端(VCOM)，用于为显示区1中的公共信号线提供公共电压信号。信号端4的至少一部分可对应于绑定子区21之间的间隔，例如，信号端4的至少一部分可位于第一防静电层3的靠近显示区1的一侧。
在相关技术中，显示基板在制作、移动等过程中产生的静电很容易从绑定子区21之间的间隔传导至信号端4，进而传导至显示区1，从而显示区1内可能发生显示不良。而在本公开实施例中，由于第一防静电层3的至少一部分位于相邻的绑定子区21之间，因此，当相邻的绑定子区21之间产生静电时，第一防静电层3可以将静电及时导出至驱动电路板的接地端，从而对信号端4起到静电防护的作用， 提高显示基板的抗静电能力。
需要说明的是，在本公开实施例中，绑定子区21的具体形状可以和覆晶薄膜的与绑定子区21绑定的部分的形状相同。
如图1所示，第一防静电层3可包括第一防静电子层31和第二防静电子层32，第二防静电子层32可设置在第一防静电子层31的靠近显示区1的一侧，第一防静电子层31和第二防静电子层32均与参考信号端电连接。具体地，第一防静电子层31与第二防静电子层32可电隔离设置。当第一防静电子层31无法将静电完全导出时，可以通过第二防静电子层32将剩余的静电导出，从而提高静电防护的效果。
在一些具体实施方式中，第一防静电层3上可设置有第一通孔。具体地，图2为本公开实施例提供的第一防静电层上设置通孔的示意图。如图2所示，第一通孔V1的形状可以为条形，事实上，根据需要，第一通孔V1的形状也可以为圆形或三角形等形状，在此不做限制。由于第一防静电层3可以由金属导电材料制成，且金属导电材料具有一定的反光性，因此，通过在第一防静电层3上设置第一通孔V1，可以降低第一防静电层3的表面积，从而改善第一防静电层3的反光问题；同时，通过设置第一通孔V1，可以使第一防静电层3呈网状，增加静电的释放路径，提高第一防静电层3的导电能力，使静电可以被第一防静电层3及时地导出。在一些具体实施方式中，第一通孔V1为沿多个绑定子区21的排列方向(例如，图1中的左右方向)延伸的条形通孔，但是，第一通孔V1也可以为垂直于多个绑定子区21的排列方向延伸的条形通孔，例如，可以为沿图1中的上下方向延伸的条形通孔，或者，第一通孔V1还可以是沿其他任意方向延伸的条形通孔，在此不做限制。
图3为本公开实施例提供的显示基板的示意图之二，如图1和图3所示，所述显示基板还包括依次连接的第一边框区11、第二边框区12和第三边框区13，第一边框区11、第二边框区12、第三边框区13和绑定区2围绕显示区1，例如，第一边框区11和第三边框区13分别位于显示区1的相对两侧，第二边框区12和绑定区2分别 位于显示区1的相对两侧，第一边框区11、第二边框区12和第三边框区13中均可设置有第二防静电层5。第二防静电层5也可与绑定区2中的参考信号端电连接。
具体地，如图3所示，第二防静电层5在第一边框区11、第二边框区12、第三边框区13的部分可以分别为条形，可以形成为一体结构，第二防静电层5位于第一边框区11和第三边框区13的部分可分别沿第一边框区11和第三边框区13延伸至绑定区2的两端，且分别与其相邻的绑定子区21上的参考信号端电连接，举例而言，如图3所示，第二防静电层5的位于第一边框区11的部分可以与其所靠近的绑定子区21a上的参考信号端电连接，第二防静电层5的位于第三边框区13的部分可以与其所靠近的绑定子区21b上的参考信号端电连接。通过设置第二防静电层5，可以对显示基板的除绑定区2所在侧之外的另外三侧形成静电保护，使显示基板周边的任意一侧产生静电时，均可以通过相应的防静电层(第一防静电层3或第二防静电层5)将静电及时导出，从而提高显示基板的抗静电能力。
在一些具体实施方式中，本公开实施例的显示基板还可包括导电层6，如图3所示，导电层6包括连接线61和与连接线61并联的辅助导电部62，第二防静电层5可通过连接线61与参考信号端电连接。
具体地，辅助导电部62可以与连接线61同层设置，且设置在连接线61的两侧，从而使连接线61与辅助导电部62形成整层连续的导电层，降低第二防静电层5与参考信号端之间的连接电阻。由公式Q＝I 2RT(Q为热量，I为电流，R为电阻，T为时间)可知，电阻越小，产生的热量越小，从而可以使连接线61被击穿的可能性降低，提高显示基板的抗静电能力。
通常，显示基板的边缘位置可设置有对位标记，该对位标记可以包括多个标记线，形成游标(Vernier Mark)。在制备工艺中，可以根据对位标记对掩膜板、对盒基板或其他结构进行位置调整。对位标记通常采用金属材料制成，但是，这样就会导致在对位标记上积累静电电荷，静电电荷积累到一定程度之后发生静电释放，较大的瞬时 电流可能进入邻近的第二防静电层5，容易导致第二防静电层5被击穿，引起显示不良。
为了防止这一现象，本公开实施例中，可以增加对位标记与显示基板边缘之间的距离，从而改善在对位标记上积累静电电荷的问题。图4为本公开实施例提供的对位标记的示意图，如图4所示，第二防静电层5的靠近显示基板的角部的位置可设置有第二通孔V2，第二通孔V2中可设置有对位标记51。
相较于将对位标记51设置在显示基板的边缘处，本公开实施例中将对位标记51设置在第二通孔V2中，可以使对位标记51与显示基板的边缘的距离增大，防止静电电荷在对位标记51上积累进而产生静电释放而击穿附近的第二防静电层5。可以理解的是，用于与显示基板相对设置的对盒基板上也可以设置有对位标记，在使显示基板上的对位标记51与显示基板的边缘的距离增大后，还可以将对盒基板上的对位标记的位置进行相应调整，以使显示基板上的对位标记51和对盒基板上的对位标记相对应。
当然，在本公开实施例中，也可以直接将对位标记51去除，从而防止静电进入显示基板，进而防止第二防静电层5被击穿。
本公开实施例还提供一种显示装置，图5为本公开实施例提供的显示装置的示意图。如图5所示，所述显示装置包括上述实施例的显示基板，所述显示装置还包括：覆晶薄膜7，覆晶薄膜7的一端与绑定子区21绑定，覆晶薄膜的另一端将与驱动电路板绑定。驱动电路板上可设置有接地端，参考信号端通过覆晶薄膜7与驱动电路板上的接地端电连接。
具体地，参考信号端可以设置在绑定子区21上，覆晶薄膜7上可以设置接地信号线，接地信号线的一端与参考信号端电连接，另一端与驱动电路板上的接地端电连接，从而使参考信号端通过覆晶薄膜7与驱动电路板上的接地端电连接。每个绑定子区21上可以设置有绑定电极，覆晶薄膜7的一端与绑定子区21绑定是指，覆晶薄膜7一端的导电部与绑定子区21上的绑定电极电连接；覆晶薄膜的另一端将与驱动电路板绑定是指，覆晶薄膜7另一端的导电部将与驱动电 路板上的信号输出部电连接。绑定区2的靠近显示区1的一侧还可以设置有信号端4，在一些实施方式中，该信号端4为公共信号端(VCOM)，用于为显示区1中的公共信号线提供公共电压信号。信号端4的至少一部分可对应于绑定子区21之间的间隔，例如，信号端4的至少一部分可位于第一防静电层3的靠近显示区1的一侧。
采用本公开实施例的显示装置，由于显示基板中，第一防静电层3的至少一部分位于相邻的绑定子区21之间，因此，当相邻的绑定子区21之间产生静电时，第一防静电层3可以将静电及时导出至驱动电路板的接地端，从而对信号端4起到静电防护的作用，提高显示基板的抗静电能力。
如图5所示，信号端4通过第一防静电层3与外界隔离，具体地，第一防静电层3可以与邻近该第一防静电层3的覆晶薄膜7例如在第一方向上部分重叠，第一方向可以为绑定区2与所述显示区1的排列方向(如图5中的上下方向)。第一防静电层3与邻近该第一防静电层3的覆晶薄膜7在第一方向上部分重叠，从而可以使信号端4可以通过第一防静电层3完全与外界隔离，提高静电防护效果。
在一些具体实施方式中，覆晶薄膜7包括本体部72和突出部71，每个覆晶薄膜7的突出部71自本体部72朝向相邻的覆晶薄膜7突出。图6为本公开实施例中第一防静电层的结构示意图，结合图5和图6所示，第一防静电子层31可包括第一防静电部311、第二防静电部312和第三防静电部313，第二防静电部312位于相邻的覆晶薄膜7的本体部72之间，第一防静电部311位于第二防静电部312的远离显示区1的一侧，且第一防静电部311的至少一部分位于相邻的覆晶薄膜7的突出部71之间，第三防静电部313位于第二防静电部312的靠近显示区1的一侧。在一些具体实施方式中，第一防静电部311、第二防静电部312和第三防静电部313形成为一体结构。
在本公开实施例中，第一防静电层3还可包括第二防静电子层32，第二防静电子层32可以位于第三防静电部313的靠近显示区1的一侧。第一防静电子层31和第二防静电子层32均与参考信号端电连接，且第一防静电子层31和第二防静电子层32可电隔离设置。
可以理解的是，以上实施例及实施方式仅仅是为了说明本公开的原理而采用的示例性实施例及实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为落入本公开的保护范围。

Claims (14)

  1. 一种显示基板，包括，显示区和位于所述显示区一侧的绑定区，所述绑定区包括多个间隔设置的绑定子区，各所述绑定子区沿显示区边缘的延伸方向排布，且所述绑定子区用于绑定覆晶薄膜，其中，
    所述绑定区上设置有第一防静电层，所述第一防静电层的至少一部分位于相邻的所述绑定子区之间，所述第一防静电层与参考信号端电连接。
  2. 根据权利要求1所述的显示基板，还包括信号端，所述信号端配置为向所述显示区提供显示信号，位于所述绑定区内靠近所述显示区的一侧，且所述信号端位于所述显示区与所述第一防静电层之间，通过所述第一防静电层与外界隔离。
  3. 根据权利要求1所述的显示基板，其中，所述参考信号端设置在所述绑定子区上，且配置为能够通过所述覆晶薄膜电连接至外部接地端。
  4. 根据权利要求1所述的显示基板，其中，所述第一防静电层包括第一防静电子层和第二防静电子层，所述第二防静电子层设置在所述第一防静电子层的靠近所述显示区的一侧，所述第一防静电子层和所述第二防静电子层均与所述参考信号端电连接。
  5. 根据权利要求4所述的显示基板，其中，所述第一防静电子层与所述第二防静电子层电隔离设置。
  6. 根据权利要求1所述的显示基板，其中，所述第一防静电层上设置有第一通孔。
  7. 根据权利要求6所述的显示基板，其中，所述第一通孔为条 形通孔。
  8. 根据权利要求1所述的显示基板，还包括依次连接的第一边框区、第二边框区和第三边框区，所述第一边框区、所述第二边框区、所述第三边框区和所述绑定区围绕所述显示区，且所述第一边框区、所述第二边框区和所述第三边框区上均设置有第二防静电层，所述第二防静电层与所述参考信号端电连接。
  9. 根据权利要求8所述的显示基板，还包括导电层，所述导电层包括连接线和与所述连接线并联的辅助导电部，所述第二防静电层通过所述连接线与所述参考信号端电连接。
  10. 根据权利要求8所述的显示基板，其中，所述第二防静电层的靠近所述显示基板角部的位置设置有第二通孔，所述第二通孔中设置有对位标记，所述对位标记用于位置对准及调整。
  11. 一种显示装置，包括权利要求1至10中任一项所述的显示基板，
    所述显示装置还包括覆晶薄膜，所述覆晶薄膜的一端与所述绑定子区绑定，所述覆晶薄膜的另一端将与驱动电路板绑定；
    所述驱动电路板上设置有接地端，所述参考信号端通过所述覆晶薄膜与所述驱动电路板上的接地端电连接。
  12. 根据权利要求11所述的显示装置，其中，所述第一防静电层与邻近该第一防静电层的所述覆晶薄膜在第一方向上部分重叠，所述第一方向为所述绑定区与所述显示区的排列方向。
  13. 根据权利要求11所述的显示装置，其中，所述覆晶薄膜包括本体部和突出部，所述突出部自所述本体部朝向相邻的所述覆晶薄膜突出；
    所述第一防静电子层包括第一防静电部、第二防静电部和第三防静电部，所述第二防静电部位于相邻的所述覆晶薄膜的本体部之间，所述第一防静电部位于所述第二防静电部的远离所述显示区的一侧，且所述第一防静电部的至少一部分位于相邻的所述覆晶薄膜的突出部之间，所述第三防静电部位于所述第二防静电部的靠近所述显示区的一侧。
  14. 根据权利要求13所述的显示装置，其中，所述第一防静电部、所述第二防静电部和所述第三防静电部形成为一体结构。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114296268A (zh) * 2022-01-21 2022-04-08 惠科股份有限公司 液晶显示面板及显示装置
TWI806771B (zh) * 2022-09-16 2023-06-21 英業達股份有限公司 抗靜電型電子裝置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111179743B (zh) * 2020-02-19 2022-01-25 京东方科技集团股份有限公司 显示基板和显示装置

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001281687A (ja) * 2000-03-28 2001-10-10 Nec Corp 液晶表示装置の実装構造及びその製造方法
US20100079693A1 (en) * 2008-09-30 2010-04-01 Epson Imaging Devices Corporation Liquid crystal device and electronic apparatus
CN104656293A (zh) * 2015-03-18 2015-05-27 合肥京东方光电科技有限公司 液晶显示面板及其制作方法、显示装置
CN107342284A (zh) * 2017-08-14 2017-11-10 武汉天马微电子有限公司 显示基板及显示装置
CN108766994A (zh) * 2018-06-20 2018-11-06 武汉天马微电子有限公司 有机发光显示面板和有机发光显示装置
CN109671703A (zh) * 2018-12-14 2019-04-23 厦门天马微电子有限公司 显示面板及显示装置
CN109709731A (zh) * 2019-02-25 2019-05-03 京东方科技集团股份有限公司 一种阵列基板及显示装置
CN110471567A (zh) * 2019-08-15 2019-11-19 昆山国显光电有限公司 显示装置
CN111179743A (zh) * 2020-02-19 2020-05-19 京东方科技集团股份有限公司 显示基板和显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101577667B1 (ko) * 2014-05-27 2015-12-16 엘지디스플레이 주식회사 액정표시패널 및 그 장치
CN205452280U (zh) * 2016-03-30 2016-08-10 京东方科技集团股份有限公司 静电防护结构、阵列基板及显示装置
CN105807482A (zh) * 2016-05-26 2016-07-27 京东方科技集团股份有限公司 一种彩膜基板及显示装置
US10955711B2 (en) * 2016-08-04 2021-03-23 Samsung Display Co., Ltd. Liquid crystal display device
CN106324882A (zh) * 2016-10-31 2017-01-11 上海天马微电子有限公司 一种液晶显示面板及液晶显示装置
CN106773387B (zh) * 2016-12-28 2019-07-02 武汉华星光电技术有限公司 液晶显示面板的静电防护结构
CN107247373B (zh) * 2017-08-01 2020-05-22 厦门天马微电子有限公司 显示面板和显示装置
TWI657300B (zh) * 2017-08-10 2019-04-21 友達光電股份有限公司 陣列基板
CN107748457B (zh) * 2017-11-03 2024-05-28 惠科股份有限公司 显示装置
CN108363243B (zh) * 2018-03-09 2021-11-23 京东方科技集团股份有限公司 一种摩擦配向基板及其制作方法、液晶显示面板
CN108711565B (zh) * 2018-03-30 2020-05-12 京东方科技集团股份有限公司 一种显示基板及其制作方法、显示面板
CN109064902B (zh) * 2018-09-20 2020-12-11 武汉天马微电子有限公司 一种显示面板及显示装置
CN109491122B (zh) * 2018-12-27 2020-12-25 武汉华星光电技术有限公司 防静电的显示面板及制备方法
CN109979371A (zh) * 2019-04-15 2019-07-05 武汉华星光电技术有限公司 一种显示面板及装置
CN209592036U (zh) * 2019-05-31 2019-11-05 北京京东方技术开发有限公司 显示基板和显示装置
CN110286513B (zh) * 2019-06-27 2022-04-26 昆山国显光电有限公司 显示面板母板及显示面板的加工方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001281687A (ja) * 2000-03-28 2001-10-10 Nec Corp 液晶表示装置の実装構造及びその製造方法
US20100079693A1 (en) * 2008-09-30 2010-04-01 Epson Imaging Devices Corporation Liquid crystal device and electronic apparatus
CN104656293A (zh) * 2015-03-18 2015-05-27 合肥京东方光电科技有限公司 液晶显示面板及其制作方法、显示装置
CN107342284A (zh) * 2017-08-14 2017-11-10 武汉天马微电子有限公司 显示基板及显示装置
CN108766994A (zh) * 2018-06-20 2018-11-06 武汉天马微电子有限公司 有机发光显示面板和有机发光显示装置
CN109671703A (zh) * 2018-12-14 2019-04-23 厦门天马微电子有限公司 显示面板及显示装置
CN109709731A (zh) * 2019-02-25 2019-05-03 京东方科技集团股份有限公司 一种阵列基板及显示装置
CN110471567A (zh) * 2019-08-15 2019-11-19 昆山国显光电有限公司 显示装置
CN111179743A (zh) * 2020-02-19 2020-05-19 京东方科技集团股份有限公司 显示基板和显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114296268A (zh) * 2022-01-21 2022-04-08 惠科股份有限公司 液晶显示面板及显示装置
TWI806771B (zh) * 2022-09-16 2023-06-21 英業達股份有限公司 抗靜電型電子裝置

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