WO2021147738A1 - 一种显示面板及显示装置 - Google Patents

一种显示面板及显示装置 Download PDF

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Publication number
WO2021147738A1
WO2021147738A1 PCT/CN2021/071552 CN2021071552W WO2021147738A1 WO 2021147738 A1 WO2021147738 A1 WO 2021147738A1 CN 2021071552 W CN2021071552 W CN 2021071552W WO 2021147738 A1 WO2021147738 A1 WO 2021147738A1
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WIPO (PCT)
Prior art keywords
area
shift register
output transistor
display
gate shift
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Application number
PCT/CN2021/071552
Other languages
English (en)
French (fr)
Inventor
魏昕宇
张锴
郭永林
肖云升
王苗
范鸿梅
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/778,606 priority Critical patent/US20230005410A1/en
Publication of WO2021147738A1 publication Critical patent/WO2021147738A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • This application relates to the field of display technology, in particular to a display panel and a display device.
  • some special-shaped areas will be set on the display panel, such as the slot in the area where the front camera is located, or the display Chamfer at the edge of the panel.
  • the existence of the irregular area causes the number of pixels connected to the writing gate line corresponding to the irregular area to be different from the number of pixels connected to the writing gate line corresponding to the normal area, that is, the load of the writing gate line corresponding to the irregular area is less than that of the normal area.
  • the load of the write gate line results in poor display uniformity in each area of the display panel.
  • a compensation capacitor is provided to be electrically connected to the write gate line.
  • the compensation capacitor needs to occupy a larger area, that is, the frame area of the display panel is increased. , It is not conducive to the narrow bezel design of the display panel.
  • the embodiments of the present application provide a display panel and a display device, and the specific solutions are as follows:
  • an embodiment of the present application provides a display panel, the display panel including: a display area and a peripheral area surrounding the display area, the display area including a first sub-display area and a second sub-display area;
  • the display area includes multiple rows of pixels and write gate lines electrically connected to the pixels in each row;
  • the pixels include a pixel circuit and a light emitting device, the pixel circuit is electrically connected to the write gate line, the The pixel circuit is configured to receive a data signal under the control of the write gate line, and drive the light-emitting device to emit light according to the received data signal;
  • the number of pixels in a row in the second sub-display area is less than the number of pixels in a row in the first sub-display area
  • the peripheral area includes a gate shift register electrically connected to each of the write gate lines, the shift register includes an output transistor, the source electrode of the output transistor is electrically connected to a clock signal line, and the output The drain electrode of the transistor is electrically connected to the write gate line, and the output transistor is used to output an effective pulse signal to the write gate line;
  • the gate shift register that is electrically connected to the write gate line in the first sub-display area is a first gate shift register, and is connected to the gate shift register in the second sub-display area.
  • the gate shift register electrically connected to the write gate line is a second gate shift register; the width-to-length ratio of the channel region of the output transistor in the second gate shift register is smaller than the The width to length ratio of the channel region of the output transistor in the first gate shift register.
  • the length of the channel region of the output transistor in the second gate shift register and the first gate shift are equal;
  • the width of the channel region of the output transistor in the second gate shift register is smaller than the width of the channel region of the output transistor in the first gate shift register.
  • the width of the channel region of the output transistor in the second gate shift register and the first gate shift are equal;
  • the length of the channel region of the output transistor in the second gate shift register is greater than the length of the channel region of the output transistor in the first gate shift register.
  • the width-to-length ratio of the channel region of the output transistor in the second gate shift register is that of the first gate
  • the width-to-length ratio of the channel region of the output transistor in the shift register is 20%-50%.
  • the second sub-display area includes a first area, a second area, and a middle area in the extending direction of the write gate line. , The first area and the second area are spaced apart by the intermediate area;
  • first area and the second area include multiple rows of the pixels.
  • the middle area is groove-shaped, and one side of the groove-shaped opening is located next to the first boundary of the display panel.
  • the length of the side of the middle region close to the opening in the extending direction of the writing gate line is greater than that of the middle region far away from the The length of one side of the opening in the extending direction of the write gate line.
  • the aspect ratio of the channel region of the output transistor in the second gate shift register close to the first boundary is It is smaller than the width-to-length ratio of the channel region of the output transistor in the second gate shift register far from the first boundary.
  • the write gate line in the first region and the write gate line in the second region are in the The middle regions are disconnected from each other, and the disconnected write gate lines are each connected to the second gate shift register.
  • At least part of the edges of the first area, the second area, and the middle area are curved, rounded, or chamfered. Or incision
  • Each row of the pixels in the first area and the second area extends to the curved edge, round corner, chamfer or cut.
  • an embodiment of the present application also provides a display device, which includes the display panel provided in any one of the foregoing implementations.
  • FIG. 1 is one of the structural schematic diagrams of a display panel provided by an embodiment of the application
  • FIG 2 is the second schematic diagram of the structure of the display panel provided by the embodiment of the application.
  • FIG. 3 is one of the structural schematic diagrams of the pixel circuit provided by the embodiment of the application.
  • FIG. 4 is a second structural diagram of a pixel circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of a structure of a gate shift register provided by an embodiment of the application.
  • FIG. 6 is a timing diagram corresponding to the gate shift register shown in FIG. 5;
  • FIG. 7 is a schematic top view of the structure of an output transistor provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of the size of the channel region of an output transistor provided by an embodiment of the application.
  • FIG. 9 is a schematic diagram of a structure of a second sub-display area provided by an embodiment of the application.
  • the display panel in the related art may have a special-shaped area, and the special-shaped area may be a groove/hole in the area where the front camera is located, or a chamfer at the edge of the display panel.
  • the existence of the irregular area causes the number of pixels connected by a row of gate lines in the irregular area to be less than the number of pixels connected by a row of gate lines in the normal area, that is, the load of the gate lines in the irregular area is less than the load of the gate lines in the normal area, resulting in the display panel
  • the display uniformity of each area is poor.
  • a compensation capacitor is set to be electrically connected to the gate line in the irregular area.
  • the compensation capacitor needs to occupy a larger area, that is, the frame area of the display panel is increased, which is not conducive to The display panel realizes a narrow bezel design.
  • embodiments of the present application provide a display panel and a display device.
  • the specific implementations of a display panel and a display device provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only used to illustrate and explain the application, and are not used to limit the application. And if there is no conflict, the embodiments in the application and the features in the embodiments can be combined with each other.
  • an embodiment of the present application provides a display panel.
  • the display panel includes: a display area A and a peripheral area B surrounding the display area A.
  • the display area A includes a first sub-display. Area A1 and a second sub-display area A2; display area A includes multiple rows of pixels PX and write gate lines G electrically connected to each row of pixels PX; wherein the number of pixels in one row of pixels PX in the second sub-display area A2 is smaller than the first row of pixels PX The number of pixels of one row of pixels PX in one sub-display area A1.
  • the peripheral area B includes a gate shift register S1 or S2 electrically connected to each write gate line G (the specific structure of the gate shift register is not shown in FIGS. 1 and 2).
  • the load of each write gate line G in the second sub-display area is less than If the load of each write gate line G in the first sub-display area A1 is not compensated, the charging time of each pixel in the second sub-display area will be longer, making the first sub-display area and the second sub-display area longer.
  • the brightness of pixels in the display area is inconsistent.
  • the pixel PX includes a pixel circuit P1 and a light-emitting device P2.
  • the pixel circuit P1 is electrically connected to the writing gate line G.
  • the pixel circuit P1 is used to receive data signals under the control of the writing gate line G, and according to The received data signal drives the light emitting device P2 to emit light.
  • the pixel circuit P1 includes a driving transistor DTFT, a switching transistor T1, and a capacitor C1.
  • the switching transistor T1 receives the data signal D under the control of the gate line G.
  • the pixel circuit P1 includes a driving transistor DTFT, switching transistors T1 to T4, capacitors C1 and C2, and the switching transistor T2 receives the data signal D under the control of the gate line G2.
  • the threshold voltage, V S is the source electrode voltage of the driving transistor DTFT, and V G is the gate voltage of the driving transistor DTFT.
  • the charging time of the pixels in the first sub-display area and the second sub-display area corresponds to the write gate line G in the first sub-display area A1.
  • the connected gate shift register is the first gate shift register S1
  • the gate shift register electrically connected to the write gate line G in the second sub-display area A2 is the second gate shift register S2
  • the aspect ratio of the channel region of the output transistor T5 in the second gate shift register S2 is smaller than the aspect ratio of the channel region of the output transistor in the first gate shift register S1.
  • the gate shift register includes an output transistor.
  • the source electrode of the output transistor is electrically connected to the corresponding clock signal line, and the drain electrode of the output transistor is electrically connected to the corresponding write gate line.
  • the output transistor is used to output a valid output to the write gate line. Pulse signal.
  • the gate shift register can output a pulse signal to the corresponding write gate line, and only an effective pulse signal can control the pixel circuit to receive the data signal. Taking the pixel circuits of Figures 3 and 4 as an example, if the switching transistor T1 of Figure 3 is a P-type switching transistor, then the effective pulse signal written on the gate line is a low potential signal.
  • the switching transistor T1 of Figure 3 is an N-type switching transistor Switching transistor, the effective pulse signal written on the gate line is a high potential signal. If the switching transistor T2 in Figure 4 is a P-type switching transistor, then the effective pulse signal written on the gate line is a low potential signal. The switching transistor T2 is an N-type switching transistor, so the effective pulse signal written on the gate line is a high potential signal.
  • the effective pulse signal output by the gate shift register is output by the output transistor. Therefore, the performance of the output transistor can determine the effective pulse signal written on the gate line.
  • the aspect ratio of the channel region is smaller than the aspect ratio of the channel region of the output transistor in the first gate shift register, that is, by reducing the width and length of the channel region of the output transistor in the second gate shift register Ratio, the on-resistance of the output transistor in the second gate shift register can be increased, and the RC delay becomes larger, so that the rising edge (Tr) and falling edge time (Tf) of the output effective pulse signal increase, and then decrease
  • the charging time of each pixel circuit in the second sub-display area reduces the difference between the drive current of each pixel in the second sub-display area and the drive current of each pixel in the first sub-display area, so that the The brightness is consistent with the brightness area of each pixel in the first sub-display area.
  • the gate line used to control the reception of the data signal D in this application is the write gate line G.
  • the gate line G1 connected to the gate of the switching transistor T1 in FIG. 3 is the write gate line, such as FIG. 4
  • the gate line G2 connected to the gate of the switching transistor T2 is a write gate line.
  • EM1, EM2, and G1 in FIG. 4 these are not write gate lines.
  • the write gate line corresponding to the pixel circuit is a gate line used to control the pixel circuit to receive data signals.
  • the gate shift register in addition to the output transistor T5 and the clock signal terminal CB, the gate shift register also includes: T1 transistor, T2 transistor, T3 transistor, T4 transistor, T6 transistor , T7 transistors, T8 transistors, C1 capacitors and C2 capacitors, and also include GI signal terminals, VL signal terminals, VH signal terminals, CK clock signal terminals and GO output signal terminals for providing signals, wherein the output signal terminal GO is connected to
  • the corresponding write gate lines in the display area are electrically connected, in addition to the connection nodes between the transistors, such as the N1 node, the N2 node, the N3 node, and the N4 node.
  • the working process of the shift register shown in FIG. 5 is the same as the working process of the shift register in the related art, and will not be repeated here.
  • FIG. 5 only uses the structure of a gate shift register as an example to illustrate the connection relationship of the output transistors, and does not specifically limit the structure of the first gate shift register and the second gate shift register.
  • the gate shift register and the second gate shift register may have the structure shown in FIG. 5, or may have any other gate shift register structure.
  • the structures of the first gate shift register and the second gate shift register may be the same or different, as long as the output transistors included in the shift register comply with the foregoing principles, which are not specifically limited herein.
  • the gate shift register shown in FIG. 5 can be driven by the timing diagram shown in FIG. 6, which includes five driving stages (T1, T2, T3, T4, and T5).
  • the corresponding signal terminals (GI, CK, and CB) provide corresponding driving signals, so that the output signal terminal GO provides a gate driving signal to the corresponding write gate line.
  • the timing diagram shown in FIG. 6 is only one driving method of the shift register shown in FIG. 5, and other timings may also be used for driving, which can be selected according to actual needs, and is not specifically limited here.
  • the arrangement of pixels in the second sub-display area may be as shown in FIG. 1.
  • the pixels PX in the same row are electrically connected to different write gate lines G, or As shown in FIG. 2, the pixels PX in the same row are electrically connected to the same write gate line G, which is not specifically limited here.
  • the position of the grooved area in the second sub-display area can be determined according to actual design requirements, and is not limited to the two forms shown in Figure 1 and Figure 2, and can also be any other position or shape. There is no specific limitation.
  • FIG. 7 is a schematic diagram of a top view structure of an output transistor provided by an embodiment of the application, which includes a semiconductor layer Poly, a gate layer Ga on the semiconductor layer Poly, and a source electrode S and a drain electrode on the gate layer Ga D, and an insulating layer exists between the semiconductor layer Poly, the gate layer Ga, and the layer where the source electrode S and the drain electrode D are located.
  • the source electrode S and the drain electrode D are electrically connected to the semiconductor layer Poly through via holes, respectively, and the semiconductor layer Poly includes a source doped region and a drain doped region.
  • the distance between the source doped region and the drain doped region in a transistor is called the length of the channel region, and the width of the channel region perpendicular to its extension direction is called the channel width.
  • the width of the channel region of the output transistor is W1+W2+W3
  • the length of the channel region of the output transistor is L
  • the aspect ratio of the channel region of the output transistor is (W1+W2 +W3)/L.
  • the first sub-display area and the channel width-to-length ratio of the output transistor in the first gate shift register and the channel width to length ratio of the output transistor in the second gate shift register can be adjusted to make the first sub-display area and The display brightness of each pixel in the second sub-display area tends to be consistent.
  • adjustment methods There are two specific adjustment methods:
  • the length LB of the channel region of the output transistor in the second gate shift register is equal to the length LA of the channel region of the output transistor in the first gate shift register;
  • the width WB of the channel region of the output transistor in the second gate shift register is smaller than the width WA of the channel region of the output transistor in the first gate shift register.
  • the smaller the width-to-length ratio of the channel region of the output transistor the longer the time for the rising edge and the falling edge of the signal provided to the corresponding write gate line, so that the The charging time of the pixel circuit is shortened to reduce the driving current difference of the pixel circuit, so that the brightness of the light-emitting devices in the first sub-display area and the second sub-display area are consistent.
  • width-to-length ratio WB/LB of the channel region of the output transistor in the second gate shift register smaller than that of the output in the first gate shift register.
  • the width-to-length ratio of the channel region of the transistor WA/LA, when LB and LA are equal, can make WB ⁇ WA, so that WB/LB ⁇ WA/LA.
  • width WB of the channel region of the output transistor in the second gate shift register is equal to the width WA of the channel region of the output transistor in the first gate shift register
  • the length LB of the channel region of the output transistor in the second gate shift register is greater than the length LA of the channel region of the output transistor in the first gate shift register.
  • the smaller the width-to-length ratio of the channel region of the output transistor the longer the time for the rising edge and the falling edge of the signal provided to the corresponding write gate line, so that the The charging time of the pixel circuit is shortened to reduce the driving current difference of the pixel circuit, so that the brightness of the light-emitting devices in the first sub-display area and the second sub-display area are consistent.
  • width-to-length ratio WB/LB of the channel region of the output transistor in the second gate shift register smaller than that of the output in the first gate shift register.
  • the width-to-length ratio of the channel region of the transistor WA/LA, when WB and WA are equal, can make LB>LA, so that WB/LB ⁇ WA/LA.
  • FIGS. 7 and 8 are only a schematic description of the structure of the output transistor provided by the embodiment of the present application.
  • the output transistor is not limited to the structure shown in FIGS. 7 and 8, and may be any other conforming to the present invention.
  • the output transistor of the application implementation principle is not specifically limited here.
  • the width-to-length ratio of the channel region of the output transistor in the second gate shift register is the width of the channel region of the output transistor in the first gate shift register.
  • the length ratio is 20% to 50%.
  • the width-to-length ratio of the channel region of the output transistor in the second gate shift register is the ratio of the width-to-length ratio of the channel region of the output transistor in the first gate shift register.
  • the time of the rising edge of the driving signal provided by the second gate shift register to the write gate line increases by 2.29%, and the time of the falling edge increases by 7.39%; in the second gate shift register, the time of the output transistor
  • the width-to-length ratio of the channel region is 20% of the width-to-length ratio of the channel region of the output transistor in the first gate shift register
  • the rising edge of the drive signal provided by the second gate shift register to the write gate line The time of the falling edge is increased by 5.14%, and the time of the falling edge is increased by 18.16%.
  • the second sub-display area includes a first area a1, a second area a2, and a middle area a3 in the extending direction of the write gate line.
  • the first area a1 and the second area a2 are spaced apart by the middle area a3;
  • first area a1 and the second area a2 include multiple rows of pixels.
  • the second sub-display area is divided into three areas by the middle area, where the first area and the second area are respectively provided There are multiple rows of pixels, and no pixels are set in the middle area. Slots can be set in the middle area to hold devices such as front cameras, photosensitive elements, and earpieces, so that the display device has other functions besides display.
  • the middle area is groove-shaped, and one side of the groove-shaped opening is located next to the first boundary of the display panel.
  • the middle area may be in the shape of a groove and arranged adjacent to a border of the display panel.
  • the middle area is adjacent to the upper border of the display panel (No. A boundary) is taken as an example for description, of course, it can also be located in other areas of the display panel, which is not specifically limited here.
  • the middle area may be not only a groove shape, but also a closed shape such as a rectangle, a circle, an ellipse, or a polygon, which is not specifically limited herein.
  • the length of the side of the middle region near the opening in the extending direction of the write gate line is greater than the length of the side of the middle region away from the opening in the extending direction of the writing gate line.
  • the middle area can be set as an area with different widths according to different devices to be set.
  • the width is smaller, the corresponding first area
  • the width of the second area and the second area are relatively large, and more pixels can be set.
  • the width is large, the width of the first area and the second area are relatively small, and the set pixels are also less.
  • the middle area is a groove shape with a wide top and a narrow bottom
  • the first area and the second area close to the upper boundary of the display panel include more pixels and are far from the upper boundary of the display panel.
  • the first area and the second area include fewer pixels.
  • the width-to-length ratio of the channel region of the output transistor of the second gate shift register close to the first boundary can be made smaller than that of the second gate shift register far from the first boundary.
  • the width-to-length ratio of the channel region of the output transistor makes the display brightness area uniform in each region of the display panel, and improves the display uniformity of the display panel.
  • the write gate line in the first region and the write gate line in the second region are disconnected from each other in the middle region, and the disconnected write gate line Each is connected to a second gate shift register.
  • the pixels in the second sub-display area are arranged in the structure shown in FIG. 1. Since there are grooves in the middle area, the write gate line in the first area and the second area can be simplified to simplify the design.
  • the write gate line in the area is disconnected, and a second gate shift register is respectively arranged at the peripheral area corresponding to the first area and the second area to drive the pixels in the first area and the second area.
  • the write gate line in the first area and the write gate line in the second area may also be electrically connected to provide a first gate shift register, but it will increase the difficulty of the design accordingly. How to set can be selected according to actual usage, and there is no specific limitation here.
  • At least part of the edges of the first area a1, the second area a2, and the middle area a3 are curved edges, rounded corners, chamfered corners, or cuts. ;
  • Each row of pixels in the first area a1 and the second area a2 extends to a curved edge, a rounded corner, a chamfer, or a cut.
  • the boundaries of the first area a1, the second area a2, and the middle area a3 all include rounded corners or chamfered corners.
  • the setting will also cause differences in the number of pixels in different rows in the second sub-display area. This difference can be compensated by adjusting the width-to-length ratio of the channel region of the output transistor in the corresponding second shift register to improve each The display uniformity of the area.
  • an embodiment of the present application also provides a display device, which includes the display panel provided in any of the foregoing embodiments.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.
  • Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the application.
  • the implementation of the display device can be referred to the embodiment of the above-mentioned display panel, and the repetition will not be repeated.
  • the embodiments of the present application provide a display panel and a display device.
  • the display panel includes a display area and a peripheral area surrounding the display area.
  • the display area includes a first sub-display area and a second sub-display area; the display area includes multiple rows of pixels and A write gate line electrically connected to each row of pixels; the number of pixels in a row in the second sub-display area is less than the number of pixels in a row in the first sub-display area;
  • the peripheral area includes gates electrically connected to each write gate line A shift register, the shift register includes an output transistor, the output transistor is used to output an effective pulse signal to the write gate line; wherein, the gate shift register electrically connected to the write gate line in the first sub-display area is the first A gate shift register, the gate shift register electrically connected to the write gate line in the second sub-display area is the second gate shift register; the output transistor in the second gate shift register
  • the aspect ratio of the track region is smaller than the aspect ratio of the channel region of the output transistor
  • the width-to-length ratio of the channel region of the output transistor in the second gate shift register corresponding to the second sub-display area is reduced, thereby reducing the charging time of each pixel in the second sub-display area, so that the second The brightness of each pixel in the sub-display area is consistent with the brightness area of each pixel in the first sub-display area.

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Abstract

本申请公开了一种显示面板及显示装置，该显示面板包括：显示区域和围绕显示区域的周边区域，显示区域包括第一子显示区域和第二子显示区域；通过降低第二子显示区域对应的第二栅极移位寄存器内的输出晶体管的沟道区的宽长比，从而降低第二子显示区域内各像素的充电时间，使第二子显示区域内各像素的亮度与第一子显示区域内各像素的亮度区域一致。通过上述设置可以不改变现有的电路结构，且不占用额外的边框面积，在提高显示面板的显示均一性的基础上，更加有利于窄边框的实现。

Description

一种显示面板及显示装置
相关申请的交叉引用
本申请要求在2020年01月21日提交中国专利局、申请号为202010072398.5、申请名称为“一种显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤指一种显示面板及显示装置。
背景技术
随着显示技术的发展，人们对显示装置的要求越来越高，为满足显示装置的一些功能性需求，在显示面板上会设置一些异形区域，如前置摄像头所在区域的挖槽，或者显示面板边缘处的倒角。该异形区域的存在，导致该异形区域对应写入栅线连接的像素数量与正常区域对应的写入栅线连接的像素数量不同，即该异形区域对应的写入栅线的负载小于正常区域的写入栅线的负载，从而致使显示面板的各区域的显示均一性较差。
相关技术中，为增加异形区域对应的写入栅线的负载，会设置补偿电容与该写入栅线电连接，但是，该补偿电容需要占用较大的面积，即增加了显示面板的边框区域，不利于显示面板实现窄边框设计。
因此，如何在实现窄边框的同时提高显示面板的显示均一性，是本领域技术人员亟待解决的技术问题。
发明内容
有鉴于此，本申请实施例提供了一种显示面板及显示装置，具体方案如下：
一方面，本申请实施例提供了一种显示面板，该显示面板包括：显示区 域和围绕所述显示区域的周边区域，所述显示区域包括第一子显示区域和第二子显示区域；
所述显示区域包括多行像素以及与每一行所述像素对应电连接的写入栅线；所述像素包括像素电路和发光器件，所述像素电路与所述写入栅线电连接，所述像素电路用于在所述写入栅线的控制下接收数据信号，并根据接收的所述数据信号驱动所述发光器件发光；
所述第二子显示区域内一行所述像素的数量小于所述第一子显示区域内一行所述像素的数量；
所述周边区域包括：与各所述写入栅线对应电连接的栅极移位寄存器，所述移位寄存器包括输出晶体管，所述输出晶体管的源电极与时钟信号线电连接，所述输出晶体管的漏电极与所述写入栅线电连接，所述输出晶体管用于向所述写入栅线输出有效脉冲信号；
其中，与所述第一子显示区域内的所述写入栅线对应电连接的所述栅极移位寄存器为第一栅极移位寄存器，与所述第二子显示区域内的所述写入栅线对应电连接的所述栅极移位寄存器为第二栅极移位寄存器；所述第二栅极移位寄存器中的所述输出晶体管的沟道区的宽长比小于所述第一栅极移位寄存器中的所述输出晶体管的沟道区的宽长比。
在一种可能的实施方式中，在本申请实施例提供的显示面板中，所述第二栅极移位寄存器中的所述输出晶体管的沟道区的长度与所述第一栅极移位寄存器中的所述输出晶体管的沟道区的长度相等；
所述第二栅极移位寄存器中的所述输出晶体管的沟道区的宽度小于所述第一栅极移位寄存器中的所述输出晶体管的沟道区的宽度。
在一种可能的实施方式中，在本申请实施例提供的显示面板中，所述第二栅极移位寄存器中的所述输出晶体管的沟道区的宽度与所述第一栅极移位寄存器中的所述输出晶体管的沟道区的宽度相等；
所述第二栅极移位寄存器中的所述输出晶体管的沟道区的长度大于所述第一栅极移位寄存器中的所述输出晶体管的沟道区的长度。
在一种可能的实施方式中，在本申请实施例提供的显示面板中，所述第二栅极移位寄存器中的所述输出晶体管的沟道区的宽长比是所述第一栅极移位寄存器中的所述输出晶体管的沟道区的宽长比的20％～50％。
在一种可能的实施方式中，在本申请实施例提供的显示面板中，所述第二子显示区域在所述写入栅线的延伸方向上包括：第一区域、第二区域和中间区域，所述第一区域和所述第二区域被所述中间区域间隔设置；
且仅所述第一区域和所述第二区域包括多行所述像素。
在一种可能的实施方式中，在本申请实施例提供的显示面板中，所述中间区域为凹槽形，且所述凹槽形的开口一侧紧邻所述显示面板的第一边界设置。
在一种可能的实施方式中，在本申请实施例提供的显示面板中，所述中间区域靠近所述开口一侧在所述写入栅线延伸方向上的长度大于所述中间区域远离所述开口一侧在所述写入栅线延伸方向上的长度。
在一种可能的实施方式中，在本申请实施例提供的显示面板中，靠近所述第一边界的所述第二栅极移位寄存器中的所述输出晶体管的沟道区的宽长比小于远离所述第一边界的所述第二栅极移位寄存器中的所述输出晶体管的沟道区的宽长比。
在一种可能的实施方式中，在本申请实施例提供的显示面板中，所述第一区域内的所述写入栅线和所述第二区域内的所述写入栅线在所述中间区域相互断开，且断开后的所述写入栅线各连接一所述第二栅极移位寄存器。
在一种可能的实施方式中，在本申请实施例提供的显示面板中，所述第一区域，所述第二区域，以及所述中间区域的至少部分边缘为曲边、圆角、倒角或切口；
所述第一区域和所述第二区域中的各行所述像素延伸至所述曲边、圆角、倒角或切口。
另一方面，本申请实施例还提供了一种显示装置，该显示装置包括上述任一实施了提供的显示面板。
附图说明
图1为本申请实施例提供的显示面板的结构示意图之一；
图2为本申请实施例提供的显示面板的结构示意图之二；
图3为本申请实施例提供的像素电路的结构示意图之一；
图4为本申请实施例提供的像素电路的结构示意图之二；
图5为本申请实施例提供的栅极移位寄存器的一种结构示意图；
图6为图5所示栅极移位寄存器对应的时序图；
图7为本申请实施例提供的输出晶体管的俯视结构示意图；
图8为本申请实施例提供的输出晶体管的沟道区尺寸的结构示意图；
图9为本申请实施例提供的第二子显示区域的一种结构示意图。
具体实施方式
相关技术中的显示面板会存在异形区域，该异形区域可以为前置摄像头所在区域的挖槽/挖孔，或者显示面板边缘处的倒角。该异形区域的存在，导致该异形区域一行栅线连接的像素数量小于正常区域一行栅线连接的像素数量即异形区域的栅线的负载小于与正常区域的栅线的负载，从而致使显示面板的各区域的显示均一性较差。
相关技术中，为增加异形区域的栅线的负载，会设置补偿电容与异形区域的栅线电连接，但是，该补偿电容需要占用较大的面积，即增加了显示面板的边框区域，不利于显示面板实现窄边框设计。
基于相关技术中的显示面板存在的上述问题，本申请实施例提供了一种显示面板及显示装置。为了使本申请的目的，技术方案和优点更加清楚，下面结合附图，对本申请实施例提供的一种显示面板及显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅用于说明和解释本申请，并不用于限定本申请。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
除非另外定义，本申请使用的技术用语或者科学术语应当为本申请所属 领域内具有一般技能的人士所理解的通常意义。本申请中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
附图中各部件的形状和大小不反应真实比例，目的只是示意说明本申请内容。
具体地，本申请实施例提供了一种显示面板，如图1和图2所示，该显示面板包括：显示区域A和围绕显示区域A的周边区域B，该显示区域A包括第一子显示区域A1和第二子显示区域A2；显示区域A包括多行像素PX以及与每一行像素PX对应电连接的写入栅线G；其中第二子显示区域A2内一行像素PX的像素数量小于第一子显示区域A1内一行像素PX的像素数量。周边区域B包括：与各写入栅线G对应电连接的栅极移位寄存器S1或S2(栅极移位寄存器的具体结构图1和2中未视出)。
在本申请中，由于第二子显示区域A2内一行像素PX的像素数量小于第一子显示区域A1内一行像素PX的像素数量，因此第二子显示区域内各写入栅线G的负载小于第一子显示区域A1内的各写入栅线G的负载，如果不进行补偿，会导致第二子显示区域内的各像素的充电时间较长，使得第一子显示区域内和第二子显示区域内像素的亮度不一致。
参见图3和图4，像素PX包括像素电路P1和发光器件P2，像素电路P1与写入栅线G电连接，像素电路P1用于在写入栅线G的控制下接收数据信号，并根据接收的数据信号驱动发光器件P2发光。
本申请对像素电路的具体结构不作限定，可以是能够实现上述功能的任何结构，例如可以是如图3所示的传统的像素电路，还可以是具有补偿效果 的任意像素电路，例如图4所示的像素电路。以图3和图4所示的像素电路为例，参见图3，像素电路P1包括驱动晶体管DTFT、开关晶体管T1和电容C1，开关晶体管T1在栅线G控制下接收数据信号D。参见图4，像素电路P1包括驱动晶体管DTFT、开关晶体管T1～T4、电容C1和C2，开关晶体管T2在栅线G2控制下接收数据信号D。驱动晶体管DTFT根据接收的数据信号D驱动发光器件P1发光，其中驱动电流I＝K(V GS-V th) 2＝K(V G-V S-V th) 2，V th为驱动晶体管DTFT的阈值电压，V S为驱动晶体管DTFT的源电极电压，V G为驱动晶体管DTFT的栅极电压，在数据信号D固定的情况下V G的大小与充电时间有关。因此，当第一子显示区域和第二子显示区域内的各像素的充电时间不一致时，会导致第一子显示区域内和第二子显示区域内像素的驱动电流不一致，从而使得第一子显示区域内和第二子显示区域内像素的亮度不一致。
为了使第一子显示区域和第二子显示区域内的像素的充电时间一致，如图1和图2所示，本申请中，与第一子显示区域A1内的写入栅线G对应电连接的栅极移位寄存器为第一栅极移位寄存器S1，与第二子显示区域A2内的写入栅线G对应电连接的栅极移位寄存器为第二栅极移位寄存器S2，第二栅极移位寄存器S2中的输出晶体管T5的沟道区的宽长比小于第一栅极移位寄存器S1中的输出晶体管的沟道区的宽长比。
栅极移位寄存器中包括输出晶体管，输出晶体管的源电极与对应的时钟信号线电连接，输出晶体管的漏电极与对应的写入栅线电连接，输出晶体管用于向写入栅线输出有效脉冲信号。具体地，栅极移位寄存器可以向对应的写入栅线输出脉冲信号，而只有有效脉冲信号才可以控制像素电路接收数据信号。以图3和图4的像素电路为例，如果图3的开关晶体管T1为P型开关晶体管，那么写入栅线上的有效脉冲信号为低电位信号，如果图3的开关晶体管T1为N型开关晶体管，那么写入栅线上的有效脉冲信号为高电位信号，如果图4的开关晶体管T2为P型开关晶体管，那么写入栅线上的有效脉冲信号为低电位信号，如果图4的开关晶体管T2为N型开关晶体管，那么写入栅 线上的有效脉冲信号为高电位信号。
栅极移位寄存器输出的有效脉冲信号是由输出晶体管输出的，因此输出晶体管的性能可以决定写入栅线上的有效脉冲信号，本申请通过使第二栅极移位寄存器中的输出晶体管的沟道区的宽长比小于第一栅极移位寄存器中的输出晶体管的沟道区的宽长比，即通过减小第二栅极移位寄存器中的输出晶体管的沟道区的宽长比，可以使第二栅极移位寄存器中的输出晶体管的导通电阻增大，RC延迟变大，从而输出的有效脉冲信号的上升沿(Tr)和下降沿时间(Tf)增加，进而降低第二子显示区域内各像素电路的充电时间，降低第二子显示区域内各像素的驱动电流与第一子显示区域内各像素的驱动电流的差异，使第二子显示区域内各像素的亮度与第一子显示区域内各像素的亮度区域一致。通过上述设置可以不改变现有的电路结构，且不占用额外的边框面积，在提高显示面板的显示均一性的基础上，更加有利于窄边框的实现。
需要说明的是，本申请中用于控制接收数据信号D的栅线为写入栅线G，例如图3中与开关晶体管T1的栅极连接的栅线G1为写入栅线，例如图4中与开关晶体管T2的栅极连接的栅线G2为写入栅线。虽然图4中还有EM1、EM2、G1，但是这些都不是写入栅线，本申请中，与像素电路对应的写入栅线为用于控制该像素电路接收数据信号的栅线。
还需要说明的是，图1和图2中所示出的相邻的第一栅极移位寄存器、第二栅极移位寄存器之间存在级联关系(在图中未具体示出)，其级联关系与相关技术中的相邻栅极移位寄存器之间的级联关系相同，在此不作具体限定。
本申请对栅极移位寄存器的结构不作限定。以图5所示的栅极移位寄存器的结构为例，栅极移位寄存器除了包括输出晶体管T5和时钟信号端CB以外，还包括：T1晶体管、T2晶体管、T3晶体管、T4晶体管、T6晶体管、T7晶体管、T8晶体管、C1电容和C2电容，还包括用于提供信号的GI信号端、VL信号端、VH信号端、CK时钟信号端和GO输出信号端，其中，该输出信号端GO与显示区域内对应的写入栅线电连接，除此之外，还包括位于各晶体管之间的连接节点，如N1节点、N2节点、N3节点和N4节点。图5 所示的移位寄存器的工作过程与相关技术中的移位寄存器的工作过程相同，在此不再赘述。
其中，图5仅是以一种栅极移位寄存器的结构为例说明输出晶体管的连接关系，对第一栅极移位寄存器和第二栅极移位寄存器的结构并不作具体限定，第一栅极移位寄存器和第二栅极移位寄存器可以为图5所示的结构，也可以为其他任一种栅极移位寄存器的结构。并且第一栅极移位寄存器与第二栅极移位寄存器的结构可以相同，也可以不同，只要保证其所包括的输出晶体管符合上述原理即可，在此不作具体限定。
图5所示的栅极移位寄存器可以采用图6所示的时序图进行驱动，该时序图包括五个驱动阶段(T1、T2、T3、T4和T5)，在对应的阶段向移位寄存器对应的信号端(GI、CK和CB)提供对应的驱动信号，以使输出信号端GO向对应的写入栅线提供栅极驱动信号。当然，图6所示的时序图仅是图5所示移位寄存器的一种驱动方式，还可以采用其他方式的时序进行驱动，可根据实际需要进行选择，在此不作具体限定。
需要说明的是，在本申请实施例提供的显示面板中，第二子显示区域内像素的排列方式可以为图1所示，同一行像素PX与不同的写入栅线G电连接，也可以如图2所示，同一行像素PX与同一写入栅线G电连接，在此不作具体限定。并且，第二子显示区域内挖槽区域的位置可根据实际设计需求进行确定，并不限定为如图1和图2所示的两种形式，还可以为其他任何的位置或形状，在此不作具体限定。
图7为本申请实施例提供的输出晶体管的一种俯视结构示意图，其中，包括半导体层Poly，位于半导体层Poly上的栅极层Ga，以及位于栅极层Ga上的源电极S和漏电极D，且半导体层Poly、栅极层Ga和源电极S和漏电极D所在的层之间均存在绝缘层。其中，源电极S和漏电极D分别通过通孔与半导体层Poly电连接，半导体层Poly中包括源掺杂区和漏掺杂区。
晶体管中源掺杂区和漏掺杂区之间的距离称为沟道区的长度，沟道区在垂直于其延伸方向上的宽度称为沟道宽度。
如图8所示，该输出晶体管的沟道区的宽度为W1+W2+W3，该输出晶体管的沟道区的长度为L，该输出晶体管的沟道区的宽长比为(W1+W2+W3)/L。
本申请实施例，可以通过调节第一栅极移位寄存器中输出晶体管的沟道宽长比和第二栅极移位寄存器中输出晶体管的沟道宽长比，来使第一子显示区域和第二子显示区域内各像素的显示亮度趋于一致。具体调节方式有以下两种：
其中，第一栅极移位寄存器中输出晶体管的沟道区的总宽度为WA＝W1+W2+W3，可以通过调节W1、W2和/或W3的尺寸来调节WA的值；第一栅极移位寄存器中输出晶体管的沟道区的长度为LA＝L，可以通过调节L的尺寸来调节LA的值；
同理，第二栅极移位寄存器中输出晶体管的沟道区的总宽度为WB＝W1+W2+W3，可以通过调节W1、W2和/或W3的尺寸来调节WB的值；第二栅极移位寄存器中输出晶体管的沟道区的长度为LB＝L，可以通过调节L的尺寸来调节LB的值。
其中一种调节方式为：第二栅极移位寄存器中输出晶体管的沟道区的长度LB与第一栅极移位寄存器中输出晶体管的沟道区的长度LA相等；
第二栅极移位寄存器中输出晶体管的沟道区的宽度WB小于第一栅极移位寄存器中输出晶体管的沟道区的宽度WA。
在本申请实施例提供的显示面板中，输出晶体管的沟道区的宽长比越小，其提供给对应写入栅线的信号的上升沿和下降沿的时间也就越长，从而使得对像素电路的充电时间变短，以减小像素电路的驱动电流差异，使第一子显示区域和第二子显示区域的发光器件的亮度一致。
因此，为了减少第二子显示区域内各像素电路的充电时间，需要使得第二栅极移位寄存器中输出晶体管的沟道区的宽长比WB/LB小于第一栅极移位寄存器中输出晶体管的沟道区的宽长比WA/LA，在LB与LA相等时，可以使WB<WA，从而使得WB/LB<WA/LA。
另一种调节方式为：第二栅极移位寄存器中输出晶体管的沟道区的宽度WB与第一栅极移位寄存器中输出晶体管的沟道区的宽度WA相等；
第二栅极移位寄存器中输出晶体管的沟道区的长度LB大于第一栅极移位寄存器中输出晶体管的沟道区的长度LA。
在本申请实施例提供的显示面板中，输出晶体管的沟道区的宽长比越小，其提供给对应写入栅线的信号的上升沿和下降沿的时间也就越长，从而使得对像素电路的充电时间变短，以减小像素电路的驱动电流差异，使第一子显示区域和第二子显示区域的发光器件的亮度一致。
因此，为了减少第二子显示区域内各像素电路的充电时间，需要使得第二栅极移位寄存器中输出晶体管的沟道区的宽长比WB/LB小于第一栅极移位寄存器中输出晶体管的沟道区的宽长比WA/LA，在WB与WA相等时，可以使LB>LA，从而使得WB/LB<WA/LA。
需要说明的是，图7和图8仅是对本申请实施例提供的输出晶体管的结构进行示意性说明，该输出晶体管并不仅限于图7和图8所示的结构，还可以是任何其他符合本申请实施原理的输出晶体管，在此不作具体限定。
可选地，在本申请实施例提供的显示面板中，第二栅极移位寄存器中输出晶体管的沟道区的宽长比是第一栅极移位寄存器中输出晶体管的沟道区的宽长比的20％～50％。
在本申请实施例提供的显示面板中，在第二栅极移位寄存器中输出晶体管的沟道区的宽长比是第一栅极移位寄存器中输出晶体管的沟道区的宽长比的50％时，第二栅极移位寄存器提供给写入栅线的驱动信号的上升沿的时间增加2.29％，下降沿的时间增加了7.39％；在第二栅极移位寄存器中输出晶体管的沟道区的宽长比是第一栅极移位寄存器中输出晶体管的沟道区的宽长比的20％时，第二栅极移位寄存器提供给写入栅线的驱动信号的上升沿的时间增加5.14％，下降沿的时间增加了18.16％。由于驱动信号的总体时间是一定的，上升沿的时间和下降沿的时间增加了，则必然导致给像素的充电时间降低，上升沿的时间和下降沿的时间增加的百分比越大，充电时间降低的百分 比也就越大。
可选地，在本申请实施例提供的显示面板中，如图9所示，第二子显示区域在写入栅线的延伸方向上包括：第一区域a1、第二区域a2和中间区域a3，第一区域a1和第二区域a2被中间区域a3间隔设置；
且仅第一区域a1和第二区域a2包括多行像素。
在一种实施例中，在本申请实施例提供的显示面板中，如图9所示，第二子显示区域被中间区域分割成三个区域，其中，第一区域和第二区域内分别设置多行像素，而中间区域内不设置像素，可以在中间区域内设置挖槽，用于盛放前置摄像头、感光元件和听筒等器件，以使显示装置具有除显示以外的其他功能。
可选地，在本申请实施例提供的显示面板中，中间区域为凹槽形，且凹槽形的开口一侧紧邻显示面板的第一边界设置。
示例性的，在本申请实施例提供的显示面板中，该中间区域可以为凹槽形，紧邻显示面板的一个边界设置，其中，图9中是以该中间区域紧邻显示面板的上边界(第一边界)为例进行说明的，当然也可以位于显示面板的其他区域，在此不作具体限定。
需要说明的是，在本申请实施例提供的显示面板中，该中间区域除了可以为凹槽形以外，还可以为矩形、圆形、椭圆形或多边形等封闭图形，在此不作具体限定。
可选地，在本申请实施例提供的显示面板中，中间区域靠近开口一侧在写入栅线延伸方向上的长度大于中间区域远离开口一侧在写入栅线延伸方向上的长度。
示例性的，在本申请实施例提供的显示面板中，该中间区域根据所设置的器件的不同，可以将中间区域设置为具有不同宽度的区域，在其宽度较小时，则对应的第一区域和第二区域的宽度相对较大，可以设置更多的像素，在其宽度较大时，则第一区域和第二区域的宽度相对较小，设置的像素也较少。如该中间区域为上宽下窄的凹槽形时，则在第二子显示区域内，靠近显 示面板的上边界的第一区域和第二区域包括更多的像素，远离显示面板的上边界的第一区域和第二区域包括较少的像素。
基于上述，为了实现更精细的亮度调节，可以使靠近第一边界的第二栅极移位寄存器的输出晶体管的沟道区的宽长比小于远离第一边界的第二栅极移位寄存器的输出晶体管的沟道区的宽长比，从而使得显示面板的各区域内的显示亮度区域均一，提高显示面板的显示均匀性。
可选地，在本申请实施例提供的显示面板中，第一区域内的写入栅线和第二区域内的写入栅线在中间区域相互断开，且断开后的写入栅线各连接一第二栅极移位寄存器。
示例性的，在第二子显示区域内的各像素是如图1所示的结构进行排列的，由于中间区域存在挖槽，为简化设计可以使第一区域内的写入栅线与第二区域内的写入栅线断开，在第一区域和第二区域对应的周边区域处分别设置一个第二栅极移位寄存器，以对第一区域和第二区域内的像素进行驱动。当然，第一区域内的写入栅线和第二区域内的写入栅线也可以存在电连接的关系，以设置一个第一栅极移位寄存器，但是会相应的增加设计的难度，具体如何设置可根据实际使用情况进行选择，在此不作具体限定。
可选地，在本申请实施例提供的显示面板中，如图9所示，第一区域a1，第二区域a2，以及中间区域a3的至少部分边缘为曲边、圆角、倒角或切口；
第一区域a1和第二区域a2中的各行像素延伸至曲边、圆角、倒角或切口。
具体地，在本申请实施例提供的显示面板中，如图9所示，第一区域a1、第二区域a2和中间区域a3的边界均包括圆角或倒角，该圆角或倒角的设置也会使得第二子显示区域内不同行的像素数量存在差异，可以通过调节各自对应的第二移位寄存器中的输出晶体管的沟道区的宽长比，来补偿该差异，以提高各区域的显示均一性。
基于同一发明构思，本申请实施例还提供了一种显示装置，该显示装置包括上述任一实施例提供的显示面板。
该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、 数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本申请的限制。该显示装置的实施可以参见上述显示面板的实施例，重复之处不再赘述。
本申请实施例提供了一种显示面板及显示装置，该显示面板包括显示区域和围绕显示区域的周边区域，显示区域包括第一子显示区域和第二子显示区域；显示区域包括多行像素以及与每一行像素对应电连接的写入栅线；第二子显示区域内一行像素的数量小于第一子显示区域内一行像素的数量；周边区域包括与各写入栅线对应电连接的栅极移位寄存器，移位寄存器包括输出晶体管，输出晶体管用于向写入栅线输出有效脉冲信号；其中，与第一子显示区域内的写入栅线对应电连接的栅极移位寄存器为第一栅极移位寄存器，与第二子显示区域内的写入栅线对应电连接的栅极移位寄存器为第二栅极移位寄存器；第二栅极移位寄存器中的输出晶体管的沟道区的宽长比小于第一栅极移位寄存器中的输出晶体管的沟道区的宽长比。本申请实施例通过降低第二子显示区域对应的第二栅极移位寄存器内的输出晶体管的沟道区的宽长比，从而降低第二子显示区域内各像素的充电时间，使第二子显示区域内各像素的亮度与第一子显示区域内各像素的亮度区域一致。通过上述设置可以不改变现有的电路结构，且不占用额外的边框面积，在提高显示面板的显示均一性的基础上，更加有利于窄边框的实现。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的精神和范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (11)

  1. 一种显示面板，其中，包括：显示区域和围绕所述显示区域的周边区域，所述显示区域包括第一子显示区域和第二子显示区域；
    所述显示区域包括多行像素以及与每一行所述像素对应电连接的写入栅线；所述像素包括像素电路和发光器件，所述像素电路与所述写入栅线电连接，所述像素电路用于在所述写入栅线的控制下接收数据信号，并根据接收的所述数据信号驱动所述发光器件发光；
    所述第二子显示区域内一行所述像素的数量小于所述第一子显示区域内一行所述像素的数量；
    所述周边区域包括与各所述写入栅线对应电连接的栅极移位寄存器，所述移位寄存器包括输出晶体管，所述输出晶体管的源电极与时钟信号线电连接，所述输出晶体管的漏电极与所述写入栅线电连接，所述输出晶体管用于向所述写入栅线输出有效脉冲信号；
    其中，与所述第一子显示区域内的所述写入栅线对应电连接的所述栅极移位寄存器为第一栅极移位寄存器，与所述第二子显示区域内的所述写入栅线对应电连接的所述栅极移位寄存器为第二栅极移位寄存器；所述第二栅极移位寄存器中的所述输出晶体管的沟道区的宽长比小于所述第一栅极移位寄存器中的所述输出晶体管的沟道区的宽长比。
  2. 如权利要求1所述的显示面板，其中，所述第二栅极移位寄存器中的所述输出晶体管的沟道区的长度与所述第一栅极移位寄存器中的所述输出晶体管的沟道区的长度相等；
    所述第二栅极移位寄存器中的所述输出晶体管的沟道区的宽度小于所述第一栅极移位寄存器中的所述输出晶体管的沟道区的宽度。
  3. 如权利要求1所述的显示面板，其中，所述第二栅极移位寄存器中的所述输出晶体管的沟道区的宽度与所述第一栅极移位寄存器中的所述输出晶体管的沟道区的宽度相等；
    所述第二栅极移位寄存器中的所述输出晶体管的沟道区的长度大于所述第一栅极移位寄存器中的所述输出晶体管的沟道区的长度。
  4. 如权利要求1-3任一项所述的显示面板，其中，所述第二栅极移位寄存器中的所述输出晶体管的沟道区的宽长比是所述第一栅极移位寄存器中的所述输出晶体管的沟道区的宽长比的20％～50％。
  5. 如权利要求1-3任一项所述的显示面板，其中，所述第二子显示区域在所述写入栅线的延伸方向上包括：第一区域、第二区域和中间区域，所述第一区域和所述第二区域被所述中间区域间隔设置；
    且仅所述第一区域和所述第二区域包括多行所述像素。
  6. 如权利要求5所述的显示面板，其中，所述中间区域为凹槽形，且所述凹槽形的开口一侧紧邻所述显示面板的第一边界设置。
  7. 如权利要求6所述的显示面板，其中，所述中间区域靠近所述开口一侧在所述写入栅线延伸方向上的长度大于所述中间区域远离所述开口一侧在所述写入栅线延伸方向上的长度。
  8. 如权利要求6所述的显示面板，其中，靠近所述第一边界的所述第二栅极移位寄存器中的所述输出晶体管的沟道区的宽长比小于远离所述第一边界的所述第二栅极移位寄存器中的所述输出晶体管的沟道区的宽长比。
  9. 如权利要求5所述的显示面板，其中，所述第一区域内的所述写入栅线和所述第二区域内的所述写入栅线在所述中间区域相互断开，且断开后的所述写入栅线各连接一所述第二栅极移位寄存器。
  10. 如权利要求5所述的显示面板，其中，所述第一区域，所述第二区域，以及所述中间区域的至少部分边缘为曲边、圆角、倒角或切口；
    所述第一区域和所述第二区域中的各行所述像素延伸至所述曲边、圆角、倒角或切口。
  11. 一种显示装置，其中，包括权利要求1-10任一项所述的显示面板。
PCT/CN2021/071552 2020-01-21 2021-01-13 一种显示面板及显示装置 WO2021147738A1 (zh)

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